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Commit 7aaa5a60cec8c0f139c8be5fea7d639e06a0f88e

Authored by Tom Warren
1 parent 6c43f6c8d9
Exists in v2017.01-smarct4x and in 30 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

ARM: Tegra210: Add support to common Tegra source/config files 

Derived from Tegra124, modified as appropriate during T210
board bringup. Cleaned up debug statements to conserve
string space, too. This also adds misc 64-bit changes
from Thierry Reding/Stephen Warren.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>

Showing 21 changed files with 509 additions and 43 deletions Side-by-side Diff

arch/arm/dts/tegra210.dtsi
Diff comments   View file @ 7aaa5a6
  1 +#include <dt-bindings/clock/tegra210-car.h>
  2 +#include <dt-bindings/gpio/tegra-gpio.h>
  3 +#include <dt-bindings/pinctrl/pinctrl-tegra.h>
  4 +#include <dt-bindings/interrupt-controller/arm-gic.h>
  5 +#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
  6 +
  7 +#include "skeleton.dtsi"
  8 +
  9 +/ {
  10 + compatible = "nvidia,tegra210";
  11 + interrupt-parent = <&gic>;
  12 + #address-cells = <2>;
  13 + #size-cells = <2>;
  14 +
  15 + gic: interrupt-controller@0,50041000 {
  16 + compatible = "arm,gic-400";
  17 + #interrupt-cells = <3>;
  18 + interrupt-controller;
  19 + reg = <0x0 0x50041000 0x0 0x1000>,
  20 + <0x0 0x50042000 0x0 0x2000>,
  21 + <0x0 0x50044000 0x0 0x2000>,
  22 + <0x0 0x50046000 0x0 0x2000>;
  23 + interrupts = <GIC_PPI 9
  24 + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
  25 + interrupt-parent = <&gic>;
  26 + };
  27 +
  28 + tegra_car: clock@0,60006000 {
  29 + compatible = "nvidia,tegra210-car";
  30 + reg = <0x0 0x60006000 0x0 0x1000>;
  31 + #clock-cells = <1>;
  32 + #reset-cells = <1>;
  33 + };
  34 +
  35 + gpio: gpio@0,6000d000 {
  36 + compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio";
  37 + reg = <0x0 0x6000d000 0x0 0x1000>;
  38 + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
  39 + <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
  40 + <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
  41 + <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
  42 + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
  43 + <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
  44 + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
  45 + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
  46 + #gpio-cells = <2>;
  47 + gpio-controller;
  48 + #interrupt-cells = <2>;
  49 + interrupt-controller;
  50 + };
  51 +
  52 + i2c@0,7000c000 {
  53 + compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
  54 + reg = <0x0 0x7000c000 0x0 0x100>;
  55 + interrupts = <0 38 0x04>;
  56 + #address-cells = <1>;
  57 + #size-cells = <0>;
  58 + clocks = <&tegra_car 12>;
  59 + status = "disabled";
  60 + };
  61 +
  62 + i2c@0,7000c400 {
  63 + compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
  64 + reg = <0x0 0x7000c400 0x0 0x100>;
  65 + interrupts = <0 84 0x04>;
  66 + #address-cells = <1>;
  67 + #size-cells = <0>;
  68 + clocks = <&tegra_car 54>;
  69 + status = "disabled";
  70 + };
  71 +
  72 + i2c@0,7000c500 {
  73 + compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
  74 + reg = <0x0 0x7000c500 0x0 0x100>;
  75 + interrupts = <0 92 0x04>;
  76 + #address-cells = <1>;
  77 + #size-cells = <0>;
  78 + clocks = <&tegra_car 67>;
  79 + status = "disabled";
  80 + };
  81 +
  82 + i2c@0,7000c700 {
  83 + compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
  84 + reg = <0x0 0x7000c700 0x0 0x100>;
  85 + interrupts = <0 120 0x04>;
  86 + #address-cells = <1>;
  87 + #size-cells = <0>;
  88 + clocks = <&tegra_car 103>;
  89 + status = "disabled";
  90 + };
  91 +
  92 + i2c@0,7000d000 {
  93 + compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
  94 + reg = <0x0 0x7000d000 0x0 0x100>;
  95 + interrupts = <0 53 0x04>;
  96 + #address-cells = <1>;
  97 + #size-cells = <0>;
  98 + clocks = <&tegra_car 47>;
  99 + status = "disabled";
  100 + };
  101 +
  102 + i2c@0,7000d100 {
  103 + compatible = "nvidia,tegra210-i2c", "nvidia,tegra114-i2c";
  104 + reg = <0x0 0x7000d100 0x0 0x100>;
  105 + interrupts = <0 53 0x04>;
  106 + #address-cells = <1>;
  107 + #size-cells = <0>;
  108 + clocks = <&tegra_car 47>;
  109 + status = "disabled";
  110 + };
  111 +
  112 + uarta: serial@0,70006000 {
  113 + compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
  114 + reg = <0x0 0x70006000 0x0 0x40>;
  115 + reg-shift = <2>;
  116 + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
  117 + clocks = <&tegra_car TEGRA210_CLK_UARTA>;
  118 + resets = <&tegra_car 6>;
  119 + reset-names = "serial";
  120 + status = "disabled";
  121 + };
  122 +
  123 + uartb: serial@0,70006040 {
  124 + compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
  125 + reg = <0x0 0x70006040 0x0 0x40>;
  126 + reg-shift = <2>;
  127 + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
  128 + clocks = <&tegra_car TEGRA210_CLK_UARTB>;
  129 + resets = <&tegra_car 7>;
  130 + reset-names = "serial";
  131 + status = "disabled";
  132 + };
  133 +
  134 + uartc: serial@0,70006200 {
  135 + compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
  136 + reg = <0x0 0x70006200 0x0 0x40>;
  137 + reg-shift = <2>;
  138 + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
  139 + clocks = <&tegra_car TEGRA210_CLK_UARTC>;
  140 + resets = <&tegra_car 55>;
  141 + reset-names = "serial";
  142 + status = "disabled";
  143 + };
  144 +
  145 + uartd: serial@0,70006300 {
  146 + compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart";
  147 + reg = <0x0 0x70006300 0x0 0x40>;
  148 + reg-shift = <2>;
  149 + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
  150 + clocks = <&tegra_car TEGRA210_CLK_UARTD>;
  151 + resets = <&tegra_car 65>;
  152 + reset-names = "serial";
  153 + status = "disabled";
  154 + };
  155 +
  156 + spi@0,7000d400 {
  157 + compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
  158 + reg = <0x0 0x7000d400 0x0 0x200>;
  159 + interrupts = <0 59 0x04>;
  160 + #address-cells = <1>;
  161 + #size-cells = <0>;
  162 + clocks = <&tegra_car TEGRA210_CLK_SBC1>;
  163 + resets = <&tegra_car 41>;
  164 + reset-names = "spi";
  165 + status = "disabled";
  166 + };
  167 +
  168 + spi@0,7000d600 {
  169 + compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
  170 + reg = <0x0 0x7000d600 0x0 0x200>;
  171 + interrupts = <0 82 0x04>;
  172 + #address-cells = <1>;
  173 + #size-cells = <0>;
  174 + clocks = <&tegra_car TEGRA210_CLK_SBC2>;
  175 + resets = <&tegra_car 44>;
  176 + reset-names = "spi";
  177 + status = "disabled";
  178 + };
  179 +
  180 + spi@0,7000d800 {
  181 + compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
  182 + reg = <0x0 0x7000d800 0x0 0x200>;
  183 + interrupts = <0 83 0x04>;
  184 + #address-cells = <1>;
  185 + #size-cells = <0>;
  186 + clocks = <&tegra_car TEGRA210_CLK_SBC3>;
  187 + resets = <&tegra_car 46>;
  188 + reset-names = "spi";
  189 + status = "disabled";
  190 + };
  191 +
  192 + spi@0,7000da00 {
  193 + compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi";
  194 + reg = <0x0 0x7000da00 0x0 0x200>;
  195 + interrupts = <0 93 0x04>;
  196 + #address-cells = <1>;
  197 + #size-cells = <0>;
  198 + clocks = <&tegra_car TEGRA210_CLK_SBC4>;
  199 + resets = <&tegra_car 68>;
  200 + reset-names = "spi";
  201 + status = "disabled";
  202 + };
  203 +
  204 + spi@0,70410000 {
  205 + compatible = "nvidia,tegra210-qspi";
  206 + reg = <0x0 0x70410000 0x0 0x1000>;
  207 + interrupts = <0 10 0x04>;
  208 + #address-cells = <1>;
  209 + #size-cells = <0>;
  210 + clocks = <&tegra_car 211>;
  211 + status = "disabled";
  212 + };
  213 +
  214 + padctl: padctl@0,7009f000 {
  215 + compatible = "nvidia,tegra210-xusb-padctl";
  216 + reg = <0x0 0x7009f000 0x0 0x1000>;
  217 + resets = <&tegra_car 142>;
  218 + reset-names = "padctl";
  219 + #phy-cells = <1>;
  220 + };
  221 +
  222 + sdhci@0,700b0000 {
  223 + compatible = "nvidia,tegra210-sdhci";
  224 + reg = <0x0 0x700b0000 0x0 0x200>;
  225 + interrupts = <0 14 0x04>;
  226 + clocks = <&tegra_car TEGRA210_CLK_SDMMC1>;
  227 + resets = <&tegra_car 14>;
  228 + reset-names = "sdhci";
  229 + status = "disabled";
  230 + };
  231 +
  232 + sdhci@0,700b0200 {
  233 + compatible = "nvidia,tegra210-sdhci";
  234 + reg = <0x0 0x700b0200 0x0 0x200>;
  235 + interrupts = <0 15 0x04>;
  236 + clocks = <&tegra_car TEGRA210_CLK_SDMMC2>;
  237 + resets = <&tegra_car 9>;
  238 + reset-names = "sdhci";
  239 + status = "disabled";
  240 + };
  241 +
  242 + sdhci@0,700b0400 {
  243 + compatible = "nvidia,tegra210-sdhci";
  244 + reg = <0x0 0x700b0400 0x0 0x200>;
  245 + interrupts = <0 19 0x04>;
  246 + clocks = <&tegra_car TEGRA210_CLK_SDMMC3>;
  247 + resets = <&tegra_car 69>;
  248 + reset-names = "sdhci";
  249 + status = "disabled";
  250 + };
  251 +
  252 + sdhci@0,700b0600 {
  253 + compatible = "nvidia,tegra210-sdhci";
  254 + reg = <0x0 0x700b0600 0x0 0x200>;
  255 + interrupts = <0 31 0x04>;
  256 + clocks = <&tegra_car TEGRA210_CLK_SDMMC4>;
  257 + resets = <&tegra_car 15>;
  258 + reset-names = "sdhci";
  259 + status = "disabled";
  260 + };
  261 +
  262 + usb@0,7d000000 {
  263 + compatible = "nvidia,tegra210-ehci";
  264 + reg = <0x0 0x7d000000 0x0 0x4000>;
  265 + interrupts = <0 20 0x04>;
  266 + phy_type = "utmi";
  267 + clocks = <&tegra_car TEGRA210_CLK_USBD>;
  268 + resets = <&tegra_car 22>;
  269 + reset-names = "usb";
  270 + status = "disabled";
  271 + };
  272 +
  273 + usb@0,7d004000 {
  274 + compatible = "nvidia,tegra210-ehci";
  275 + reg = <0x0 0x7d004000 0x0 0x4000>;
  276 + interrupts = < 53 >;
  277 + phy_type = "utmi";
  278 + clocks = <&tegra_car TEGRA210_CLK_USB2>;
  279 + resets = <&tegra_car 58>;
  280 + reset-names = "usb";
  281 + status = "disabled";
  282 + };
  283 +};
arch/arm/include/asm/arch-tegra/ap.h
Diff comments   View file @ 7aaa5a6
1 1 /*
2   - * (C) Copyright 2010-2011
  2 + * (C) Copyright 2010-2015
3 3 * NVIDIA Corporation <www.nvidia.com>
4 4 *
5 5 * SPDX-License-Identifier: GPL-2.0+
... ... @@ -24,8 +24,6 @@
24 24 #define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */
25 25 #define PG_UP_TAG_0 0x0
26 26  
27   -#define CORESIGHT_UNLOCK 0xC5ACCE55;
28   -
29 27 /* AP base physical address of internal SRAM */
30 28 #define NV_PA_BASE_SRAM 0x40000000
31 29  
... ... @@ -66,7 +64,7 @@
66 64 /* Do any chip-specific cache config */
67 65 void config_cache(void);
68 66  
69   -#if defined(CONFIG_TEGRA124)
  67 +#if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
70 68 /* Do chip-specific vpr config */
71 69 void config_vpr(void);
72 70 #else
arch/arm/include/asm/arch-tegra/clk_rst.h
Diff comments   View file @ 7aaa5a6
... ... @@ -48,6 +48,7 @@
48 48 TEGRA_CLK_REGS_VW = 2, /* Number of clock enable regs V/W */
49 49 TEGRA_CLK_SOURCES_VW = 32, /* Number of ppl clock sources V/W */
50 50 TEGRA_CLK_SOURCES_X = 32, /* Number of ppl clock sources X */
  51 + TEGRA_CLK_SOURCES_Y = 18, /* Number of ppl clock sources Y */
51 52 };
52 53  
53 54 /* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */
54 55  
... ... @@ -94,8 +95,16 @@
94 95 uint crc_rst_dev_x_set; /* _RST_DEV_X_SET_0, 0x290 */
95 96 uint crc_rst_dev_x_clr; /* _RST_DEV_X_CLR_0, 0x294 */
96 97  
97   - uint crc_reserved21[23]; /* _reserved_21, 0x298-2f0 */
  98 + uint crc_clk_out_enb_y; /* _CLK_OUT_ENB_Y_0, 0x298 */
  99 + uint crc_clk_enb_y_set; /* _CLK_ENB_Y_SET_0, 0x29c */
  100 + uint crc_clk_enb_y_clr; /* _CLK_ENB_Y_CLR_0, 0x2a0 */
98 101  
  102 + uint crc_rst_devices_y; /* _RST_DEVICES_Y_0, 0x2a4 */
  103 + uint crc_rst_dev_y_set; /* _RST_DEV_Y_SET_0, 0x2a8 */
  104 + uint crc_rst_dev_y_clr; /* _RST_DEV_Y_CLR_0, 0x2ac */
  105 +
  106 + uint crc_reserved21[17]; /* _reserved_21, 0x2b0-2f0 */
  107 +
99 108 uint crc_dfll_base; /* _DFLL_BASE_0, 0x2f4 */
100 109  
101 110 uint crc_reserved22[2]; /* _reserved_22, 0x2f8-2fc */
... ... @@ -136,7 +145,7 @@
136 145 struct clk_set_clr crc_rst_dev_ex_vw[TEGRA_CLK_REGS_VW];
137 146 /* _CLK_ENB_V/W_CLR_0 0x440 ~ 0x44c */
138 147 struct clk_set_clr crc_clk_enb_ex_vw[TEGRA_CLK_REGS_VW];
139   - /* Additional (T114) registers */
  148 + /* Additional (T114+) registers */
140 149 uint crc_rst_cpug_cmplx_set; /* _RST_CPUG_CMPLX_SET_0, 0x450 */
141 150 uint crc_rst_cpug_cmplx_clr; /* _RST_CPUG_CMPLX_CLR_0, 0x454 */
142 151 uint crc_rst_cpulp_cmplx_set; /* _RST_CPULP_CMPLX_SET_0, 0x458 */
... ... @@ -207,9 +216,18 @@
207 216 u32 _rsv32_1[7]; /* 0x574-58c */
208 217 struct clk_pll_simple plldp; /* _PLLDP_BASE, 0x590 _PLLDP_MISC */
209 218 u32 crc_plldp_ss_cfg; /* _PLLDP_SS_CFG, 0x598 */
210   - u32 _rsrv32_2[25];
211   - /* Tegra124 */
212   - uint crc_clk_src_x[TEGRA_CLK_SOURCES_X]; /* XUSB, etc, 0x600-0x678 */
  219 +
  220 + /* Tegra124+ - skip to 0x600 here for new CLK_SOURCE_ regs */
  221 + uint _rsrv32_2[25]; /* _0x59C - 0x5FC */
  222 + uint crc_clk_src_x[TEGRA_CLK_SOURCES_X]; /* XUSB, etc, 0x600-0x67C */
  223 +
  224 + /* Tegra210 - skip to 0x694 here for new CLK_SOURCE_ regs */
  225 + uint crc_reserved61[5]; /* _reserved_61, 0x680 - 0x690 */
  226 + /*
  227 + * NOTE: PLLA1 regs are in the middle of this Y region. Break this in
  228 + * two later if PLLA1 is needed, but for now this is cleaner.
  229 + */
  230 + uint crc_clk_src_y[TEGRA_CLK_SOURCES_Y]; /* SPARE1, etc, 0x694-0x6D8 */
213 231 };
214 232  
215 233 /* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_0 */
... ... @@ -233,6 +251,8 @@
233 251  
234 252 #define PLL_DIVP_SHIFT 20
235 253 #define PLL_DIVP_MASK (7U << PLL_DIVP_SHIFT)
  254 +/* Special case for T210 PLLU DIVP */
  255 +#define PLLU_DIVP_SHIFT 16
236 256  
237 257 #define PLL_DIVN_SHIFT 8
238 258 #define PLL_DIVN_MASK (0x3ffU << PLL_DIVN_SHIFT)
... ... @@ -260,6 +280,12 @@
260 280  
261 281 #define PLL_LFCON_SHIFT 4
262 282 #define PLL_LFCON_MASK (15U << PLL_LFCON_SHIFT)
  283 +
  284 +/* CPCON/LFCON replaced by KCP/KVCO in T210 PLLU */
  285 +#define PLLU_KVCO_SHIFT 24
  286 +#define PLLU_KVCO_MASK (3U << PLLU_KVCO_SHIFT)
  287 +#define PLLU_KCP_SHIFT 25
  288 +#define PLLU_KCP_MASK (1U << PLLU_KCP_SHIFT)
263 289  
264 290 #define PLLU_VCO_FREQ_SHIFT 20
265 291 #define PLLU_VCO_FREQ_MASK (1U << PLLU_VCO_FREQ_SHIFT)
arch/arm/include/asm/arch-tegra/gp_padctrl.h
Diff comments   View file @ 7aaa5a6
1 1 /*
2   - * (C) Copyright 2010-2012
  2 + * (C) Copyright 2010-2015
3 3 * NVIDIA Corporation <www.nvidia.com>
4 4 *
5 5 * SPDX-License-Identifier: GPL-2.0+
... ... @@ -21,6 +21,7 @@
21 21 #define CHIPID_TEGRA30 0x30
22 22 #define CHIPID_TEGRA114 0x35
23 23 #define CHIPID_TEGRA124 0x40
  24 +#define CHIPID_TEGRA210 0x21
24 25  
25 26 #endif /* _TEGRA_GP_PADCTRL_H_ */
arch/arm/include/asm/arch-tegra/pmc.h
Diff comments   View file @ 7aaa5a6
1 1 /*
2   - * (C) Copyright 2010,2011,2014
  2 + * (C) Copyright 2010-2015
3 3 * NVIDIA Corporation <www.nvidia.com>
4 4 *
5 5 * SPDX-License-Identifier: GPL-2.0+
... ... @@ -294,6 +294,7 @@
294 294 #define CRAIL 0
295 295 #define CE0 14
296 296 #define C0NC 15
  297 +#define SOR 17
297 298  
298 299 #define PMC_XOFS_SHIFT 1
299 300 #define PMC_XOFS_MASK (0x3F << PMC_XOFS_SHIFT)
... ... @@ -303,7 +304,7 @@
303 304 #define TIMER_MULT_MASK (3 << TIMER_MULT_SHIFT)
304 305 #define TIMER_MULT_CPU_SHIFT 2
305 306 #define TIMER_MULT_CPU_MASK (3 << TIMER_MULT_CPU_SHIFT)
306   -#elif defined(CONFIG_TEGRA124)
  307 +#elif defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
307 308 #define TIMER_MULT_SHIFT 0
308 309 #define TIMER_MULT_MASK (7 << TIMER_MULT_SHIFT)
309 310 #define TIMER_MULT_CPU_SHIFT 3
... ... @@ -314,7 +315,7 @@
314 315 #define MULT_2 1
315 316 #define MULT_4 2
316 317 #define MULT_8 3
317   -#if defined(CONFIG_TEGRA124)
  318 +#if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
318 319 #define MULT_16 4
319 320 #endif
320 321  
arch/arm/include/asm/arch-tegra/tegra.h
Diff comments   View file @ 7aaa5a6
1 1 /*
2   - * (C) Copyright 2010,2011
  2 + * (C) Copyright 2010-2015
3 3 * NVIDIA Corporation <www.nvidia.com>
4 4 *
5 5 * SPDX-License-Identifier: GPL-2.0+
... ... @@ -74,6 +74,7 @@
74 74 SKU_ID_T114_ENG = 0x00, /* Dalmore value, unfused */
75 75 SKU_ID_T114_1 = 0x01,
76 76 SKU_ID_T124_ENG = 0x00, /* Venice2 value, unfused */
  77 + SKU_ID_T210_ENG = 0x00, /* unfused value TBD */
77 78 };
78 79  
79 80 /*
... ... @@ -88,6 +89,7 @@
88 89 TEGRA_SOC_T30,
89 90 TEGRA_SOC_T114,
90 91 TEGRA_SOC_T124,
  92 + TEGRA_SOC_T210,
91 93  
92 94 TEGRA_SOC_CNT,
93 95 TEGRA_SOC_UNKNOWN = -1,
arch/arm/include/asm/arch-tegra/usb.h
Diff comments   View file @ 7aaa5a6
... ... @@ -266,6 +266,9 @@
266 266  
267 267 /* USBx_UTMIP_BIAS_CFG1_0 */
268 268 #define UTMIP_FORCE_PDTRK_POWERDOWN 1
  269 +#define UTMIP_BIAS_DEBOUNCE_TIMESCALE_SHIFT 8
  270 +#define UTMIP_BIAS_DEBOUNCE_TIMESCALE_MASK \
  271 + (0x3f << UTMIP_BIAS_DEBOUNCE_TIMESCALE_SHIFT)
269 272 #define UTMIP_BIAS_PDTRK_COUNT_SHIFT 3
270 273 #define UTMIP_BIAS_PDTRK_COUNT_MASK \
271 274 (0x1f << UTMIP_BIAS_PDTRK_COUNT_SHIFT)
arch/arm/mach-tegra/Kconfig
Diff comments   View file @ 7aaa5a6
... ... @@ -34,6 +34,17 @@
34 34 bool "Tegra124 family"
35 35 select TEGRA_ARMV7_COMMON
36 36  
  37 +config TEGRA210
  38 + bool "Tegra210 family"
  39 + select OF_CONTROL
  40 + select ARM64
  41 + select DM
  42 + select DM_SPI_FLASH
  43 + select DM_SERIAL
  44 + select DM_I2C
  45 + select DM_SPI
  46 + select DM_GPIO
  47 +
37 48 endchoice
38 49  
39 50 config SYS_MALLOC_F_LEN
... ... @@ -43,6 +54,7 @@
43 54 source "arch/arm/mach-tegra/tegra30/Kconfig"
44 55 source "arch/arm/mach-tegra/tegra114/Kconfig"
45 56 source "arch/arm/mach-tegra/tegra124/Kconfig"
  57 +source "arch/arm/mach-tegra/tegra210/Kconfig"
46 58  
47 59 endif
arch/arm/mach-tegra/Makefile
Diff comments   View file @ 7aaa5a6
1 1 #
2   -# (C) Copyright 2010,2011 Nvidia Corporation.
  2 +# (C) Copyright 2010-2015 Nvidia Corporation.
3 3 #
4 4 # (C) Copyright 2000-2008
5 5 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6 6  
... ... @@ -24,7 +24,9 @@
24 24 obj-y += powergate.o
25 25 obj-y += xusb-padctl.o
26 26 obj-$(CONFIG_DISPLAY_CPUINFO) += sys_info.o
  27 +#TCW Fix this to use a common config switch (CONFIG_LOCK_VPR?)
27 28 obj-$(CONFIG_TEGRA124) += vpr.o
  29 +obj-$(CONFIG_TEGRA210) += vpr.o
28 30 obj-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o
29 31  
30 32 ifndef CONFIG_SPL_BUILD
... ... @@ -35,4 +37,5 @@
35 37 obj-$(CONFIG_TEGRA30) += tegra30/
36 38 obj-$(CONFIG_TEGRA114) += tegra114/
37 39 obj-$(CONFIG_TEGRA124) += tegra124/
  40 +obj-$(CONFIG_TEGRA210) += tegra210/
arch/arm/mach-tegra/ap.c
Diff comments   View file @ 7aaa5a6
1 1 /*
2   -* (C) Copyright 2010-2014
  2 +* (C) Copyright 2010-2015
3 3 * NVIDIA Corporation <www.nvidia.com>
4 4 *
5 5 * SPDX-License-Identifier: GPL-2.0+
... ... @@ -92,6 +92,13 @@
92 92 return TEGRA_SOC_T124;
93 93 }
94 94 break;
  95 + case CHIPID_TEGRA210:
  96 + switch (sku_id) {
  97 + case SKU_ID_T210_ENG:
  98 + default:
  99 + return TEGRA_SOC_T210;
  100 + }
  101 + break;
95 102 }
96 103  
97 104 /* unknown chip/sku id */
... ... @@ -100,6 +107,7 @@
100 107 return TEGRA_SOC_UNKNOWN;
101 108 }
102 109  
  110 +#ifndef CONFIG_ARM64
103 111 static void enable_scu(void)
104 112 {
105 113 struct scu_ctlr *scu = (struct scu_ctlr *)NV_PA_ARM_PERIPHBASE;
... ... @@ -222,4 +230,5 @@
222 230 /* init vpr */
223 231 config_vpr();
224 232 }
  233 +#endif
arch/arm/mach-tegra/board.c
Diff comments   View file @ 7aaa5a6
1 1 /*
2   - * (C) Copyright 2010-2014
  2 + * (C) Copyright 2010-2015
3 3 * NVIDIA Corporation <www.nvidia.com>
4 4 *
5 5 * SPDX-License-Identifier: GPL-2.0+
6 6  
... ... @@ -143,11 +143,17 @@
143 143 -1,
144 144 FUNCMUX_UART4_GMI, /* UARTD */
145 145 -1,
146   -#else /* Tegra124 */
  146 +#elif defined(CONFIG_TEGRA124)
147 147 FUNCMUX_UART1_KBC, /* UARTA */
148 148 -1,
149 149 -1,
150 150 FUNCMUX_UART4_GPIO, /* UARTD */
  151 + -1,
  152 +#else /* Tegra210 */
  153 + FUNCMUX_UART1_UART1, /* UARTA */
  154 + -1,
  155 + -1,
  156 + FUNCMUX_UART4_UART4, /* UARTD */
151 157 -1,
152 158 #endif
153 159 };
arch/arm/mach-tegra/cache.c
Diff comments   View file @ 7aaa5a6
... ... @@ -21,6 +21,7 @@
21 21 #include <asm/arch-tegra/ap.h>
22 22 #include <asm/arch/gp_padctrl.h>
23 23  
  24 +#ifndef CONFIG_ARM64
24 25 void config_cache(void)
25 26 {
26 27 u32 reg = 0;
... ... @@ -44,4 +45,5 @@
44 45 reg |= 2;
45 46 asm("mcr p15, 1, %0, c9, c0, 2" : : "r" (reg));
46 47 }
  48 +#endif
arch/arm/mach-tegra/clock.c
Diff comments   View file @ 7aaa5a6
1 1 /*
2   - * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
  2 + * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved.
3 3 *
4 4 * This program is free software; you can redistribute it and/or modify it
5 5 * under the terms and conditions of the GNU General Public License,
... ... @@ -113,7 +113,11 @@
113 113 data = readl(&pll->pll_misc);
114 114 *cpcon = (data & PLL_CPCON_MASK) >> PLL_CPCON_SHIFT;
115 115 *lfcon = (data & PLL_LFCON_MASK) >> PLL_LFCON_SHIFT;
116   -
  116 +#if defined(CONFIG_TEGRA210)
  117 + /* T210 PLLU uses KCP/KVCO instead of CPCON/LFCON */
  118 + *cpcon = (data & PLLU_KCP_MASK) >> PLLU_KCP_SHIFT;
  119 + *lfcon = (data & PLLU_KVCO_MASK) >> PLLU_KVCO_SHIFT;
  120 +#endif
117 121 return 0;
118 122 }
119 123  
120 124  
121 125  
122 126  
... ... @@ -132,14 +136,28 @@
132 136 * - same fields are always mapped at same offsets, except DCCON
133 137 * - DCCON is always 0, doesn't conflict
134 138 * - M,N, P of PLLP values are ignored for PLLP
  139 + * NOTE: Above is no longer true with T210 - TBD: FIX THIS
135 140 */
136 141 misc_data = (cpcon << PLL_CPCON_SHIFT) | (lfcon << PLL_LFCON_SHIFT);
137 142  
  143 +#if defined(CONFIG_TEGRA210)
  144 + /* T210 PLLU uses KCP/KVCO instead of cpcon/lfcon */
  145 + if (clkid == CLOCK_ID_USB) {
  146 + /* preserve EN_LOCKDET, set by default */
  147 + misc_data = readl(&pll->pll_misc);
  148 + misc_data |= (cpcon << PLLU_KCP_SHIFT) |
  149 + (lfcon << PLLU_KVCO_SHIFT);
  150 + }
  151 +#endif
138 152 data = (divm << PLL_DIVM_SHIFT) | (divn << PLL_DIVN_SHIFT) |
139 153 (0 << PLL_BYPASS_SHIFT) | (1 << PLL_ENABLE_SHIFT);
140 154  
141 155 if (clkid == CLOCK_ID_USB)
  156 +#if defined(CONFIG_TEGRA210)
  157 + data |= divp << PLLU_DIVP_SHIFT;
  158 +#else
142 159 data |= divp << PLLU_VCO_FREQ_SHIFT;
  160 +#endif
143 161 else
144 162 data |= divp << PLL_DIVP_SHIFT;
145 163 if (pll) {
146 164  
... ... @@ -534,8 +552,15 @@
534 552  
535 553 /* Set cpcon to PLL_MISC */
536 554 misc_reg = readl(&pll->pll_misc);
  555 +#if !defined(CONFIG_TEGRA210)
537 556 misc_reg &= ~PLL_CPCON_MASK;
538 557 misc_reg |= cpcon << PLL_CPCON_SHIFT;
  558 +#else
  559 + /* T210 uses KCP instead, use the most common bit shift (PLLA/U/D2) */
  560 + misc_reg &= ~PLLU_KCP_MASK;
  561 + misc_reg |= cpcon << PLLU_KCP_SHIFT;
  562 +#endif
  563 +
539 564 writel(misc_reg, &pll->pll_misc);
540 565  
541 566 /* Enable PLL */
... ... @@ -628,6 +653,7 @@
628 653 /*
629 654 * This function is useful on Tegra30, and any later SoCs that have compatible
630 655 * PLLP configuration registers.
  656 + * NOTE: Not used on Tegra210 - see tegra210_setup_pllp in T210 clock.c
631 657 */
632 658 void tegra30_set_up_pllp(void)
633 659 {
arch/arm/mach-tegra/cpu.c
Diff comments   View file @ 7aaa5a6
1 1 /*
2   - * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
  2 + * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved.
3 3 *
4 4 * This program is free software; you can redistribute it and/or modify it
5 5 * under the terms and conditions of the GNU General Public License,
... ... @@ -29,6 +29,7 @@
29 29 {
30 30 struct apb_misc_gp_ctlr *gp;
31 31 uint rev;
  32 + debug("%s entry\n", __func__);
32 33  
33 34 gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
34 35 rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
... ... @@ -39,6 +40,8 @@
39 40 break;
40 41 case CHIPID_TEGRA30:
41 42 case CHIPID_TEGRA114:
  43 + case CHIPID_TEGRA124:
  44 + case CHIPID_TEGRA210:
42 45 default:
43 46 return 4;
44 47 break;
45 48  
46 49  
... ... @@ -128,13 +131,30 @@
128 131 { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
129 132 { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
130 133 },
  134 +
  135 + /*
  136 + * T210: 700 MHz
  137 + *
  138 + * Register Field Bits Width
  139 + * ------------------------------
  140 + * PLLX_BASE p 24:20 5
  141 + * PLLX_BASE n 15: 8 8
  142 + * PLLX_BASE m 7: 0 8
  143 + */
  144 + {
  145 + { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz = 702 MHz*/
  146 + { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz = 700.8 MHz*/
  147 + { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz = 696 MHz*/
  148 + { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz = 702 MHz*/
  149 + },
131 150 };
132 151  
133 152 static inline void pllx_set_iddq(void)
134 153 {
135   -#if defined(CONFIG_TEGRA124)
  154 +#if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
136 155 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
137 156 u32 reg;
  157 + debug("%s entry\n", __func__);
138 158  
139 159 /* Disable IDDQ */
140 160 reg = readl(&clkrst->crc_pllx_misc3);
141 161  
142 162  
... ... @@ -151,15 +171,14 @@
151 171 {
152 172 int chip = tegra_get_chip();
153 173 u32 reg;
  174 + debug("%s entry\n", __func__);
154 175  
155 176 /* If PLLX is already enabled, just return */
156 177 if (readl(&pll->pll_base) & PLL_ENABLE_MASK) {
157   - debug("pllx_set_rate: PLLX already enabled, returning\n");
  178 + debug("%s: PLLX already enabled, returning\n", __func__);
158 179 return 0;
159 180 }
160 181  
161   - debug(" pllx_set_rate entry\n");
162   -
163 182 pllx_set_iddq();
164 183  
165 184 /* Set BYPASS, m, n and p to PLLX_BASE */
166 185  
167 186  
... ... @@ -182,19 +201,19 @@
182 201 reg = readl(&pll->pll_base);
183 202 reg &= ~PLL_BYPASS_MASK;
184 203 writel(reg, &pll->pll_base);
185   - debug("pllx_set_rate: base = 0x%08X\n", reg);
  204 + debug("%s: base = 0x%08X\n", __func__, reg);
186 205  
187 206 /* Set lock_enable to PLLX_MISC */
188 207 reg = readl(&pll->pll_misc);
189 208 reg |= PLL_LOCK_ENABLE_MASK;
190 209 writel(reg, &pll->pll_misc);
191   - debug("pllx_set_rate: misc = 0x%08X\n", reg);
  210 + debug("%s: misc = 0x%08X\n", __func__, reg);
192 211  
193 212 /* Enable PLLX last, once it's all configured */
194 213 reg = readl(&pll->pll_base);
195 214 reg |= PLL_ENABLE_MASK;
196 215 writel(reg, &pll->pll_base);
197   - debug("pllx_set_rate: base final = 0x%08X\n", reg);
  216 + debug("%s: base final = 0x%08X\n", __func__, reg);
198 217  
199 218 return 0;
200 219 }
201 220  
202 221  
203 222  
204 223  
205 224  
... ... @@ -206,24 +225,23 @@
206 225 int soc_type, sku_info, chip_sku;
207 226 enum clock_osc_freq osc;
208 227 struct clk_pll_table *sel;
  228 + debug("%s entry\n", __func__);
209 229  
210   - debug("init_pllx entry\n");
211   -
212 230 /* get SOC (chip) type */
213 231 soc_type = tegra_get_chip();
214   - debug(" init_pllx: SoC = 0x%02X\n", soc_type);
  232 + debug("%s: SoC = 0x%02X\n", __func__, soc_type);
215 233  
216 234 /* get SKU info */
217 235 sku_info = tegra_get_sku_info();
218   - debug(" init_pllx: SKU info byte = 0x%02X\n", sku_info);
  236 + debug("%s: SKU info byte = 0x%02X\n", __func__, sku_info);
219 237  
220 238 /* get chip SKU, combo of the above info */
221 239 chip_sku = tegra_get_chip_sku();
222   - debug(" init_pllx: Chip SKU = %d\n", chip_sku);
  240 + debug("%s: Chip SKU = %d\n", __func__, chip_sku);
223 241  
224 242 /* get osc freq */
225 243 osc = clock_get_osc_freq();
226   - debug(" init_pllx: osc = %d\n", osc);
  244 + debug("%s: osc = %d\n", __func__, osc);
227 245  
228 246 /* set pllx */
229 247 sel = &tegra_pll_x_table[chip_sku][osc];
... ... @@ -234,6 +252,7 @@
234 252 {
235 253 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
236 254 u32 clk;
  255 + debug("%s entry\n", __func__);
237 256  
238 257 /*
239 258 * NOTE:
... ... @@ -282,6 +301,7 @@
282 301 {
283 302 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
284 303 u32 reg;
  304 + debug("%s entry\n", __func__);
285 305  
286 306 /* Remove the clamps on the CPU I/O signals */
287 307 reg = readl(&pmc->pmc_remove_clamping);
... ... @@ -297,6 +317,7 @@
297 317 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
298 318 u32 reg;
299 319 int timeout = IO_STABILIZATION_DELAY;
  320 + debug("%s entry\n", __func__);
300 321  
301 322 if (!is_cpu_powered()) {
302 323 /* Toggle the CPU power state (OFF -> ON) */
... ... @@ -336,7 +357,7 @@
336 357 int num_cpus = get_num_cpus();
337 358 int cpu;
338 359  
339   - debug("reset_a9_cpu entry\n");
  360 + debug("%s entry\n", __func__);
340 361 /* Hold CPUs 1 onwards in reset, and CPU 0 if asked */
341 362 for (cpu = 1; cpu < num_cpus; cpu++)
342 363 reset_cmplx_set_enable(cpu, mask, 1);
... ... @@ -350,7 +371,7 @@
350 371 {
351 372 u32 rst, src = 2;
352 373  
353   - debug("clock_enable_coresight entry\n");
  374 + debug("%s entry\n", __func__);
354 375 clock_set_enable(PERIPH_ID_CORESIGHT, enable);
355 376 reset_set_enable(PERIPH_ID_CORESIGHT, !enable);
356 377  
... ... @@ -377,6 +398,8 @@
377 398  
378 399 void halt_avp(void)
379 400 {
  401 + debug("%s entry\n", __func__);
  402 +
380 403 for (;;) {
381 404 writel(HALT_COP_EVENT_JTAG | (FLOW_MODE_STOP << 29),
382 405 FLOW_CTLR_HALT_COP_EVENTS);
arch/arm/mach-tegra/cpu.h
Diff comments   View file @ 7aaa5a6
1 1 /*
2   - * (C) Copyright 2010-2014
  2 + * (C) Copyright 2010-2015
3 3 * NVIDIA Corporation <www.nvidia.com>
4 4 *
5 5 * SPDX-License-Identifier: GPL-2.0+
... ... @@ -14,7 +14,7 @@
14 14 #define NVBL_PLLP_KHZ 216000
15 15 #define CSITE_KHZ 144000
16 16 #elif defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114) || \
17   - defined(CONFIG_TEGRA124)
  17 + defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
18 18 #define NVBL_PLLP_KHZ 408000
19 19 #define CSITE_KHZ 204000
20 20 #else
... ... @@ -35,7 +35,7 @@
35 35 #define PG_UP_TAG_0_PID_CPU 0x55555555 /* CPU aka "a9" aka "mpcore" */
36 36 #define PG_UP_TAG_0 0x0
37 37  
38   -#define CORESIGHT_UNLOCK 0xC5ACCE55;
  38 +#define CORESIGHT_UNLOCK 0xC5ACCE55
39 39  
40 40 #define EXCEP_VECTOR_CPU_RESET_VECTOR (NV_PA_EVP_BASE + 0x100)
41 41 #define CSITE_CPU_DBG0_LAR (NV_PA_CSITE_BASE + 0x10FB0)
... ... @@ -52,6 +52,10 @@
52 52 #define FLOW_MODE_NONE 0
53 53  
54 54 #define SIMPLE_PLLX (CLOCK_ID_XCPU - CLOCK_ID_FIRST_SIMPLE)
  55 +
  56 +/* SB_AA64_RESET_LOW and _HIGH defines for CPU reset vector */
  57 +#define SB_AA64_RESET_LOW 0x6000C230
  58 +#define SB_AA64_RESET_HIGH 0x6000C234
55 59  
56 60 struct clk_pll_table {
57 61 u16 n;
arch/arm/mach-tegra/lowlevel_init.S
Diff comments   View file @ 7aaa5a6
... ... @@ -10,8 +10,22 @@
10 10 #include <config.h>
11 11 #include <linux/linkage.h>
12 12  
  13 +#ifdef CONFIG_ARM64
13 14 .align 5
14 15 ENTRY(reset_cpu)
  16 + /* get address for global reset register */
  17 + ldr x1, =PRM_RSTCTRL
  18 + ldr w3, [x1]
  19 + /* force reset */
  20 + orr w3, w3, #0x10
  21 + str w3, [x1]
  22 + mov w0, w0
  23 +1:
  24 + b 1b
  25 +ENDPROC(reset_cpu)
  26 +#else
  27 + .align 5
  28 +ENTRY(reset_cpu)
15 29 ldr r1, rstctl @ get addr for global reset
16 30 @ reg
17 31 ldr r3, [r1]
... ... @@ -23,4 +37,5 @@
23 37 rstctl:
24 38 .word PRM_RSTCTRL
25 39 ENDPROC(reset_cpu)
  40 +#endif
drivers/mmc/tegra_mmc.c
Diff comments   View file @ 7aaa5a6
... ... @@ -2,7 +2,7 @@
2 2 * (C) Copyright 2009 SAMSUNG Electronics
3 3 * Minkyu Kang <mk7.kang@samsung.com>
4 4 * Jaehoon Chung <jh80.chung@samsung.com>
5   - * Portions Copyright 2011-2013 NVIDIA Corporation
  5 + * Portions Copyright 2011-2015 NVIDIA Corporation
6 6 *
7 7 * SPDX-License-Identifier: GPL-2.0+
8 8 */
... ... @@ -667,6 +667,16 @@
667 667 int node_list[CONFIG_SYS_MMC_MAX_DEVICE], count;
668 668 const void *blob = gd->fdt_blob;
669 669 debug("%s entry\n", __func__);
  670 +
  671 + /* See if any Tegra210 MMC controllers are present */
  672 + count = fdtdec_find_aliases_for_id(blob, "sdhci",
  673 + COMPAT_NVIDIA_TEGRA210_SDMMC, node_list,
  674 + CONFIG_SYS_MMC_MAX_DEVICE);
  675 + debug("%s: count of Tegra210 sdhci nodes is %d\n", __func__, count);
  676 + if (process_nodes(blob, node_list, count)) {
  677 + printf("%s: Error processing T30 mmc node(s)!\n", __func__);
  678 + return;
  679 + }
670 680  
671 681 /* See if any Tegra124 MMC controllers are present */
672 682 count = fdtdec_find_aliases_for_id(blob, "sdhci",
drivers/usb/host/ehci-tegra.c
Diff comments   View file @ 7aaa5a6
1 1 /*
2 2 * Copyright (c) 2011 The Chromium OS Authors.
3   - * Copyright (c) 2009-2013 NVIDIA Corporation
  3 + * Copyright (c) 2009-2015 NVIDIA Corporation
4 4 * Copyright (c) 2013 Lucas Stach
5 5 *
6 6 * SPDX-License-Identifier: GPL-2.0+
... ... @@ -64,6 +64,7 @@
64 64 USB_CTLR_T20,
65 65 USB_CTLR_T30,
66 66 USB_CTLR_T114,
  67 + USB_CTLR_T210,
67 68  
68 69 USB_CTRL_COUNT,
69 70 };
... ... @@ -149,6 +150,15 @@
149 150 { 0x3C0, 0x1A, 0x00, 0xC, 2, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 0xB }
150 151 };
151 152  
  153 +/* NOTE: 13/26MHz settings are N/A for T210, so dupe 12MHz settings for now */
  154 +static const unsigned T210_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = {
  155 + /* DivN, DivM, DivP, KCP, KVCO, Delays Debounce, Bias */
  156 + { 0x028, 0x01, 0x01, 0x0, 0, 0x02, 0x2F, 0x08, 0x76, 30000, 5 },
  157 + { 0x019, 0x01, 0x01, 0x0, 0, 0x03, 0x4B, 0x0C, 0xBB, 48000, 8 },
  158 + { 0x028, 0x01, 0x01, 0x0, 0, 0x02, 0x2F, 0x08, 0x76, 30000, 5 },
  159 + { 0x028, 0x01, 0x01, 0x0, 0, 0x02, 0x2F, 0x08, 0x76, 30000, 5 },
  160 +};
  161 +
152 162 /* UTMIP Idle Wait Delay */
153 163 static const u8 utmip_idle_wait_delay = 17;
154 164  
... ... @@ -177,6 +187,10 @@
177 187 .has_hostpc = 1,
178 188 .pll_parameter = (const unsigned *)T114_usb_pll,
179 189 },
  190 + {
  191 + .has_hostpc = 1,
  192 + .pll_parameter = (const unsigned *)T210_usb_pll,
  193 + },
180 194 };
181 195  
182 196 /*
... ... @@ -458,6 +472,16 @@
458 472 UTMIP_DEBOUNCE_CFG0_MASK,
459 473 timing[PARAM_DEBOUNCE_A_TIME] << UTMIP_DEBOUNCE_CFG0_SHIFT);
460 474  
  475 + if (timing[PARAM_DEBOUNCE_A_TIME] > 0xFFFF) {
  476 + clrsetbits_le32(&usbctlr->utmip_debounce_cfg0,
  477 + UTMIP_DEBOUNCE_CFG0_MASK,
  478 + (timing[PARAM_DEBOUNCE_A_TIME] >> 1)
  479 + << UTMIP_DEBOUNCE_CFG0_SHIFT);
  480 + clrsetbits_le32(&usbctlr->utmip_bias_cfg1,
  481 + UTMIP_BIAS_DEBOUNCE_TIMESCALE_MASK,
  482 + 1 << UTMIP_BIAS_DEBOUNCE_TIMESCALE_SHIFT);
  483 + }
  484 +
461 485 setbits_le32(&usbctlr->utmip_tx_cfg0, UTMIP_FS_PREAMBLE_J);
462 486  
463 487 /* Disable battery charge enabling bit */
... ... @@ -643,6 +667,10 @@
643 667  
644 668 static void config_clock(const u32 timing[])
645 669 {
  670 + debug("%s: DIVM = %d, DIVN = %d, DIVP = %d, cpcon/lfcon = %d/%d\n",
  671 + __func__, timing[PARAM_DIVM], timing[PARAM_DIVN],
  672 + timing[PARAM_DIVP], timing[PARAM_CPCON], timing[PARAM_LFCON]);
  673 +
646 674 clock_start_pll(CLOCK_ID_USB,
647 675 timing[PARAM_DIVM], timing[PARAM_DIVN], timing[PARAM_DIVP],
648 676 timing[PARAM_CPCON], timing[PARAM_LFCON]);
... ... @@ -823,6 +851,7 @@
823 851 { .compatible = "nvidia,tegra20-ehci", .data = USB_CTLR_T20 },
824 852 { .compatible = "nvidia,tegra30-ehci", .data = USB_CTLR_T30 },
825 853 { .compatible = "nvidia,tegra114-ehci", .data = USB_CTLR_T114 },
  854 + { .compatible = "nvidia,tegra210-ehci", .data = USB_CTLR_T210 },
826 855 { }
827 856 };
828 857  
include/configs/tegra-common-post.h
Diff comments   View file @ 7aaa5a6
... ... @@ -62,11 +62,19 @@
62 62 #define CONFIG_CHROMEOS_EXTRA_ENV_SETTINGS
63 63 #endif
64 64  
  65 +#ifdef CONFIG_ARM64
  66 +#define FDT_HIGH "ffffffffffffffff"
  67 +#define INITRD_HIGH "ffffffffffffffff"
  68 +#else
  69 +#define FDT_HIGH "ffffffff"
  70 +#define INITRD_HIGH "ffffffff"
  71 +#endif
  72 +
65 73 #define CONFIG_EXTRA_ENV_SETTINGS \
66 74 TEGRA_DEVICE_SETTINGS \
67 75 MEM_LAYOUT_ENV_SETTINGS \
68   - "fdt_high=ffffffff\0" \
69   - "initrd_high=ffffffff\0" \
  76 + "fdt_high=" FDT_HIGH "\0" \
  77 + "initrd_high=" INITRD_HIGH "\0" \
70 78 BOOTENV \
71 79 BOARD_EXTRA_ENV_SETTINGS \
72 80 CONFIG_CHROMEOS_EXTRA_ENV_SETTINGS
... ... @@ -137,6 +137,7 @@
137 137 COMPAT_NVIDIA_TEGRA124_SOR, /* Tegra 124 Serial Output Resource */
138 138 COMPAT_NVIDIA_TEGRA124_PMC, /* Tegra 124 power mgmt controller */
139 139 COMPAT_NVIDIA_TEGRA20_DC, /* Tegra 2 Display controller */
  140 + COMPAT_NVIDIA_TEGRA210_SDMMC, /* Tegra210 SDMMC controller */
140 141 COMPAT_NVIDIA_TEGRA124_SDMMC, /* Tegra124 SDMMC controller */
141 142 COMPAT_NVIDIA_TEGRA30_SDMMC, /* Tegra30 SDMMC controller */
142 143 COMPAT_NVIDIA_TEGRA20_SDMMC, /* Tegra20 SDMMC controller */
... ... @@ -145,6 +146,8 @@
145 146 COMPAT_NVIDIA_TEGRA20_PCIE, /* Tegra 20 PCIe controller */
146 147 COMPAT_NVIDIA_TEGRA124_XUSB_PADCTL,
147 148 /* Tegra124 XUSB pad controller */
  149 + COMPAT_NVIDIA_TEGRA210_XUSB_PADCTL,
  150 + /* Tegra210 XUSB pad controller */
148 151 COMPAT_SMSC_LAN9215, /* SMSC 10/100 Ethernet LAN9215 */
149 152 COMPAT_SAMSUNG_EXYNOS5_SROMC, /* Exynos5 SROMC */
150 153 COMPAT_SAMSUNG_S3C2440_I2C, /* Exynos I2C Controller */
... ... @@ -31,6 +31,7 @@
31 31 COMPAT(NVIDIA_TEGRA124_SOR, "nvidia,tegra124-sor"),
32 32 COMPAT(NVIDIA_TEGRA124_PMC, "nvidia,tegra124-pmc"),
33 33 COMPAT(NVIDIA_TEGRA20_DC, "nvidia,tegra20-dc"),
  34 + COMPAT(NVIDIA_TEGRA210_SDMMC, "nvidia,tegra210-sdhci"),
34 35 COMPAT(NVIDIA_TEGRA124_SDMMC, "nvidia,tegra124-sdhci"),
35 36 COMPAT(NVIDIA_TEGRA30_SDMMC, "nvidia,tegra30-sdhci"),
36 37 COMPAT(NVIDIA_TEGRA20_SDMMC, "nvidia,tegra20-sdhci"),
... ... @@ -38,6 +39,7 @@
38 39 COMPAT(NVIDIA_TEGRA30_PCIE, "nvidia,tegra30-pcie"),
39 40 COMPAT(NVIDIA_TEGRA20_PCIE, "nvidia,tegra20-pcie"),
40 41 COMPAT(NVIDIA_TEGRA124_XUSB_PADCTL, "nvidia,tegra124-xusb-padctl"),
  42 + COMPAT(NVIDIA_TEGRA210_XUSB_PADCTL, "nvidia,tegra210-xusb-padctl"),
41 43 COMPAT(SMSC_LAN9215, "smsc,lan9215"),
42 44 COMPAT(SAMSUNG_EXYNOS5_SROMC, "samsung,exynos-sromc"),
43 45 COMPAT(SAMSUNG_S3C2440_I2C, "samsung,s3c2440-i2c"),