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Commit 7ac9d47a22f05320db159f7a9386ee2266639d9b

Authored by Matthias Fuchs
Committed by Tom Rini
1 parent bc114076dc
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

ppc4xx: remove DU440 board 

Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>

Showing 11 changed files with 1 additions and 1440 deletions Side-by-side Diff

arch/powerpc/cpu/ppc4xx/Kconfig
Diff comments   View file @ 7ac9d47
... ... @@ -125,9 +125,6 @@
125 125 config TARGET_CPCI405DT
126 126 bool "Support CPCI405DT"
127 127  
128   -config TARGET_DU440
129   - bool "Support DU440"
130   -
131 128 config TARGET_HH405
132 129 bool "Support HH405"
133 130  
... ... @@ -238,7 +235,6 @@
238 235 source "board/dave/PPChameleonEVB/Kconfig"
239 236 source "board/esd/cpci2dp/Kconfig"
240 237 source "board/esd/cpci405/Kconfig"
241   -source "board/esd/du440/Kconfig"
242 238 source "board/esd/hh405/Kconfig"
243 239 source "board/esd/hub405/Kconfig"
244 240 source "board/esd/ocrtc/Kconfig"
board/esd/du440/Kconfig
View file @ 7ac9d47
1   -if TARGET_DU440
2   -
3   -config SYS_BOARD
4   - default "du440"
5   -
6   -config SYS_VENDOR
7   - default "esd"
8   -
9   -config SYS_CONFIG_NAME
10   - default "DU440"
11   -
12   -endif
board/esd/du440/MAINTAINERS
View file @ 7ac9d47
1   -DU440 BOARD
2   -M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
3   -S: Maintained
4   -F: board/esd/du440/
5   -F: include/configs/DU440.h
6   -F: configs/DU440_defconfig
board/esd/du440/Makefile
View file @ 7ac9d47
1   -#
2   -# (C) Copyright 2002-2006
3   -# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   -#
5   -# SPDX-License-Identifier: GPL-2.0+
6   -#
7   -
8   -obj-y = du440.o
9   -extra-y += init.o
board/esd/du440/config.mk
View file @ 7ac9d47
1   -#
2   -# (C) Copyright 2002-2010
3   -# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4   -#
5   -# SPDX-License-Identifier: GPL-2.0+
6   -#
7   -
8   -PLATFORM_CPPFLAGS += -DCONFIG_440=1
9   -
10   -ifeq ($(debug),1)
11   -PLATFORM_CPPFLAGS += -DDEBUG
12   -endif
13   -
14   -ifeq ($(dbcr),1)
15   -PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
16   -endif
board/esd/du440/du440.c
View file @ 7ac9d47
1   -/*
2   - * (C) Copyright 2008
3   - * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -#include <common.h>
9   -#include <asm/processor.h>
10   -#include <asm/io.h>
11   -#include <asm/bitops.h>
12   -#include <command.h>
13   -#include <i2c.h>
14   -#include <asm/ppc440.h>
15   -#include "du440.h"
16   -
17   -DECLARE_GLOBAL_DATA_PTR;
18   -
19   -extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
20   -extern ulong flash_get_size (ulong base, int banknum);
21   -
22   -int usbhub_init(void);
23   -int dvi_init(void);
24   -int eeprom_write_enable (unsigned dev_addr, int state);
25   -int board_revision(void);
26   -
27   -static int du440_post_errors;
28   -
29   -int board_early_init_f(void)
30   -{
31   - u32 sdr0_cust0;
32   - u32 sdr0_pfc1, sdr0_pfc2;
33   - u32 reg;
34   -
35   - mtdcr(EBC0_CFGADDR, EBC0_CFG);
36   - mtdcr(EBC0_CFGDATA, 0xb8400000);
37   -
38   - /*
39   - * Setup the GPIO pins
40   - */
41   - out_be32((void*)GPIO0_OR, 0x00000000 | CONFIG_SYS_GPIO0_EP_EEP);
42   - out_be32((void*)GPIO0_TCR, 0x0000001f | CONFIG_SYS_GPIO0_EP_EEP);
43   - out_be32((void*)GPIO0_OSRL, 0x50055400);
44   - out_be32((void*)GPIO0_OSRH, 0x55005000);
45   - out_be32((void*)GPIO0_TSRL, 0x50055400);
46   - out_be32((void*)GPIO0_TSRH, 0x55005000);
47   - out_be32((void*)GPIO0_ISR1L, 0x50000000);
48   - out_be32((void*)GPIO0_ISR1H, 0x00000000);
49   - out_be32((void*)GPIO0_ISR2L, 0x00000000);
50   - out_be32((void*)GPIO0_ISR2H, 0x00000000);
51   - out_be32((void*)GPIO0_ISR3L, 0x00000000);
52   - out_be32((void*)GPIO0_ISR3H, 0x00000000);
53   -
54   - out_be32((void*)GPIO1_OR, 0x00000000);
55   - out_be32((void*)GPIO1_TCR, 0xc2000000 |
56   - CONFIG_SYS_GPIO1_IORSTN |
57   - CONFIG_SYS_GPIO1_IORST2N |
58   - CONFIG_SYS_GPIO1_LEDUSR1 |
59   - CONFIG_SYS_GPIO1_LEDUSR2 |
60   - CONFIG_SYS_GPIO1_LEDPOST |
61   - CONFIG_SYS_GPIO1_LEDDU);
62   - out_be32((void*)GPIO1_ODR, CONFIG_SYS_GPIO1_LEDDU);
63   - out_be32((void*)GPIO1_OSRL, 0x0c280000);
64   - out_be32((void*)GPIO1_OSRH, 0x00000000);
65   - out_be32((void*)GPIO1_TSRL, 0xcc000000);
66   - out_be32((void*)GPIO1_TSRH, 0x00000000);
67   - out_be32((void*)GPIO1_ISR1L, 0x00005550);
68   - out_be32((void*)GPIO1_ISR1H, 0x00000000);
69   - out_be32((void*)GPIO1_ISR2L, 0x00050000);
70   - out_be32((void*)GPIO1_ISR2H, 0x00000000);
71   - out_be32((void*)GPIO1_ISR3L, 0x01400000);
72   - out_be32((void*)GPIO1_ISR3H, 0x00000000);
73   -
74   - /*
75   - * Setup the interrupt controller polarities, triggers, etc.
76   - */
77   - mtdcr(UIC0SR, 0xffffffff); /* clear all */
78   - mtdcr(UIC0ER, 0x00000000); /* disable all */
79   - mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
80   - mtdcr(UIC0PR, 0xfffff7ff); /* per ref-board manual */
81   - mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
82   - mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
83   - mtdcr(UIC0SR, 0xffffffff); /* clear all */
84   -
85   - /*
86   - * UIC1:
87   - * bit30: ext. Irq 1: PLD : int 32+30
88   - */
89   - mtdcr(UIC1SR, 0xffffffff); /* clear all */
90   - mtdcr(UIC1ER, 0x00000000); /* disable all */
91   - mtdcr(UIC1CR, 0x00000000); /* all non-critical */
92   - mtdcr(UIC1PR, 0xfffffffd);
93   - mtdcr(UIC1TR, 0x00000000);
94   - mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
95   - mtdcr(UIC1SR, 0xffffffff); /* clear all */
96   -
97   - /*
98   - * UIC2
99   - * bit3: ext. Irq 2: DCF77 : int 64+3
100   - */
101   - mtdcr(UIC2SR, 0xffffffff); /* clear all */
102   - mtdcr(UIC2ER, 0x00000000); /* disable all */
103   - mtdcr(UIC2CR, 0x00000000); /* all non-critical */
104   - mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
105   - mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
106   - mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
107   - mtdcr(UIC2SR, 0xffffffff); /* clear all */
108   -
109   - /* select Ethernet pins */
110   - mfsdr(SDR0_PFC1, sdr0_pfc1);
111   - mfsdr(SDR0_PFC2, sdr0_pfc2);
112   -
113   - /* setup EMAC bridge interface */
114   - if (board_revision() == 0) {
115   - /* 1 x MII */
116   - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
117   - SDR0_PFC1_SELECT_CONFIG_1_2;
118   - sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
119   - SDR0_PFC2_SELECT_CONFIG_1_2;
120   - } else {
121   - /* 2 x SMII */
122   - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
123   - SDR0_PFC1_SELECT_CONFIG_6;
124   - sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
125   - SDR0_PFC2_SELECT_CONFIG_6;
126   - }
127   -
128   - /* enable 2nd IIC */
129   - sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
130   -
131   - mtsdr(SDR0_PFC2, sdr0_pfc2);
132   - mtsdr(SDR0_PFC1, sdr0_pfc1);
133   -
134   - /* PCI arbiter enabled */
135   - mfsdr(SDR0_PCI0, reg);
136   - mtsdr(SDR0_PCI0, 0x80000000 | reg);
137   -
138   - /* setup NAND FLASH */
139   - mfsdr(SDR0_CUST0, sdr0_cust0);
140   - sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
141   - SDR0_CUST0_NDFC_ENABLE |
142   - SDR0_CUST0_NDFC_BW_8_BIT |
143   - SDR0_CUST0_NDFC_ARE_MASK |
144   - (0x80000000 >> (28 + CONFIG_SYS_NAND0_CS)) |
145   - (0x80000000 >> (28 + CONFIG_SYS_NAND1_CS));
146   - mtsdr(SDR0_CUST0, sdr0_cust0);
147   -
148   - return 0;
149   -}
150   -
151   -int misc_init_r(void)
152   -{
153   - uint pbcr;
154   - int size_val = 0;
155   - u32 reg;
156   - unsigned long usb2d0cr = 0;
157   - unsigned long usb2phy0cr, usb2h0cr = 0;
158   - unsigned long sdr0_pfc1;
159   - unsigned long sdr0_srst0, sdr0_srst1;
160   - int i, j;
161   -
162   - /* adjust flash start and offset */
163   - gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
164   - gd->bd->bi_flashoffset = 0;
165   -
166   - mtdcr(EBC0_CFGADDR, PB0CR);
167   - pbcr = mfdcr(EBC0_CFGDATA);
168   - size_val = ffs(gd->bd->bi_flashsize) - 21;
169   - pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
170   - mtdcr(EBC0_CFGADDR, PB0CR);
171   - mtdcr(EBC0_CFGDATA, pbcr);
172   -
173   - /*
174   - * Re-check to get correct base address
175   - */
176   - flash_get_size(gd->bd->bi_flashstart, 0);
177   -
178   - /*
179   - * USB suff...
180   - */
181   - /* SDR Setting */
182   - mfsdr(SDR0_PFC1, sdr0_pfc1);
183   - mfsdr(SDR0_USB0, usb2d0cr);
184   - mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
185   - mfsdr(SDR0_USB2H0CR, usb2h0cr);
186   -
187   - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
188   - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
189   - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
190   - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
191   - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
192   - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
193   - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
194   - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
195   - usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
196   - usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
197   -
198   - /* An 8-bit/60MHz interface is the only possible alternative
199   - when connecting the Device to the PHY */
200   - usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
201   - usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
202   -
203   - /* To enable the USB 2.0 Device function through the UTMI interface */
204   - usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
205   -
206   - sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
207   - sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
208   -
209   - mtsdr(SDR0_PFC1, sdr0_pfc1);
210   - mtsdr(SDR0_USB0, usb2d0cr);
211   - mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
212   - mtsdr(SDR0_USB2H0CR, usb2h0cr);
213   -
214   - /*
215   - * Take USB out of reset:
216   - * -Initial status = all cores are in reset
217   - * -deassert reset to OPB1, P4OPB0, OPB2, PLB42OPB1 OPB2PLB40 cores
218   - * -wait 1 ms
219   - * -deassert reset to PHY
220   - * -wait 1 ms
221   - * -deassert reset to HOST
222   - * -wait 4 ms
223   - * -deassert all other resets
224   - */
225   - mfsdr(SDR0_SRST1, sdr0_srst1);
226   - sdr0_srst1 &= ~(SDR0_SRST1_OPBA1 | \
227   - SDR0_SRST1_P4OPB0 | \
228   - SDR0_SRST1_OPBA2 | \
229   - SDR0_SRST1_PLB42OPB1 | \
230   - SDR0_SRST1_OPB2PLB40);
231   - mtsdr(SDR0_SRST1, sdr0_srst1);
232   - udelay(1000);
233   -
234   - mfsdr(SDR0_SRST1, sdr0_srst1);
235   - sdr0_srst1 &= ~SDR0_SRST1_USB20PHY;
236   - mtsdr(SDR0_SRST1, sdr0_srst1);
237   - udelay(1000);
238   -
239   - mfsdr(SDR0_SRST0, sdr0_srst0);
240   - sdr0_srst0 &= ~SDR0_SRST0_USB2H;
241   - mtsdr(SDR0_SRST0, sdr0_srst0);
242   - udelay(4000);
243   -
244   - /* finally all the other resets */
245   - mtsdr(SDR0_SRST1, 0x00000000);
246   - mtsdr(SDR0_SRST0, 0x00000000);
247   -
248   - printf("USB: Host(int phy)\n");
249   -
250   - /*
251   - * Clear PLB4A0_ACR[WRP]
252   - * This fix will make the MAL burst disabling patch for the Linux
253   - * EMAC driver obsolete.
254   - */
255   - reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK;
256   - mtdcr(PLB4A0_ACR, reg);
257   -
258   - /*
259   - * release IO-RST#
260   - * We have to wait at least 560ms until we may call usbhub_init
261   - */
262   - out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) |
263   - CONFIG_SYS_GPIO1_IORSTN | CONFIG_SYS_GPIO1_IORST2N);
264   -
265   - /*
266   - * flash USR1/2 LEDs (600ms)
267   - * This results in the necessary delay from IORST# until
268   - * calling usbhub_init will succeed
269   - */
270   - for (j = 0; j < 3; j++) {
271   - out_be32((void*)GPIO1_OR,
272   - (in_be32((void*)GPIO1_OR) & ~CONFIG_SYS_GPIO1_LEDUSR2) |
273   - CONFIG_SYS_GPIO1_LEDUSR1);
274   -
275   - for (i = 0; i < 100; i++)
276   - udelay(1000);
277   -
278   - out_be32((void*)GPIO1_OR,
279   - (in_be32((void*)GPIO1_OR) & ~CONFIG_SYS_GPIO1_LEDUSR1) |
280   - CONFIG_SYS_GPIO1_LEDUSR2);
281   -
282   - for (i = 0; i < 100; i++)
283   - udelay(1000);
284   - }
285   -
286   - out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) &
287   - ~(CONFIG_SYS_GPIO1_LEDUSR1 | CONFIG_SYS_GPIO1_LEDUSR2));
288   -
289   - if (usbhub_init())
290   - du440_post_errors++;
291   -
292   - if (dvi_init())
293   - du440_post_errors++;
294   -
295   - return 0;
296   -}
297   -
298   -int pld_revision(void)
299   -{
300   - out_8((void *)CONFIG_SYS_CPLD_BASE, 0x00);
301   - return (int)(in_8((void *)CONFIG_SYS_CPLD_BASE) & CPLD_VERSION_MASK);
302   -}
303   -
304   -int board_revision(void)
305   -{
306   - int rpins = (int)((in_be32((void*)GPIO1_IR) & CONFIG_SYS_GPIO1_HWVER_MASK)
307   - >> CONFIG_SYS_GPIO1_HWVER_SHIFT);
308   -
309   - return ((rpins & 1) << 3) | ((rpins & 2) << 1) |
310   - ((rpins & 4) >> 1) | ((rpins & 8) >> 3);
311   -}
312   -
313   -#if defined(CONFIG_SHOW_ACTIVITY)
314   -void board_show_activity (ulong timestamp)
315   -{
316   - if ((timestamp % 100) == 0)
317   - out_be32((void*)GPIO1_OR,
318   - in_be32((void*)GPIO1_OR) ^ CONFIG_SYS_GPIO1_LEDUSR1);
319   -}
320   -
321   -void show_activity(int arg)
322   -{
323   -}
324   -#endif /* CONFIG_SHOW_ACTIVITY */
325   -
326   -int du440_phy_addr(int devnum)
327   -{
328   - if (board_revision() == 0)
329   - return devnum;
330   -
331   - return devnum + 1;
332   -}
333   -
334   -int checkboard(void)
335   -{
336   - char serno[32];
337   -
338   - puts("Board: DU440");
339   -
340   - if (getenv_f("serial#", serno, sizeof(serno)) > 0) {
341   - puts(", serial# ");
342   - puts(serno);
343   - }
344   -
345   - printf(", HW-Rev. 1.%d, CPLD-Rev. 1.%d\n",
346   - board_revision(), pld_revision());
347   - return (0);
348   -}
349   -
350   -int last_stage_init(void)
351   -{
352   - int e, i;
353   -
354   - /* everyting is ok: turn on POST-LED */
355   - out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | CONFIG_SYS_GPIO1_LEDPOST);
356   -
357   - /* slowly blink on errors and finally keep LED off */
358   - for (e = 0; e < du440_post_errors; e++) {
359   - out_be32((void*)GPIO1_OR,
360   - in_be32((void*)GPIO1_OR) | CONFIG_SYS_GPIO1_LEDPOST);
361   -
362   - for (i = 0; i < 500; i++)
363   - udelay(1000);
364   -
365   - out_be32((void*)GPIO1_OR,
366   - in_be32((void*)GPIO1_OR) & ~CONFIG_SYS_GPIO1_LEDPOST);
367   -
368   - for (i = 0; i < 500; i++)
369   - udelay(1000);
370   - }
371   -
372   - return 0;
373   -}
374   -
375   -/*
376   - * read field strength from I2C ADC
377   - */
378   -int dcf77_status(void)
379   -{
380   - unsigned int oldbus;
381   - uchar u[2];
382   - int mv;
383   -
384   - oldbus = I2C_GET_BUS();
385   - I2C_SET_BUS(1);
386   -
387   - if (i2c_read (IIC1_MCP3021_ADDR, 0, 0, u, 2)) {
388   - I2C_SET_BUS(oldbus);
389   - return -1;
390   - }
391   -
392   - mv = (int)(((u[0] << 8) | u[1]) >> 2) * 3300 / 1024;
393   -
394   - I2C_SET_BUS(oldbus);
395   - return mv;
396   -}
397   -
398   -int do_dcf77(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
399   -{
400   - int mv;
401   - u32 pin, pinold;
402   - unsigned long long t1, t2;
403   - bd_t *bd = gd->bd;
404   -
405   - printf("DCF77: ");
406   - mv = dcf77_status();
407   - if (mv > 0)
408   - printf("signal=%d mV\n", mv);
409   - else
410   - printf("ERROR - no signal\n");
411   -
412   - t1 = t2 = 0;
413   - pinold = in_be32((void*)GPIO1_IR) & CONFIG_SYS_GPIO1_DCF77;
414   - while (!ctrlc()) {
415   - pin = in_be32((void*)GPIO1_IR) & CONFIG_SYS_GPIO1_DCF77;
416   - if (pin && !pinold) { /* bit start */
417   - t1 = get_ticks();
418   - if (t2 && ((unsigned int)(t1 - t2) /
419   - (bd->bi_procfreq / 1000) >= 1800))
420   - printf("Start of minute\n");
421   -
422   - t2 = t1;
423   - }
424   - if (t1 && !pin && pinold) { /* bit end */
425   - printf("%5d\n", (unsigned int)(get_ticks() - t1) /
426   - (bd->bi_procfreq / 1000));
427   - }
428   - pinold = pin;
429   - }
430   -
431   - printf("Abort\n");
432   - return 0;
433   -}
434   -U_BOOT_CMD(
435   - dcf77, 1, 1, do_dcf77,
436   - "Check DCF77 receiver",
437   - ""
438   -);
439   -
440   -/*
441   - * initialize USB hub via I2C1
442   - */
443   -int usbhub_init(void)
444   -{
445   - int reg;
446   - int ret = 0;
447   - unsigned int oldbus;
448   - uchar u[] = {0x04, 0x24, 0x04, 0x07, 0x25, 0x00, 0x00, 0xd3,
449   - 0x18, 0xe0, 0x00, 0x00, 0x01, 0x64, 0x01, 0x64,
450   - 0x32};
451   - uchar stcd;
452   -
453   - printf("Hub: ");
454   -
455   - oldbus = I2C_GET_BUS();
456   - I2C_SET_BUS(1);
457   -
458   - for (reg = 0; reg < sizeof(u); reg++)
459   - if (i2c_write (IIC1_USB2507_ADDR, reg, 1, &u[reg], 1)) {
460   - ret = -1;
461   - break;
462   - }
463   -
464   - if (ret == 0) {
465   - stcd = 0x03;
466   - if (i2c_write (IIC1_USB2507_ADDR, 0, 1, &stcd, 1))
467   - ret = -1;
468   - }
469   -
470   - if (ret == 0)
471   - printf("initialized\n");
472   - else
473   - printf("failed - cannot initialize USB hub\n");
474   -
475   - I2C_SET_BUS(oldbus);
476   - return ret;
477   -}
478   -
479   -int do_hubinit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
480   -{
481   - usbhub_init();
482   - return 0;
483   -}
484   -U_BOOT_CMD(
485   - hubinit, 1, 1, do_hubinit,
486   - "Initialize USB hub",
487   - ""
488   -);
489   -
490   -#define CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS 3
491   -int boot_eeprom_write (unsigned dev_addr,
492   - unsigned offset,
493   - uchar *buffer,
494   - unsigned cnt)
495   -{
496   - unsigned end = offset + cnt;
497   - unsigned blk_off;
498   - int rcode = 0;
499   -
500   -#if defined(CONFIG_SYS_EEPROM_WREN)
501   - eeprom_write_enable(dev_addr, 1);
502   -#endif
503   - /*
504   - * Write data until done or would cross a write page boundary.
505   - * We must write the address again when changing pages
506   - * because the address counter only increments within a page.
507   - */
508   -
509   - while (offset < end) {
510   - unsigned alen, len;
511   - unsigned maxlen;
512   -
513   - uchar addr[2];
514   -
515   - blk_off = offset & 0xFF; /* block offset */
516   -
517   - addr[0] = offset >> 8; /* block number */
518   - addr[1] = blk_off; /* block offset */
519   - alen = 2;
520   - addr[0] |= dev_addr; /* insert device address */
521   -
522   - len = end - offset;
523   -
524   - /*
525   - * For a FRAM device there is no limit on the number of the
526   - * bytes that can be ccessed with the single read or write
527   - * operation.
528   - */
529   -#if defined(CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS)
530   -
531   -#define BOOT_EEPROM_PAGE_SIZE (1 << CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS)
532   -#define BOOT_EEPROM_PAGE_OFFSET(x) ((x) & (BOOT_EEPROM_PAGE_SIZE - 1))
533   -
534   - maxlen = BOOT_EEPROM_PAGE_SIZE -
535   - BOOT_EEPROM_PAGE_OFFSET(blk_off);
536   -#else
537   - maxlen = 0x100 - blk_off;
538   -#endif
539   - if (maxlen > I2C_RXTX_LEN)
540   - maxlen = I2C_RXTX_LEN;
541   -
542   - if (len > maxlen)
543   - len = maxlen;
544   -
545   - if (i2c_write (addr[0], offset, alen - 1, buffer, len) != 0)
546   - rcode = 1;
547   -
548   - buffer += len;
549   - offset += len;
550   -
551   -#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS)
552   - udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
553   -#endif
554   - }
555   -#if defined(CONFIG_SYS_EEPROM_WREN)
556   - eeprom_write_enable(dev_addr, 0);
557   -#endif
558   - return rcode;
559   -}
560   -
561   -int do_setup_boot_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
562   -{
563   - ulong sdsdp[4];
564   -
565   - if (argc > 1) {
566   - if (!strcmp(argv[1], "533")) {
567   - printf("Bootstrapping for 533MHz\n");
568   - sdsdp[0] = 0x87788252;
569   - /* PLB-PCI-divider = 3 : sync PCI clock=44MHz */
570   - sdsdp[1] = 0x095fa030;
571   - sdsdp[2] = 0x40082350;
572   - sdsdp[3] = 0x0d050000;
573   - } else if (!strcmp(argv[1], "533-66")) {
574   - printf("Bootstrapping for 533MHz (66MHz PCI)\n");
575   - sdsdp[0] = 0x87788252;
576   - /* PLB-PCI-divider = 2 : sync PCI clock=66MHz */
577   - sdsdp[1] = 0x0957a030;
578   - sdsdp[2] = 0x40082350;
579   - sdsdp[3] = 0x0d050000;
580   - } else if (!strcmp(argv[1], "667")) {
581   - printf("Bootstrapping for 667MHz\n");
582   - sdsdp[0] = 0x8778a256;
583   - /* PLB-PCI-divider = 4 : sync PCI clock=33MHz */
584   - sdsdp[1] = 0x0947a030;
585   - /* PLB-PCI-divider = 3 : sync PCI clock=44MHz
586   - * -> not working when overclocking 533MHz chips
587   - * -> untested on 667MHz chips */
588   - /* sdsdp[1]=0x095fa030; */
589   - sdsdp[2] = 0x40082350;
590   - sdsdp[3] = 0x0d050000;
591   - } else if (!strcmp(argv[1], "667-166")) {
592   - printf("Bootstrapping for 667-166MHz\n");
593   - sdsdp[0] = 0x8778a252;
594   - sdsdp[1] = 0x09d7a030;
595   - sdsdp[2] = 0x40082350;
596   - sdsdp[3] = 0x0d050000;
597   - }
598   - } else {
599   - printf("Bootstrapping for 533MHz (default)\n");
600   - sdsdp[0] = 0x87788252;
601   - /* PLB-PCI-divider = 3 : sync PCI clock=44MHz */
602   - sdsdp[1] = 0x095fa030;
603   - sdsdp[2] = 0x40082350;
604   - sdsdp[3] = 0x0d050000;
605   - }
606   -
607   - printf("Writing boot EEPROM ...\n");
608   - if (boot_eeprom_write(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR,
609   - 0, (uchar*)sdsdp, 16) != 0)
610   - printf("boot_eeprom_write failed\n");
611   - else
612   - printf("done (dump via 'i2c md 52 0.1 10')\n");
613   -
614   - return 0;
615   -}
616   -U_BOOT_CMD(
617   - sbe, 2, 0, do_setup_boot_eeprom,
618   - "setup boot eeprom",
619   - ""
620   -);
621   -
622   -#if defined(CONFIG_SYS_EEPROM_WREN)
623   -/*
624   - * Input: <dev_addr> I2C address of EEPROM device to enable.
625   - * <state> -1: deliver current state
626   - * 0: disable write
627   - * 1: enable write
628   - * Returns: -1: wrong device address
629   - * 0: dis-/en- able done
630   - * 0/1: current state if <state> was -1.
631   - */
632   -int eeprom_write_enable (unsigned dev_addr, int state)
633   -{
634   - if ((CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) &&
635   - (CONFIG_SYS_I2C_BOOT_EEPROM_ADDR != dev_addr))
636   - return -1;
637   - else {
638   - switch (state) {
639   - case 1:
640   - /* Enable write access, clear bit GPIO_SINT2. */
641   - out_be32((void*)GPIO0_OR,
642   - in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_GPIO0_EP_EEP);
643   - state = 0;
644   - break;
645   - case 0:
646   - /* Disable write access, set bit GPIO_SINT2. */
647   - out_be32((void*)GPIO0_OR,
648   - in_be32((void*)GPIO0_OR) | CONFIG_SYS_GPIO0_EP_EEP);
649   - state = 0;
650   - break;
651   - default:
652   - /* Read current status back. */
653   - state = (0 == (in_be32((void*)GPIO0_OR) &
654   - CONFIG_SYS_GPIO0_EP_EEP));
655   - break;
656   - }
657   - }
658   - return state;
659   -}
660   -
661   -int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
662   -{
663   - int query = argc == 1;
664   - int state = 0;
665   -
666   - if (query) {
667   - /* Query write access state. */
668   - state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, -1);
669   - if (state < 0)
670   - puts ("Query of write access state failed.\n");
671   - else {
672   - printf ("Write access for device 0x%0x is %sabled.\n",
673   - CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
674   - state = 0;
675   - }
676   - } else {
677   - if ('0' == argv[1][0]) {
678   - /* Disable write access. */
679   - state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 0);
680   - } else {
681   - /* Enable write access. */
682   - state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 1);
683   - }
684   - if (state < 0)
685   - puts ("Setup of write access state failed.\n");
686   - }
687   -
688   - return state;
689   -}
690   -
691   -U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
692   - "Enable / disable / query EEPROM write access",
693   - ""
694   -);
695   -#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
696   -
697   -static int got_pldirq;
698   -
699   -static int pld_interrupt(u32 arg)
700   -{
701   - int rc = -1; /* not for us */
702   - u8 status = in_8((void *)CONFIG_SYS_CPLD_BASE);
703   -
704   - /* check for PLD interrupt */
705   - if (status & PWR_INT_FLAG) {
706   - /* reset this int */
707   - out_8((void *)CONFIG_SYS_CPLD_BASE, 0);
708   - rc = 0;
709   - got_pldirq = 1; /* trigger backend */
710   - }
711   -
712   - return rc;
713   -}
714   -
715   -int do_waitpwrirq(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
716   -{
717   - got_pldirq = 0;
718   -
719   - /* clear any pending interrupt */
720   - out_8((void *)CONFIG_SYS_CPLD_BASE, 0);
721   -
722   - irq_install_handler(CPLD_IRQ,
723   - (interrupt_handler_t *)pld_interrupt, 0);
724   -
725   - printf("Waiting ...\n");
726   - while(!got_pldirq) {
727   - /* Abort if ctrl-c was pressed */
728   - if (ctrlc()) {
729   - puts("\nAbort\n");
730   - break;
731   - }
732   - }
733   - if (got_pldirq) {
734   - printf("Got interrupt!\n");
735   - printf("Power %sready!\n",
736   - in_8((void *)CONFIG_SYS_CPLD_BASE) &
737   - PWR_RDY ? "":"NOT ");
738   - }
739   -
740   - irq_free_handler(CPLD_IRQ);
741   - return 0;
742   -}
743   -U_BOOT_CMD(
744   - wpi, 1, 1, do_waitpwrirq,
745   - "Wait for power change interrupt",
746   - ""
747   -);
748   -
749   -/*
750   - * initialize DVI panellink transmitter
751   - */
752   -int dvi_init(void)
753   -{
754   - int i;
755   - int ret = 0;
756   - unsigned int oldbus;
757   - uchar u[] = {0x08, 0x34,
758   - 0x09, 0x20,
759   - 0x0a, 0x90,
760   - 0x0c, 0x89,
761   - 0x08, 0x35};
762   -
763   - printf("DVI: ");
764   -
765   - oldbus = I2C_GET_BUS();
766   - I2C_SET_BUS(0);
767   -
768   - for (i = 0; i < sizeof(u); i += 2)
769   - if (i2c_write (0x38, u[i], 1, &u[i + 1], 1)) {
770   - ret = -1;
771   - break;
772   - }
773   -
774   - if (ret == 0)
775   - printf("initialized\n");
776   - else
777   - printf("failed - cannot initialize DVI transmitter\n");
778   -
779   - I2C_SET_BUS(oldbus);
780   - return ret;
781   -}
782   -
783   -int do_dviinit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
784   -{
785   - dvi_init();
786   - return 0;
787   -}
788   -U_BOOT_CMD(
789   - dviinit, 1, 1, do_dviinit,
790   - "Initialize DVI Panellink transmitter",
791   - ""
792   -);
793   -
794   -/*
795   - * TODO: 'time' command might be useful for others as well.
796   - * Move to 'common' directory.
797   - */
798   -int do_time(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
799   -{
800   - unsigned long long start, end;
801   - char c, cmd[CONFIG_SYS_CBSIZE];
802   - char *p, *d = cmd;
803   - int ret, i;
804   - ulong us;
805   -
806   - for (i = 1; i < argc; i++) {
807   - p = argv[i];
808   -
809   - if (i > 1)
810   - *d++ = ' ';
811   -
812   - while ((c = *p++) != '\0') {
813   - *d++ = c;
814   - }
815   - }
816   - *d = '\0';
817   -
818   - start = get_ticks();
819   - ret = run_command(cmd, 0);
820   - end = get_ticks();
821   -
822   - printf("ticks=%ld\n", (ulong)(end - start));
823   - us = (ulong)((1000L * (end - start)) / (get_tbclk() / 1000));
824   - printf("usec=%ld\n", us);
825   -
826   - return ret;
827   -}
828   -U_BOOT_CMD(
829   - time, CONFIG_SYS_MAXARGS, 1, do_time,
830   - "run command and output execution time",
831   - ""
832   -);
833   -
834   -extern void video_hw_rectfill (
835   - unsigned int bpp, /* bytes per pixel */
836   - unsigned int dst_x, /* dest pos x */
837   - unsigned int dst_y, /* dest pos y */
838   - unsigned int dim_x, /* frame width */
839   - unsigned int dim_y, /* frame height */
840   - unsigned int color /* fill color */
841   - );
842   -
843   -/*
844   - * graphics demo
845   - * draw rectangles using pseudorandom number generator
846   - * (see http://www.embedded.com/columns/technicalinsights/20900500)
847   - */
848   -unsigned int rprime = 9972;
849   -static unsigned int r;
850   -static unsigned int Y;
851   -
852   -unsigned int prng(unsigned int max)
853   -{
854   - if (r == 0 || r == 1 || r == -1)
855   - r = rprime; /* keep from getting stuck */
856   -
857   - r = (9973 * ~r) + ((Y) % 701); /* the actual algorithm */
858   - Y = (r >> 16) % max; /* choose upper bits and reduce */
859   - return Y;
860   -}
861   -
862   -int do_gfxdemo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
863   -{
864   - unsigned int color;
865   - unsigned int x, y, dx, dy;
866   -
867   - while (!ctrlc()) {
868   - x = prng(1280 - 1);
869   - y = prng(1024 - 1);
870   - dx = prng(1280- x - 1);
871   - dy = prng(1024 - y - 1);
872   - color = prng(0x10000);
873   - video_hw_rectfill(2, x, y, dx, dy, color);
874   - }
875   -
876   - return 0;
877   -}
878   -U_BOOT_CMD(
879   - gfxdemo, CONFIG_SYS_MAXARGS, 1, do_gfxdemo,
880   - "demo",
881   - ""
882   -);
board/esd/du440/du440.h
View file @ 7ac9d47
1   -/*
2   - * (C) Copyright 2008
3   - * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -#define SDR0_USB0 0x0320 /* USB Control Register */
9   -
10   -#define CONFIG_SYS_GPIO0_EP_EEP (0x80000000 >> 23) /* GPIO0_23 */
11   -#define CONFIG_SYS_GPIO1_DCF77 (0x80000000 >> (42-32)) /* GPIO1_42 */
12   -
13   -#define CONFIG_SYS_GPIO1_IORSTN (0x80000000 >> (55-32)) /* GPIO1_55 */
14   -#define CONFIG_SYS_GPIO1_IORST2N (0x80000000 >> (47-32)) /* GPIO1_47 */
15   -
16   -#define CONFIG_SYS_GPIO1_HWVER_MASK 0x000000f0 /* GPIO1_56-59 */
17   -#define CONFIG_SYS_GPIO1_HWVER_SHIFT 4
18   -#define CONFIG_SYS_GPIO1_LEDUSR1 0x00000008 /* GPIO1_60 */
19   -#define CONFIG_SYS_GPIO1_LEDUSR2 0x00000004 /* GPIO1_61 */
20   -#define CONFIG_SYS_GPIO1_LEDPOST 0x00000002 /* GPIO1_62 */
21   -#define CONFIG_SYS_GPIO1_LEDDU 0x00000001 /* GPIO1_63 */
22   -
23   -#define CPLD_VERSION_MASK 0x0f
24   -#define PWR_INT_FLAG 0x80
25   -#define PWR_RDY 0x10
26   -
27   -#define CPLD_IRQ (32+30)
board/esd/du440/init.S
View file @ 7ac9d47
1   -/*
2   - * (C) Copyright 2008
3   - * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
4   - *
5   - * SPDX-License-Identifier: GPL-2.0+
6   - */
7   -
8   -#include <asm-offsets.h>
9   -#include <ppc_asm.tmpl>
10   -#include <asm/mmu.h>
11   -#include <config.h>
12   -
13   -/*
14   - * TLB TABLE
15   - *
16   - * This table is used by the cpu boot code to setup the initial tlb
17   - * entries. Rather than make broad assumptions in the cpu source tree,
18   - * this table lets each board set things up however they like.
19   - *
20   - * Pointer to the table is returned in r1
21   - */
22   - .section .bootpg,"ax"
23   - .globl tlbtab
24   -
25   -tlbtab:
26   - tlbtab_start
27   -
28   - /*
29   - * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
30   - * speed up boot process. It is patched after relocation to enable SA_I
31   - */
32   - tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_RWX | SA_G )
33   -
34   -#ifdef CONFIG_SYS_INIT_RAM_DCACHE
35   - /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
36   - tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_RWX | SA_G )
37   -#endif
38   -
39   - /* TLB-entry for PCI Memory */
40   - tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_RW | SA_IG )
41   - tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_RW | SA_IG )
42   - tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_RW | SA_IG )
43   - tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_RW | SA_IG )
44   -
45   - /* TLB-entry for PCI IO */
46   - tlbentry( CONFIG_SYS_PCI_IOBASE, SZ_64K, CONFIG_SYS_PCI_IOBASE, 1, AC_RW | SA_IG )
47   -
48   - /* TLB-entries for EBC: CPLD, DUMEM, DUIO */
49   - tlbentry( CONFIG_SYS_CPLD_BASE, SZ_1K, CONFIG_SYS_CPLD_BASE, 1, AC_RWX | SA_IG )
50   - tlbentry( CONFIG_SYS_DUMEM_BASE, SZ_1M, CONFIG_SYS_DUMEM_BASE, 1, AC_RWX | SA_IG )
51   - tlbentry( CONFIG_SYS_DUIO_BASE, SZ_64K, CONFIG_SYS_DUIO_BASE, 1, AC_RWX | SA_IG )
52   -
53   - /* TLB-entry for NAND */
54   - tlbentry( CONFIG_SYS_NAND0_ADDR, SZ_1K, CONFIG_SYS_NAND0_ADDR, 1, AC_RWX | SA_IG )
55   - tlbentry( CONFIG_SYS_NAND1_ADDR, SZ_1K, CONFIG_SYS_NAND1_ADDR, 1, AC_RWX | SA_IG )
56   -
57   - /* TLB-entry for Internal Registers & OCM */
58   - tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0, AC_RWX | SA_I )
59   -
60   - /* TLB-entry PCI registers */
61   - tlbentry( 0xEEC00000, SZ_1K, 0xEEC00000, 1, AC_RWX | SA_IG )
62   -
63   - /* TLB-entry for peripherals */
64   - tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_RWX | SA_IG)
65   -
66   - tlbtab_end
configs/DU440_defconfig
View file @ 7ac9d47
1   -CONFIG_PPC=y
2   -CONFIG_4xx=y
3   -CONFIG_TARGET_DU440=y
doc/README.scrapyard
Diff comments   View file @ 7ac9d47
... ... @@ -12,6 +12,7 @@
12 12  
13 13 Board Arch CPU Commit Removed Last known maintainer/contact
14 14 =================================================================================================
  15 +DU440 ppc4xx 440epx - - Matthias Fuchs <matthias.fuchs@esd.eu>
15 16 DU405 ppc4xx 405gpr - - Matthias Fuchs <matthias.fuchs@esd.eu>
16 17 DP405 ppc4xx 405ep - - Matthias Fuchs <matthias.fuchs@esd.eu>
17 18 CPCIISER4 ppc4xx 405gp - - Matthias Fuchs <matthias.fuchs@esd.eu>
include/configs/DU440.h
View file @ 7ac9d47
1   -/*
2   - * (C) Copyright 2008
3   - * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
4   - *
5   - * based on the Sequoia board configuration by
6   - * Stefan Roese, Jacqueline Pira-Ferriol and Alain Saurel
7   - *
8   - * SPDX-License-Identifier: GPL-2.0+
9   - */
10   -
11   -/*
12   - **********************************************************************
13   - * DU440.h - configuration for esd's DU440 board (Power PC440EPx)
14   - **********************************************************************
15   - */
16   -#ifndef __CONFIG_H
17   -#define __CONFIG_H
18   -
19   -/*
20   - * High Level Configuration Options
21   - */
22   -#define CONFIG_DU440 1 /* Board is esd DU440 */
23   -#define CONFIG_440EPX 1 /* Specific PPC440EPx */
24   -#define CONFIG_SYS_CLK_FREQ 33333400 /* external freq to pll */
25   -
26   -#ifndef CONFIG_SYS_TEXT_BASE
27   -#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
28   -#endif
29   -
30   -#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
31   -#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
32   -#define CONFIG_LAST_STAGE_INIT 1 /* last_stage_init */
33   -
34   -/*
35   - * Base addresses -- Note these are effective addresses where the
36   - * actual resources get mapped (not physical addresses)
37   - */
38   -#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */
39   -#define CONFIG_SYS_MALLOC_LEN (8 << 20) /* Reserve 8 MB for malloc() */
40   -
41   -#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
42   -#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
43   -#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */
44   -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
45   -#define CONFIG_SYS_NAND0_ADDR 0xd0000000 /* NAND Flash */
46   -#define CONFIG_SYS_NAND1_ADDR 0xd0100000 /* NAND Flash */
47   -#define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
48   -#define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */
49   -#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
50   -#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000
51   -#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
52   -#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
53   -#define CONFIG_SYS_PCI_IOBASE 0xe8000000
54   -#define CONFIG_SYS_PCI_SUBSYS_VENDORID PCI_VENDOR_ID_ESDGMBH
55   -#define CONFIG_SYS_PCI_SUBSYS_ID 0x0444 /* device ID for DU440 */
56   -
57   -#define CONFIG_SYS_USB2D0_BASE 0xe0000100
58   -#define CONFIG_SYS_USB_DEVICE 0xe0000000
59   -#define CONFIG_SYS_USB_HOST 0xe0000400
60   -
61   -/*
62   - * Initial RAM & stack pointer
63   - */
64   -/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */
65   -#define CONFIG_SYS_INIT_RAM_OCM 1 /* OCM as init ram */
66   -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
67   -
68   -#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
69   -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
70   -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
71   -
72   -/*
73   - * Serial Port
74   - */
75   -#define CONFIG_CONS_INDEX 1 /* Use UART0 */
76   -#define CONFIG_SYS_NS16550
77   -#define CONFIG_SYS_NS16550_SERIAL
78   -#define CONFIG_SYS_NS16550_REG_SIZE 1
79   -#define CONFIG_SYS_NS16550_CLK get_serial_clock()
80   -#undef CONFIG_SYS_EXT_SERIAL_CLOCK
81   -#define CONFIG_BAUDRATE 115200
82   -
83   -#define CONFIG_SYS_BAUDRATE_TABLE \
84   - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
85   -
86   -/*
87   - * Video Port
88   - */
89   -#define CONFIG_VIDEO
90   -#define CONFIG_VIDEO_SMI_LYNXEM
91   -#define CONFIG_CFB_CONSOLE
92   -#define CONFIG_VIDEO_LOGO
93   -#define CONFIG_VGA_AS_SINGLE_DEVICE
94   -#define CONFIG_SPLASH_SCREEN
95   -#define CONFIG_SPLASH_SCREEN_ALIGN
96   -#define CONFIG_VIDEO_BMP_GZIP /* gzip compressed bmp images */
97   -#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (4 << 20) /* for decompressed img */
98   -#define CONFIG_SYS_DEFAULT_VIDEO_MODE 0x31a /* 1280x1024,16bpp */
99   -#define CONFIG_SYS_CONSOLE_IS_IN_ENV
100   -#define CONFIG_SYS_ISA_IO CONFIG_SYS_PCI_IOBASE
101   -
102   -/*
103   - * Environment
104   - */
105   -#define CONFIG_ENV_IS_IN_EEPROM 1 /* use FLASH for environment vars */
106   -
107   -/*
108   - * FLASH related
109   - */
110   -#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
111   -#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
112   -
113   -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
114   -
115   -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
116   -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
117   -
118   -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
119   -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
120   -
121   -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
122   -/* CFI_FLASH_PROTECTION make flash_protect hang sometimes -> disabled */
123   -#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */
124   -
125   -#define CONFIG_SYS_FLASH_EMPTY_INFO
126   -#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
127   -
128   -#ifdef CONFIG_ENV_IS_IN_FLASH
129   -#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
130   -#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
131   -#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
132   -
133   -/* Address and size of Redundant Environment Sector */
134   -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
135   -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
136   -#endif
137   -
138   -#ifdef CONFIG_ENV_IS_IN_EEPROM
139   -#define CONFIG_ENV_OFFSET 0 /* environment starts at */
140   - /* the beginning of the EEPROM */
141   -#define CONFIG_ENV_SIZE 0x1000 /* 4096 bytes may be used for env vars */
142   -#endif
143   -
144   -/*
145   - * DDR SDRAM
146   - */
147   -#define CONFIG_SYS_MBYTES_SDRAM (1024) /* 512 MiB TODO: remove */
148   -#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
149   -#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes */
150   - /* 440EPx errata CHIP 11 */
151   -#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */
152   -#define CONFIG_DDR_ECC /* Use ECC when available */
153   -#define SPD_EEPROM_ADDRESS {0x50}
154   -#define CONFIG_PROG_SDRAM_TLB
155   -
156   -/*
157   - * I2C
158   - */
159   -#define CONFIG_SYS_I2C
160   -#define CONFIG_SYS_I2C_PPC4XX
161   -#define CONFIG_SYS_I2C_PPC4XX_CH0
162   -#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
163   -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
164   -#define CONFIG_SYS_I2C_PPC4XX_CH1
165   -#define CONFIG_SYS_I2C_PPC4XX_SPEED_1 100000
166   -#define CONFIG_SYS_I2C_PPC4XX_SLAVE_1 0x7F
167   -
168   -#define CONFIG_SYS_SPD_BUS_NUM 0
169   -#define IIC1_MCP3021_ADDR 0x4d
170   -#define IIC1_USB2507_ADDR 0x2c
171   -#define CONFIG_SYS_I2C_NOPROBES { {1, IIC1_USB2507_ADDR} }
172   -
173   -#define CONFIG_SYS_I2C_MULTI_EEPROMS
174   -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
175   -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
176   -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
177   -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
178   -#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01
179   -
180   -#define CONFIG_SYS_EEPROM_WREN 1
181   -#define CONFIG_SYS_I2C_BOOT_EEPROM_ADDR 0x52
182   -
183   -/*
184   - * standard dtt sensor configuration - bottom bit will determine local or
185   - * remote sensor of the TMP401
186   - */
187   -#define CONFIG_DTT_SENSORS { 0, 1 }
188   -
189   -/*
190   - * The PMC440 uses a TI TMP401 temperature sensor. This part
191   - * is basically compatible to the ADM1021 that is supported
192   - * by U-Boot.
193   - *
194   - * - i2c addr 0x4c
195   - * - conversion rate 0x02 = 0.25 conversions/second
196   - * - ALERT ouput disabled
197   - * - local temp sensor enabled, min set to 0 deg, max set to 70 deg
198   - * - remote temp sensor enabled, min set to 0 deg, max set to 70 deg
199   - */
200   -#define CONFIG_DTT_ADM1021
201   -#define CONFIG_SYS_DTT_ADM1021 { { 0x4c, 0x02, 0, 1, 70, 0, 1, 70, 0} }
202   -
203   -/*
204   - * RTC stuff
205   - */
206   -#define CONFIG_RTC_DS1338
207   -#define CONFIG_SYS_I2C_RTC_ADDR 0x68
208   -
209   -#undef CONFIG_BOOTARGS
210   -
211   -#define CONFIG_EXTRA_ENV_SETTINGS \
212   - "netdev=eth0\0" \
213   - "ethrotate=no\0" \
214   - "hostname=du440\0" \
215   - "nfsargs=setenv bootargs root=/dev/nfs rw " \
216   - "nfsroot=${serverip}:${rootpath}\0" \
217   - "ramargs=setenv bootargs root=/dev/ram rw\0" \
218   - "addip=setenv bootargs ${bootargs} " \
219   - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
220   - ":${hostname}:${netdev}:off panic=1\0" \
221   - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
222   - "flash_self=run ramargs addip addtty optargs;" \
223   - "bootm ${kernel_addr} ${ramdisk_addr}\0" \
224   - "net_nfs=tftp 200000 ${img};run nfsargs addip addtty optargs;" \
225   - "bootm\0" \
226   - "rootpath=/tftpboot/du440/target_root_du440\0" \
227   - "img=/tftpboot/du440/uImage\0" \
228   - "kernel_addr=FFC00000\0" \
229   - "ramdisk_addr=FFE00000\0" \
230   - "initrd_high=30000000\0" \
231   - "load=tftp 100000 /tftpboot/du440/u-boot.bin\0" \
232   - "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \
233   - "cp.b 100000 FFFA0000 60000\0" \
234   - ""
235   -
236   -#define CONFIG_PREBOOT /* enable preboot variable */
237   -
238   -#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
239   -
240   -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
241   -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
242   -
243   -#ifndef __ASSEMBLY__
244   -int du440_phy_addr(int devnum);
245   -#endif
246   -
247   -#define CONFIG_PPC4xx_EMAC
248   -#define CONFIG_IBM_EMAC4_V4 1
249   -#define CONFIG_MII 1 /* MII PHY management */
250   -#define CONFIG_PHY_ADDR du440_phy_addr(0) /* PHY address */
251   -
252   -#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
253   -#undef CONFIG_PHY_GIGE /* no GbE detection */
254   -
255   -#define CONFIG_HAS_ETH0
256   -#define CONFIG_SYS_RX_ETH_BUFFER 128
257   -
258   -#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
259   -#define CONFIG_PHY1_ADDR du440_phy_addr(1)
260   -
261   -/*
262   - * USB
263   - */
264   -#define CONFIG_USB_OHCI_NEW
265   -#define CONFIG_USB_STORAGE
266   -#define CONFIG_SYS_OHCI_BE_CONTROLLER
267   -
268   -#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
269   -#define CONFIG_SYS_USB_OHCI_REGS_BASE CONFIG_SYS_USB_HOST
270   -#define CONFIG_SYS_USB_OHCI_SLOT_NAME "du440"
271   -#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
272   -
273   -/* Comment this out to enable USB 1.1 device */
274   -#define USB_2_0_DEVICE
275   -
276   -/* Partitions */
277   -#define CONFIG_MAC_PARTITION
278   -#define CONFIG_DOS_PARTITION
279   -#define CONFIG_ISO_PARTITION
280   -
281   -#include <config_cmd_default.h>
282   -
283   -#define CONFIG_CMD_ASKENV
284   -#define CONFIG_CMD_BMP
285   -#define CONFIG_CMD_BSP
286   -#define CONFIG_CMD_DATE
287   -#define CONFIG_CMD_DHCP
288   -#define CONFIG_CMD_DIAG
289   -#define CONFIG_CMD_DTT
290   -#define CONFIG_CMD_EEPROM
291   -#define CONFIG_CMD_ELF
292   -#define CONFIG_CMD_FAT
293   -#define CONFIG_CMD_I2C
294   -#define CONFIG_CMD_IRQ
295   -#define CONFIG_CMD_MII
296   -#define CONFIG_CMD_NAND
297   -#define CONFIG_CMD_NET
298   -#define CONFIG_CMD_NFS
299   -#define CONFIG_CMD_PCI
300   -#define CONFIG_CMD_PING
301   -#define CONFIG_CMD_REGINFO
302   -#define CONFIG_CMD_SDRAM
303   -#define CONFIG_CMD_SOURCE
304   -#define CONFIG_CMD_USB
305   -
306   -#define CONFIG_SUPPORT_VFAT
307   -
308   -/*
309   - * Miscellaneous configurable options
310   - */
311   -#define CONFIG_SYS_LONGHELP /* undef to save memory */
312   -#if defined(CONFIG_CMD_KGDB)
313   -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
314   -#else
315   -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
316   -#endif
317   -/* Print Buffer Size */
318   -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
319   -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
320   -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
321   -
322   -#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
323   -#define CONFIG_SYS_MEMTEST_END 0x3f000000 /* 4 ... < 1GB DRAM */
324   -
325   -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
326   -#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
327   -
328   -#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
329   -#define CONFIG_LOOPW 1 /* enable loopw command */
330   -#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
331   -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
332   -#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
333   -
334   -#define CONFIG_AUTOBOOT_KEYED 1
335   -#define CONFIG_AUTOBOOT_PROMPT \
336   - "Press SPACE to abort autoboot in %d seconds\n", bootdelay
337   -#define CONFIG_AUTOBOOT_DELAY_STR "d"
338   -#define CONFIG_AUTOBOOT_STOP_STR " "
339   -
340   -/*
341   - * PCI stuff
342   - */
343   -#define CONFIG_PCI /* include pci support */
344   -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
345   -#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */
346   -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
347   -#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/
348   -
349   -/* Board-specific PCI */
350   -#define CONFIG_SYS_PCI_TARGET_INIT
351   -#define CONFIG_SYS_PCI_MASTER_INIT
352   -
353   -/*
354   - * For booting Linux, the board info and command line data
355   - * have to be in the first 8 MB of memory, since this is
356   - * the maximum mapped by the Linux kernel during initialization.
357   - */
358   -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
359   -
360   -/*
361   - * External Bus Controller (EBC) Setup
362   - */
363   -#define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE
364   -
365   -#define CONFIG_SYS_CPLD_BASE 0xC0000000
366   -#define CONFIG_SYS_CPLD_RANGE 0x00000010
367   -#define CONFIG_SYS_DUMEM_BASE 0xC0100000
368   -#define CONFIG_SYS_DUMEM_RANGE 0x00100000
369   -#define CONFIG_SYS_DUIO_BASE 0xC0200000
370   -#define CONFIG_SYS_DUIO_RANGE 0x00010000
371   -
372   -#define CONFIG_SYS_NAND0_CS 2 /* NAND chip connected to CSx */
373   -#define CONFIG_SYS_NAND1_CS 3 /* NAND chip connected to CSx */
374   -/* Memory Bank 0 (NOR-FLASH) initialization */
375   -#define CONFIG_SYS_EBC_PB0AP 0x04017200
376   -#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH_BASE | 0xda000)
377   -
378   -/* Memory Bank 1 (CPLD, 16 bytes needed, but 1MB is minimum) */
379   -#define CONFIG_SYS_EBC_PB1AP 0x018003c0
380   -#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_CPLD_BASE | 0x18000)
381   -
382   -/* Memory Bank 2 (NAND-FLASH) initialization */
383   -#define CONFIG_SYS_EBC_PB2AP 0x018003c0
384   -#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_NAND0_ADDR | 0x1c000)
385   -
386   -/* Memory Bank 3 (NAND-FLASH) initialization */
387   -#define CONFIG_SYS_EBC_PB3AP 0x018003c0
388   -#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_NAND1_ADDR | 0x1c000)
389   -
390   -/* Memory Bank 4 (DUMEM, 1MB) initialization */
391   -#define CONFIG_SYS_EBC_PB4AP 0x018053c0
392   -#define CONFIG_SYS_EBC_PB4CR (CONFIG_SYS_DUMEM_BASE | 0x18000)
393   -
394   -/* Memory Bank 5 (DUIO, 64KB needed, but 1MB is minimum) */
395   -#define CONFIG_SYS_EBC_PB5AP 0x018053c0
396   -#define CONFIG_SYS_EBC_PB5CR (CONFIG_SYS_DUIO_BASE | 0x18000)
397   -
398   -/*
399   - * NAND FLASH
400   - */
401   -#define CONFIG_SYS_MAX_NAND_DEVICE 2
402   -#define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
403   -#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND0_ADDR + CONFIG_SYS_NAND0_CS, \
404   - CONFIG_SYS_NAND1_ADDR + CONFIG_SYS_NAND1_CS}
405   -
406   -#if defined(CONFIG_CMD_KGDB)
407   -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
408   -#endif
409   -
410   -#define CONFIG_SOURCE 1
411   -
412   -#define CONFIG_OF_LIBFDT
413   -#define CONFIG_OF_BOARD_SETUP
414   -
415   -#endif /* __CONFIG_H */