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Commit 7b5b9343139f934f1ce876e9466c065f20c8265c

Authored by Anatolij Gustschin
Committed by Stefano Babic
1 parent 88366b96ee
Exists in smarc_8mq_lf_v2020.04 and in 9 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

imx: add imx8x capricorn giedi board 

Add support for i.MX8X based Capricorn Giedi SoM.

Supported interfaces: GPIO, ENET, eMMC, I2C, UART.

Console output:

  U-Boot SPL 2020.01-00003-gfd1c98f (Jan 07 2020 - 15:51:25 +0100)
  Trying to boot from MMC1
  Load image from MMC/SD 0x3e400

  U-Boot 2020.01-00003-gfd1c98f (Jan 07 2020 - 15:51:25 +0100) ##v01.07

  CPU:   NXP i.MX8QXP RevB A35 at 1200 MHz at 30C

  Model: Siemens Giedi
  Board: Capricorn
  Boot:  MMC0
  DRAM:  1022 MiB
  MMC:   FSL_SDHC: 0
  Loading Environment from MMC... OK
  In:    serial@5a080000
  Out:   serial@5a080000
  Err:   serial@5a080000
  Net:   eth1: ethernet@5b050000 [PRIME]
  Autobooting in 1 seconds, press "<Esc><Esc>" to stop

Signed-off-by: Anatolij Gustschin <agust@denx.de>

Showing 18 changed files with 1528 additions and 1 deletions Side-by-side Diff

arch/arm/dts/Makefile
Diff comments   View file @ 7b5b934
... ... @@ -699,7 +699,8 @@
699 699 imx8qm-rom7720-a1.dtb \
700 700 fsl-imx8qxp-ai_ml.dtb \
701 701 fsl-imx8qxp-colibri.dtb \
702   - fsl-imx8qxp-mek.dtb
  702 + fsl-imx8qxp-mek.dtb \
  703 + imx8-giedi.dtb
703 704  
704 705 dtb-$(CONFIG_ARCH_IMX8M) += \
705 706 imx8mm-evk.dtb \
arch/arm/dts/imx8-giedi.dts
Diff comments   View file @ 7b5b934
  1 +// SPDX-License-Identifier: GPL-2.0+
  2 +/*
  3 + * Copyright 2019 Siemens AG
  4 + */
  5 +
  6 +#include "imx8qxp-capricorn.dtsi"
  7 +
  8 +/ {
  9 + model = "Siemens Giedi";
  10 +};
arch/arm/dts/imx8qxp-capricorn-u-boot.dtsi
Diff comments   View file @ 7b5b934
  1 +// SPDX-License-Identifier: GPL-2.0+
  2 +/*
  3 + * Copyright 2019 Siemens AG
  4 + */
  5 +
  6 +&{/imx8qx-pm} {
  7 +
  8 + u-boot,dm-spl;
  9 +};
  10 +
  11 +&mu {
  12 + u-boot,dm-spl;
  13 +};
  14 +
  15 +&clk {
  16 + u-boot,dm-spl;
  17 +};
  18 +
  19 +&iomuxc {
  20 + u-boot,dm-spl;
  21 +};
  22 +
  23 +&pd_lsio {
  24 + u-boot,dm-spl;
  25 +};
  26 +
  27 +&pd_lsio_gpio0 {
  28 + u-boot,dm-spl;
  29 +};
  30 +
  31 +&pd_lsio_gpio1 {
  32 + u-boot,dm-spl;
  33 +};
  34 +
  35 +&pd_lsio_gpio2 {
  36 + u-boot,dm-spl;
  37 +};
  38 +
  39 +&pd_lsio_gpio3 {
  40 + u-boot,dm-spl;
  41 +};
  42 +
  43 +&pd_lsio_gpio4 {
  44 + u-boot,dm-spl;
  45 +};
  46 +
  47 +&pd_lsio_gpio5 {
  48 + u-boot,dm-spl;
  49 +};
  50 +
  51 +&pd_lsio_gpio6 {
  52 + u-boot,dm-spl;
  53 +};
  54 +
  55 +&pd_lsio_gpio7 {
  56 + u-boot,dm-spl;
  57 +};
  58 +
  59 +&pd_dma {
  60 + u-boot,dm-spl;
  61 +};
  62 +
  63 +&pd_dma_lpuart0 {
  64 + u-boot,dm-spl;
  65 +};
  66 +
  67 +&pd_dma_lpuart2 {
  68 + u-boot,dm-spl;
  69 +};
  70 +
  71 +&pd_conn {
  72 + u-boot,dm-spl;
  73 +};
  74 +
  75 +&pd_conn_sdch0 {
  76 + u-boot,dm-spl;
  77 +};
  78 +
  79 +&pd_conn_sdch1 {
  80 + u-boot,dm-spl;
  81 +};
  82 +
  83 +&pd_conn_sdch2 {
  84 + u-boot,dm-spl;
  85 +};
  86 +
  87 +&gpio0 {
  88 + u-boot,dm-spl;
  89 +};
  90 +
  91 +&gpio1 {
  92 + u-boot,dm-spl;
  93 +};
  94 +
  95 +&gpio2 {
  96 + u-boot,dm-spl;
  97 +};
  98 +
  99 +&gpio3 {
  100 + u-boot,dm-spl;
  101 +};
  102 +
  103 +&gpio4 {
  104 + u-boot,dm-spl;
  105 +};
  106 +
  107 +&gpio5 {
  108 + u-boot,dm-spl;
  109 +};
  110 +
  111 +&gpio6 {
  112 + u-boot,dm-spl;
  113 +};
  114 +
  115 +&gpio7 {
  116 + u-boot,dm-spl;
  117 +};
  118 +
  119 +&lpuart0 {
  120 + u-boot,dm-spl;
  121 +};
  122 +
  123 +&lpuart2 {
  124 + u-boot,dm-spl;
  125 +};
  126 +
  127 +&usdhc1 {
  128 + u-boot,dm-spl;
  129 +};
  130 +
  131 +&usdhc2 {
  132 + u-boot,dm-spl;
  133 +};
arch/arm/dts/imx8qxp-capricorn.dtsi
Diff comments   View file @ 7b5b934
  1 +// SPDX-License-Identifier: GPL-2.0+
  2 +/*
  3 + * Copyright 2017 NXP
  4 + *
  5 + * Copyright 2019 Siemens AG
  6 + *
  7 + */
  8 +
  9 +/dts-v1/;
  10 +
  11 +#include "fsl-imx8qxp.dtsi"
  12 +#include "imx8qxp-capricorn-u-boot.dtsi"
  13 +
  14 +/ {
  15 + model = "Siemens Giedi";
  16 + compatible = "siemens,capricorn", "fsl,imx8qxp";
  17 +
  18 + chosen {
  19 + bootargs = "console=ttyLP2,115200 earlycon=lpuart32,0x5a080000,115200";
  20 + stdout-path = &lpuart2;
  21 + };
  22 +
  23 + leds {
  24 + compatible = "gpio-leds";
  25 + pinctrl-names = "default";
  26 + pinctrl-0 = <&pinctrl_gpio_leds>;
  27 +
  28 + run {
  29 + label = "run";
  30 + gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>;
  31 + default-state = "on";
  32 + };
  33 +
  34 + flt {
  35 + label = "flt";
  36 + gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
  37 + default-state = "on";
  38 + };
  39 +
  40 + svc {
  41 + label = "svc";
  42 + gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
  43 + default-state = "on";
  44 + };
  45 +
  46 + com1_tx {
  47 + label = "com1-tx";
  48 + gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
  49 + default-state = "on";
  50 + };
  51 +
  52 + com1_rx {
  53 + label = "com1-rx";
  54 + gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
  55 + default-state = "on";
  56 + };
  57 +
  58 + com2_tx {
  59 + label = "com2-tx";
  60 + gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>;
  61 + default-state = "on";
  62 + };
  63 +
  64 + com2_rx {
  65 + label = "com2-rx";
  66 + gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>;
  67 + default-state = "on";
  68 + };
  69 +
  70 + cloud {
  71 + label = "cloud";
  72 + gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
  73 + default-state = "on";
  74 + };
  75 +
  76 + wlan {
  77 + label = "wlan";
  78 + gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
  79 + default-state = "on";
  80 + };
  81 +
  82 + dbg1 {
  83 + label = "dbg1";
  84 + gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
  85 + default-state = "on";
  86 + };
  87 +
  88 + dbg2 {
  89 + label = "dbg2";
  90 + gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>;
  91 + default-state = "on";
  92 + };
  93 +
  94 + dbg3 {
  95 + label = "dbg3";
  96 + gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>;
  97 + default-state = "on";
  98 + };
  99 +
  100 + dbg4 {
  101 + label = "dbg4";
  102 + gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
  103 + default-state = "on";
  104 + };
  105 + };
  106 +};
  107 +
  108 +&iomuxc {
  109 + pinctrl-names = "default";
  110 +
  111 + muxcgrp: imx8qxp-som {
  112 + pinctrl_gpio_leds: gpioledsgrp {
  113 + fsl,pins = <
  114 + SC_P_ESAI0_FST_LSIO_GPIO0_IO01 0x06000021
  115 + SC_P_ESAI0_TX0_LSIO_GPIO0_IO04 0x06000021
  116 + SC_P_SAI0_TXC_LSIO_GPIO0_IO26 0x06000021
  117 + SC_P_SAI1_RXD_LSIO_GPIO0_IO29 0x06000021
  118 + SC_P_FLEXCAN1_RX_LSIO_GPIO1_IO17 0x06000021
  119 + SC_P_FLEXCAN1_TX_LSIO_GPIO1_IO18 0x06000021
  120 + SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17 0x06000021
  121 + SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x06000021
  122 + SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19 0x06000021
  123 + SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000021
  124 + SC_P_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x06000021
  125 + SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x06000021
  126 + SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x06000021
  127 + >;
  128 + };
  129 +
  130 + pinctrl_lpi2c0: lpi2c0grp {
  131 + fsl,pins = <
  132 + SC_P_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL 0x0C000020
  133 + SC_P_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA 0x0C000020
  134 + >;
  135 + };
  136 +
  137 + pinctrl_lpi2c1: lpi2c1grp {
  138 + fsl,pins = <
  139 + SC_P_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL 0x0C000020
  140 + SC_P_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA 0x0C000020
  141 + >;
  142 + };
  143 +
  144 + pinctrl_lpuart2: lpuart2grp {
  145 + fsl,pins = <
  146 + SC_P_UART2_RX_ADMA_UART2_RX 0x06000020
  147 + SC_P_UART2_TX_ADMA_UART2_TX 0x06000020
  148 + >;
  149 + };
  150 +
  151 + pinctrl_usdhc1: usdhc1grp {
  152 + fsl,pins = <
  153 + SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
  154 + SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
  155 + SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
  156 + SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
  157 + SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
  158 + SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
  159 + SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
  160 + SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
  161 + SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
  162 + SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
  163 + SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041
  164 + SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
  165 + SC_P_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 0x06000021
  166 + >;
  167 + };
  168 +
  169 + pinctrl_usdhc2: usdhc2grp {
  170 + fsl,pins = <
  171 + SC_P_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041
  172 + SC_P_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021
  173 + SC_P_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021
  174 + SC_P_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021
  175 + SC_P_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021
  176 + SC_P_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021
  177 + SC_P_ENET0_RGMII_TXD2_CONN_USDHC1_CD_B 0x06000021
  178 + //SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x06000021
  179 + SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x06000021
  180 + >;
  181 + };
  182 +
  183 + pinctrl_fec2: fec2grp {
  184 + fsl,pins = <
  185 + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0
  186 + SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0
  187 + SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0
  188 +
  189 + SC_P_ENET0_MDC_CONN_ENET1_MDC 0x00000060
  190 + SC_P_ENET0_MDIO_CONN_ENET1_MDIO 0x00000060
  191 +
  192 + SC_P_ESAI0_FSR_CONN_ENET1_RCLK50M_IN 0x00000060
  193 + SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x00000060
  194 + SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x00000060
  195 + SC_P_ESAI0_TX2_RX3_CONN_ENET1_RMII_RX_ER 0x00000060
  196 + SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x00000060
  197 + SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x00000060
  198 + SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x00000060
  199 + SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x00000060 /* ERST: Reset pin */
  200 + >;
  201 + };
  202 + };
  203 +};
  204 +
  205 +&i2c0 {
  206 + clock-frequency = <100000>;
  207 + pinctrl-names = "default";
  208 + pinctrl-0 = <&pinctrl_lpi2c0>;
  209 + status = "okay";
  210 +};
  211 +
  212 +&i2c1 {
  213 + clock-frequency = <100000>;
  214 + pinctrl-names = "default";
  215 + pinctrl-0 = <&pinctrl_lpi2c1>;
  216 + status = "okay";
  217 +};
  218 +
  219 +&lpuart2 {
  220 + pinctrl-names = "default";
  221 + pinctrl-0 = <&pinctrl_lpuart2>;
  222 + status = "okay";
  223 +};
  224 +
  225 +&usdhc1 {
  226 + pinctrl-names = "default";
  227 + pinctrl-0 = <&pinctrl_usdhc1>;
  228 + clock-frequency=<52000000>;
  229 + no-1-8-v;
  230 + bus-width = <8>;
  231 + non-removable;
  232 + status = "okay";
  233 +};
  234 +
  235 +&gpio0 {
  236 + status = "okay";
  237 +};
  238 +
  239 +&gpio1 {
  240 + status = "okay";
  241 +};
  242 +
  243 +&gpio2 {
  244 + status = "okay";
  245 +};
  246 +
  247 +&gpio3 {
  248 + status = "okay";
  249 +};
  250 +
  251 +&gpio4 {
  252 + status = "okay";
  253 +};
  254 +
  255 +&gpio5 {
  256 + status = "okay";
  257 +};
  258 +
  259 +&fec1 {
  260 + status ="disabled";
  261 +};
  262 +
  263 +&fec2 {
  264 + pinctrl-names = "default";
  265 + pinctrl-0 = <&pinctrl_fec2>;
  266 + phy-mode = "rmii";
  267 +
  268 + phy-handle = <&ethphy1>;
  269 + fsl,magic-packet;
  270 + status = "okay";
  271 +
  272 + mdio {
  273 + #address-cells = <1>;
  274 + #size-cells = <0>;
  275 +
  276 + ethphy0: ethernet-phy@0 {
  277 + compatible = "ethernet-phy-ieee802.3-c22";
  278 + reg = <0>;
  279 + };
  280 + ethphy1: ethernet-phy@1 {
  281 + compatible = "ethernet-phy-ieee802.3-c22";
  282 + reg = <1>;
  283 + };
  284 + };
  285 +};
arch/arm/mach-imx/imx8/Kconfig
Diff comments   View file @ 7b5b934
... ... @@ -55,6 +55,11 @@
55 55 select BOARD_LATE_INIT
56 56 select IMX8QXP
57 57  
  58 +config TARGET_GIEDI
  59 + bool "Support i.MX8QXP Capricorn Giedi board"
  60 + select BOARD_LATE_INIT
  61 + select IMX8QXP
  62 +
58 63 config TARGET_IMX8QM_MEK
59 64 bool "Support i.MX8QM MEK board"
60 65 select BOARD_LATE_INIT
... ... @@ -78,6 +83,7 @@
78 83 source "board/advantech/imx8qm_rom7720_a1/Kconfig"
79 84 source "board/toradex/apalis-imx8/Kconfig"
80 85 source "board/toradex/colibri-imx8x/Kconfig"
  86 +source "board/siemens/capricorn/Kconfig"
81 87  
82 88 endif
board/siemens/capricorn/Kconfig
Diff comments   View file @ 7b5b934
  1 +if TARGET_GIEDI
  2 +
  3 +config SYS_BOARD
  4 + default "capricorn"
  5 +
  6 +config SYS_VENDOR
  7 + default "siemens"
  8 +
  9 +config SYS_CONFIG_NAME
  10 + default "giedi"
  11 +
  12 +endif
board/siemens/capricorn/MAINTAINERS
Diff comments   View file @ 7b5b934
  1 +CAPRICORN BOARD
  2 +M: Anatolij Gustschin <agust@denx.de>
  3 +S: Maintained
  4 +F: board/siemens/capricorn/
  5 +F: include/configs/capricorn-common.h
  6 +F: include/configs/giedi.h
  7 +F: include/configs/siemens-ccp-common.h
  8 +F: include/configs/siemens-env-common.h
  9 +F: configs/giedi_defconfig
board/siemens/capricorn/Makefile
Diff comments   View file @ 7b5b934
  1 +# SPDX-License-Identifier: GPL-2.0+
  2 +#
  3 +# Copyright 2019 Siemens AG
  4 +#
  5 +
  6 +obj-y += board.o
  7 +
  8 +ifdef CONFIG_SPL_BUILD
  9 +obj-y += spl.o
  10 +else
  11 +obj-y += ../common/factoryset.o
  12 +endif
board/siemens/capricorn/board.c
Diff comments   View file @ 7b5b934
  1 +// SPDX-License-Identifier: GPL-2.0+
  2 +/*
  3 + * Copyright 2017-2019 NXP
  4 + *
  5 + * Copyright 2019 Siemens AG
  6 + *
  7 + */
  8 +#include <common.h>
  9 +#include <dm.h>
  10 +#include <errno.h>
  11 +#include <netdev.h>
  12 +#include <env_internal.h>
  13 +#include <fsl_esdhc_imx.h>
  14 +#include <i2c.h>
  15 +#include <led.h>
  16 +#include <pca953x.h>
  17 +#include <power-domain.h>
  18 +#include <asm/gpio.h>
  19 +#include <asm/arch/imx8-pins.h>
  20 +#include <asm/arch/iomux.h>
  21 +#include <asm/arch/sci/sci.h>
  22 +#include <asm/arch/sys_proto.h>
  23 +#ifndef CONFIG_SPL
  24 +#include <asm/arch-imx8/clock.h>
  25 +#endif
  26 +#include "../common/factoryset.h"
  27 +
  28 +#define GPIO_PAD_CTRL \
  29 + ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
  30 + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
  31 + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
  32 + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
  33 +
  34 +#define ENET_NORMAL_PAD_CTRL \
  35 + ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
  36 + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
  37 + (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \
  38 + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
  39 +
  40 +#define UART_PAD_CTRL \
  41 + ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
  42 + (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
  43 + (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
  44 + (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
  45 +
  46 +static iomux_cfg_t uart2_pads[] = {
  47 + SC_P_UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  48 + SC_P_UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  49 +};
  50 +
  51 +static void setup_iomux_uart(void)
  52 +{
  53 + imx8_iomux_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
  54 +}
  55 +
  56 +int board_early_init_f(void)
  57 +{
  58 + /* Set UART clock root to 80 MHz */
  59 + sc_pm_clock_rate_t rate = SC_80MHZ;
  60 + int ret;
  61 +
  62 + ret = sc_pm_setup_uart(SC_R_UART_0, rate);
  63 + ret |= sc_pm_setup_uart(SC_R_UART_2, rate);
  64 + if (ret)
  65 + return ret;
  66 +
  67 + setup_iomux_uart();
  68 +
  69 + return 0;
  70 +}
  71 +
  72 +#define ENET_PHY_RESET IMX_GPIO_NR(0, 3)
  73 +#define ENET_TEST_1 IMX_GPIO_NR(0, 8)
  74 +#define ENET_TEST_2 IMX_GPIO_NR(0, 9)
  75 +
  76 +/*#define ETH_IO_TEST*/
  77 +static iomux_cfg_t enet_reset[] = {
  78 + SC_P_ESAI0_SCKT | MUX_MODE_ALT(4) | MUX_PAD_CTRL(GPIO_PAD_CTRL),
  79 +#ifdef ETH_IO_TEST
  80 + /* GPIO0.IO08 MODE3: TXD0 */
  81 + SC_P_ESAI0_TX4_RX1 | MUX_MODE_ALT(4) |
  82 + MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
  83 + /* GPIO0.IO09 MODE3: TXD1 */
  84 + SC_P_ESAI0_TX5_RX0 | MUX_MODE_ALT(4) |
  85 + MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
  86 +#endif
  87 +};
  88 +
  89 +static void enet_device_phy_reset(void)
  90 +{
  91 + int ret = 0;
  92 +
  93 + imx8_iomux_setup_multiple_pads(enet_reset, ARRAY_SIZE(enet_reset));
  94 +
  95 + ret = gpio_request(ENET_PHY_RESET, "enet_phy_reset");
  96 + if (!ret) {
  97 + gpio_direction_output(ENET_PHY_RESET, 1);
  98 + gpio_set_value(ENET_PHY_RESET, 0);
  99 + /* SMSC9303 TRM chapter 14.5.2 */
  100 + udelay(200);
  101 + gpio_set_value(ENET_PHY_RESET, 1);
  102 + } else {
  103 + printf("ENET RESET failed!\n");
  104 + }
  105 +
  106 +#ifdef ETH_IO_TEST
  107 + ret = gpio_request(ENET_TEST_1, "enet_test1");
  108 + if (!ret) {
  109 + int i;
  110 +
  111 + printf("ENET TEST 1!\n");
  112 + for (i = 0; i < 20; i++) {
  113 + gpio_direction_output(ENET_TEST_1, 1);
  114 + gpio_set_value(ENET_TEST_1, 0);
  115 + udelay(50);
  116 + gpio_set_value(ENET_TEST_1, 1);
  117 + udelay(50);
  118 + }
  119 + gpio_free(ENET_TEST_1);
  120 + } else {
  121 + printf("GPIO for ENET TEST 1 failed!\n");
  122 + }
  123 + ret = gpio_request(ENET_TEST_2, "enet_test2");
  124 + if (!ret) {
  125 + int i;
  126 +
  127 + printf("ENET TEST 2!\n");
  128 + for (i = 0; i < 20; i++) {
  129 + gpio_direction_output(ENET_TEST_2, 1);
  130 + gpio_set_value(ENET_TEST_2, 0);
  131 + udelay(50);
  132 + gpio_set_value(ENET_TEST_2, 1);
  133 + udelay(50);
  134 + }
  135 + gpio_free(ENET_TEST_2);
  136 + } else {
  137 + printf("GPIO for ENET TEST 2 failed!\n");
  138 + }
  139 +#endif
  140 +}
  141 +
  142 +int setup_gpr_fec(void)
  143 +{
  144 + sc_ipc_t ipc_handle = -1;
  145 + sc_err_t err = 0;
  146 + unsigned int test;
  147 +
  148 + /*
  149 + * TX_CLK_SEL: it controls a mux between clock coming from the pad 50M
  150 + * input pin and clock generated internally to connectivity subsystem
  151 + * 0: internal clock
  152 + * 1: external clock ---> your choice for RMII
  153 + *
  154 + * CLKDIV_SEL: it controls a div by 2 on the internal clock path à
  155 + * it should be don’t care when using external clock
  156 + * 0: non-divided clock
  157 + * 1: clock divided by 2
  158 + * 50_DISABLE or 125_DISABLE:
  159 + * it’s used to disable the clock tree going outside the chip
  160 + * when reference clock is generated internally.
  161 + * It should be don’t care when reference clock is provided
  162 + * externally.
  163 + * 0: clock is enabled
  164 + * 1: clock is disabled
  165 + *
  166 + * SC_C_TXCLK = 24,
  167 + * SC_C_CLKDIV = 25,
  168 + * SC_C_DISABLE_50 = 26,
  169 + * SC_C_DISABLE_125 = 27,
  170 + */
  171 +
  172 + err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_TXCLK, 1);
  173 + if (err != SC_ERR_NONE)
  174 + printf("Error in setting up SC_C %d\n\r", SC_C_TXCLK);
  175 +
  176 + sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_TXCLK, &test);
  177 + debug("TEST SC_C %d-->%d\n\r", SC_C_TXCLK, test);
  178 +
  179 + err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_CLKDIV, 0);
  180 + if (err != SC_ERR_NONE)
  181 + printf("Error in setting up SC_C %d\n\r", SC_C_CLKDIV);
  182 +
  183 + sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_CLKDIV, &test);
  184 + debug("TEST SC_C %d-->%d\n\r", SC_C_CLKDIV, test);
  185 +
  186 + err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_DISABLE_50, 0);
  187 + if (err != SC_ERR_NONE)
  188 + printf("Error in setting up SC_C %d\n\r", SC_C_DISABLE_50);
  189 +
  190 + sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_TXCLK, &test);
  191 + debug("TEST SC_C %d-->%d\n\r", SC_C_DISABLE_50, test);
  192 +
  193 + err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_DISABLE_125, 1);
  194 + if (err != SC_ERR_NONE)
  195 + printf("Error in setting up SC_C %d\n\r", SC_C_DISABLE_125);
  196 +
  197 + sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_TXCLK, &test);
  198 + debug("TEST SC_C %d-->%d\n\r", SC_C_DISABLE_125, test);
  199 +
  200 + err = sc_misc_set_control(ipc_handle, SC_R_ENET_1, SC_C_SEL_125, 1);
  201 + if (err != SC_ERR_NONE)
  202 + printf("Error in setting up SC_C %d\n\r", SC_C_SEL_125);
  203 +
  204 + sc_misc_get_control(ipc_handle, SC_R_ENET_1, SC_C_SEL_125, &test);
  205 + debug("TEST SC_C %d-->%d\n\r", SC_C_SEL_125, test);
  206 +
  207 + return 0;
  208 +}
  209 +
  210 +#if IS_ENABLED(CONFIG_FEC_MXC)
  211 +#include <miiphy.h>
  212 +int board_phy_config(struct phy_device *phydev)
  213 +{
  214 + if (phydev->drv->config)
  215 + phydev->drv->config(phydev);
  216 +
  217 + return 0;
  218 +}
  219 +
  220 +#endif
  221 +
  222 +static int setup_fec(void)
  223 +{
  224 + setup_gpr_fec();
  225 + /* Reset ENET PHY */
  226 + enet_device_phy_reset();
  227 + return 0;
  228 +}
  229 +
  230 +void reset_cpu(ulong addr)
  231 +{
  232 +}
  233 +
  234 +#ifndef CONFIG_SPL_BUILD
  235 +/* LED's */
  236 +static int board_led_init(void)
  237 +{
  238 + struct udevice *bus, *dev;
  239 + u8 pca_led[2] = { 0x00, 0x00 };
  240 + int ret;
  241 +
  242 + /* init all GPIO LED's */
  243 + if (IS_ENABLED(CONFIG_LED))
  244 + led_default_state();
  245 +
  246 + /* enable all leds on PCA9552 */
  247 + ret = uclass_get_device_by_seq(UCLASS_I2C, PCA9552_1_I2C_BUS, &bus);
  248 + if (ret) {
  249 + printf("ERROR: I2C get %d\n", ret);
  250 + return ret;
  251 + }
  252 +
  253 + ret = dm_i2c_probe(bus, PCA9552_1_I2C_ADDR, 0, &dev);
  254 + if (ret) {
  255 + printf("ERROR: PCA9552 probe failed\n");
  256 + return ret;
  257 + }
  258 +
  259 + ret = dm_i2c_write(dev, 0x16, pca_led, sizeof(pca_led));
  260 + if (ret) {
  261 + printf("ERROR: PCA9552 write failed\n");
  262 + return ret;
  263 + }
  264 +
  265 + mdelay(1);
  266 + return ret;
  267 +}
  268 +#endif /* !CONFIG_SPL_BUILD */
  269 +
  270 +int checkboard(void)
  271 +{
  272 + puts("Board: Capricorn\n");
  273 +
  274 + /*
  275 + * Running build_info() doesn't work with current SCFW blob.
  276 + * Uncomment below call when new blob is available.
  277 + */
  278 + /*build_info();*/
  279 +
  280 + print_bootinfo();
  281 + return 0;
  282 +}
  283 +
  284 +int board_init(void)
  285 +{
  286 + setup_fec();
  287 + return 0;
  288 +}
  289 +
  290 +#ifdef CONFIG_OF_BOARD_SETUP
  291 +int ft_board_setup(void *blob, bd_t *bd)
  292 +{
  293 + return 0;
  294 +}
  295 +#endif
  296 +
  297 +int board_mmc_get_env_dev(int devno)
  298 +{
  299 + return devno;
  300 +}
  301 +
  302 +static int check_mmc_autodetect(void)
  303 +{
  304 + char *autodetect_str = env_get("mmcautodetect");
  305 +
  306 + if (autodetect_str && (strcmp(autodetect_str, "yes") == 0))
  307 + return 1;
  308 +
  309 + return 0;
  310 +}
  311 +
  312 +/* This should be defined for each board */
  313 +__weak int mmc_map_to_kernel_blk(int dev_no)
  314 +{
  315 + return dev_no;
  316 +}
  317 +
  318 +void board_late_mmc_env_init(void)
  319 +{
  320 + char cmd[32];
  321 + char mmcblk[32];
  322 + u32 dev_no = mmc_get_env_dev();
  323 +
  324 + if (!check_mmc_autodetect())
  325 + return;
  326 +
  327 + env_set_ulong("mmcdev", dev_no);
  328 +
  329 + /* Set mmcblk env */
  330 + sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw",
  331 + mmc_map_to_kernel_blk(dev_no));
  332 + env_set("mmcroot", mmcblk);
  333 +
  334 + sprintf(cmd, "mmc dev %d", dev_no);
  335 + run_command(cmd, 0);
  336 +}
  337 +
  338 +#ifndef CONFIG_SPL_BUILD
  339 +int factoryset_read_eeprom(int i2c_addr);
  340 +
  341 +static int load_parameters_from_factoryset(void)
  342 +{
  343 + int ret;
  344 +
  345 + ret = factoryset_read_eeprom(EEPROM_I2C_ADDR);
  346 + if (ret)
  347 + return ret;
  348 +
  349 + return factoryset_env_set();
  350 +}
  351 +
  352 +int board_late_init(void)
  353 +{
  354 + env_set("sec_boot", "no");
  355 +#ifdef CONFIG_AHAB_BOOT
  356 + env_set("sec_boot", "yes");
  357 +#endif
  358 +
  359 +#ifdef CONFIG_ENV_IS_IN_MMC
  360 + board_late_mmc_env_init();
  361 +#endif
  362 + /* Init LEDs */
  363 + if (board_led_init())
  364 + printf("I2C LED init failed\n");
  365 +
  366 + /* Set environment from factoryset */
  367 + if (load_parameters_from_factoryset())
  368 + printf("Loading factoryset parameters failed!\n");
  369 +
  370 + return 0;
  371 +}
  372 +
  373 +/* Service button */
  374 +#define MAX_PIN_NUMBER 128
  375 +#define BOARD_DEFAULT_BUTTON_GPIO IMX_GPIO_NR(1, 31)
  376 +
  377 +unsigned char get_button_state(char * const envname, unsigned char def)
  378 +{
  379 + int button = 0;
  380 + int gpio;
  381 + char *ptr_env;
  382 +
  383 + /* If button is not found we take default */
  384 + ptr_env = env_get(envname);
  385 + if (!ptr_env) {
  386 + printf("Using default: %u\n", def);
  387 + gpio = def;
  388 + } else {
  389 + gpio = (unsigned char)simple_strtoul(ptr_env, NULL, 0);
  390 + if (gpio > MAX_PIN_NUMBER)
  391 + gpio = def;
  392 + }
  393 +
  394 + gpio_request(gpio, "");
  395 + gpio_direction_input(gpio);
  396 + if (gpio_get_value(gpio))
  397 + button = 1;
  398 + else
  399 + button = 0;
  400 +
  401 + gpio_free(gpio);
  402 +
  403 + return button;
  404 +}
  405 +
  406 +/*
  407 + * This command returns the status of the user button on
  408 + * Input - none
  409 + * Returns - 1 if button is held down
  410 + * 0 if button is not held down
  411 + */
  412 +static int
  413 +do_userbutton(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  414 +{
  415 + int button = 0;
  416 +
  417 + button = get_button_state("button_usr1", BOARD_DEFAULT_BUTTON_GPIO);
  418 +
  419 + if (argc > 1)
  420 + printf("Button state: %u\n", button);
  421 +
  422 + return button;
  423 +}
  424 +
  425 +U_BOOT_CMD(
  426 + usrbutton, CONFIG_SYS_MAXARGS, 2, do_userbutton,
  427 + "Return the status of user button",
  428 + "[print]"
  429 +);
  430 +
  431 +#define ERST IMX_GPIO_NR(0, 3)
  432 +
  433 +static int
  434 +do_eth_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  435 +{
  436 + gpio_request(ERST, "ERST");
  437 + gpio_direction_output(ERST, 0);
  438 + udelay(200);
  439 + gpio_set_value(ERST, 1);
  440 + return 0;
  441 +}
  442 +
  443 +U_BOOT_CMD(
  444 + switch_rst, CONFIG_SYS_MAXARGS, 2, do_eth_reset,
  445 + "Reset eth phy",
  446 + "[print]"
  447 +);
  448 +#endif /* ! CONFIG_SPL_BUILD */
board/siemens/capricorn/imximage.cfg
Diff comments   View file @ 7b5b934
  1 +/* SPDX-License-Identifier: GPL-2.0+ */
  2 +/*
  3 + * Copyright 2018 NXP
  4 + *
  5 + * Refer doc/README.imx8image for more details about how-to configure
  6 + * and create imx8image boot image
  7 + */
  8 +
  9 +#define __ASSEMBLY__
  10 +
  11 +/* Boot from SD, sector size 0x400 */
  12 +BOOT_FROM SD 0x400
  13 +/* SoC type IMX8QX */
  14 +SOC_TYPE IMX8QX
  15 +/* Append seco container image */
  16 +APPEND ahab-container.img
  17 +/* Create the 2nd container */
  18 +CONTAINER
  19 +/* Add scfw image with exec attribute */
  20 +IMAGE SCU capricorn-scfw-tcm.bin
  21 +/* Add ATF image with exec attribute */
  22 +IMAGE A35 spl/u-boot-spl.bin 0x00100000
board/siemens/capricorn/spl.c
Diff comments   View file @ 7b5b934
  1 +// SPDX-License-Identifier: GPL-2.0+
  2 +/*
  3 + * Copyright 2018 NXP
  4 + *
  5 + * Copyright 2019 Siemens AG
  6 + *
  7 + */
  8 +#include <common.h>
  9 +#include <spl.h>
  10 +#include <dm.h>
  11 +#include <dm/uclass.h>
  12 +#include <dm/device.h>
  13 +#include <dm/uclass-internal.h>
  14 +#include <dm/device-internal.h>
  15 +
  16 +DECLARE_GLOBAL_DATA_PTR;
  17 +
  18 +void spl_board_init(void)
  19 +{
  20 + struct udevice *dev;
  21 +
  22 + uclass_find_first_device(UCLASS_MISC, &dev);
  23 +
  24 + for (; dev; uclass_find_next_device(&dev)) {
  25 + if (device_probe(dev))
  26 + continue;
  27 + }
  28 +
  29 + arch_cpu_init();
  30 +
  31 + board_early_init_f();
  32 +
  33 + timer_init();
  34 +
  35 + preloader_console_init();
  36 +}
  37 +
  38 +void board_init_f(ulong dummy)
  39 +{
  40 + /* Clear global data */
  41 + memset((void *)gd, 0, sizeof(gd_t));
  42 +
  43 + /* Clear the BSS. */
  44 + memset(__bss_start, 0, __bss_end - __bss_start);
  45 +
  46 + board_init_r(NULL, 0);
  47 +}
board/siemens/capricorn/uboot-container.cfg
Diff comments   View file @ 7b5b934
  1 +/* SPDX-License-Identifier: GPL-2.0+ */
  2 +/*
  3 + * Copyright 2019 NXP
  4 + */
  5 +
  6 +#define __ASSEMBLY__
  7 +
  8 +/* This file is to create a container image could be loaded by SPL */
  9 +BOOT_FROM SD 0x400
  10 +SOC_TYPE IMX8QX
  11 +CONTAINER
  12 +IMAGE A35 bl31.bin 0x80000000
  13 +IMAGE A35 u-boot.bin CONFIG_SYS_TEXT_BASE
board/siemens/common/factoryset.c
Diff comments   View file @ 7b5b934
... ... @@ -13,7 +13,9 @@
13 13 #include <env_internal.h>
14 14 #include <i2c.h>
15 15 #include <asm/io.h>
  16 +#if !CONFIG_IS_ENABLED(TARGET_GIEDI) && !CONFIG_IS_ENABLED(TARGET_DENEB)
16 17 #include <asm/arch/cpu.h>
  18 +#endif
17 19 #include <asm/arch/sys_proto.h>
18 20 #include <asm/unaligned.h>
19 21 #include <net.h>
configs/giedi_defconfig
Diff comments   View file @ 7b5b934
  1 +CONFIG_ARM=y
  2 +CONFIG_SPL_SYS_ICACHE_OFF=y
  3 +CONFIG_SPL_SYS_DCACHE_OFF=y
  4 +CONFIG_ARCH_IMX8=y
  5 +CONFIG_SYS_TEXT_BASE=0x80020000
  6 +CONFIG_SPL_GPIO_SUPPORT=y
  7 +CONFIG_SPL_LIBCOMMON_SUPPORT=y
  8 +CONFIG_SPL_LIBGENERIC_SUPPORT=y
  9 +CONFIG_SYS_MALLOC_F_LEN=0x4000
  10 +CONFIG_SPL_LOAD_IMX_CONTAINER=y
  11 +CONFIG_IMX_CONTAINER_CFG="board/siemens/capricorn/uboot-container.cfg"
  12 +CONFIG_TARGET_GIEDI=y
  13 +CONFIG_SPL_MMC_SUPPORT=y
  14 +CONFIG_SPL_SERIAL_SUPPORT=y
  15 +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
  16 +CONFIG_ENV_SIZE=0x2000
  17 +CONFIG_ENV_OFFSET=0x0
  18 +CONFIG_NR_DRAM_BANKS=3
  19 +CONFIG_SPL=y
  20 +CONFIG_SPL_TEXT_BASE=0x100000
  21 +CONFIG_OF_BOARD_SETUP=y
  22 +CONFIG_OF_SYSTEM_SETUP=y
  23 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/siemens/capricorn/imximage.cfg"
  24 +CONFIG_BOOTDELAY=3
  25 +CONFIG_LOG=y
  26 +CONFIG_SPL_BOARD_INIT=y
  27 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y
  28 +CONFIG_SPL_SEPARATE_BSS=y
  29 +CONFIG_SPL_POWER_SUPPORT=y
  30 +CONFIG_SPL_POWER_DOMAIN=y
  31 +CONFIG_SPL_WATCHDOG_SUPPORT=y
  32 +CONFIG_HUSH_PARSER=y
  33 +CONFIG_SYS_PROMPT="U-Boot# "
  34 +CONFIG_AUTOBOOT_KEYED=y
  35 +CONFIG_AUTOBOOT_PROMPT="Autobooting in %d seconds, press \"<Esc><Esc>\" to stop\n"
  36 +CONFIG_AUTOBOOT_STOP_STR="\x1b\x1b"
  37 +CONFIG_AUTOBOOT_KEYED_CTRLC=y
  38 +CONFIG_CMD_CPU=y
  39 +# CONFIG_CMD_IMPORTENV is not set
  40 +CONFIG_CMD_CLK=y
  41 +CONFIG_CMD_DM=y
  42 +CONFIG_CMD_FUSE=y
  43 +CONFIG_CMD_GPIO=y
  44 +CONFIG_CMD_I2C=y
  45 +CONFIG_CMD_MMC=y
  46 +CONFIG_CMD_DHCP=y
  47 +CONFIG_CMD_MII=y
  48 +CONFIG_CMD_PING=y
  49 +CONFIG_CMD_CACHE=y
  50 +CONFIG_CMD_EXT2=y
  51 +CONFIG_CMD_EXT4=y
  52 +CONFIG_CMD_FAT=y
  53 +CONFIG_CMD_FS_GENERIC=y
  54 +CONFIG_SPL_OF_CONTROL=y
  55 +CONFIG_DEFAULT_DEVICE_TREE="imx8-giedi"
  56 +CONFIG_ENV_IS_IN_MMC=y
  57 +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
  58 +CONFIG_ENV_OFFSET_REDUND=0x2000
  59 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
  60 +CONFIG_NET_RANDOM_ETHADDR=y
  61 +CONFIG_SPL_DM=y
  62 +CONFIG_SPL_CLK=y
  63 +CONFIG_CLK_IMX8=y
  64 +CONFIG_CPU=y
  65 +CONFIG_DM_GPIO=y
  66 +CONFIG_MXC_GPIO=y
  67 +CONFIG_DM_I2C=y
  68 +CONFIG_SYS_I2C_IMX_LPI2C=y
  69 +CONFIG_LED=y
  70 +CONFIG_LED_GPIO=y
  71 +CONFIG_MISC=y
  72 +CONFIG_DM_MMC=y
  73 +CONFIG_SUPPORT_EMMC_BOOT=y
  74 +CONFIG_MMC_IO_VOLTAGE=y
  75 +CONFIG_MMC_UHS_SUPPORT=y
  76 +CONFIG_MMC_HS400_SUPPORT=y
  77 +CONFIG_FSL_USDHC=y
  78 +CONFIG_PHYLIB=y
  79 +CONFIG_MV88E61XX_SWITCH=y
  80 +CONFIG_MV88E61XX_CPU_PORT=5
  81 +CONFIG_MV88E61XX_PHY_PORTS=0x7
  82 +CONFIG_MV88E61XX_FIXED_PORTS=0x0
  83 +CONFIG_DM_ETH=y
  84 +CONFIG_FEC_MXC_SHARE_MDIO=y
  85 +CONFIG_FEC_MXC_MDIO_BASE=0x5B050000
  86 +CONFIG_FEC_MXC=y
  87 +CONFIG_MII=y
  88 +CONFIG_PINCTRL=y
  89 +CONFIG_SPL_PINCTRL=y
  90 +CONFIG_PINCTRL_IMX8=y
  91 +CONFIG_POWER_DOMAIN=y
  92 +CONFIG_IMX8_POWER_DOMAIN=y
  93 +CONFIG_DM_REGULATOR=y
  94 +CONFIG_DM_REGULATOR_FIXED=y
  95 +CONFIG_DM_REGULATOR_GPIO=y
  96 +CONFIG_SPL_DM_REGULATOR_GPIO=y
  97 +CONFIG_DM_SERIAL=y
  98 +CONFIG_FSL_LPUART=y
  99 +CONFIG_DM_THERMAL=y
  100 +CONFIG_IMX_SCU_THERMAL=y
  101 +# CONFIG_SPL_WDT is not set
  102 +CONFIG_SPL_TINY_MEMSET=y
  103 +# CONFIG_EFI_LOADER is not set
include/configs/capricorn-common.h
Diff comments   View file @ 7b5b934
  1 +/* SPDX-License-Identifier: GPL-2.0+ */
  2 +/*
  3 + * Copyright 2017-2018 NXP
  4 + * Copyright 2019 Siemens AG
  5 + */
  6 +
  7 +#ifndef __IMX8X_CAPRICORN_H
  8 +#define __IMX8X_CAPRICORN_H
  9 +
  10 +#include <linux/sizes.h>
  11 +#include <asm/arch/imx-regs.h>
  12 +
  13 +#include "siemens-env-common.h"
  14 +#include "siemens-ccp-common.h"
  15 +
  16 +/* SPL config */
  17 +#ifdef CONFIG_SPL_BUILD
  18 +
  19 +#define CONFIG_SPL_MAX_SIZE (124 * 1024)
  20 +#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
  21 +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
  22 +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x800
  23 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 0
  24 +
  25 +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
  26 +#define CONFIG_SPL_STACK 0x013E000
  27 +#define CONFIG_SPL_BSS_START_ADDR 0x00128000
  28 +#define CONFIG_SPL_BSS_MAX_SIZE 0x1000 /* 4 KB */
  29 +#define CONFIG_SYS_SPL_MALLOC_START 0x00120000
  30 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3000 /* 12 KB */
  31 +#define CONFIG_MALLOC_F_ADDR 0x00120000
  32 +
  33 +#define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE
  34 +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
  35 +
  36 +#endif /* CONFIG_SPL_BUILD */
  37 +
  38 +#define CONFIG_FACTORYSET
  39 +
  40 +#undef CONFIG_IDENT_STRING
  41 +#define CONFIG_IDENT_STRING GENERATE_CCP_VERSION("01", "07")
  42 +
  43 +#define CONFIG_REMAKE_ELF
  44 +
  45 +#define CONFIG_BOARD_EARLY_INIT_F
  46 +
  47 +/* Commands */
  48 +#define CONFIG_CMD_READ
  49 +
  50 +#undef CONFIG_CMD_EXPORTENV
  51 +#undef CONFIG_CMD_IMPORTENV
  52 +#undef CONFIG_CMD_IMLS
  53 +#undef CONFIG_CMD_CRC32
  54 +#undef CONFIG_BOOTM_NETBSD
  55 +
  56 +/* ENET Config */
  57 +#define CONFIG_FEC_XCV_TYPE RMII
  58 +#define FEC_QUIRK_ENET_MAC
  59 +
  60 +/* ENET1 connects to base board and MUX with ESAI */
  61 +#define CONFIG_FEC_ENET_DEV 1
  62 +#define CONFIG_FEC_MXC_PHYADDR 0x0
  63 +#define CONFIG_ETHPRIME "eth1"
  64 +
  65 +/* I2C Configuration */
  66 +#ifndef CONFIG_SPL_BUILD
  67 +#define CONFIG_SYS_I2C_SPEED 400000
  68 +/* EEPROM */
  69 +#define EEPROM_I2C_BUS 0 /* I2C0 */
  70 +#define EEPROM_I2C_ADDR 0x50
  71 +/* PCA9552 */
  72 +#define PCA9552_1_I2C_BUS 1 /* I2C1 */
  73 +#define PCA9552_1_I2C_ADDR 0x60
  74 +#endif /* !CONFIG_SPL_BUILD */
  75 +
  76 +/* AHAB */
  77 +#ifdef CONFIG_AHAB_BOOT
  78 +#define AHAB_ENV "sec_boot=yes\0"
  79 +#else
  80 +#define AHAB_ENV "sec_boot=no\0"
  81 +#endif
  82 +
  83 +#define MFG_ENV_SETTINGS_DEFAULT \
  84 + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \
  85 + "rdinit=/linuxrc " \
  86 + "clk_ignore_unused "\
  87 + "\0" \
  88 + "kboot=booti\0"\
  89 + "bootcmd_mfg=run mfgtool_args;" \
  90 + "if iminfo ${initrd_addr}; then " \
  91 + "if test ${tee} = yes; then " \
  92 + "bootm ${tee_addr} ${initrd_addr} ${fdt_addr}; " \
  93 + "else " \
  94 + "booti ${loadaddr} ${initrd_addr} ${fdt_addr}; " \
  95 + "fi; " \
  96 + "else " \
  97 + "echo \"Run fastboot ...\"; fastboot 0; " \
  98 + "fi;\0"
  99 +
  100 +/* Boot M4 */
  101 +#define M4_BOOT_ENV \
  102 + "m4_0_image=m4_0.bin\0" \
  103 + "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} " \
  104 + "${loadaddr} ${m4_0_image}\0" \
  105 + "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
  106 +
  107 +#define CONFIG_MFG_ENV_SETTINGS \
  108 + MFG_ENV_SETTINGS_DEFAULT \
  109 + "initrd_addr=0x83100000\0" \
  110 + "initrd_high=0xffffffffffffffff\0" \
  111 + "emmc_dev=0\0"
  112 +
  113 +/* Initial environment variables */
  114 +#define CONFIG_EXTRA_ENV_SETTINGS \
  115 + CONFIG_MFG_ENV_SETTINGS \
  116 + M4_BOOT_ENV \
  117 + AHAB_ENV \
  118 + ENV_COMMON \
  119 + "script=boot.scr\0" \
  120 + "image=Image\0" \
  121 + "panel=NULL\0" \
  122 + "console=ttyLP2\0" \
  123 + "fdt_addr=0x83000000\0" \
  124 + "fdt_high=0xffffffffffffffff\0" \
  125 + "cntr_addr=0x88000000\0" \
  126 + "cntr_file=os_cntr_signed.bin\0" \
  127 + "initrd_addr=0x83800000\0" \
  128 + "initrd_high=0xffffffffffffffff\0" \
  129 + "netdev=eth0\0" \
  130 + "nfsopts=vers=3,udp,rsize=4096,wsize=4096,nolock rw\0" \
  131 + "hostname=capricorn\0" \
  132 + ENV_EMMC \
  133 + ENV_NET
  134 +
  135 +#define CONFIG_BOOTCOMMAND \
  136 + "if usrbutton; then " \
  137 + "run flash_self_test; " \
  138 + "reset; " \
  139 + "fi;" \
  140 + "run flash_self;" \
  141 + "reset;"
  142 +
  143 +/* Default location for tftp and bootm */
  144 +#define CONFIG_LOADADDR 0x80280000
  145 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
  146 +#define CONFIG_SYS_INIT_SP_ADDR 0x80200000
  147 +
  148 +#define CONFIG_BOOTCOUNT_LIMIT
  149 +#define CONFIG_BOOTCOUNT_ENV
  150 +
  151 +/* Environment organisation */
  152 +#define CONFIG_ENV_OVERWRITE
  153 +#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1, eMMC */
  154 +#define CONFIG_SYS_MMC_ENV_PART 2 /* 2nd boot partition */
  155 +
  156 +/* On CCP board, USDHC1 is for eMMC */
  157 +#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* eMMC */
  158 +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
  159 +
  160 +/* Size of malloc() pool */
  161 +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024)
  162 +
  163 +#define CONFIG_SYS_SDRAM_BASE 0x80000000
  164 +#define PHYS_SDRAM_1 0x80000000
  165 +#define PHYS_SDRAM_2 0x880000000
  166 +/* DDR3 board total DDR is 1 GB */
  167 +#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1 GB */
  168 +#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 GB */
  169 +
  170 +#define CONFIG_SYS_MEMTEST_START 0xA0000000
  171 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
  172 + (PHYS_SDRAM_1_SIZE >> 2))
  173 +
  174 +/* Console buffer and boot args */
  175 +#define CONFIG_SYS_CBSIZE 2048
  176 +#define CONFIG_SYS_MAXARGS 64
  177 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  178 +
  179 +/* Generic Timer Definitions */
  180 +#define COUNTER_FREQUENCY 8000000 /* 8MHz */
  181 +
  182 +#define BOOTAUX_RESERVED_MEM_BASE 0x88000000
  183 +#define BOOTAUX_RESERVED_MEM_SIZE SZ_128M /* Reserve from second 128MB */
  184 +
  185 +#endif /* __IMX8X_CAPRICORN_H */
include/configs/giedi.h
Diff comments   View file @ 7b5b934
  1 +/* SPDX-License-Identifier: GPL-2.0+ */
  2 +/*
  3 + * Copyright 2019 Siemens AG
  4 + *
  5 + */
  6 +
  7 +#ifndef __GIEDI_H
  8 +#define __GIEDI_H
  9 +
  10 +#include "capricorn-common.h"
  11 +
  12 +#undef CONFIG_IDENT_STRING
  13 +#define CONFIG_IDENT_STRING GENERATE_CCP_VERSION("01", "07")
  14 +
  15 +/* DDR3 board total DDR is 1 GB */
  16 +#undef PHYS_SDRAM_1_SIZE
  17 +#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1 GB */
  18 +
  19 +#endif /* __GIEDI_H */
include/configs/siemens-ccp-common.h
Diff comments   View file @ 7b5b934
  1 +/* SPDX-License-Identifier: GPL-2.0+ */
  2 +/* Be very careful updating CONFIG_IDENT_STRING
  3 + * This string will control the update flow whether an U-Boot should be
  4 + * updated or not. If the version of installed U-Boot (in flash) is smaller
  5 + * than the version to be installed (from update file), an update will
  6 + * be performed.
  7 + *
  8 + * General rules:
  9 + * 1. First 4 characters ' ##v' or IDENT_MAGIC represent kind of a magic number
  10 + * to identify the following strings after easily. Don't change them!
  11 + *
  12 + * 2. First 2 digits after 'v' or CCP_MAJOR are updated with U-Boot version
  13 + * change, e.g. from 2015.04 to 2018.03
  14 + *
  15 + * 3. Second 2 digits after '.' or CCP_MINOR are updated if we want to upgrade
  16 + * U-Boot within an U-Boot version.
  17 + */
  18 +#define CCP_IDENT_MAGIC " ##v"
  19 +#define GENERATE_CCP_VERSION(MAJOR, MINOR) CCP_IDENT_MAGIC MAJOR "." MINOR
include/configs/siemens-env-common.h
Diff comments   View file @ 7b5b934
  1 +/* SPDX-License-Identifier: GPL-2.0+ */
  2 +
  3 +/* Common env settings */
  4 +
  5 +/** set_bootargs()
  6 + * input:
  7 + * console: string, tty, etc.
  8 + * baudrate: string, tty baudrate
  9 + * testargs: string
  10 + * optargs: string
  11 + * output:
  12 + * bootargs: string, default boot string
  13 + */
  14 +#define ENV_BOOTARGS_DEFAULT "set_bootargs=" \
  15 + "setenv bootargs " \
  16 + "console=${console} " \
  17 + "${testargs} " \
  18 + "${optargs}\0"
  19 +
  20 +/** set_bootargs_net()
  21 + * input:
  22 + * kernel_name:
  23 + * dtb_name:
  24 + * project_dir:
  25 + * output:
  26 + */
  27 +#define ENV_NET_FCT_NETARGS "set_bootargs_net=" \
  28 + "run set_bootargs;" \
  29 + "setenv bootfile ${project_dir}/boot/${kernel_name};" \
  30 + "setenv bootdtb ${project_dir}/boot/${dtb_name_nfs}.dtb;" \
  31 + "setenv rootpath /home/projects/${project_dir}/;" \
  32 + "setenv bootargs ${bootargs} " \
  33 + "root=/dev/nfs " \
  34 + "nfsroot=${serverip}:${rootpath},${nfsopts} " \
  35 + "ip=${ipaddr}:${serverip}:" \
  36 + "${gatewayip}:${netmask}:${hostname}:eth0:off\0"
  37 +
  38 +/** net_nfs()
  39 + * input:
  40 + * output:
  41 + */
  42 +#define ENV_NET_FCT_BOOT "net_nfs=" \
  43 + "echo Booting from network ...; " \
  44 + "run set_bootargs_net; " \
  45 + "tftpboot ${dtb_loadaddr} ${serverip}:${bootdtb};" \
  46 + "if test $? -eq 1;" \
  47 + "then " \
  48 + "echo Loading default.dtb!;" \
  49 + "tftpboot ${dtb_loadaddr} ${serverip}:${project_dir}/boot/${dtb_name_default}.dtb;" \
  50 + "fi;" \
  51 + "tftpboot ${kernel_loadaddr} ${serverip}:${bootfile};" \
  52 + "printenv bootargs;" \
  53 + "booti ${kernel_loadaddr} - ${dtb_loadaddr}\0"
  54 +
  55 +/** check_update()
  56 + * input:
  57 + * upgrade_available: [0|1], if set to 1 check bootcount variables
  58 + * bootcount: int, bootcount
  59 + * bootlimit: int, limit cootcount
  60 + * toggle_partition(): - toggles active partition set
  61 + * output:
  62 + * upgrade_available: [0|1], set to 0 if bootcount > bootlimit
  63 + */
  64 +#define ENV_FCT_CHECK_UPGRADE "check_upgrade="\
  65 + "if test ${upgrade_available} -eq 1; " \
  66 + "then " \
  67 + "echo upgrade_available is set; " \
  68 + "if test ${bootcount} -gt ${bootlimit}; " \
  69 + "then " \
  70 + "setenv upgrade_available 0;" \
  71 + "echo toggle partition;" \
  72 + "run toggle_partition;" \
  73 + "fi;" \
  74 + "fi;\0"
  75 +
  76 +/** toggle_partition()
  77 + * input:
  78 + * partitionset_active: [A|B], selected partition set
  79 + * output:
  80 + * partitionset_active: [A|B], toggle
  81 + */
  82 +#define ENV_FCT_TOGGLE_PARTITION "toggle_partition="\
  83 + "setenv ${partitionset_active} true;" \
  84 + "if test -n ${A}; " \
  85 + "then " \
  86 + "setenv partitionset_active B; " \
  87 + "env delete A; " \
  88 + "fi;" \
  89 + "if test -n ${B}; "\
  90 + "then " \
  91 + "setenv partitionset_active A; " \
  92 + "env delete B; " \
  93 + "fi;" \
  94 + "saveenv\0"
  95 +
  96 +/** set_partition()
  97 + * input:
  98 + * partitionset_active: [A|B], selected partition set
  99 + * rootfs_name: string, mmc device file in kernel, e.g. /dev/mmcblk0
  100 + * output:
  101 + * mmc_active_vol: string, mmc partition device file in kernel, e.g. /dev/mmcblk0p2
  102 + * mmc_part_nr: int, partition number of mmc, e.g. /dev/mmcblk0p2 --> 2
  103 + */
  104 +#define ENV_EMMC_FCT_SET_ACTIVE_PARTITION "set_partition=" \
  105 + "setenv ${partitionset_active} true;" \
  106 + "if test -n ${A}; " \
  107 + "then " \
  108 + "setenv mmc_part_nr 1;" \
  109 + "fi;" \
  110 + "if test -n ${B}; " \
  111 + "then " \
  112 + "setenv mmc_part_nr 2;" \
  113 + "fi;" \
  114 + "setenv mmc_active_vol ${rootfs_name}p${mmc_part_nr} \0"
  115 +
  116 +/** set_bootargs_mmc()
  117 + * input:
  118 + * bootargs: string, default bootargs
  119 + * mmc_active_vol string, mmc partition device file in kernel, e.g. /dev/mmcblk0p2
  120 + * ip_method: string, [none|?]
  121 + * output:
  122 + * bootargs: string
  123 + */
  124 +#define ENV_EMMC_FCT_SET_EMMC_BOOTARGS "set_bootargs_mmc=" \
  125 + "setenv bootargs ${bootargs} " \
  126 + "root=${mmc_active_vol} rw " \
  127 + "rootdelay=1 rootwait " \
  128 + "rootfstype=ext4 " \
  129 + "ip=${ip_method} \0"
  130 +
  131 +/** mmc_load_bootfiles()
  132 + * input:
  133 + * mmc_part_nr:
  134 + * dtb_loadaddr:
  135 + * dtb_name:
  136 + * kernel_loadaddr:
  137 + * kernel_name:
  138 + */
  139 +#define ENV_EMMC_FCT_LOADFROM_EMMC "mmc_load_bootfiles=" \
  140 + "echo Loading from eMMC ...;" \
  141 + "ext4load mmc 0:${mmc_part_nr} ${dtb_loadaddr} boot/${dtb_name}.dtb;" \
  142 + "if test $? -eq 1;" \
  143 + "then " \
  144 + "echo Loading default.dtb!;" \
  145 + "ext4load mmc 0:${mmc_part_nr} ${dtb_loadaddr} boot/${dtb_name_default}.dtb;" \
  146 + "fi;" \
  147 + "ext4load mmc 0:${mmc_part_nr} ${kernel_loadaddr} boot/${kernel_name};" \
  148 + "printenv bootargs;\0"
  149 +
  150 +/** mmc_boot()
  151 + * input:
  152 + * mmc_part_nr:
  153 + * dtb_loadaddr:
  154 + * dtb_name:
  155 + * kernel_loadaddr:
  156 + * kernel_name:
  157 + */
  158 +#define ENV_EMMC_FCT_EMMC_BOOT "mmc_boot=" \
  159 + "run set_bootargs;" \
  160 + "run check_upgrade; " \
  161 + "run set_partition;" \
  162 + "run set_bootargs_mmc;" \
  163 + "run mmc_load_bootfiles;" \
  164 + "echo Booting from eMMC ...; " \
  165 + "booti ${kernel_loadaddr} - ${dtb_loadaddr} \0"
  166 +
  167 +#define ENV_EMMC_ALIASES "" \
  168 + "flash_self=run mmc_boot\0" \
  169 + "flash_self_test=setenv testargs test; " \
  170 + "run mmc_boot\0"
  171 +
  172 +#define ENV_COMMON "" \
  173 + "project_dir=targetdir/rootfs\0" \
  174 + "serverip=192.168.251.2\0" \
  175 + "ipaddr=192.168.251.1\0" \
  176 + "dtb_name_nfs=default\0" \
  177 + "dtb_name_default=default\0" \
  178 + "kernel_name=Image\0" \
  179 + "partitionset_active=A\0" \
  180 + "dtb_loadaddr=0x83000000\0" \
  181 + "kernel_loadaddr=0x80280000\0" \
  182 + "ip_method=none\0" \
  183 + "rootfs_name=/dev/mmcblk0\0" \
  184 + "upgrade_available=0\0" \
  185 + "bootlimit=3\0" \
  186 + "altbootcmd=run bootcmd\0" \
  187 + "optargs=\0" \
  188 +
  189 +/**********************************************************************/
  190 +
  191 +#define ENV_EMMC ENV_EMMC_FCT_EMMC_BOOT \
  192 + ENV_EMMC_FCT_LOADFROM_EMMC \
  193 + ENV_EMMC_FCT_SET_EMMC_BOOTARGS \
  194 + ENV_EMMC_FCT_SET_ACTIVE_PARTITION \
  195 + ENV_FCT_CHECK_UPGRADE \
  196 + ENV_EMMC_ALIASES \
  197 + ENV_FCT_TOGGLE_PARTITION
  198 +
  199 +#define ENV_NET ENV_NET_FCT_BOOT \
  200 + ENV_NET_FCT_NETARGS \
  201 + ENV_BOOTARGS_DEFAULT