Eric Lee / smarc-uboot

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Commit 7bcee5f7eef740c506117e6da1226bc8ec7f466a

Authored by Tom Rini
2 parents 985a71d15b 5480ac3217
Exists in master and in 56 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf-6.6.52-2.2.0, emb_lf_v2022.04, emb_lf_v2023.04, emb_lf_v2024.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

Merge branch 'master' of git://git.denx.de/u-boot-arm

Showing 20 changed files Side-by-side Diff

... ... @@ -464,6 +464,10 @@
464 464 mvblm7 MPC8343
465 465 mvsmr MPC5200
466 466  
  467 +Inderpal Singh <inderpal.singh@linaro.org>
  468 +
  469 + Arndale ARM ARMV7 (EXYNOS5250 SoC)
  470 +
467 471 Jon Smirl <jonsmirl@gmail.com>
468 472  
469 473 pcm030 MPC5200
... ... @@ -867,7 +867,7 @@
867 867 $(obj)tools/gdb/{astest,gdbcont,gdbsend} \
868 868 $(obj)tools/gen_eth_addr $(obj)tools/img2srec \
869 869 $(obj)tools/mk{env,}image $(obj)tools/mpc86x_clk \
870   - $(obj)tools/mk{smdk5250,}spl \
  870 + $(obj)tools/mk{$(BOARD),}spl \
871 871 $(obj)tools/mxsboot \
872 872 $(obj)tools/ncb $(obj)tools/ubsha1 \
873 873 $(obj)tools/kernel-doc/docproc \
arch/arm/include/asm/arch-exynos/gpio.h
Diff comments   View file @ 7bcee5f
... ... @@ -290,10 +290,19 @@
290 290 return EXYNOS5_GPIO_PART2_MAX;
291 291  
292 292 } else if (cpu_is_exynos4()) {
293   - if (nr < EXYNOS4_GPIO_PART1_MAX)
294   - return 0;
295   - else
296   - return EXYNOS4_GPIO_PART1_MAX;
  293 + if (proid_is_exynos4412()) {
  294 + if (nr < EXYNOS4X12_GPIO_PART1_MAX)
  295 + return 0;
  296 + else if (nr < EXYNOS4X12_GPIO_PART2_MAX)
  297 + return EXYNOS4X12_GPIO_PART1_MAX;
  298 + else
  299 + return EXYNOS4X12_GPIO_PART2_MAX;
  300 + } else {
  301 + if (nr < EXYNOS4_GPIO_PART1_MAX)
  302 + return 0;
  303 + else
  304 + return EXYNOS4_GPIO_PART1_MAX;
  305 + }
297 306 }
298 307  
299 308 return 0;
arch/arm/include/asm/arch-exynos/mmc.h
Diff comments   View file @ 7bcee5f
... ... @@ -8,6 +8,8 @@
8 8 #ifndef __ASM_ARCH_MMC_H_
9 9 #define __ASM_ARCH_MMC_H_
10 10  
  11 +#define S5P_MMC_DEV_OFFSET 0x10000
  12 +
11 13 #define SDHCI_CONTROL2 0x80
12 14 #define SDHCI_CONTROL3 0x84
13 15 #define SDHCI_CONTROL4 0x8C
... ... @@ -55,7 +57,9 @@
55 57  
56 58 static inline unsigned int s5p_mmc_init(int index, int bus_width)
57 59 {
58   - unsigned int base = samsung_get_base_mmc() + (0x10000 * index);
  60 + unsigned int base = samsung_get_base_mmc() +
  61 + (S5P_MMC_DEV_OFFSET * index);
  62 +
59 63 return s5p_sdhci_init(base, index, bus_width);
60 64 }
61 65 #endif
arch/arm/include/asm/arch-s5pc1xx/mmc.h
Diff comments   View file @ 7bcee5f
... ... @@ -8,6 +8,8 @@
8 8 #ifndef __ASM_ARCH_MMC_H_
9 9 #define __ASM_ARCH_MMC_H_
10 10  
  11 +#define S5P_MMC_DEV_OFFSET 0x100000
  12 +
11 13 #define SDHCI_CONTROL2 0x80
12 14 #define SDHCI_CONTROL3 0x84
13 15 #define SDHCI_CONTROL4 0x8C
... ... @@ -55,7 +57,9 @@
55 57  
56 58 static inline unsigned int s5p_mmc_init(int index, int bus_width)
57 59 {
58   - unsigned int base = samsung_get_base_mmc() + (0x10000 * index);
  60 + unsigned int base = samsung_get_base_mmc() +
  61 + (S5P_MMC_DEV_OFFSET * index);
  62 +
59 63 return s5p_sdhci_init(base, index, bus_width);
60 64 }
61 65 #endif
board/samsung/arndale/Makefile
Diff comments   View file @ 7bcee5f
  1 +#
  2 +# Copyright (C) 2013 Samsung Electronics
  3 +#
  4 +# SPDX-License-Identifier: GPL-2.0+
  5 +#
  6 +
  7 +include $(TOPDIR)/config.mk
  8 +
  9 +LIB = $(obj)lib$(BOARD).o
  10 +
  11 +COBJS += arndale_spl.o
  12 +
  13 +ifndef CONFIG_SPL_BUILD
  14 +COBJS += arndale.o
  15 +endif
  16 +
  17 +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
  18 +OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
  19 +
  20 +ALL := $(obj).depend $(LIB)
  21 +
  22 +all: $(ALL)
  23 +
  24 +$(LIB): $(OBJS)
  25 + $(call cmd_link_o_target, $(OBJS))
  26 +
  27 +#########################################################################
  28 +
  29 +# defines $(obj).depend target
  30 +include $(SRCTREE)/rules.mk
  31 +
  32 +sinclude $(obj).depend
  33 +
  34 +#########################################################################
board/samsung/arndale/arndale.c
Diff comments   View file @ 7bcee5f
  1 +/*
  2 + * Copyright (C) 2013 Samsung Electronics
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <common.h>
  8 +#include <asm/arch/pinmux.h>
  9 +#include <asm/arch/dwmmc.h>
  10 +#include <asm/arch/power.h>
  11 +
  12 +DECLARE_GLOBAL_DATA_PTR;
  13 +
  14 +int board_init(void)
  15 +{
  16 + gd->bd->bi_boot_params = (PHYS_SDRAM_1 + 0x100UL);
  17 + return 0;
  18 +}
  19 +
  20 +int dram_init(void)
  21 +{
  22 + int i;
  23 + u32 addr;
  24 +
  25 + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
  26 + addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
  27 + gd->ram_size += get_ram_size((long *)addr, SDRAM_BANK_SIZE);
  28 + }
  29 + return 0;
  30 +}
  31 +
  32 +int power_init_board(void)
  33 +{
  34 + set_ps_hold_ctrl();
  35 + return 0;
  36 +}
  37 +
  38 +void dram_init_banksize(void)
  39 +{
  40 + int i;
  41 + u32 addr, size;
  42 +
  43 + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
  44 + addr = CONFIG_SYS_SDRAM_BASE + (i * SDRAM_BANK_SIZE);
  45 + size = get_ram_size((long *)addr, SDRAM_BANK_SIZE);
  46 +
  47 + gd->bd->bi_dram[i].start = addr;
  48 + gd->bd->bi_dram[i].size = size;
  49 + }
  50 +}
  51 +
  52 +#ifdef CONFIG_GENERIC_MMC
  53 +int board_mmc_init(bd_t *bis)
  54 +{
  55 + int ret;
  56 + /* dwmmc initializattion for available channels */
  57 + ret = exynos_dwmmc_init(gd->fdt_blob);
  58 + if (ret)
  59 + debug("dwmmc init failed\n");
  60 +
  61 + return ret;
  62 +}
  63 +#endif
  64 +
  65 +static int board_uart_init(void)
  66 +{
  67 + int err = 0, uart_id;
  68 +
  69 + for (uart_id = PERIPH_ID_UART0; uart_id <= PERIPH_ID_UART3; uart_id++) {
  70 + err = exynos_pinmux_config(uart_id, PINMUX_FLAG_NONE);
  71 + if (err) {
  72 + debug("UART%d not configured\n",
  73 + (uart_id - PERIPH_ID_UART0));
  74 + return err;
  75 + }
  76 + }
  77 + return err;
  78 +}
  79 +
  80 +#ifdef CONFIG_BOARD_EARLY_INIT_F
  81 +int board_early_init_f(void)
  82 +{
  83 + int err;
  84 +
  85 + err = board_uart_init();
  86 + if (err) {
  87 + debug("UART init failed\n");
  88 + return err;
  89 + }
  90 + return err;
  91 +}
  92 +#endif
  93 +
  94 +#ifdef CONFIG_DISPLAY_BOARDINFO
  95 +int checkboard(void)
  96 +{
  97 + printf("\nBoard: Arndale\n");
  98 +
  99 + return 0;
  100 +}
  101 +#endif
board/samsung/arndale/arndale_spl.c
Diff comments   View file @ 7bcee5f
  1 +/*
  2 + * Copyright (c) 2012 The Chromium OS Authors.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <common.h>
  8 +#include <asm/arch/spl.h>
  9 +
  10 +#define SIGNATURE 0xdeadbeef
  11 +
  12 +/* Parameters of early board initialization in SPL */
  13 +static struct spl_machine_param machine_param
  14 + __attribute__((section(".machine_param"))) = {
  15 + .signature = SIGNATURE,
  16 + .version = 1,
  17 + .params = "vmubfasirM",
  18 + .size = sizeof(machine_param),
  19 +
  20 + .mem_iv_size = 0x1f,
  21 + .mem_type = DDR_MODE_DDR3,
  22 +
  23 + /*
  24 + * Set uboot_size to 0x100000 bytes.
  25 + *
  26 + * This is an overly conservative value chosen to accommodate all
  27 + * possible U-Boot image. You are advised to set this value to a
  28 + * smaller realistic size via scripts that modifies the .machine_param
  29 + * section of output U-Boot image.
  30 + */
  31 + .uboot_size = 0x100000,
  32 +
  33 + .boot_source = BOOT_MODE_OM,
  34 + .frequency_mhz = 800,
  35 + .arm_freq_mhz = 1000,
  36 + .serial_base = 0x12c30000,
  37 + .i2c_base = 0x12c60000,
  38 + .mem_manuf = MEM_MANUF_SAMSUNG,
  39 +};
  40 +
  41 +struct spl_machine_param *spl_get_machine_params(void)
  42 +{
  43 + if (machine_param.signature != SIGNATURE) {
  44 + /* Will hang if SIGNATURE dont match */
  45 + while (1)
  46 + ;
  47 + }
  48 +
  49 + return &machine_param;
  50 +}
board/samsung/dts/exynos5250-arndale.dts
Diff comments   View file @ 7bcee5f
  1 +/*
  2 + * SAMSUNG Arndale board device tree source
  3 + *
  4 + * Copyright (c) 2013 Samsung Electronics Co., Ltd.
  5 + * http://www.samsung.com
  6 + *
  7 + * SPDX-License-Identifier: GPL-2.0+
  8 +*/
  9 +
  10 +/dts-v1/;
  11 +#include "exynos5250.dtsi"
  12 +
  13 +/ {
  14 + model = "SAMSUNG Arndale board based on EXYNOS5250";
  15 + compatible = "samsung,arndale", "samsung,exynos5250";
  16 +
  17 + aliases {
  18 + serial0 = "/serial@12C20000";
  19 + console = "/serial@12C20000";
  20 + };
  21 +
  22 + mmc@12200000 {
  23 + samsung,bus-width = <8>;
  24 + samsung,timing = <1 3 3>;
  25 + };
  26 +
  27 + mmc@12210000 {
  28 + status = "disabled";
  29 + };
  30 +
  31 + mmc@12220000 {
  32 + samsung,bus-width = <4>;
  33 + samsung,timing = <1 2 3>;
  34 + };
  35 +
  36 + mmc@12230000 {
  37 + status = "disabled";
  38 + };
  39 +};
board/samsung/goni/config.mk
View file @ 7bcee5f
1   -#
2   -# Copyright (C) 2010 Samsung Electronics
3   -# Kyungmin Park <kyungmin.park@samsung.com>
4   -#
5   -# SPDX-License-Identifier: GPL-2.0+
6   -#
7   -
8   -# On S5PC100 we use the 128 MiB OneDRAM bank at
9   -#
10   -# 0x30000000 to 0x35000000 (80MiB)
11   -# 0x38000000 to 0x40000000 (128MiB)
12   -#
13   -# On S5PC110 we use the 128 MiB OneDRAM bank at
14   -#
15   -# 0x30000000 to 0x35000000 (80MiB)
16   -# 0x40000000 to 0x50000000 (256MiB)
17   -#
18   -CONFIG_SYS_TEXT_BASE = 0x34800000
board/samsung/goni/goni.c
Diff comments   View file @ 7bcee5f
... ... @@ -72,7 +72,7 @@
72 72 #ifdef CONFIG_GENERIC_MMC
73 73 int board_mmc_init(bd_t *bis)
74 74 {
75   - int i;
  75 + int i, ret, ret_sd = 0;
76 76  
77 77 /* MASSMEMORY_EN: XMSMDATA7: GPJ2[7] output high */
78 78 s5p_gpio_direction_output(&s5pc110_gpio->j2, 7, 1);
... ... @@ -95,7 +95,36 @@
95 95 s5p_gpio_set_drv(&s5pc110_gpio->g0, i, GPIO_DRV_4X);
96 96 }
97 97  
98   - return s5p_mmc_init(0, 4);
  98 + ret = s5p_mmc_init(0, 4);
  99 + if (ret)
  100 + error("MMC: Failed to init MMC:0.\n");
  101 +
  102 + /*
  103 + * SD card (T_FLASH) detect and init
  104 + * T_FLASH_DETECT: EINT28: GPH3[4] input mode
  105 + */
  106 + s5p_gpio_cfg_pin(&s5pc110_gpio->h3, 4, GPIO_INPUT);
  107 + s5p_gpio_set_pull(&s5pc110_gpio->h3, 4, GPIO_PULL_UP);
  108 +
  109 + if (!s5p_gpio_get_value(&s5pc110_gpio->h3, 4)) {
  110 + for (i = 0; i < 7; i++) {
  111 + if (i == 2)
  112 + continue;
  113 +
  114 + /* GPG2[0:6] special function 2 */
  115 + s5p_gpio_cfg_pin(&s5pc110_gpio->g2, i, 0x2);
  116 + /* GPG2[0:6] pull disable */
  117 + s5p_gpio_set_pull(&s5pc110_gpio->g2, i, GPIO_PULL_NONE);
  118 + /* GPG2[0:6] drv 4x */
  119 + s5p_gpio_set_drv(&s5pc110_gpio->g2, i, GPIO_DRV_4X);
  120 + }
  121 +
  122 + ret_sd = s5p_mmc_init(2, 4);
  123 + if (ret_sd)
  124 + error("MMC: Failed to init SD card (MMC:2).\n");
  125 + }
  126 +
  127 + return ret & ret_sd;
99 128 }
100 129 #endif
101 130  
board/samsung/smdkc100/config.mk
View file @ 7bcee5f
1   -#
2   -# Copyright (C) 2008 # Samsung Elecgtronics
3   -# Kyungmin Park <kyungmin.park@samsung.com>
4   -#
5   -
6   -# On S5PC100 we use the 128 MiB OneDRAM bank at
7   -#
8   -# 0x30000000 to 0x35000000 (80MiB)
9   -# 0x38000000 to 0x40000000 (128MiB)
10   -#
11   -# On S5PC110 we use the 128 MiB OneDRAM bank at
12   -#
13   -# 0x30000000 to 0x35000000 (80MiB)
14   -# 0x40000000 to 0x48000000 (128MiB)
15   -#
16   -CONFIG_SYS_TEXT_BASE = 0x34800000
... ... @@ -327,6 +327,7 @@
327 327 dra7xx_evm arm armv7 dra7xx ti omap5
328 328 s5p_goni arm armv7 goni samsung s5pc1xx
329 329 smdkc100 arm armv7 smdkc100 samsung s5pc1xx
  330 +arndale arm armv7 arndale samsung exynos
330 331 origen arm armv7 origen samsung exynos
331 332 s5pc210_universal arm armv7 universal_c210 samsung exynos
332 333 snow arm armv7 smdk5250 samsung exynos
drivers/power/pmic/pmic_max77686.c
Diff comments   View file @ 7bcee5f
... ... @@ -14,6 +14,198 @@
14 14  
15 15 DECLARE_GLOBAL_DATA_PTR;
16 16  
  17 +static const char max77686_buck_addr[] = {
  18 + 0xff, 0x10, 0x12, 0x1c, 0x26, 0x30, 0x32, 0x34, 0x36, 0x38
  19 +};
  20 +
  21 +static unsigned int max77686_ldo_volt2hex(int ldo, ulong uV)
  22 +{
  23 + unsigned int hex = 0;
  24 +
  25 + switch (ldo) {
  26 + case 1:
  27 + case 2:
  28 + case 6:
  29 + case 7:
  30 + case 8:
  31 + case 15:
  32 + hex = (uV - 800000) / 25000;
  33 + break;
  34 + default:
  35 + hex = (uV - 800000) / 50000;
  36 + }
  37 +
  38 + if (hex >= 0 && hex <= MAX77686_LDO_VOLT_MAX_HEX)
  39 + return hex;
  40 +
  41 + debug("%s: %ld is wrong voltage value for LDO%d\n", __func__, uV, ldo);
  42 + return 0;
  43 +}
  44 +
  45 +int max77686_set_ldo_voltage(struct pmic *p, int ldo, ulong uV)
  46 +{
  47 + unsigned int val, ret, hex, adr;
  48 +
  49 + if (ldo < 1 && ldo > 26) {
  50 + printf("%s: %d is wrong ldo number\n", __func__, ldo);
  51 + return -1;
  52 + }
  53 +
  54 + adr = MAX77686_REG_PMIC_LDO1CTRL1 + ldo - 1;
  55 + hex = max77686_ldo_volt2hex(ldo, uV);
  56 +
  57 + if (!hex)
  58 + return -1;
  59 +
  60 + ret = pmic_reg_read(p, adr, &val);
  61 + if (ret)
  62 + return ret;
  63 +
  64 + val &= ~MAX77686_LDO_VOLT_MASK;
  65 + val |= hex;
  66 + ret |= pmic_reg_write(p, adr, val);
  67 +
  68 + return ret;
  69 +}
  70 +
  71 +int max77686_set_ldo_mode(struct pmic *p, int ldo, char opmode)
  72 +{
  73 + unsigned int val, ret, adr, mode;
  74 +
  75 + if (ldo < 1 && 26 < ldo) {
  76 + printf("%s: %d is wrong ldo number\n", __func__, ldo);
  77 + return -1;
  78 + }
  79 +
  80 + adr = MAX77686_REG_PMIC_LDO1CTRL1 + ldo - 1;
  81 +
  82 + /* mode */
  83 + switch (opmode) {
  84 + case OPMODE_OFF:
  85 + mode = MAX77686_LDO_MODE_OFF;
  86 + break;
  87 + case OPMODE_STANDBY:
  88 + switch (ldo) {
  89 + case 2:
  90 + case 6:
  91 + case 7:
  92 + case 8:
  93 + case 10:
  94 + case 11:
  95 + case 12:
  96 + case 14:
  97 + case 15:
  98 + case 16:
  99 + mode = MAX77686_LDO_MODE_STANDBY;
  100 + break;
  101 + default:
  102 + mode = 0xff;
  103 + }
  104 + break;
  105 + case OPMODE_LPM:
  106 + mode = MAX77686_LDO_MODE_LPM;
  107 + break;
  108 + case OPMODE_ON:
  109 + mode = MAX77686_LDO_MODE_ON;
  110 + break;
  111 + default:
  112 + mode = 0xff;
  113 + }
  114 +
  115 + if (mode == 0xff) {
  116 + printf("%s: %d is not supported on LDO%d\n",
  117 + __func__, opmode, ldo);
  118 + return -1;
  119 + }
  120 +
  121 + ret = pmic_reg_read(p, adr, &val);
  122 + if (ret)
  123 + return ret;
  124 +
  125 + val &= ~MAX77686_LDO_MODE_MASK;
  126 + val |= mode;
  127 + ret |= pmic_reg_write(p, adr, val);
  128 +
  129 + return ret;
  130 +}
  131 +
  132 +int max77686_set_buck_mode(struct pmic *p, int buck, char opmode)
  133 +{
  134 + unsigned int val, ret, mask, adr, size, mode, mode_shift;
  135 +
  136 + size = ARRAY_SIZE(max77686_buck_addr);
  137 + if (buck >= size) {
  138 + printf("%s: %d is wrong buck number\n", __func__, buck);
  139 + return -1;
  140 + }
  141 +
  142 + adr = max77686_buck_addr[buck];
  143 +
  144 + /* mask */
  145 + switch (buck) {
  146 + case 2:
  147 + case 3:
  148 + case 4:
  149 + mode_shift = MAX77686_BUCK_MODE_SHIFT_2;
  150 + break;
  151 + default:
  152 + mode_shift = MAX77686_BUCK_MODE_SHIFT_1;
  153 + }
  154 +
  155 + mask = MAX77686_BUCK_MODE_MASK << mode_shift;
  156 +
  157 + /* mode */
  158 + switch (opmode) {
  159 + case OPMODE_OFF:
  160 + mode = MAX77686_BUCK_MODE_OFF;
  161 + break;
  162 + case OPMODE_STANDBY:
  163 + switch (buck) {
  164 + case 1:
  165 + case 2:
  166 + case 3:
  167 + case 4:
  168 + mode = MAX77686_BUCK_MODE_STANDBY << mode_shift;
  169 + break;
  170 + default:
  171 + mode = 0xff;
  172 + }
  173 + break;
  174 + case OPMODE_LPM:
  175 + switch (buck) {
  176 + case 2:
  177 + case 3:
  178 + case 4:
  179 + mode = MAX77686_BUCK_MODE_LPM << mode_shift;
  180 + break;
  181 + default:
  182 + mode = 0xff;
  183 + }
  184 + break;
  185 + case OPMODE_ON:
  186 + mode = MAX77686_BUCK_MODE_ON << mode_shift;
  187 + break;
  188 + default:
  189 + mode = 0xff;
  190 + }
  191 +
  192 + if (mode == 0xff) {
  193 + printf("%s: %d is not supported on BUCK%d\n",
  194 + __func__, opmode, buck);
  195 + return -1;
  196 + }
  197 +
  198 + ret = pmic_reg_read(p, adr, &val);
  199 + if (ret)
  200 + return ret;
  201 +
  202 + val &= ~mask;
  203 + val |= mode;
  204 + ret |= pmic_reg_write(p, adr, val);
  205 +
  206 + return ret;
  207 +}
  208 +
17 209 int pmic_init(unsigned char bus)
18 210 {
19 211 static const char name[] = "MAX77686_PMIC";
include/configs/arndale.h
Diff comments   View file @ 7bcee5f
  1 +/*
  2 + * Copyright (C) 2013 Samsung Electronics
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + *
  6 + * Configuration settings for the SAMSUNG Arndale board.
  7 + */
  8 +
  9 +#ifndef __CONFIG_ARNDALE_H
  10 +#define __CONFIG_ARNDALE_H
  11 +
  12 +/* High Level Configuration Options */
  13 +#define CONFIG_SAMSUNG /* in a SAMSUNG core */
  14 +#define CONFIG_S5P /* S5P Family */
  15 +#define CONFIG_EXYNOS5 /* which is in a Exynos5 Family */
  16 +#define CONFIG_EXYNOS5250
  17 +
  18 +#include <asm/arch/cpu.h> /* get chip and board defs */
  19 +
  20 +#define CONFIG_SYS_GENERIC_BOARD
  21 +#define CONFIG_ARCH_CPU_INIT
  22 +#define CONFIG_DISPLAY_CPUINFO
  23 +#define CONFIG_DISPLAY_BOARDINFO
  24 +
  25 +/* Enable fdt support for Exynos5250 */
  26 +#define CONFIG_ARCH_DEVICE_TREE exynos5250
  27 +#define CONFIG_OF_CONTROL
  28 +#define CONFIG_OF_SEPARATE
  29 +
  30 +/* Allow tracing to be enabled */
  31 +#define CONFIG_TRACE
  32 +#define CONFIG_CMD_TRACE
  33 +#define CONFIG_TRACE_BUFFER_SIZE (16 << 20)
  34 +#define CONFIG_TRACE_EARLY_SIZE (8 << 20)
  35 +#define CONFIG_TRACE_EARLY
  36 +#define CONFIG_TRACE_EARLY_ADDR 0x50000000
  37 +
  38 +/* Keep L2 Cache Disabled */
  39 +#define CONFIG_SYS_DCACHE_OFF
  40 +
  41 +#define CONFIG_SYS_SDRAM_BASE 0x40000000
  42 +#define CONFIG_SYS_TEXT_BASE 0x43E00000
  43 +
  44 +/* input clock of PLL: SMDK5250 has 24MHz input clock */
  45 +#define CONFIG_SYS_CLK_FREQ 24000000
  46 +
  47 +#define CONFIG_SETUP_MEMORY_TAGS
  48 +#define CONFIG_CMDLINE_TAG
  49 +#define CONFIG_INITRD_TAG
  50 +#define CONFIG_CMDLINE_EDITING
  51 +
  52 +/* Power Down Modes */
  53 +#define S5P_CHECK_SLEEP 0x00000BAD
  54 +#define S5P_CHECK_DIDLE 0xBAD00000
  55 +#define S5P_CHECK_LPA 0xABAD0000
  56 +
  57 +/* Offset for inform registers */
  58 +#define INFORM0_OFFSET 0x800
  59 +#define INFORM1_OFFSET 0x804
  60 +
  61 +/* Size of malloc() pool */
  62 +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20))
  63 +
  64 +/* select serial console configuration */
  65 +#define CONFIG_BAUDRATE 115200
  66 +#define EXYNOS5_DEFAULT_UART_OFFSET 0x010000
  67 +#define CONFIG_SILENT_CONSOLE
  68 +
  69 +/* Console configuration */
  70 +#define CONFIG_CONSOLE_MUX
  71 +#define CONFIG_SYS_CONSOLE_IS_IN_ENV
  72 +#define EXYNOS_DEVICE_SETTINGS \
  73 + "stdin=serial\0" \
  74 + "stdout=serial\0" \
  75 + "stderr=serial\0"
  76 +
  77 +#define CONFIG_EXTRA_ENV_SETTINGS \
  78 + EXYNOS_DEVICE_SETTINGS
  79 +
  80 +/* SD/MMC configuration */
  81 +#define CONFIG_GENERIC_MMC
  82 +#define CONFIG_MMC
  83 +#define CONFIG_SDHCI
  84 +#define CONFIG_S5P_SDHCI
  85 +#define CONFIG_DWMMC
  86 +#define CONFIG_EXYNOS_DWMMC
  87 +#define CONFIG_SUPPORT_EMMC_BOOT
  88 +
  89 +
  90 +#define CONFIG_BOARD_EARLY_INIT_F
  91 +#define CONFIG_SKIP_LOWLEVEL_INIT
  92 +
  93 +/* PWM */
  94 +#define CONFIG_PWM
  95 +
  96 +/* allow to overwrite serial and ethaddr */
  97 +#define CONFIG_ENV_OVERWRITE
  98 +
  99 +/* Command definition*/
  100 +#include <config_cmd_default.h>
  101 +
  102 +#define CONFIG_CMD_PING
  103 +#define CONFIG_CMD_ELF
  104 +#define CONFIG_CMD_MMC
  105 +#define CONFIG_CMD_EXT2
  106 +#define CONFIG_CMD_FAT
  107 +#define CONFIG_CMD_NET
  108 +#define CONFIG_CMD_HASH
  109 +
  110 +#define CONFIG_BOOTDELAY 3
  111 +#define CONFIG_ZERO_BOOTDELAY_CHECK
  112 +
  113 +/* USB */
  114 +#define CONFIG_CMD_USB
  115 +#define CONFIG_USB_EHCI
  116 +#define CONFIG_USB_EHCI_EXYNOS
  117 +#define CONFIG_USB_STORAGE
  118 +
  119 +/* MMC SPL */
  120 +#define CONFIG_SPL
  121 +#define COPY_BL2_FNPTR_ADDR 0x02020030
  122 +
  123 +#define CONFIG_SPL_LIBCOMMON_SUPPORT
  124 +
  125 +/* specific .lds file */
  126 +#define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds"
  127 +#define CONFIG_SPL_TEXT_BASE 0x02023400
  128 +#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024)
  129 +
  130 +#define CONFIG_BOOTCOMMAND "mmc read 40007000 451 2000; bootm 40007000"
  131 +
  132 +/* Miscellaneous configurable options */
  133 +#define CONFIG_SYS_LONGHELP /* undef to save memory */
  134 +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
  135 +#define CONFIG_SYS_PROMPT "ARNDALE # "
  136 +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  137 +#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
  138 +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  139 +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
  140 +/* Boot Argument Buffer Size */
  141 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  142 +/* memtest works on */
  143 +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
  144 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000)
  145 +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
  146 +
  147 +#define CONFIG_SYS_HZ 1000
  148 +
  149 +#define CONFIG_RD_LVL
  150 +
  151 +#define CONFIG_NR_DRAM_BANKS 8
  152 +#define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */
  153 +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
  154 +#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE
  155 +#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE)
  156 +#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE
  157 +#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE))
  158 +#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE
  159 +#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE))
  160 +#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE
  161 +#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE))
  162 +#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE
  163 +#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE))
  164 +#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE
  165 +#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE))
  166 +#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE
  167 +#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE))
  168 +#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE
  169 +
  170 +#define CONFIG_SYS_MONITOR_BASE 0x00000000
  171 +
  172 +/* FLASH and environment organization */
  173 +#define CONFIG_SYS_NO_FLASH
  174 +#undef CONFIG_CMD_IMLS
  175 +#define CONFIG_IDENT_STRING " for ARNDALE"
  176 +
  177 +#define CONFIG_SYS_MMC_ENV_DEV 0
  178 +
  179 +#define CONFIG_ENV_IS_IN_MMC
  180 +#define CONFIG_SECURE_BL1_ONLY
  181 +
  182 +/* Secure FW size configuration */
  183 +#ifdef CONFIG_SECURE_BL1_ONLY
  184 +#define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */
  185 +#else
  186 +#define CONFIG_SEC_FW_SIZE 0
  187 +#endif
  188 +
  189 +/* Configuration of BL1, BL2, ENV Blocks on mmc */
  190 +#define CONFIG_RES_BLOCK_SIZE (512)
  191 +#define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/
  192 +#define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */
  193 +#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */
  194 +
  195 +#define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE)
  196 +#define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
  197 +#define CONFIG_ENV_OFFSET (CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE)
  198 +
  199 +/* U-boot copy size from boot Media to DRAM.*/
  200 +#define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512)
  201 +#define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512)
  202 +
  203 +#define CONFIG_SPI_BOOTING
  204 +#define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058
  205 +#define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
  206 +
  207 +#define CONFIG_DOS_PARTITION
  208 +#define CONFIG_EFI_PARTITION
  209 +#define CONFIG_CMD_PART
  210 +#define CONFIG_PARTITION_UUIDS
  211 +
  212 +
  213 +#define CONFIG_IRAM_STACK 0x02050000
  214 +
  215 +#define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_STACK
  216 +
  217 +/* I2C */
  218 +#define CONFIG_SYS_I2C_INIT_BOARD
  219 +#define CONFIG_HARD_I2C
  220 +#define CONFIG_CMD_I2C
  221 +#define CONFIG_SYS_I2C_SPEED 100000 /* 100 Kbps */
  222 +#define CONFIG_DRIVER_S3C24X0_I2C
  223 +#define CONFIG_I2C_MULTI_BUS
  224 +#define CONFIG_MAX_I2C_NUM 8
  225 +#define CONFIG_SYS_I2C_SLAVE 0x0
  226 +#define CONFIG_I2C_EDID
  227 +
  228 +/* PMIC */
  229 +#define CONFIG_PMIC
  230 +#define CONFIG_PMIC_I2C
  231 +#define CONFIG_PMIC_MAX77686
  232 +
  233 +#define CONFIG_DEFAULT_DEVICE_TREE exynos5250-arndale
  234 +
  235 +/* Ethernet Controllor Driver */
  236 +#ifdef CONFIG_CMD_NET
  237 +#define CONFIG_SMC911X
  238 +#define CONFIG_SMC911X_BASE 0x5000000
  239 +#define CONFIG_SMC911X_16_BIT
  240 +#define CONFIG_ENV_SROM_BANK 1
  241 +#endif /*CONFIG_CMD_NET*/
  242 +
  243 +/* Enable PXE Support */
  244 +#ifdef CONFIG_CMD_NET
  245 +#define CONFIG_CMD_PXE
  246 +#define CONFIG_MENU
  247 +#endif
  248 +
  249 +/* Enable devicetree support */
  250 +#define CONFIG_OF_LIBFDT
  251 +
  252 +/* Enable Time Command */
  253 +#define CONFIG_CMD_TIME
  254 +
  255 +#endif /* __CONFIG_H */
include/configs/exynos5250-dt.h
Diff comments   View file @ 7bcee5f
... ... @@ -13,7 +13,7 @@
13 13 #define CONFIG_SAMSUNG /* in a SAMSUNG core */
14 14 #define CONFIG_S5P /* S5P Family */
15 15 #define CONFIG_EXYNOS5 /* which is in a Exynos5 Family */
16   -#define CONFIG_SMDK5250 /* which is in a SMDK5250 */
  16 +#define CONFIG_EXYNOS5250
17 17  
18 18 #include <asm/arch/cpu.h> /* get chip and board defs */
19 19  
include/configs/s5p_goni.h
Diff comments   View file @ 7bcee5f
... ... @@ -29,6 +29,9 @@
29 29 /* DRAM Base */
30 30 #define CONFIG_SYS_SDRAM_BASE 0x30000000
31 31  
  32 +/* Text Base */
  33 +#define CONFIG_SYS_TEXT_BASE 0x34800000
  34 +
32 35 #define CONFIG_SETUP_MEMORY_TAGS
33 36 #define CONFIG_CMDLINE_TAG
34 37 #define CONFIG_INITRD_TAG
include/configs/smdkc100.h
Diff comments   View file @ 7bcee5f
... ... @@ -34,6 +34,9 @@
34 34 /* DRAM Base */
35 35 #define CONFIG_SYS_SDRAM_BASE 0x30000000
36 36  
  37 +/* Text Base */
  38 +#define CONFIG_SYS_TEXT_BASE 0x34800000
  39 +
37 40 #define CONFIG_SETUP_MEMORY_TAGS
38 41 #define CONFIG_CMDLINE_TAG
39 42 #define CONFIG_INITRD_TAG
include/power/max77686_pmic.h
Diff comments   View file @ 7bcee5f
... ... @@ -139,6 +139,32 @@
139 139 EN_LDO = (0x3 << 6),
140 140 };
141 141  
  142 +enum {
  143 + OPMODE_OFF = 0,
  144 + OPMODE_STANDBY,
  145 + OPMODE_LPM,
  146 + OPMODE_ON,
  147 +};
  148 +
  149 +int max77686_set_ldo_voltage(struct pmic *p, int ldo, ulong uV);
  150 +int max77686_set_ldo_mode(struct pmic *p, int ldo, char opmode);
  151 +int max77686_set_buck_mode(struct pmic *p, int buck, char opmode);
  152 +
  153 +#define MAX77686_LDO_VOLT_MAX_HEX 0x3f
  154 +#define MAX77686_LDO_VOLT_MASK 0x3f
  155 +#define MAX77686_LDO_MODE_MASK 0xc0
  156 +#define MAX77686_LDO_MODE_OFF (0x00 << 0x06)
  157 +#define MAX77686_LDO_MODE_STANDBY (0x01 << 0x06)
  158 +#define MAX77686_LDO_MODE_LPM (0x02 << 0x06)
  159 +#define MAX77686_LDO_MODE_ON (0x03 << 0x06)
  160 +#define MAX77686_BUCK_MODE_MASK 0x03
  161 +#define MAX77686_BUCK_MODE_SHIFT_1 0x00
  162 +#define MAX77686_BUCK_MODE_SHIFT_2 0x04
  163 +#define MAX77686_BUCK_MODE_OFF 0x00
  164 +#define MAX77686_BUCK_MODE_STANDBY 0x01
  165 +#define MAX77686_BUCK_MODE_LPM 0x02
  166 +#define MAX77686_BUCK_MODE_ON 0x03
  167 +
142 168 /* Buck1 1 volt value */
143 169 #define MAX77686_BUCK1OUT_1V 0x5
144 170 /* Buck1 1.05 volt value */
... ... @@ -52,7 +52,7 @@
52 52 BIN_FILES-$(CONFIG_XWAY_SWAP_BYTES) += xway-swap-bytes$(SFX)
53 53 BIN_FILES-y += mkenvimage$(SFX)
54 54 BIN_FILES-y += mkimage$(SFX)
55   -BIN_FILES-$(CONFIG_SMDK5250) += mksmdk5250spl$(SFX)
  55 +BIN_FILES-$(CONFIG_EXYNOS5250) += mk$(BOARD)spl$(SFX)
56 56 BIN_FILES-$(CONFIG_MX23) += mxsboot$(SFX)
57 57 BIN_FILES-$(CONFIG_MX28) += mxsboot$(SFX)
58 58 BIN_FILES-$(CONFIG_NETCONSOLE) += ncb$(SFX)
... ... @@ -87,6 +87,7 @@
87 87 OBJ_FILES-$(CONFIG_BUILD_ENVCRC) += envcrc.o
88 88 OBJ_FILES-$(CONFIG_CMD_LOADS) += img2srec.o
89 89 OBJ_FILES-$(CONFIG_CMD_NET) += gen_eth_addr.o
  90 +OBJ_FILES-$(CONFIG_EXYNOS5250) += mkexynosspl.o
90 91 OBJ_FILES-$(CONFIG_KIRKWOOD) += kwboot.o
91 92 OBJ_FILES-$(CONFIG_LCD_LOGO) += bmp_logo.o
92 93 OBJ_FILES-$(CONFIG_MX23) += mxsboot.o