MLK-19181-2: i.MX850: SPL enable usb support

Enable DWC3 USB support at i.MX850D platform Signed-off-by: Frank Li <Frank.Li@nxp.com>

MLK-19181-2: i.MX850: SPL enable usb support
Enable DWC3 USB support at i.MX850D platform Signed-off-by: Frank Li <Frank.Li@nxp.com>
Frank Li · Eric Lee · Eric Lee · Eric Lee · Eric Lee · Eric Lee
1 parent ab6696c4f7
Showing 3 changed files with 57 additions and 2 deletions Side-by-side Diff
arch/arm/mach-imx/imx8m/soc.c
board/freescale/common/tcpc.h
board/freescale/imx8mq_evk/spl.c
@@ -410,18 +410,58 @@
  
 #define FSL_SIP_GPC			0xC2000000
 #define FSL_SIP_CONFIG_GPC_PM_DOMAIN	0x03
+
+#ifdef CONFIG_SPL_BUILD
+static uint32_t gpc_pu_m_core_offset[11] = {
+	0xc00, 0xc40, 0xc80, 0xcc0,
+	0xdc0, 0xe00, 0xe40, 0xe80,
+	0xec0, 0xf00, 0xf40,
+};
+
+#define PGC_PCR				0
+
+void imx_gpc_set_m_core_pgc(unsigned int offset, bool pdn)
+{
+	uintptr_t val;
+
+	val = readl(GPC_BASE_ADDR + offset);
+	val &= ~(0x1 << PGC_PCR);
+
+	if(pdn)
+		val |= 0x1 << PGC_PCR;
+	writel(val, GPC_BASE_ADDR + offset);
+}
+
+void imx8m_usb_power_domain(uint32_t domain_id, bool on)
+{
+	uint32_t val;
+	uintptr_t reg;
+
+	imx_gpc_set_m_core_pgc(gpc_pu_m_core_offset[domain_id], true);
+
+	reg = GPC_BASE_ADDR + (on ? 0xf8 : 0x104);
+	val = 1 << (domain_id > 3 ? (domain_id + 3) : domain_id);
+	writel(val, reg);
+	while (readl(reg) & val)
+		;
+	imx_gpc_set_m_core_pgc(gpc_pu_m_core_offset[domain_id], false);
+}
+#endif
+
 int imx8m_usb_power(int usb_id, bool on)
 {
 	unsigned long ret;
  
 	if (usb_id > 1)
 		return -EINVAL;
-
+#ifdef CONFIG_SPL_BUILD
+	imx8m_usb_power_domain(2 + usb_id, on);
+#else
 	ret = call_imx_sip(FSL_SIP_GPC,
 			FSL_SIP_CONFIG_GPC_PM_DOMAIN, 2 + usb_id, on, 0);
 	if (ret)
 		return -EPERM;
-
+#endif
 	return 0;
 }
@@ -451,5 +451,17 @@
 bool tcpc_pd_sink_check_charging(struct tcpc_port *port);
 void tcpc_print_log(struct tcpc_port *port);
  
+#ifdef CONFIG_SPL_BUILD
+int tcpc_setup_ufp_mode(struct tcpc_port *port)
+{
+	return 0;
+}
+#endif
+#ifdef CONFIG_SPL_BUILD
+int tcpc_setup_dfp_mode(struct tcpc_port *port)
+{
+	return 0;
+}
+#endif
 #endif /* __TCPCI_H */
@@ -197,11 +197,14 @@
 	/* DDR initialization */
 	spl_dram_init();
  
+#ifndef CONFIG_SPL_USB_SDP_SUPPORT
 	/* Serial download mode */
 	if (is_usb_boot()) {
 		puts("Back to ROM, SDP\n");
 		restore_boot_params();
 	}
+#endif
+
 	puts("Normal Boot\n");
 }
...	...	@@ -410,18 +410,58 @@
410	410
411	411	#define FSL_SIP_GPC 0xC2000000
412	412	#define FSL_SIP_CONFIG_GPC_PM_DOMAIN 0x03
	413	+
	414	+#ifdef CONFIG_SPL_BUILD
	415	+static uint32_t gpc_pu_m_core_offset[11] = {
	416	+ 0xc00, 0xc40, 0xc80, 0xcc0,
	417	+ 0xdc0, 0xe00, 0xe40, 0xe80,
	418	+ 0xec0, 0xf00, 0xf40,
	419	+};
	420	+
	421	+#define PGC_PCR 0
	422	+
	423	+void imx_gpc_set_m_core_pgc(unsigned int offset, bool pdn)
	424	+{
	425	+ uintptr_t val;
	426	+
	427	+ val = readl(GPC_BASE_ADDR + offset);
	428	+ val &= ~(0x1 << PGC_PCR);
	429	+
	430	+ if(pdn)
	431	+ val \|= 0x1 << PGC_PCR;
	432	+ writel(val, GPC_BASE_ADDR + offset);
	433	+}
	434	+
	435	+void imx8m_usb_power_domain(uint32_t domain_id, bool on)
	436	+{
	437	+ uint32_t val;
	438	+ uintptr_t reg;
	439	+
	440	+ imx_gpc_set_m_core_pgc(gpc_pu_m_core_offset[domain_id], true);
	441	+
	442	+ reg = GPC_BASE_ADDR + (on ? 0xf8 : 0x104);
	443	+ val = 1 << (domain_id > 3 ? (domain_id + 3) : domain_id);
	444	+ writel(val, reg);
	445	+ while (readl(reg) & val)
	446	+ ;
	447	+ imx_gpc_set_m_core_pgc(gpc_pu_m_core_offset[domain_id], false);
	448	+}
	449	+#endif
	450	+
413	451	int imx8m_usb_power(int usb_id, bool on)
414	452	{
415	453	unsigned long ret;
416	454
417	455	if (usb_id > 1)
418	456	return -EINVAL;
419		-
	457	+#ifdef CONFIG_SPL_BUILD
	458	+ imx8m_usb_power_domain(2 + usb_id, on);
	459	+#else
420	460	ret = call_imx_sip(FSL_SIP_GPC,
421	461	FSL_SIP_CONFIG_GPC_PM_DOMAIN, 2 + usb_id, on, 0);
422	462	if (ret)
423	463	return -EPERM;
424		-
	464	+#endif
425	465	return 0;
426	466	}
...	...	@@ -451,5 +451,17 @@
451	451	bool tcpc_pd_sink_check_charging(struct tcpc_port *port);
452	452	void tcpc_print_log(struct tcpc_port *port);
453	453
	454	+#ifdef CONFIG_SPL_BUILD
	455	+int tcpc_setup_ufp_mode(struct tcpc_port *port)
	456	+{
	457	+ return 0;
	458	+}
	459	+#endif
	460	+#ifdef CONFIG_SPL_BUILD
	461	+int tcpc_setup_dfp_mode(struct tcpc_port *port)
	462	+{
	463	+ return 0;
	464	+}
	465	+#endif
454	466	#endif /* __TCPCI_H */
...	...	@@ -197,11 +197,14 @@
197	197	/* DDR initialization */
198	198	spl_dram_init();
199	199
	200	+#ifndef CONFIG_SPL_USB_SDP_SUPPORT
200	201	/* Serial download mode */
201	202	if (is_usb_boot()) {
202	203	puts("Back to ROM, SDP\n");
203	204	restore_boot_params();
204	205	}
	206	+#endif
	207	+
205	208	puts("Normal Boot\n");
206	209	}
207	210