Eric Lee / smarc-uboot | Embedian Git Server

Commit 7c7a23bd5a0bc149d2edd665ec46381726b24e0c

Authored by wdenk 2002-12-07 08:20:59 +0800

Exists in master and in 54 other branches

* Patch by Hans-Joerg Frieden, 06 Dec 2002

Fix misc problems with AmigaOne support

* Patch by Chris Hallinan, 3 Dec 2002:
  minor cleanup to the MPC8245 EPIC driver

* Patch by Pierre Aubert , 28 Nov 2002
  Add support for external (SIU) interrupts on MPC8xx

* Patch by Pierre Aubert , 28 Nov 2002
  Fix nested syscalls bug in standalone applications

* Patch by David Müller, 27 Nov 2002:
  fix output of "pciinfo" command for CardBus bridge devices.

* Fix bug in TQM8260 board detection - boards got stuck when board ID
  was not readable

Showing 30 changed files with 589 additions and 262 deletions Inline Diff

CHANGELOG
board/MAI/AmigaOneG3SE/AmigaOneG3SE.c
board/MAI/AmigaOneG3SE/Makefile
board/MAI/AmigaOneG3SE/articiaS.c
board/MAI/AmigaOneG3SE/articiaS_pci.c
board/MAI/AmigaOneG3SE/config.mk
board/MAI/AmigaOneG3SE/video.c
board/MAI/bios_emulator/glue.c
board/MAI/bios_emulator/scitech/src/x86emu/makefile.uboot
board/MAI/bios_emulator/x86interface.c
board/MAI/menu/cmd_menu.c
board/hermes/u-boot.lds
board/tqm8260/tqm8260.c
board/trab/vfd.c
common/cmd_pci.c
common/env_common.c
common/env_nvram.c
cpu/74xx_7xx/start.S
cpu/mpc824x/drivers/epic/epic.h
cpu/mpc824x/drivers/epic/epic1.c
cpu/mpc824x/interrupts.c
cpu/mpc824x/start.S
cpu/mpc8260/start.S
cpu/mpc8xx/interrupts.c
cpu/mpc8xx/start.S
cpu/ppc4xx/start.S
examples/timer.c
include/commproc.h
include/configs/AmigaOneG3SE.h
lib_ppc/board.c

CHANGELOG

Diff comments View file @ 7c7a23b

 ======================================================================
 Changes since for U-Boot 0.1.0:
 ======================================================================
+* Patch by Hans-Joerg Frieden, 06 Dec 2002
+  Fix misc problems with AmigaOne support
+* Patch by Chris Hallinan, 3 Dec 2002:
+  minor cleanup to the MPC8245 EPIC driver
+* Patch by Pierre Aubert , 28 Nov 2002
+  Add support for external (SIU) interrupts on MPC8xx
+* Patch by Pierre Aubert , 28 Nov 2002
+  Fix nested syscalls bug in standalone applications
+* Patch by David Müller, 27 Nov 2002:
+  fix output of "pciinfo" command for CardBus bridge devices.
+* Fix bug in TQM8260 board detection - boards got stuck when board ID
+  was not readable
 * Add LED indication for IDE activity on KUP4K board
 * Fix startup problems with VFD display on TRAB
 * Patch by Pierre Aubert, 20 Nov 2002
   Add driver for Epson SED13806 graphic controller.
   Add support for BMP logos in cfb_console driver.
 * Added support for both PCMCIA slots (at the same time!) on MPC8xx
 * Patch by Rod Boyce, 21 Nov 2002:
   fix PCMCIA on MBX8xx board
 * Patch by Pierre Aubert , 21 Nov 2002
   Add CFG_CPM_POST_WORD_ADDR to make the offset of the
   bootmode word in DPRAM configurable
 * Patch by Daniel Engström, 18 Nov 2002:
   Fixes for x86 port (mostly strings issues)
 * Patch by Ken Chou, 18 Nov 2002:
   Fix for natsemi NIC cards (DP83815)
 * Patch by Pierre Aubert, 19 Nov 2002:
   fix a bug for the MII configuration, and some warnings
 * Patch by Thomas Frieden, 13 Nov 2002:
   Add code for AmigaOne board
   (preliminary merge to U-Boot, still WIP)
 * Patch by Jon Diekema, 12 Nov 2002:
   - Adding URL for IEEE OUI lookup
   - Making the autoboot #defines dependent on CONFIG_AUTOBOOT_KEYED
     being defined.
   - In the CONFIG_EXTRA_ENV_SETTINGS #define, the root-on-initrd and
     root-on-nfs macros are designed to switch how the default boot
     method gets defined.
 * Patch by Daniel Engström, 13 Nov 2002:
   Add support for i386 architecture and AMD SC520 board
 * Patch by Pierre Aubert, 12 Nov 2002:
   Add support for DOS filesystem and booting from DOS floppy disk
 * Patch by Jim Sandoz, 07 Nov 2002:
   Increase number of network RX buffers (PKTBUFSRX in
   "include/net.h") for EEPRO100 based boards (especially SP8240)
   which showed "Receiver is not ready" errors when U-Boot was
   processing the receive buffers slower than the network controller
   was filling them.
 * Patch by Andreas Oberritter, 09 Nov 2002:
   Change behaviour of NetLoop(): return -1 for errors, filesize
   otherwise; return code 0 is valid an means no file loaded - in this
   case the environment still gets updated!
 * Patches by Jon Diekema, 9 Nov 2002:
   - improve ADC/DAC clocking on the SACSng board to align
     the failing edges of LRCLK and SCLK
   - sbc8260 configuration tweaks
   - add status LED support for 82xx systems
   - wire sspi/sspo commands into command handler; improved error
     handlering
   - add timestamp support and alternate memory test to the
     SACSng configuration
 * Patch by Vince Husovsky, 7 Nov 2002:
   Add "-n" to linker options to get rid of "Not enough room for
   program headers" problem
 * Patch by David Müller, 05 Nov 2002
   Rename CONFIG_PLL_INPUT_FREQ to CONFIG_SYS_CLK_FREQ
   so we can use an already existing name
 * Patch by Pierre Aubert, 05 Nov 2002
   Hardware relatied improvments in FDC boot code
 * Patch by Holger Schurig, 5 Nov 2002:
   Make the PXA really change it's frequency
 * Patch by Pierre Aubert, 05 Nov 2002
   Add support for slave serial Spartan 2 FPGAs
 * Fix uninitialized memory (MAC  address)  in  8xx  SCC/FEC  ethernet
   drivers
 * Add support for log buffer which can be passed to Linux kernel's
   syslog mechanism; used especially for POST results.
 * Patch by Klaus Heydeck, 31 Oct 2002:
   Add initial support for kup4k board
 * Patch by Robert Schwebel, 04 Nov 2002:
   - use watchdog to reset PXA250 systems
   - added progress callbacks to (some of the) ARM code
   - update for Cogent CSB226 board
 * Add support for FPS860 board
 * Patch by Guillaume Alexandre,, 04 Nov 2002:
   Improve PCI access on 32-bits Compact PCI bus
 * Fix mdelay() on TRAB - this was still the debugging version with
   seconds instead of ms.
 * Patch by Robert Schwebel, 1 Nov 2002:
   XScale related cleanup (affects all ARM boards)
 * Cleanup of names and README.
 ======================================================================
 Notes for U-Boot 0.1.0:
 ======================================================================
 This is the initial version of "Das U-Boot", the Universal Boot Loader.
 It is based on version 2.0.0 (the "Halloween Release") of PPCBoot.
 For information about the history of the project please see the
 PPCBoot project page at http://sourceforge.net/projects/ppcboot
 ======================================================================

board/MAI/AmigaOneG3SE/AmigaOneG3SE.c

Diff comments View file @ 7c7a23b

1	/*	1	/*
2	* (C) Copyright 2002	2	* (C) Copyright 2002
3	* Hyperion Entertainment, ThomasF@hyperion-entertainment.com	3	* Hyperion Entertainment, ThomasF@hyperion-entertainment.com
4	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.	4	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5	*	5	*
6	* See file CREDITS for list of people who contributed to this	6	* See file CREDITS for list of people who contributed to this
7	* project.	7	* project.
8	*	8	*
9	* This program is free software; you can redistribute it and/or	9	* This program is free software; you can redistribute it and/or
10	* modify it under the terms of the GNU General Public License as	10	* modify it under the terms of the GNU General Public License as
11	* published by the Free Software Foundation; either version 2 of	11	* published by the Free Software Foundation; either version 2 of
12	* the License, or (at your option) any later version.	12	* the License, or (at your option) any later version.
13	*	13	*
14	* This program is distributed in the hope that it will be useful,	14	* This program is distributed in the hope that it will be useful,
15	* but WITHOUT ANY WARRANTY; without even the implied warranty of	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17	* GNU General Public License for more details.	17	* GNU General Public License for more details.
18	*	18	*
19	* You should have received a copy of the GNU General Public License	19	* You should have received a copy of the GNU General Public License
20	* along with this program; if not, write to the Free Software	20	* along with this program; if not, write to the Free Software
21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22	* MA 02111-1307 USA	22	* MA 02111-1307 USA
23	*/	23	*/
24		24
25	#include <common.h>	25	#include <common.h>
26	#include <command.h>	26	#include <command.h>
27	#include <pci.h>	27	#include <pci.h>
28	#include "articiaS.h"	28	#include "articiaS.h"
29	#include "memio.h"	29	#include "memio.h"
30	#include "via686.h"	30	#include "via686.h"
31		31
32	__asm(" .globl send_kb \n	32	__asm(" .globl send_kb \n
33	send_kb: \n	33	send_kb: \n
34	lis r9, 0xfe00 \n	34	lis r9, 0xfe00 \n
35	\n	35	\n
36	li r4, 0x10 # retries \n	36	li r4, 0x10 # retries \n
37	mtctr r4 \n	37	mtctr r4 \n
38	\n	38	\n
39	idle: \n	39	idle: \n
40	lbz r4, 0x64(r9) \n	40	lbz r4, 0x64(r9) \n
41	andi. r4, r4, 0x02 \n	41	andi. r4, r4, 0x02 \n
42	bne idle \n	42	bne idle \n
43	\n	43	\n
44	ready: \n	44	ready: \n
45	stb r3, 0x60(r9) \n	45	stb r3, 0x60(r9) \n
46	\n	46	\n
47	check: \n	47	check: \n
48	lbz r4, 0x64(r9) \n	48	lbz r4, 0x64(r9) \n
49	andi. r4, r4, 0x01 \n	49	andi. r4, r4, 0x01 \n
50	beq check \n	50	beq check \n
51	\n	51	\n
52	lbz r4, 0x60(r9) \n	52	lbz r4, 0x60(r9) \n
53	cmpwi r4, 0xfa \n	53	cmpwi r4, 0xfa \n
54	beq done \n	54	beq done \n
55	\n	55	\n
56	bdnz idle \n	56	bdnz idle \n
57	\n	57	\n
58	li r3, 0 \n	58	li r3, 0 \n
59	blr \n	59	blr \n
60	\n	60	\n
61	done: \n	61	done: \n
62	li r3, 1 \n	62	li r3, 1 \n
63	blr \n	63	blr \n
64	\n	64	\n
65	.globl test_kb \n	65	.globl test_kb \n
66	test_kb: \n	66	test_kb: \n
67	mflr r10 \n	67	mflr r10 \n
68	li r3, 0xed \n	68	li r3, 0xed \n
69	bl send_kb \n	69	bl send_kb \n
70	li r3, 0x01 \n	70	li r3, 0x01 \n
71	bl send_kb \n	71	bl send_kb \n
72	mtlr r10 \n	72	mtlr r10 \n
73	blr \n	73	blr \n
74	");	74	");
75		75
76		76
77	int checkboard (void)	77	int checkboard (void)
78	{	78	{
79	printf ("AmigaOneG3SE\n");	79	printf ("Board: AmigaOneG3SE\n");
80		80	return 0;
81	return 1;
82	}	81	}
83		82
84	long initdram (int board_type)	83	long initdram (int board_type)
85	{	84	{
86	return articiaS_ram_init ();	85	return articiaS_ram_init ();
87	}	86	}
88		87
89		88
90		89
91	void after_reloc (ulong dest_addr)	90	void after_reloc (ulong dest_addr, gd_t *gd)
92	{	91	{
93	DECLARE_GLOBAL_DATA_PTR;	92	/* HJF: DECLARE_GLOBAL_DATA_PTR; */
94		93
95	board_init_r (gd, dest_addr);	94	board_init_r (gd, dest_addr);
96	}	95	}
97		96
98		97
99	int misc_init_r (void)	98	int misc_init_r (void)
100	{	99	{
101	extern pci_dev_t video_dev;	100	extern pci_dev_t video_dev;
102	extern void drv_video_init (void);	101	extern void drv_video_init (void);
103		102
104	if (video_dev != ~0)	103	if (video_dev != ~0)
105	drv_video_init ();	104	drv_video_init ();
106		105
107	return (0);	106	return (0);
108	}	107	}
109		108
110		109
111	void pci_init (void)	110	void pci_init (void)
112	{	111	{
113	#ifndef CONFIG_RAMBOOT	112	#ifndef CONFIG_RAMBOOT
114	articiaS_pci_init ();	113	articiaS_pci_init ();
115	#endif	114	#endif
116	}	115	}
117		116

board/MAI/AmigaOneG3SE/Makefile

Diff comments View file @ 7c7a23b

board/MAI/AmigaOneG3SE/articiaS.c

Diff comments View file @ 7c7a23b

 /*
  * (C) Copyright 2002
  * Hyperion Entertainment, ThomasF@hyperion-entertainment.com
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 #include <common.h>
 #include <pci.h>
 #include <asm/processor.h>
 #include "memio.h"
 #include "articiaS.h"
 #include "smbus.h"
 #include "via686.h"
 #undef DEBUG
 struct dimm_bank {
 	uint8 used;			/* Bank is populated */
 	uint32 rows;			/* Number of row addresses */
 	uint32 columns;			/* Number of column addresses */
 	uint8 registered;		/* SIMM is registered */
 	uint8 ecc;			/* SIMM has ecc */
 	uint8 burst_len;		/* Supported burst lengths */
 	uint32 cas_lat;			/* Supported CAS latencies */
 	uint32 cas_used;		/* CAS to use (not set by user) */
 	uint32 trcd;			/* RAS to CAS latency */
 	uint32 trp;			/* Precharge latency */
 	uint32 tclk_hi;			/* SDRAM cycle time (highest CAS latency) */
 	uint32 tclk_2hi;		/* SDRAM second highest CAS latency */
 	uint32 size;			/* Size of bank in bytes */
 	uint8 auto_refresh;		/* Module supports auto refresh */
 	uint32 refresh_time;		/* Refresh time (in ns) */
 };
 /*
 ** Based in part on the evb64260 code
 */
 /*
  * translate ns.ns/10 coding of SPD timing values
  * into 10 ps unit values
  */
 static inline unsigned short NS10to10PS (unsigned char spd_byte)
 {
 	unsigned short ns, ns10;
 	/* isolate upper nibble */
 	ns = (spd_byte >> 4) & 0x0F;
 	/* isolate lower nibble */
 	ns10 = (spd_byte & 0x0F);
 	return (ns * 100 + ns10 * 10);
 }
 /*
  * translate ns coding of SPD timing values
  * into 10 ps unit values
  */
 static inline unsigned short NSto10PS (unsigned char spd_byte)
 {
 	return (spd_byte * 100);
 }
 long detect_sdram (uint8 * rom, int dimmNum, struct dimm_bank *banks)
 {
+    DECLARE_GLOBAL_DATA_PTR;
 	int dimm_address = (dimmNum == 0) ? SM_DIMM0_ADDR : SM_DIMM1_ADDR;
-	uint32 busclock = get_bus_freq (0);
+	uint32 busclock = gd->bus_clk;
 	uint32 memclock = busclock;
 	uint32 tmemclock = 1000000000 / (memclock / 100);
 	uint32 datawidth;
 	if (sm_get_data (rom, dimm_address) == 0) {
 		/* Nothing in slot, make both banks empty */
 		debug ("Slot %d: vacant\n", dimmNum);
 		banks[0].used = 0;
 		banks[1].used = 0;
 		return 0;
 	}
 	if (rom[2] != 0x04) {
 		debug ("Slot %d: No SDRAM\n", dimmNum);
 		banks[0].used = 0;
 		banks[1].used = 0;
 		return 0;
 	}
 	/* Determine number of banks/rows */
 	if (rom[5] == 1) {
 		banks[0].used = 1;
 		banks[1].used = 0;
 	} else {
 		banks[0].used = 1;
 		banks[1].used = 1;
 	}
 	/* Determine number of row addresses */
 	if (rom[3] & 0xf0) {
 		/* Different banks sizes */
 		banks[0].rows = rom[3] & 0x0f;
 		banks[1].rows = (rom[3] & 0xf0) >> 4;
 	} else {
 		/* Equal sized banks */
 		banks[0].rows = rom[3] & 0x0f;
 		banks[1].rows = banks[0].rows;
 	}
 	/* Determine number of column addresses */
 	if (rom[4] & 0xf0) {
 		/* Different bank sizes */
 		banks[0].columns = rom[4] & 0x0f;
 		banks[1].columns = (rom[4] & 0xf0) >> 4;
 	} else {
 		banks[0].columns = rom[4] & 0x0f;
 		banks[1].columns = banks[0].columns;
 	}
 	/* Check Jedec revision, and modify row/column accordingly */
 	if (rom[62] > 0x10) {
 		if (banks[0].rows <= 3)
 			banks[0].rows += 15;
 		if (banks[1].rows <= 3)
 			banks[1].rows += 15;
 		if (banks[0].columns <= 3)
 			banks[0].columns += 15;
 		if (banks[0].columns <= 3)
 			banks[0].columns += 15;
 	}
 	/* Check registered/unregisterd */
 	if (rom[21] & 0x12) {
 		banks[0].registered = 1;
 		banks[1].registered = 1;
 	} else {
 		banks[0].registered = 0;
 		banks[1].registered = 0;
 	}
 #ifdef CONFIG_ECC
 	/* Check parity/ECC */
 	banks[0].ecc = (rom[11] == 0x02);
 	banks[1].ecc = (rom[11] == 0x02);
 #endif
 	/* Find burst lengths supported */
 	banks[0].burst_len = rom[16] & 0x8f;
 	banks[1].burst_len = rom[16] & 0x8f;
 	/* Find possible cas latencies */
 	banks[0].cas_lat = rom[18] & 0x7F;
 	banks[1].cas_lat = rom[18] & 0x7F;
 	/* RAS/CAS latency */
 	banks[0].trcd = (NSto10PS (rom[29]) + (tmemclock - 1)) / tmemclock;
 	banks[1].trcd = (NSto10PS (rom[29]) + (tmemclock - 1)) / tmemclock;
 	/* Precharge latency */
 	banks[0].trp = (NSto10PS (rom[27]) + (tmemclock - 1)) / tmemclock;
 	banks[1].trp = (NSto10PS (rom[27]) + (tmemclock - 1)) / tmemclock;
 	/* highest CAS latency */
 	banks[0].tclk_hi = NS10to10PS (rom[9]);
 	banks[1].tclk_hi = NS10to10PS (rom[9]);
 	/* second highest CAS latency */
 	banks[0].tclk_2hi = NS10to10PS (rom[23]);
 	banks[1].tclk_2hi = NS10to10PS (rom[23]);
 	/* bank sizes */
 	datawidth = rom[13] & 0x7f;
 	banks[0].size =
 			(1L << (banks[0].rows + banks[0].columns)) *
 			/* FIXME datawidth */ 8 * rom[17];
 	if (rom[13] & 0x80)
 		banks[1].size = 2 * banks[0].size;
 	else
 		banks[1].size = (1L << (banks[1].rows + banks[1].columns)) *
 				/* FIXME datawidth */ 8 * rom[17];
 	/* Refresh */
 	if (rom[12] & 0x80) {
 		banks[0].auto_refresh = 1;
 		banks[1].auto_refresh = 1;
 	} else {
 		banks[0].auto_refresh = 0;
 		banks[1].auto_refresh = 0;
 	}
 	switch (rom[12] & 0x7f) {
 	case 0:
 		banks[0].refresh_time = (1562500 + (tmemclock - 1)) / tmemclock;
 		banks[1].refresh_time = (1562500 + (tmemclock - 1)) / tmemclock;
 		break;
 	case 1:
 		banks[0].refresh_time = (390600 + (tmemclock - 1)) / tmemclock;
 		banks[1].refresh_time = (390600 + (tmemclock - 1)) / tmemclock;
 		break;
 	case 2:
 		banks[0].refresh_time = (781200 + (tmemclock - 1)) / tmemclock;
 		banks[1].refresh_time = (781200 + (tmemclock - 1)) / tmemclock;
 		break;
 	case 3:
 		banks[0].refresh_time = (3125000 + (tmemclock - 1)) / tmemclock;
 		banks[1].refresh_time = (3125000 + (tmemclock - 1)) / tmemclock;
 		break;
 	case 4:
 		banks[0].refresh_time = (6250000 + (tmemclock - 1)) / tmemclock;
 		banks[1].refresh_time = (6250000 + (tmemclock - 1)) / tmemclock;
 		break;
 	case 5:
 		banks[0].refresh_time = (12500000 + (tmemclock - 1)) / tmemclock;
 		banks[1].refresh_time = (12500000 + (tmemclock - 1)) / tmemclock;
 		break;
 	default:
 		banks[0].refresh_time = 0x100;	/* Default of Articia S */
 		banks[1].refresh_time = 0x100;
 		break;
 	}
 #ifdef DEBUG
 	printf ("\nInformation for SIMM bank %ld:\n", dimmNum);
 	printf ("Number of banks: %ld\n", banks[0].used + banks[1].used);
 	printf ("Number of row addresses: %ld\n", banks[0].rows);
 	printf ("Number of coumns addresses: %ld\n", banks[0].columns);
 	printf ("SIMM is %sregistered\n",
 			banks[0].registered == 0 ? "not " : "");
 #ifdef CONFIG_ECC
 	printf ("SIMM %s ECC\n",
 			banks[0].ecc == 1 ? "supports" : "doesn't support");
 #endif
 	printf ("Supported burst lenghts: %s %s %s %s %s\n",
 			banks[0].burst_len & 0x08 ? "8" : " ",
 			banks[0].burst_len & 0x04 ? "4" : " ",
 			banks[0].burst_len & 0x02 ? "2" : " ",
 			banks[0].burst_len & 0x01 ? "1" : " ",
 			banks[0].burst_len & 0x80 ? "PAGE" : "    ");
 	printf ("Supported CAS latencies: %s %s %s\n",
 			banks[0].cas_lat & 0x04 ? "CAS 3" : "     ",
 			banks[0].cas_lat & 0x02 ? "CAS 2" : "     ",
 			banks[0].cas_lat & 0x01 ? "CAS 1" : "     ");
 	printf ("RAS to CAS latency: %ld\n", banks[0].trcd);
 	printf ("Precharge latency: %ld\n", banks[0].trp);
 	printf ("SDRAM highest CAS latency: %ld\n", banks[0].tclk_hi);
 	printf ("SDRAM 2nd highest CAS latency: %ld\n", banks[0].tclk_2hi);
 	printf ("SDRAM data width: %ld\n", datawidth);
 	printf ("Auto Refresh %ssupported\n",
 			banks[0].auto_refresh ? "" : "not ");
 	printf ("Refresh time: %ld clocks\n", banks[0].refresh_time);
 	if (banks[0].used)
 		printf ("Bank 0 size: %ld MB\n", banks[0].size / 1024 / 1024);
 	if (banks[1].used)
 		printf ("Bank 1 size: %ld MB\n", banks[1].size / 1024 / 1024);
 	printf ("\n");
 #endif
 	sm_term ();
 	return 1;
 }
 void select_cas (struct dimm_bank *banks, uint8 fast)
 {
 	if (!banks[0].used) {
 		banks[0].cas_used = 0;
 		banks[0].cas_used = 0;
 		return;
 	}
 	if (fast) {
 		/* Search for fast CAS */
 		uint32 i;
 		uint32 c = 0x01;
 		for (i = 1; i < 5; i++) {
 			if (banks[0].cas_lat & c) {
 				banks[0].cas_used = i;
 				banks[1].cas_used = i;
 				debug ("Using CAS %d (fast)\n", i);
 				return;
 			}
 			c <<= 1;
 		}
 		/* Default to CAS 3 */
 		banks[0].cas_used = 3;
 		banks[1].cas_used = 3;
 		debug ("Using CAS 3 (fast)\n");
 		return;
 	} else {
 		/* Search for slow cas */
 		uint32 i;
 		uint32 c = 0x08;
 		for (i = 4; i > 1; i--) {
 			if (banks[0].cas_lat & c) {
 				banks[0].cas_used = i;
 				banks[1].cas_used = i;
 				debug ("Using CAS %d (slow)\n", i);
 				return;
 			}
 			c >>= 1;
 		}
 		/* Default to CAS 3 */
 		banks[0].cas_used = 3;
 		banks[1].cas_used = 3;
 		debug ("Using CAS 3 (slow)\n");
 		return;
 	}
 	banks[0].cas_used = 3;
 	banks[1].cas_used = 3;
 	debug ("Using CAS 3\n");
 	return;
 }
 uint32 get_reg_setting (uint32 banks, uint32 rows, uint32 columns, uint32 size)
 {
 	uint32 i;
 	struct RowColumnSize {
 		uint32 banks;
 		uint32 rows;
 		uint32 columns;
 		uint32 size;
 		uint32 register_value;
 	};
 	struct RowColumnSize rcs_map[] = {
 		/*  Sbk Radr Cadr   MB     Value */
 		{1, 11, 8, 8, 0x00840f00},
 		{1, 11, 9, 16, 0x00925f00},
 		{1, 11, 10, 32, 0x00a64f00},
 		{2, 12, 8, 32, 0x00c55f00},
 		{2, 12, 9, 64, 0x00d66f00},
 		{2, 12, 10, 128, 0x00e77f00},
 		{2, 12, 11, 256, 0x00ff8f00},
 		{2, 13, 11, 512, 0x00ff9f00},
 		{0, 0, 0, 0, 0x00000000}
 	};
 	i = 0;
 	while (rcs_map[i].banks != 0) {
 		if (rows == rcs_map[i].rows
 			&& columns == rcs_map[i].columns
 			&& (size / 1024 / 1024) == rcs_map[i].size)
 			return rcs_map[i].register_value;
 		i++;
 	}
 	return 0;
 }
 uint32 burst_to_len (uint32 support)
 {
 	if (support & 0x80)
 		return 0x7;
 	else if (support & 0x8)
 		return 0x3;
 	else if (support & 0x4)
 		return 0x2;
 	else if (support & 0x2)
 		return 0x1;
 	else if (support & 0x1)
 		return 0x0;
 	return 0;
 }
 long articiaS_ram_init (void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
 	register uint32 i;
 	register uint32 value1;
 	register uint32 value2;
 	uint8 rom[128];
 	uint32 burst_len;
 	uint32 burst_support;
 	uint32 total_ram = 0;
 	struct dimm_bank banks[4];	/* FIXME: Move to initram */
-	uint32 busclock = get_bus_freq (0);
+	uint32 busclock = gd->bus_clk;
 	uint32 memclock = busclock;
 	uint32 reg32;
 	uint32 refresh_clocks;
 	uint8 auto_refresh;
 	memset (banks, 0, sizeof (struct dimm_bank) * 4);
 	detect_sdram (rom, 0, &banks[0]);
 	detect_sdram (rom, 1, &banks[2]);
 	for (i = 0; i < 4; i++) {
 		total_ram = total_ram + (banks[i].used * banks[i].size);
 	}
 	pci_write_cfg_long (0, 0, GLOBALINFO0, 0x117430c0);
 	pci_write_cfg_long (0, 0, HBUSACR0, 0x1f0100b0);
 	pci_write_cfg_long (0, 0, SRAM_CR, 0x00f12000);	/* Note: Might also try 0x00f10000 (original: 0x00f12000) */
 	pci_write_cfg_byte (0, 0, DRAM_RAS_CTL0, 0x3f);
 	pci_write_cfg_byte (0, 0, DRAM_RAS_CTL1, 0x00);	/*  was: 0x04); */
 	pci_write_cfg_word (0, 0, DRAM_ECC0, 0x2020);	/*  was: 0x2400);  No ECC yet */
 	/* FIXME: Move this stuff to seperate function, like setup_dimm_bank */
 	if (banks[0].used) {
 		value1 = get_reg_setting (banks[0].used + banks[1].used,
 					  banks[0].rows, banks[0].columns,
 					  banks[0].size);
 	} else {
 		value1 = 0;
 	}
 	if (banks[1].used) {
 		value2 = get_reg_setting (banks[0].used + banks[1].used,
 					  banks[1].rows, banks[1].columns,
 					  banks[1].size);
 	} else {
 		value2 = 0;
 	}
 	pci_write_cfg_long (0, 0, DIMM0_B0_SCR0, value1);
 	pci_write_cfg_long (0, 0, DIMM0_B1_SCR0, value2);
 	debug ("DIMM0_B0_SCR0 = 0x%08x\n", value1);
 	debug ("DIMM0_B1_SCR0 = 0x%08x\n", value2);
 	if (banks[2].used) {
 		value1 = get_reg_setting (banks[2].used + banks[3].used,
 					  banks[2].rows, banks[2].columns,
 					  banks[2].size);
 	} else {
 		value1 = 0;
 	}
 	if (banks[3].used) {
 		value2 = get_reg_setting (banks[2].used + banks[3].used,
 					  banks[3].rows, banks[3].columns,
 					  banks[3].size);
 	} else {
 		value2 = 0;
 	}
 	pci_write_cfg_long (0, 0, DIMM1_B2_SCR0, value1);
 	pci_write_cfg_long (0, 0, DIMM1_B3_SCR0, value2);
 	debug ("DIMM0_B2_SCR0 = 0x%08x\n", value1);
 	debug ("DIMM0_B3_SCR0 = 0x%08x\n", value2);
 	pci_write_cfg_long (0, 0, DIMM2_B4_SCR0, 0);
 	pci_write_cfg_long (0, 0, DIMM2_B5_SCR0, 0);
 	pci_write_cfg_long (0, 0, DIMM3_B6_SCR0, 0);
 	pci_write_cfg_long (0, 0, DIMM3_B7_SCR0, 0);
 	/* Determine timing */
 	select_cas (&banks[0], 0);
 	select_cas (&banks[2], 0);
 	/* FIXME: What about write recovery */
 	/*                    Auto refresh    Precharge */
 #if 0
 	reg32 = (0x3 << 13) | (0x7 << 10) | ((banks[0].trp - 2) << 8) |
 	/*    Write recovery  CAS Latency */
 		(0x1 << 6) | (banks[0].cas_used << 4) |
 	/*      RAS/CAS latency */
 		((banks[0].trcd - 1) << 0);
 	reg32 |= ((0x3 << 13) | (0x7 << 10) | ((banks[2].trp - 2) << 8) |
 		  (0x1 << 6) | (banks[2].cas_used << 4) |
 		  ((banks[2].trcd - 1) << 0)) << 16;
 #else
 	if (100000000 == gd->bus_clk)
 		reg32 = 0x71737173;
 	else
 		reg32 = 0x69736973;
 #endif
 	pci_write_cfg_long (0, 0, DIMM0_TCR0, reg32);
 	debug ("DIMM0_TCR0 = 0x%08x\n", reg32);
 	/* Write default in DIMM2/3 (not used on A1) */
 	pci_write_cfg_long (0, 0, DIMM2_TCR0, 0x7d737d73);
 	/* Determine buffered/unbuffered mode for each SIMM. Uses first bank as reference (second, if present, uses the same) */
 	reg32 = pci_read_cfg_long (0, 0, DRAM_GCR0);
 	reg32 &= 0xFF00FFFF;
 #if 0
 	if (banks[0].used && banks[0].registered)
 		reg32 |= 0x1 << 16;
 	if (banks[2].used && banks[2].registered)
 		reg32 |= 0x1 << 18;
 #else
 	if (banks[0].registered || banks[2].registered)
 		reg32 |= 0x55 << 16;
 #endif
 	pci_write_cfg_long (0, 0, DRAM_GCR0, reg32);
 	debug ("DRAM_GCR0 = 0x%08x\n", reg32);
 	/* Determine refresh */
 	refresh_clocks = 0xffffffff;
 	auto_refresh = 1;
 	for (i = 0; i < 4; i++) {
 		if (banks[i].used) {
 			if (banks[i].auto_refresh == 0)
 				auto_refresh = 0;
 			if (banks[i].refresh_time < refresh_clocks)
 				refresh_clocks = banks[i].refresh_time;
 		}
 	}
 #if 1
 	/*  It seems this is suggested by the ArticiaS data book */
 	if (100000000 == gd->bus_clk)
 		refresh_clocks = 1561;
 	else
 		refresh_clocks = 2083;
 #endif
 	debug ("Refresh set to %ld clocks, auto refresh %s\n",
 		   refresh_clocks, auto_refresh ? "on" : "off");
 	pci_write_cfg_long (0, 0, DRAM_REFRESH0,
 			(1 << 16) | (1 << 15) | (auto_refresh << 12) |
 			(refresh_clocks));
 	debug ("DRAM_REFRESH0 = 0x%08x\n",
 			(1 << 16) | (1 << 15) | (auto_refresh << 12) |
 			(refresh_clocks));
 /*     pci_write_cfg_long(0, 0, DRAM_REFRESH0,   0x00019400);  */
 	/* Set mode registers */
 	/* FIXME: For now, set same burst len for all modules. Dunno if that's necessary */
 	/* Find a common burst len */
 	burst_support = 0xff;
 	if (banks[0].used)
 		burst_support = banks[0].burst_len;
 	if (banks[1].used)
 		burst_support = banks[1].burst_len;
 	if (banks[2].used)
 		burst_support = banks[2].burst_len;
 	if (banks[3].used)
 		burst_support = banks[3].burst_len;
 	/*
 	   ** Mode register:
 	   ** Bits         Use
 	   ** 0-2          Burst len
 	   ** 3            Burst type (0 = sequential, 1 = interleave)
 	   ** 4-6          CAS latency
 	   ** 7-8          Operation mode (0 = default, all others invalid)
 	   ** 9            Write burst
 	   ** 10-11        Reserved
 	   **
 	   ** Mode register burst table:
 	   ** A2 A1 A0     lenght
 	   ** 0  0  0      1
 	   ** 0  0  1      2
 	   ** 0  1  0      4
 	   ** 0  1  1      8
 	   ** 1  0  0      invalid
 	   ** 1  0  1      invalid
 	   ** 1  1  0      invalid
 	   ** 1  1  1      page (only valid for non-interleaved)
 	 */
 	burst_len = burst_to_len (burst_support);
 	burst_len = 2;				/* FIXME */
 	if (banks[0].used) {
 		pci_write_cfg_word (0, 0, DRAM_PCR0,
 			0x8000 | burst_len | (banks[0].cas_used << 4));
 		debug ("Mode bank 0: 0x%08x\n",
 			0x8000 | burst_len | (banks[0].cas_used << 4));
 	} else {
 		/*  Seems to be needed to disable the bank */
 		pci_write_cfg_word (0, 0, DRAM_PCR0, 0x0000 | 0x032);
 	}
 	if (banks[1].used) {
 		pci_write_cfg_word (0, 0, DRAM_PCR0,
 			0x9000 | burst_len | (banks[1].cas_used << 4));
 		debug ("Mode bank 1: 0x%08x\n",
 			0x8000 | burst_len | (banks[1].cas_used << 4));
 	} else {
 		/*  Seems to be needed to disable the bank */
 		pci_write_cfg_word (0, 0, DRAM_PCR0, 0x1000 | 0x032);
 	}
 	if (banks[2].used) {
 		pci_write_cfg_word (0, 0, DRAM_PCR0,
 			0xa000 | burst_len | (banks[2].cas_used << 4));
 		debug ("Mode bank 2: 0x%08x\n",
 			0x8000 | burst_len | (banks[2].cas_used << 4));
 	} else {
 		/*  Seems to be needed to disable the bank */
 		pci_write_cfg_word (0, 0, DRAM_PCR0, 0x2000 | 0x032);
 	}
 	if (banks[3].used) {
 		pci_write_cfg_word (0, 0, DRAM_PCR0,
 			0xb000 | burst_len | (banks[3].cas_used << 4));
 		debug ("Mode bank 3: 0x%08x\n",
 			0x8000 | burst_len | (banks[3].cas_used << 4));
 	} else {
 		/*  Seems to be needed to disable the bank */
 		pci_write_cfg_word (0, 0, DRAM_PCR0, 0x3000 | 0x032);
 	}
 	pci_write_cfg_word (0, 0, 0xba, 0x00);
 	return total_ram;
 }
 extern int drv_isa_kbd_init (void);
 int last_stage_init (void)
 {
 	drv_isa_kbd_init ();
 	return 0;
 }
 int overwrite_console (void)
 {
 	return (0);
 }
 #define in_8 read_byte
 #define out_8 write_byte
 static __inline__ unsigned long get_msr (void)
 {
 	unsigned long msr;
 	asm volatile ("mfmsr %0":"=r" (msr):);
 	return msr;
 }
 static __inline__ void set_msr (unsigned long msr)
 {
 	asm volatile ("mtmsr %0"::"r" (msr));
 }
 int board_pre_init (void)
 {
 	unsigned char c_value = 0;
 	unsigned long msr;
 	/* Basic init of PS/2 keyboard (needed for some reason)... */
 	/* Ripped from John's code */
 	while ((in_8 ((unsigned char *) 0xfe000064) & 0x02) != 0);
 	out_8 ((unsigned char *) 0xfe000064, 0xaa);
 	while ((in_8 ((unsigned char *) 0xfe000064) & 0x01) == 0);
 	c_value = in_8 ((unsigned char *) 0xfe000060);
 	while ((in_8 ((unsigned char *) 0xfe000064) & 0x02) != 0);
 	out_8 ((unsigned char *) 0xfe000064, 0xab);
 	while ((in_8 ((unsigned char *) 0xfe000064) & 0x01) == 0);
 	c_value = in_8 ((unsigned char *) 0xfe000060);
 	while ((in_8 ((unsigned char *) 0xfe000064) & 0x02) != 0);
 	out_8 ((unsigned char *) 0xfe000064, 0xae);
 /*     while ((in_8((unsigned char *)0xfe000064) & 0x01) == 0); */
 /*     c_value = in_8((unsigned char *)0xfe000060); */
 	/*  Enable FPU */
 	msr = get_msr ();
 	set_msr (msr | MSR_FP);
 	via_calibrate_bus_freq ();
 	return 0;
 }

board/MAI/AmigaOneG3SE/articiaS_pci.c

Diff comments View file @ 7c7a23b

1	/*	1	/*
2	* (C) Copyright 2002	2	* (C) Copyright 2002
3	* Hyperion Entertainment, Hans-JoergF@hyperion-entertainment.com	3	* Hyperion Entertainment, Hans-JoergF@hyperion-entertainment.com
4	*	4	*
5	* See file CREDITS for list of people who contributed to this	5	* See file CREDITS for list of people who contributed to this
6	* project.	6	* project.
7	*	7	*
8	* This program is free software; you can redistribute it and/or	8	* This program is free software; you can redistribute it and/or
9	* modify it under the terms of the GNU General Public License as	9	* modify it under the terms of the GNU General Public License as
10	* published by the Free Software Foundation; either version 2 of	10	* published by the Free Software Foundation; either version 2 of
11	* the License, or (at your option) any later version.	11	* the License, or (at your option) any later version.
12	*	12	*
13	* This program is distributed in the hope that it will be useful,	13	* This program is distributed in the hope that it will be useful,
14	* but WITHOUT ANY WARRANTY; without even the implied warranty of	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16	* GNU General Public License for more details.	16	* GNU General Public License for more details.
17	*	17	*
18	* You should have received a copy of the GNU General Public License	18	* You should have received a copy of the GNU General Public License
19	* along with this program; if not, write to the Free Software	19	* along with this program; if not, write to the Free Software
20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21	* MA 02111-1307 USA	21	* MA 02111-1307 USA
22	*/	22	*/
23		23
24	#include <common.h>	24	#include <common.h>
25	#include <pci.h>	25	#include <pci.h>
26	#include "memio.h"	26	#include "memio.h"
27	#include "articiaS.h"	27	#include "articiaS.h"
28		28
29	//#define ARTICIA_PCI_DEBUG	29	#undef ARTICIA_PCI_DEBUG
30		30
31	#ifdef ARTICIA_PCI_DEBUG	31	#ifdef ARTICIA_PCI_DEBUG
32	#define PRINTF(fmt,args...) printf (fmt ,##args)	32	#define PRINTF(fmt,args...) printf (fmt ,##args)
33	#else	33	#else
34	#define PRINTF(fmt,args...)	34	#define PRINTF(fmt,args...)
35	#endif	35	#endif
36		36
37	struct pci_controller articiaS_hose;	37	struct pci_controller articiaS_hose;
38		38
39	long irq_alloc(long wanted);	39	long irq_alloc(long wanted);
40		40
41	static pci_dev_t pci_hose_find_class(struct pci_controller *hose, int bus, short find_class, int index);	41	static pci_dev_t pci_hose_find_class(struct pci_controller *hose, int bus, short find_class, int index);
42	static int articiaS_init_vga(void);	42	static int articiaS_init_vga(void);
43	static void pci_cfgfunc_dummy(struct pci_controller host, pci_dev_t dev, struct pci_config_table table);	43	static void pci_cfgfunc_dummy(struct pci_controller host, pci_dev_t dev, struct pci_config_table table);
44	unsigned char pci_irq_alloc(void);	44	unsigned char pci_irq_alloc(void);
45		45
46	extern void via_cfgfunc_via686(struct pci_controller * host, pci_dev_t dev, struct pci_config_table *table);	46	extern void via_cfgfunc_via686(struct pci_controller * host, pci_dev_t dev, struct pci_config_table *table);
47	extern void via_cfgfunc_ide_init(struct pci_controller host, pci_dev_t dev, struct pci_config_table table);	47	extern void via_cfgfunc_ide_init(struct pci_controller host, pci_dev_t dev, struct pci_config_table table);
48	extern void via_init_irq_routing(uint8 []);	48	extern void via_init_irq_routing(uint8 []);
49	extern void via_init_afterscan(void);	49	extern void via_init_afterscan(void);
50		50
51	#define cfgfunc_via686 1	51	#define cfgfunc_via686 1
52	#define cfgfunc_dummy 2	52	#define cfgfunc_dummy 2
53	#define cfgfunc_ide_init 3	53	#define cfgfunc_ide_init 3
54		54
55	static struct pci_config_table config_table[] =	55	static struct pci_config_table config_table[] =
56	{	56	{
57	{	57	{
58	0x1106, PCI_ANY_ID, PCI_CLASS_BRIDGE_ISA, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,	58	0x1106, PCI_ANY_ID, PCI_CLASS_BRIDGE_ISA, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
59	(void *)cfgfunc_via686, {0, 0, 0}	59	(void *)cfgfunc_via686, {0, 0, 0}
60	},	60	},
61	{	61	{
62	0x1106, PCI_ANY_ID, PCI_ANY_ID, 0,7,4,	62	0x1106, PCI_ANY_ID, PCI_ANY_ID, 0,7,4,
63	(void *)cfgfunc_dummy, {0,0,0}	63	(void *)cfgfunc_dummy, {0,0,0}
64	},	64	},
65	{	65	{
66	0x1106, 0x3068, PCI_ANY_ID, 0, 7, PCI_ANY_ID,	66	0x1106, 0x3068, PCI_ANY_ID, 0, 7, PCI_ANY_ID,
67	(void *)cfgfunc_dummy, {0,0,0}	67	(void *)cfgfunc_dummy, {0,0,0}
68	},	68	},
69	{	69	{
70	0x1106, PCI_ANY_ID, PCI_ANY_ID, 0,7,1,	70	0x1106, PCI_ANY_ID, PCI_ANY_ID, 0,7,1,
71	(void *)cfgfunc_ide_init, {0,0,0}	71	(void *)cfgfunc_ide_init, {0,0,0}
72	},	72	},
73	{	73	{
74	0,	74	0,
75	}	75	}
76	};	76	};
77		77
78		78
79	void pci_cfgfunc_dummy(struct pci_controller host, pci_dev_t dev, struct pci_config_table table)	79	void pci_cfgfunc_dummy(struct pci_controller host, pci_dev_t dev, struct pci_config_table table)
80	{	80	{
81		81
82		82
83	}	83	}
84		84
85	unsigned long irq_penalties[16] =	85	unsigned long irq_penalties[16] =
86	{	86	{
87	1000, /* 0:timer */	87	1000, /* 0:timer */
88	1000, /* 1:keyboard */	88	1000, /* 1:keyboard */
89	1000, /* 2:cascade */	89	1000, /* 2:cascade */
90	50, /* 3:serial (COM2) */	90	50, /* 3:serial (COM2) */
91	50, /* 4:serial (COM1) */	91	50, /* 4:serial (COM1) */
92	4, /* 5:USB2 */	92	4, /* 5:USB2 */
93	100, /* 6:floppy */	93	100, /* 6:floppy */
94	3, /* 7:parallel */	94	3, /* 7:parallel */
95	50, /* 8:AC97/MC97 */	95	50, /* 8:AC97/MC97 */
96	0, /* 9: */	96	0, /* 9: */
97	3, /* 10:: */	97	3, /* 10:: */
98	0, /* 11: */	98	0, /* 11: */
99	3, /* 12: USB1 */	99	3, /* 12: USB1 */
100	0, /* 13: */	100	0, /* 13: */
101	100, /* 14: ide0 */	101	100, /* 14: ide0 */
102	100, /* 15: ide1 */	102	100, /* 15: ide1 */
103	};	103	};
104		104
105		105
106	/*	106	/*
107	* The following defines a hard-coded interrupt mapping for the	107	* The following defines a hard-coded interrupt mapping for the
108	* know devices on the board.	108	* know devices on the board.
109	* If a device isn't found here, assumed to be a device that's	109	* If a device isn't found here, assumed to be a device that's
110	* plugged into a PCI or AGP slot	110	* plugged into a PCI or AGP slot
111	* NOTE: This table is machine dependant.	111	* NOTE: This table is machine dependant.
112	*/	112	*/
113		113
114	struct pci_irq_fixup_table	114	struct pci_irq_fixup_table
115	{	115	{
116	uint8 bus; /* Bus number */	116	uint8 bus; /* Bus number */
117	uint8 device; /* Device number */	117	uint8 device; /* Device number */
118	uint8 func; /* Function number */	118	uint8 func; /* Function number */
119	uint8 interrupt; /* Interrupt to use (0xff to disable) */	119	uint8 interrupt; /* Interrupt to use (0xff to disable) */
120	};	120	};
121		121
122	struct pci_irq_fixup_table fixuptab [] =	122	struct pci_irq_fixup_table fixuptab [] =
123	{	123	{
124	{ 0, 0, 0, 0xff}, /* Articia S host bridge */	124	{ 0, 0, 0, 0xff}, /* Articia S host bridge */
125	{ 0, 1, 0, 0xff}, /* Articia S AGP bridge */	125	{ 0, 1, 0, 0xff}, /* Articia S AGP bridge */
126	// { 0, 6, 0, 0x05}, /* 3COM ethernet */	126	// { 0, 6, 0, 0x05}, /* 3COM ethernet */
127	{ 0, 7, 0, 0xff}, /* VIA southbridge */	127	{ 0, 7, 0, 0xff}, /* VIA southbridge */
128	{ 0, 7, 1, 0x0e}, /* IDE controller in legacy mode */	128	{ 0, 7, 1, 0x0e}, /* IDE controller in legacy mode */
129	// { 0, 7, 2, 0x05}, /* First USB controller */	129	// { 0, 7, 2, 0x05}, /* First USB controller */
130	// { 0, 7, 3, 0x0c}, /* Second USB controller (shares interrupt with ethernet) */	130	// { 0, 7, 3, 0x0c}, /* Second USB controller (shares interrupt with ethernet) */
131	{ 0, 7, 4, 0xff}, /* ACPI Power Management */	131	{ 0, 7, 4, 0xff}, /* ACPI Power Management */
132	// { 0, 7, 5, 0x08}, /* AC97 */	132	// { 0, 7, 5, 0x08}, /* AC97 */
133	// { 0, 7, 6, 0x08}, /* MC97 */	133	// { 0, 7, 6, 0x08}, /* MC97 */
134	{ 0xff, 0xff, 0xff, 0xff}	134	{ 0xff, 0xff, 0xff, 0xff}
135	};	135	};
136		136
137		137
138	/*	138	/*
139	* This table maps IRQ's to PCI interrupts	139	* This table maps IRQ's to PCI interrupts
140	*/	140	*/
141		141
142	uint8 pci_intmap[4] = {0, 0, 0, 0};	142	uint8 pci_intmap[4] = {0, 0, 0, 0};
143		143
144	/*	144	/*
145	* Map PCI slots to interrupt routings	145	* Map PCI slots to interrupt routings
146	* This table lists the device number assigned to a card inserted	146	* This table lists the device number assigned to a card inserted
147	* into the slot, along with a permutation for the slot's IRQ routing.	147	* into the slot, along with a permutation for the slot's IRQ routing.
148	* NOTE: This table is machine dependant.	148	* NOTE: This table is machine dependant.
149	*/	149	*/
150		150
151	struct pci_slot_irq_routing	151	struct pci_slot_irq_routing
152	{	152	{
153	uint8 bus;	153	uint8 bus;
154	uint8 device;	154	uint8 device;
155		155
156	uint8 ints[4];	156	uint8 ints[4];
157	};	157	};
158		158
159	struct pci_slot_irq_routing amigaone_pci_routing[] =	159	struct pci_slot_irq_routing amigaone_pci_routing[] =
160	{	160	{
161	{0, 8, {0, 1, 2, 3}}, /* Slot 1 (left of riser slot) */	161	{0, 8, {0, 1, 2, 3}}, /* Slot 1 (left of riser slot) */
162	{0, 9, {1, 2, 3, 0}}, /* Slot 2 (middle slot) */	162	{0, 9, {1, 2, 3, 0}}, /* Slot 2 (middle slot) */
163	{0, 10, {2, 3, 0, 1}}, /* Slot 3 (leftmost slot) */	163	{0, 10, {2, 3, 0, 1}}, /* Slot 3 (leftmost slot) */
164	{1, 0, {1, 0, 2, 3}}, /* AGP slot (only IRQA and IRQB) */	164	{1, 0, {1, 0, 2, 3}}, /* AGP slot (only IRQA and IRQB) */
165	{1, 1, {1, 2, 3, 0}}, /* PCI slot on AGP bus */	165	{1, 1, {1, 2, 3, 0}}, /* PCI slot on AGP bus */
166	{0, 6, {3, 3, 3, 3}}, /* On board ethernet */	166	{0, 6, {3, 3, 3, 3}}, /* On board ethernet */
167	{0, 7, {0, 1, 2, 3}}, /* Southbridge */	167	{0, 7, {0, 1, 2, 3}}, /* Southbridge */
168	{0xff, 0, {0, 0, 0, 0}}	168	{0xff, 0, {0, 0, 0, 0}}
169	};	169	};
170		170
171	void articiaS_pci_irq_init(void)	171	void articiaS_pci_irq_init(void)
172	{	172	{
173	char *s;	173	char *s;
174		174
175	s = getenv("pci_irqa");	175	s = getenv("pci_irqa");
176	if (s)	176	if (s)
177	pci_intmap[0] = simple_strtoul (s, NULL, 10);	177	pci_intmap[0] = simple_strtoul (s, NULL, 10);
178	else	178	else
179	pci_intmap[0] = pci_irq_alloc();	179	pci_intmap[0] = pci_irq_alloc();
180		180
181	s = getenv("pci_irqb");	181	s = getenv("pci_irqb");
182	if (s)	182	if (s)
183	pci_intmap[1] = simple_strtoul (s, NULL, 10);	183	pci_intmap[1] = simple_strtoul (s, NULL, 10);
184	else	184	else
185	pci_intmap[1] = pci_irq_alloc();	185	pci_intmap[1] = pci_irq_alloc();
186		186
187	s = getenv("pci_irqc");	187	s = getenv("pci_irqc");
188	if (s)	188	if (s)
189	pci_intmap[2] = simple_strtoul (s, NULL, 10);	189	pci_intmap[2] = simple_strtoul (s, NULL, 10);
190	else	190	else
191	pci_intmap[2] = pci_irq_alloc();	191	pci_intmap[2] = pci_irq_alloc();
192		192
193	s = getenv("pci_irqd");	193	s = getenv("pci_irqd");
194	if (s)	194	if (s)
195	pci_intmap[3] = simple_strtoul (s, NULL, 10);	195	pci_intmap[3] = simple_strtoul (s, NULL, 10);
196	else	196	else
197	pci_intmap[3] = pci_irq_alloc();	197	pci_intmap[3] = pci_irq_alloc();
198	}	198	}
199		199
200		200
201	unsigned char pci_irq_alloc(void)	201	unsigned char pci_irq_alloc(void)
202	{	202	{
203	int i;	203	int i;
204	int interrupt = 10;	204	int interrupt = 10;
205	unsigned long min_penalty = 1000;	205	unsigned long min_penalty = 1000;
206		206
207	/* Search for the minimal penalty, favoring interrupts at the end */	207	/* Search for the minimal penalty, favoring interrupts at the end */
208	for (i = 0; i < 16; i++)	208	for (i = 0; i < 16; i++)
209	{	209	{
210	if (irq_penalties[i] <= min_penalty)	210	if (irq_penalties[i] <= min_penalty)
211	{	211	{
212	interrupt = i;	212	interrupt = i;
213	min_penalty = irq_penalties[i];	213	min_penalty = irq_penalties[i];
214	}	214	}
215	}	215	}
216		216
217	PRINTF("pci_irq_alloc: Minimal penalty is %ld for %d\n", min_penalty, interrupt);	217	PRINTF("pci_irq_alloc: Minimal penalty is %ld for %d\n", min_penalty, interrupt);
218		218
219	irq_penalties[interrupt]++;	219	irq_penalties[interrupt]++;
220		220
221	return interrupt;	221	return interrupt;
222	}	222	}
223		223
224		224
225	void articiaS_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)	225	void articiaS_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
226	{	226	{
227	int8 bus, device, func, pin, line;	227	int8 bus, device, func, pin, line;
228	int i;	228	int i;
229		229
230	bus = PCI_BUS(dev);	230	bus = PCI_BUS(dev);
231	device = PCI_DEV(dev);	231	device = PCI_DEV(dev);
232	func = PCI_FUNC(dev);	232	func = PCI_FUNC(dev);
233		233
234	PRINTF("Fixup irq of %d:%d.%d\n", bus, device, func);	234	PRINTF("Fixup irq of %d:%d.%d\n", bus, device, func);
235		235
236	/* Search for the device in the table */	236	/* Search for the device in the table */
237	for (i = 0; fixuptab[i].bus != 0xff; i++)	237	for (i = 0; fixuptab[i].bus != 0xff; i++)
238	{	238	{
239	if (bus == fixuptab[i].bus && device == fixuptab[i].device && func == fixuptab[i].func)	239	if (bus == fixuptab[i].bus && device == fixuptab[i].device && func == fixuptab[i].func)
240	{	240	{
241	/* If the device needs an interrupt, write it */	241	/* If the device needs an interrupt, write it */
242	if (fixuptab[i].interrupt != 0xff)	242	if (fixuptab[i].interrupt != 0xff)
243	{	243	{
244	PRINTF("Assigning IRQ %d (fixed)\n", fixuptab[i].interrupt);	244	PRINTF("Assigning IRQ %d (fixed)\n", fixuptab[i].interrupt);
245	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, fixuptab[i].interrupt);	245	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, fixuptab[i].interrupt);
246	}	246	}
247	else	247	else
248	{	248	{
249	/* Otherwise, see if it wants an interrupt, and disable it if needed */	249	/* Otherwise, see if it wants an interrupt, and disable it if needed */
250	pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);	250	pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
251	if (pin)	251	if (pin)
252	{	252	{
253	PRINTF("Disabling IRQ\n");	253	PRINTF("Disabling IRQ\n");
254	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 0xff);	254	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 0xff);
255	}	255	}
256	}	256	}
257		257
258	return;	258	return;
259	}	259	}
260	}	260	}
261		261
262	/* If we get here, we have another PCI device in a slot... find the appropriate IRQ */	262	/* If we get here, we have another PCI device in a slot... find the appropriate IRQ */
263		263
264	/* Find matching pin */	264	/* Find matching pin */
265	pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);	265	pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
266	pin--;	266	pin--;
267		267
268	/* Search for it's map */	268	/* Search for it's map */
269	for (i = 0; amigaone_pci_routing[i].bus != 0xff; i++)	269	for (i = 0; amigaone_pci_routing[i].bus != 0xff; i++)
270	{	270	{
271	if (bus == amigaone_pci_routing[i].bus && device == amigaone_pci_routing[i].device)	271	if (bus == amigaone_pci_routing[i].bus && device == amigaone_pci_routing[i].device)
272	{	272	{
273	line = pci_intmap[amigaone_pci_routing[i].ints[pin]];	273	line = pci_intmap[amigaone_pci_routing[i].ints[pin]];
274	PRINTF("Assigning IRQ %d (pin %d)\n", line, pin);	274	PRINTF("Assigning IRQ %d (pin %d)\n", line, pin);
275	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, line);	275	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, line);
276	return;	276	return;
277	}	277	}
278	}	278	}
279		279
280	PRINTF("Unkonwn PCI device found\n");	280	PRINTF("Unkonwn PCI device found\n");
281	}	281	}
282		282
283	void articiaS_pci_init (void)	283	void articiaS_pci_init (void)
284	{	284	{
285	int i;	285	int i;
286	char *s;	286	char *s;
287		287
288	PRINTF("atriciaS_pci_init\n");	288	PRINTF("atriciaS_pci_init\n");
289		289
290	// Why aren't these relocated??	290	// Why aren't these relocated??
291	for (i=0; config_table[i].config_device; i++)	291	for (i=0; config_table[i].config_device; i++)
292	{	292	{
293	switch((int)config_table[i].config_device)	293	switch((int)config_table[i].config_device)
294	{	294	{
295	case cfgfunc_via686: config_table[i].config_device = via_cfgfunc_via686; break;	295	case cfgfunc_via686: config_table[i].config_device = via_cfgfunc_via686; break;
296	case cfgfunc_dummy: config_table[i].config_device = pci_cfgfunc_dummy; break;	296	case cfgfunc_dummy: config_table[i].config_device = pci_cfgfunc_dummy; break;
297	case cfgfunc_ide_init: config_table[i].config_device = via_cfgfunc_ide_init; break;	297	case cfgfunc_ide_init: config_table[i].config_device = via_cfgfunc_ide_init; break;
298	default: PRINTF("Error: Unknown constant\n");	298	default: PRINTF("Error: Unknown constant\n");
299	}	299	}
300	}	300	}
301		301
302	articiaS_hose.first_busno = 0;	302	articiaS_hose.first_busno = 0;
303	articiaS_hose.last_busno = 0xff;	303	articiaS_hose.last_busno = 0xff;
304	articiaS_hose.config_table = config_table;	304	articiaS_hose.config_table = config_table;
305	articiaS_hose.fixup_irq = articiaS_pci_fixup_irq;	305	articiaS_hose.fixup_irq = articiaS_pci_fixup_irq;
306		306
307	articiaS_pci_irq_init();	307	articiaS_pci_irq_init();
308		308
309	/* System memory */	309	/* System memory */
310	pci_set_region(articiaS_hose.regions + 0,	310	pci_set_region(articiaS_hose.regions + 0,
311	ARTICIAS_SYS_BUS,	311	ARTICIAS_SYS_BUS,
312	ARTICIAS_SYS_PHYS,	312	ARTICIAS_SYS_PHYS,
313	ARTICIAS_SYS_MAXSIZE,	313	ARTICIAS_SYS_MAXSIZE,
314	PCI_REGION_MEM \| PCI_REGION_MEMORY);	314	PCI_REGION_MEM \| PCI_REGION_MEMORY);
315		315
316	/* PCI memory space */	316	/* PCI memory space */
317	pci_set_region(articiaS_hose.regions + 1,	317	pci_set_region(articiaS_hose.regions + 1,
318	ARTICIAS_PCI_BUS,	318	ARTICIAS_PCI_BUS,
319	ARTICIAS_PCI_PHYS,	319	ARTICIAS_PCI_PHYS,
320	ARTICIAS_PCI_MAXSIZE,	320	ARTICIAS_PCI_MAXSIZE,
321	PCI_REGION_MEM);	321	PCI_REGION_MEM);
322		322
323	/* PCI io space */	323	/* PCI io space */
324	pci_set_region(articiaS_hose.regions + 2,	324	pci_set_region(articiaS_hose.regions + 2,
325	ARTICIAS_PCIIO_BUS,	325	ARTICIAS_PCIIO_BUS,
326	ARTICIAS_PCIIO_PHYS,	326	ARTICIAS_PCIIO_PHYS,
327	ARTICIAS_PCIIO_MAXSIZE,	327	ARTICIAS_PCIIO_MAXSIZE,
328	PCI_REGION_IO);	328	PCI_REGION_IO);
329		329
330	/* PCI/ISA io space */	330	/* PCI/ISA io space */
331	pci_set_region(articiaS_hose.regions + 3,	331	pci_set_region(articiaS_hose.regions + 3,
332	ARTICIAS_ISAIO_BUS,	332	ARTICIAS_ISAIO_BUS,
333	ARTICIAS_ISAIO_PHYS,	333	ARTICIAS_ISAIO_PHYS,
334	ARTICIAS_ISAIO_MAXSIZE,	334	ARTICIAS_ISAIO_MAXSIZE,
335	PCI_REGION_IO);	335	PCI_REGION_IO);
336		336
337		337
338		338
339	articiaS_hose.region_count = 4;	339	articiaS_hose.region_count = 4;
340		340
341	pci_setup_indirect(&articiaS_hose, ARTICIAS_PCI_CFGADDR, ARTICIAS_PCI_CFGDATA);	341	pci_setup_indirect(&articiaS_hose, ARTICIAS_PCI_CFGADDR, ARTICIAS_PCI_CFGDATA);
342	PRINTF("Registering articia hose...\n");	342	PRINTF("Registering articia hose...\n");
343	pci_register_hose(&articiaS_hose);	343	pci_register_hose(&articiaS_hose);
344	PRINTF("Enabling AGP...\n");	344	PRINTF("Enabling AGP...\n");
345	pci_write_config_byte(PCI_BDF(0,0,0), 0x58, 0x01);	345	pci_write_config_byte(PCI_BDF(0,0,0), 0x58, 0x01);
346	PRINTF("Scanning bus...\n");	346	PRINTF("Scanning bus...\n");
347	articiaS_hose.last_busno = pci_hose_scan(&articiaS_hose);	347	articiaS_hose.last_busno = pci_hose_scan(&articiaS_hose);
348		348
349	via_init_irq_routing(pci_intmap);	349	via_init_irq_routing(pci_intmap);
350		350
351	PRINTF("After-Scan results:\n");	351	PRINTF("After-Scan results:\n");
352	PRINTF("Bus range: %d - %d\n", articiaS_hose.first_busno , articiaS_hose.last_busno);	352	PRINTF("Bus range: %d - %d\n", articiaS_hose.first_busno , articiaS_hose.last_busno);
353		353
354	via_init_afterscan();	354	via_init_afterscan();
355		355
356	pci_write_config_byte(PCI_BDF(0,1,0), PCI_INTERRUPT_LINE, 0xFF);	356	pci_write_config_byte(PCI_BDF(0,1,0), PCI_INTERRUPT_LINE, 0xFF);
357		357
358	s = getenv("as_irq");	358	s = getenv("as_irq");
359	if (s)	359	if (s)
360	{	360	{
361	pci_write_config_byte(PCI_BDF(0,0,0), PCI_INTERRUPT_LINE, simple_strtoul (s, NULL, 10));	361	pci_write_config_byte(PCI_BDF(0,0,0), PCI_INTERRUPT_LINE, simple_strtoul (s, NULL, 10));
362	}	362	}
363		363
364	s = getenv("x86_run_bios");	364	s = getenv("x86_run_bios");
365	if (!s \|\| (s && strcmp(s, "on")==0))	365	if (!s \|\| (s && strcmp(s, "on")==0))
366	{	366	{
367	if (articiaS_init_vga() == -1)	367	if (articiaS_init_vga() == -1)
368	{	368	{
369	/* If the VGA didn't init and we have stdout set to VGA, reset to serial */	369	/* If the VGA didn't init and we have stdout set to VGA, reset to serial */
370	/* s = getenv("stdout"); */	370	/* s = getenv("stdout"); */
371	/* if (s && strcmp(s, "vga") == 0) */	371	/* if (s && strcmp(s, "vga") == 0) */
372	/* { */	372	/* { */
373	/* setenv("stdout", "serial"); */	373	/* setenv("stdout", "serial"); */
374	/* } */	374	/* } */
375	}	375	}
376	}	376	}
377	pci_write_config_byte(PCI_BDF(0,1,0), PCI_INTERRUPT_LINE, 0xFF);	377	pci_write_config_byte(PCI_BDF(0,1,0), PCI_INTERRUPT_LINE, 0xFF);
378		378
379	}	379	}
380		380
381	pci_dev_t pci_hose_find_class(struct pci_controller *hose, int bus, short find_class, int index)	381	pci_dev_t pci_hose_find_class(struct pci_controller *hose, int bus, short find_class, int index)
382	{	382	{
383	unsigned int sub_bus, found_multi=0;	383	unsigned int sub_bus, found_multi=0;
384	unsigned short vendor, class;	384	unsigned short vendor, class;
385	unsigned char header_type;	385	unsigned char header_type;
386	pci_dev_t dev;	386	pci_dev_t dev;
387	u8 c1, c2;	387	u8 c1, c2;
388		388
389	sub_bus = bus;	389	sub_bus = bus;
390		390
391	for (dev = PCI_BDF(bus,0,0);	391	for (dev = PCI_BDF(bus,0,0);
392	dev < PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1);	392	dev < PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1);
393	dev += PCI_BDF(0,0,1))	393	dev += PCI_BDF(0,0,1))
394	{	394	{
395	if ( dev == PCI_BDF(hose->first_busno,0,0) )	395	if ( dev == PCI_BDF(hose->first_busno,0,0) )
396	continue;	396	continue;
397		397
398	if (PCI_FUNC(dev) && !found_multi)	398	if (PCI_FUNC(dev) && !found_multi)
399	continue;	399	continue;
400		400
401	pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);	401	pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
402		402
403	pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor);	403	pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor);
404		404
405	if (vendor != 0xffff && vendor != 0x0000)	405	if (vendor != 0xffff && vendor != 0x0000)
406	{	406	{
407		407
408	if (!PCI_FUNC(dev))	408	if (!PCI_FUNC(dev))
409	found_multi = header_type & 0x80;	409	found_multi = header_type & 0x80;
410	pci_hose_read_config_byte(hose, dev, 0x0B, &c1);	410	pci_hose_read_config_byte(hose, dev, 0x0B, &c1);
411	pci_hose_read_config_byte(hose, dev, 0x0A, &c2);	411	pci_hose_read_config_byte(hose, dev, 0x0A, &c2);
412	class = c1<<8 \| c2;	412	class = c1<<8 \| c2;
413	//printf("At %02x:%02x:%02x: class %x\n",	413	//printf("At %02x:%02x:%02x: class %x\n",
414	// PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), class);	414	// PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev), class);
415	if (class == find_class)	415	if (class == find_class)
416	{	416	{
417	if (index == 0)	417	if (index == 0)
418	return dev;	418	return dev;
419	else index--;	419	else index--;
420	}	420	}
421	}	421	}
422	}	422	}
423		423
424	return ~0;	424	return ~0;
425	}	425	}
426		426
427		427
428	/*	428	/*
429	* For a given bus number, find the bridge on this hose that provides this	429	* For a given bus number, find the bridge on this hose that provides this
430	* bus number. The function scans for bridges and peeks config space offset	430	* bus number. The function scans for bridges and peeks config space offset
431	* 0x19 (PCI_SECONDARY_BUS).	431	* 0x19 (PCI_SECONDARY_BUS).
432	*/	432	*/
433	pci_dev_t pci_find_bridge_for_bus(struct pci_controller *hose, int busnr)	433	pci_dev_t pci_find_bridge_for_bus(struct pci_controller *hose, int busnr)
434	{	434	{
435	pci_dev_t dev;	435	pci_dev_t dev;
436	int bus;	436	int bus;
437	unsigned int found_multi=0;	437	unsigned int found_multi=0;
438	unsigned char header_type;	438	unsigned char header_type;
439	unsigned short vendor;	439	unsigned short vendor;
440	unsigned char secondary_bus;	440	unsigned char secondary_bus;
441		441
442	if (hose == NULL) hose = &articiaS_hose;	442	if (hose == NULL) hose = &articiaS_hose;
443		443
444	if (busnr < hose->first_busno \|\| busnr > hose->last_busno) return PCI_ANY_ID; // Not in range	444	if (busnr < hose->first_busno \|\| busnr > hose->last_busno) return PCI_ANY_ID; // Not in range
445		445
446	/*	446	/*
447	* The bridge must be on a lower bus number	447	* The bridge must be on a lower bus number
448	*/	448	*/
449	for (bus = hose->first_busno; bus < busnr; bus++)	449	for (bus = hose->first_busno; bus < busnr; bus++)
450	{	450	{
451	for (dev = PCI_BDF(bus,0,0);	451	for (dev = PCI_BDF(bus,0,0);
452	dev < PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1);	452	dev < PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1);
453	dev += PCI_BDF(0,0,1))	453	dev += PCI_BDF(0,0,1))
454	{	454	{
455	if ( dev == PCI_BDF(hose->first_busno,0,0) )	455	if ( dev == PCI_BDF(hose->first_busno,0,0) )
456	continue;	456	continue;
457		457
458	if (PCI_FUNC(dev) && !found_multi)	458	if (PCI_FUNC(dev) && !found_multi)
459	continue;	459	continue;
460		460
461	pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);	461	pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
462		462
463	pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor);	463	pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor);
464		464
465	if (vendor != 0xffff && vendor != 0x0000)	465	if (vendor != 0xffff && vendor != 0x0000)
466	{	466	{
467		467
468	if (!PCI_FUNC(dev))	468	if (!PCI_FUNC(dev))
469	found_multi = header_type & 0x80;	469	found_multi = header_type & 0x80;
470	if (header_type == 1) // Bridge device header	470	if (header_type == 1) // Bridge device header
471	{	471	{
472	pci_hose_read_config_byte(hose, dev, PCI_SECONDARY_BUS, &secondary_bus);	472	pci_hose_read_config_byte(hose, dev, PCI_SECONDARY_BUS, &secondary_bus);
473	if ((int)secondary_bus == busnr) return dev;	473	if ((int)secondary_bus == busnr) return dev;
474	}	474	}
475		475
476	}	476	}
477	}	477	}
478	}	478	}
479	return PCI_ANY_ID;	479	return PCI_ANY_ID;
480	}	480	}
481		481
482	static short classes[] =	482	static short classes[] =
483	{	483	{
484	PCI_CLASS_DISPLAY_VGA,	484	PCI_CLASS_DISPLAY_VGA,
485	PCI_CLASS_DISPLAY_XGA,	485	PCI_CLASS_DISPLAY_XGA,
486	PCI_CLASS_DISPLAY_3D,	486	PCI_CLASS_DISPLAY_3D,
487	PCI_CLASS_DISPLAY_OTHER,	487	PCI_CLASS_DISPLAY_OTHER,
488	~0	488	~0
489	};	489	};
490		490
491	extern int execute_bios(pci_dev_t gr_dev, void *);	491	extern int execute_bios(pci_dev_t gr_dev, void *);
492		492
493	pci_dev_t video_dev;	493	pci_dev_t video_dev;
494		494
495	int articiaS_init_vga (void)	495	int articiaS_init_vga (void)
496	{	496	{
497	DECLARE_GLOBAL_DATA_PTR;	497	DECLARE_GLOBAL_DATA_PTR;
498		498
499	extern void shutdown_bios(void);	499	extern void shutdown_bios(void);
500	pci_dev_t dev = ~0;	500	pci_dev_t dev = ~0;
501	int busnr = 0;	501	int busnr = 0;
502	int classnr = 0;	502	int classnr = 0;
503		503
504	video_dev = PCI_ANY_ID;	504	video_dev = PCI_ANY_ID;
505		505
506	printf("VGA: ");	506	printf("VGA: ");
507		507
508	PRINTF("Trying to initialize x86 VGA Card(s)\n");	508	PRINTF("Trying to initialize x86 VGA Card(s)\n");
509		509
510	while (dev == ~0)	510	while (dev == ~0)
511	{	511	{
512	PRINTF("Searching for class 0x%x on bus %d\n", classes[classnr], busnr);	512	PRINTF("Searching for class 0x%x on bus %d\n", classes[classnr], busnr);
513	/* Find the first of this class on this bus */	513	/* Find the first of this class on this bus */
514	dev = pci_hose_find_class(&articiaS_hose, busnr, classes[classnr], 0);	514	dev = pci_hose_find_class(&articiaS_hose, busnr, classes[classnr], 0);
515	if (dev != ~0) break;	515	if (dev != ~0)
		516	{
		517	PRINTF("Found VGA Card at %02x:%02x:%02x\n", PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
		518	break;
		519	}
516	busnr++;	520	busnr++;
517	if (busnr > articiaS_hose.last_busno)	521	if (busnr > articiaS_hose.last_busno)
518	{	522	{
519	busnr = 0;	523	busnr = 0;
520	classnr ++;	524	classnr ++;
521	if (classes[classnr] == ~0)	525	if (classes[classnr] == ~0)
522	{	526	{
523	printf("NOT PRESENT\n");	527	printf("NOT PRESENT\n");
524	return -1;	528	return -1;
525	}	529	}
526	}	530	}
527	}	531	}
528		532
529	/*	533	/*
530	* If we get here we have found the first graphics card.	534	* If we get here we have found the first graphics card.
531	* If the bus number is not 0, then it is probably behind a bridge, and the	535	* If the bus number is not 0, then it is probably behind a bridge, and the
532	* bridge needs to be told to forward VGA access.	536	* bridge needs to be told to forward VGA access.
533	*/	537	*/
534		538
535	if (PCI_BUS(dev) != 0)	539	if (PCI_BUS(dev) != 0)
536	{	540	{
537	pci_dev_t bridge;	541	pci_dev_t bridge;
538	PRINTF("Behind bridge, looking for bridge\n");	542	PRINTF("Behind bridge, looking for bridge\n");
539	bridge = pci_find_bridge_for_bus(&articiaS_hose, PCI_BUS(dev));	543	bridge = pci_find_bridge_for_bus(&articiaS_hose, PCI_BUS(dev));
540	if (dev != PCI_ANY_ID)	544	if (dev != PCI_ANY_ID)
541	{	545	{
542	unsigned char agp_control_0;	546	unsigned char agp_control_0;
543	PRINTF("Got the bridge at %02x:%02x:%02x\n",	547	PRINTF("Got the bridge at %02x:%02x:%02x\n",
544	PCI_BUS(bridge), PCI_DEV(bridge), PCI_FUNC(bridge));	548	PCI_BUS(bridge), PCI_DEV(bridge), PCI_FUNC(bridge));
545	pci_hose_read_config_byte(&articiaS_hose, bridge, 0x3E, &agp_control_0);	549	pci_hose_read_config_byte(&articiaS_hose, bridge, 0x3E, &agp_control_0);
546	agp_control_0 \|= 0x18;	550	agp_control_0 \|= 0x18;
547	pci_hose_write_config_byte(&articiaS_hose, bridge, 0x3E, agp_control_0);	551	pci_hose_write_config_byte(&articiaS_hose, bridge, 0x3E, agp_control_0);
548	PRINTF("Configured for VGA forwarding\n");	552	PRINTF("Configured for VGA forwarding\n");
549	}	553	}
550	}	554	}
551		555
552	/*	556	/*
553	* Now try to run the bios	557	* Now try to run the bios
554	*/	558	*/
555		559	PRINTF("Trying to run bios now\n");
556	if (execute_bios(dev, gd->relocaddr))	560	if (execute_bios(dev, gd->relocaddr))
557	{	561	{
558	printf("OK\n");	562	printf("OK\n");
559	video_dev = dev;	563	video_dev = dev;
560	}	564	}
561	else	565	else
562	{	566	{
563	printf("ERROR\n");	567	printf("ERROR\n");
564	}	568	}
565		569
566	PRINTF("Done scanning.\n");	570	PRINTF("Done scanning.\n");
567		571
568	shutdown_bios();	572	shutdown_bios();
569		573
570	if (dev == PCI_ANY_ID) return -1;	574	if (dev == PCI_ANY_ID) return -1;
571	else return 0;	575	else return 0;
572		576
573	}	577	}
574		578

board/MAI/AmigaOneG3SE/config.mk

Diff comments View file @ 7c7a23b

board/MAI/AmigaOneG3SE/video.c

Diff comments View file @ 7c7a23b

 /*
  * (C) Copyright 2002
  * Hyperion Entertainment, Hans-JoergF@hyperion-entertainment.com
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 #include <common.h>
 #include <devices.h>
 #include "memio.h"
 #include <part.h>
 unsigned char *cursor_position;
 unsigned int cursor_row;
 unsigned int cursor_col;
 unsigned char current_attr;
 unsigned int video_numrows = 25;
 unsigned int video_numcols = 80;
 unsigned int video_scrolls = 0;
 #define VIDEO_BASE (unsigned char *)0xFD0B8000
 #define VIDEO_ROWS video_numrows
 #define VIDEO_COLS video_numcols
 #define VIDEO_PITCH (2 * video_numcols)
 #define VIDEO_SIZE (video_numrows * video_numcols * 2)
 #define VIDEO_NAME "vga"
 void video_test(void);
 void video_putc(char ch);
 void video_puts(char *string);
 void video_scroll(int rows);
 void video_banner(void);
 int  video_init(void);
 int  video_start(void);
 int  video_rows(void);
 int  video_cols(void);
 char *prompt_string = "=>";
 void video_set_color(unsigned char attr)
 {
     unsigned char *fb = (unsigned char *)VIDEO_BASE;
     int i;
     current_attr = video_get_attr();
     for (i=0; i<VIDEO_SIZE; i+=2)
     {
 	*(fb+i+1) = current_attr;
     }
 }
 unsigned char video_get_attr(void)
 {
     char *s;
     unsigned char attr;
     attr = 0x0f;
     s = getenv("vga_fg_color");
     if (s)
     {
 	attr = atoi(s);
     }
     s = getenv("vga_bg_color");
     if (s)
     {
 	attr |= atoi(s)<<4;
     }
     return attr;
 }
 int video_inited = 0;
 int drv_video_init(void)
 {
     int error, devices = 1 ;
     device_t vgadev ;
     if (video_inited) return 1;
     video_inited = 1;
     video_init();
     memset (&vgadev, 0, sizeof(vgadev));
     strcpy(vgadev.name, VIDEO_NAME);
     vgadev.flags =  DEV_FLAGS_OUTPUT | DEV_FLAGS_SYSTEM;
     vgadev.putc = video_putc;
     vgadev.puts = video_puts;
     vgadev.getc = NULL;
     vgadev.tstc = NULL;
     vgadev.start = video_start;
     error = device_register (&vgadev);
     if (error == 0)
     {
 	char *s = getenv("stdout");
 	if (s && strcmp(s, VIDEO_NAME)==0)
 	{
 	    if (overwrite_console()) return 1;
 	    error = console_assign(stdout, VIDEO_NAME);
 	    if (error == 0) return 1;
 	    else return error;
 	}
 	return 1;
     }
     return error;
 }
 int video_init(void)
 {
     cursor_position = VIDEO_BASE; // Color text display base
     cursor_row = 0;
     cursor_col = 0;
     current_attr = video_get_attr(); // Currently selected value for attribute.
 //    video_test();
     video_set_color(current_attr);
     return 0;
 }
 void video_set_cursor(int line, int column)
 {
     unsigned short offset = line*video_numcols + column;
     cursor_position = VIDEO_BASE +  line*VIDEO_PITCH + column*2;
     out_byte(0x3D4, 0x0E);
     out_byte(0x3D5, offset/256);
     out_byte(0x3D4, 0x0F);
     out_byte(0x3D5, offset%256);
 }
 void video_write_char(int character)
 {
     *cursor_position = character;
     *(cursor_position+1) = current_attr;
 }
 void video_test(void)
 {
 }
 void video_putc(char ch)
 {
     switch(ch)
     {
     case '\n':
 	cursor_col = 0;
 	cursor_row += 1;
 	break;
     case '\r':
 	cursor_col = 0;
 	break;
     case '\b':
 	if (cursor_col) cursor_col--;
 	else return;
 	break;
     case '\t':
 	cursor_col = (cursor_col/8+1)*8;
 	break;
     default:
 	video_write_char(ch);
 	cursor_col++;
 	if (cursor_col > VIDEO_COLS-1)
 	{
 	    cursor_row++;
 	    cursor_col=0;
 	}
     }
     if (cursor_row > VIDEO_ROWS-1)
 	video_scroll(1);
     video_set_cursor(cursor_row, cursor_col);
 }
 void video_scroll(int rows)
 {
     unsigned short clear = ((unsigned short)current_attr) | (' '<<8);
     unsigned short* addr16 = &((unsigned short *)VIDEO_BASE)[(VIDEO_ROWS-rows)*VIDEO_COLS];
     int i;
     char *s;
     s = getenv("vga_askscroll");
     video_scrolls += rows;
     if (video_scrolls >= video_numrows)
     {
 	if (s && strcmp(s, "yes"))
 	{
 	    while (-1 == tstc());
 	}
 	video_scrolls = 0;
     }
     memcpy(VIDEO_BASE, VIDEO_BASE+rows*(VIDEO_COLS*2), (VIDEO_ROWS-rows)*(VIDEO_COLS*2));
     for (i = 0 ; i < rows * VIDEO_COLS ; i++)
 	addr16[i] = clear;
     cursor_row-=rows;
     cursor_col=0;
 }
 void video_puts(char *string)
 {
     while (*string)
     {
 	video_putc(*string);
 	string++;
     }
 }
 int video_start(void)
 {
     return 0;
 }
 unsigned char video_single_box[] =
 {
     218, 196, 191,
     179,      179,
     192, 196, 217
 };
 unsigned char video_double_box[] =
 {
     201, 205, 187,
     186,      186,
     200, 205, 188
 };
 unsigned char video_single_title[] =
 {
     195, 196, 180, 180, 195
 };
 unsigned char video_double_title[] =
 {
     204, 205, 185, 181, 198
 };
 #define SINGLE_BOX 0
 #define DOUBLE_BOX 1
 unsigned char *video_addr(int x, int y)
 {
     return VIDEO_BASE + 2*(VIDEO_COLS*y) + 2*x;
 }
 void video_bios_print_string(char *s, int x, int y, int attr, int count)
 {
     int cattr = current_attr;
     if (attr != -1) current_attr = attr;
     video_set_cursor(x,y);
     while (count)
     {
 	char c = *s++;
 	if (attr == -1) current_attr = *s++;
 	video_putc(c);
 	count--;
     }
 }
 void video_draw_box(int style, int attr, char *title, int separate, int x, int y, int w, int h)
 {
     unsigned char *fb, *fb2;
     unsigned char *st = (style == SINGLE_BOX)?video_single_box : video_double_box;
     unsigned char *ti = (style == SINGLE_BOX)?video_single_title : video_double_title;
     int i;
     fb = video_addr(x,y);
     *(fb) = st[0];
     *(fb+1) = attr;
     fb += 2;
     fb2 = video_addr(x,y+h-1);
     *(fb2) = st[5];
     *(fb2+1) = attr;
     fb2 += 2;
     for (i=0; i<w-2;i++)
     {
 	*fb = st[1];
 	fb++;
 	*fb = attr;
 	fb++;
 	*fb2 = st[6];
 	fb2++;
 	*fb2 = attr;
 	fb2++;
     }
     *fb = st[2];
     *(fb+1) = attr;
     *fb2 = st[7];
     *(fb2+1) = attr;
     fb  = video_addr(x, y+1);
     fb2 = video_addr(x+w-1, y+1);
     for (i=0; i<h-2; i++)
     {
 	*fb = st[3];
 	*(fb+1) = attr; fb += 2*VIDEO_COLS;
 	*fb2 = st[4];
 	*(fb2+1) = attr; fb2 += 2*VIDEO_COLS;
     }
     // Draw title
     if (title)
     {
 	if (separate == 0)
 	{
 	    fb = video_addr(x+1, y);
 	    *fb = ti[3];
 	    fb += 2;
 	    *fb = ' ';
 	    fb += 2;
 	    while (*title)
 	    {
 		*fb = *title;
 		fb ++;
 		*fb = attr;
 		fb++; title++;
 	    }
 	    *fb = ' ';
 	    fb += 2;
 	    *fb = ti[4];
 	}
 	else
 	{
 	    fb = video_addr(x, y+2);
 	    *fb = ti[0];
 	    fb += 2;
 	    for (i=0; i<w-2; i++)
 	    {
 		*fb = ti[1];
 		*(fb+1) = attr;
 		fb += 2;
 	    }
 	    *fb = ti[2];
 	    *(fb+1) = attr;
 	    fb = video_addr(x+1, y+1);
 	    for (i=0; i<w-2; i++)
 	    {
 		*fb = ' ';
 		*(fb+1) = attr;
 		fb += 2;
 	    }
 	    fb = video_addr(x+2, y+1);
 	    while (*title)
 	    {
 		*fb = *title;
 		*(fb+1) = attr;
 		fb += 2;
 		title++;
 	    }
 	}
     }
 }
 void video_draw_text(int x, int y, int attr, char *text)
 {
     unsigned char *fb = video_addr(x,y);
     while (*text)
     {
 	*fb++ = *text++;
 	*fb++ = attr;
     }
 }
 void video_save_rect(int x, int y, int w, int h, void *save_area, int clearchar, int clearattr)
 {
     unsigned char *save = (unsigned char *)save_area;
     unsigned char *fb = video_addr(x,y);
     int i,j;
     for (i=0; i<h; i++)
     {
 	unsigned char *fbb = fb;
 	for (j=0; j<w; j++)
 	{
 	    *save ++ = *fb;
 	    if (clearchar > 0) *fb = clearchar;
 	    fb ++;
 	    *save ++ = *fb;
 	    if (clearattr > 0) *fb = clearattr;
 	}
 	fb = fbb + 2*VIDEO_COLS;
     }
 }
 void video_restore_rect(int x, int y, int w, int h, void *save_area)
 {
     unsigned char *save = (unsigned char *)save_area;
     unsigned char *fb = video_addr(x,y);
     int i,j;
     for (i=0; i<h; i++)
     {
 	unsigned char *fbb = fb;
 	for (j=0; j<w; j++)
 	{
 	    *fb ++ = *save ++;
 	    *fb ++ = *save ++;
 	}
 	fb = fbb + 2*VIDEO_COLS;
     }
 }
 int video_rows(void)
 {
     return VIDEO_ROWS;
 }
 int video_cols(void)
 {
     return VIDEO_COLS;
 }
 void video_size(int cols, int rows)
 {
     video_numrows = rows;
     video_numcols = cols;
 }
 void video_clear(void)
 {
     unsigned short *fbb = (unsigned short *)0xFD0B8000;
     int i,j;
     unsigned short val = 0x2000 | current_attr;
     for (i=0; i<video_rows(); i++)
     {
 	for (j=0; j<video_cols(); j++)
 	{
 	    *fbb++ = val;
 	}
     }
     video_set_cursor(0,0);
     cursor_row = 0;
     cursor_col = 0;
 }
 #ifdef EASTEREGG
 int video_easteregg_active = 0;
 void video_easteregg(void)
 {
     video_easteregg_active = 1;
 }
 #endif
-extern bd_t *bd_global;
 extern block_dev_desc_t * ide_get_dev(int dev);
 extern char version_string[];
 void video_banner(void)
 {
     block_dev_desc_t *ide;
+    DECLARE_GLOBAL_DATA_PTR;
     int i;
     char *s;
     int maxdev;
     if (video_inited == 0) return;
 #ifdef EASTEREGG
     if (video_easteregg_active)
     {
 	prompt_string="";
 	video_clear();
 	printf("\n");
 	printf("    **** COMMODORE 64 BASIC X2 ****\n\n");
 	printf(" 64K RAM SYSTEM  38911 BASIC BYTES FREE\n\n");
 	printf("READY\n");
     }
     else
     {
 #endif
 	s = getenv("ide_maxbus");
 	if (s)
 	    maxdev = atoi(s) * 2;
 	else
 	    maxdev = 4;
 	s = getenv("stdout");
 	if (s && strcmp(s, "serial") == 0)
 	    return;
 	video_clear();
 	printf("%s\n\nCPU: ", version_string);
 	checkcpu();
-	printf("DRAM: %ld MB\n", bd_global->bi_memsize/(1024*1024));
+	printf("DRAM: %ld MB\n", gd->bd->bi_memsize/(1024*1024));
-	printf("FSB: %ld MHz\n", bd_global->bi_busfreq/1000000);
+	printf("FSB: %ld MHz\n", gd->bd->bi_busfreq/1000000);
 	printf("\n---- Disk summary ----\n");
 	for (i = 0; i < maxdev; i++)
 	{
 	    ide = ide_get_dev(i);
 	    printf("Device %d: ", i);
 	    dev_print(ide);
 	}
 /*
     video_draw_box(SINGLE_BOX, 0x0F, "Test 1", 0, 0,18, 72, 4);
     video_draw_box(DOUBLE_BOX, 0x0F, "Test 2", 1, 4,10, 50, 6);
     video_draw_box(DOUBLE_BOX, 0x0F, "Test 3", 0, 40, 3, 20, 5);
     video_draw_text(1, 4, 0x2F, "Highlighted options");
     video_draw_text(1, 5, 0x0F, "Non-selected option");
     video_draw_text(1, 6, 0x07, "disabled option");
 */
 #ifdef EASTEREGG
     }
 #endif
 }

board/MAI/bios_emulator/glue.c

Diff comments View file @ 7c7a23b

 #include <common.h>
 #include <pci.h>
 #include <74xx_7xx.h>
 #ifdef DEBUG
 #undef DEBUG
 #endif
 #ifdef DEBUG
 #define PRINTF(format, args...) _printf(format , ## args)
 #else
 #define PRINTF(format, argc...)
 #endif
 static pci_dev_t to_pci(int bus, int devfn)
 {
     return PCI_BDF(bus, (devfn>>3), devfn&3);
 }
 int mypci_find_device(int vendor, int product, int index)
 {
     return pci_find_device(vendor, product, index);
 }
 int mypci_bus(int device)
 {
     return PCI_BUS(device);
 }
 int mypci_devfn(int device)
 {
     return (PCI_DEV(device)<<3) | PCI_FUNC(device);
 }
 #define mypci_read_func(type, size)				\
 type mypci_read_cfg_##size##(int bus, int devfn, int offset)	\
 {								\
     type c;							\
     pci_read_config_##size##(to_pci(bus, devfn), offset, &c);	\
     return c;							\
 }
 #define mypci_write_func(type, size)				\
 void mypci_write_cfg_##size##(int bus, int devfn, int offset, int value)	\
 {								\
     pci_write_config_##size##(to_pci(bus, devfn), offset, value);	\
 }
 mypci_read_func(u8,byte);
 mypci_read_func(u16,word);
 mypci_write_func(u8,byte);
 mypci_write_func(u16,word);
 u32 mypci_read_cfg_long(int bus, int devfn, int offset)
 {
     u32 c;
     pci_read_config_dword(to_pci(bus, devfn), offset, &c);
     return c;
 }
 void mypci_write_cfg_long(int bus, int devfn, int offset, int value)
 {
     pci_write_config_dword(to_pci(bus, devfn), offset, value);
 }
 void _printf(const char *fmt, ...)
 {
     va_list args;
     char buf[CFG_PBSIZE];
     va_start(args, fmt);
     (void)vsprintf(buf, fmt, args);
     va_end(args);
     printf(buf);
 }
 char *_getenv(char *name)
 {
     return getenv(name);
 }
 unsigned long get_bar_size(pci_dev_t dev, int offset)
 {
     u32 bar_back, bar_value;
     /*  Save old BAR value */
     pci_read_config_dword(dev, offset, &bar_back);
     /*  Write all 1's. */
     pci_write_config_dword(dev, offset, ~0);
     /*  Now read back the relevant bits */
     pci_read_config_dword(dev, offset, &bar_value);
     /*  Restore original value */
     pci_write_config_dword(dev, offset, bar_back);
     if (bar_value == 0) return 0xFFFFFFFF; /*  This BAR is disabled */
     if ((bar_value & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY)
     {
 	/*  This is a memory space BAR. Mask it out so we get the size of it */
 	return ~(bar_value & PCI_BASE_ADDRESS_MEM_MASK) + 1;
     }
     /*  Not suitable */
     return 0xFFFFFFFF;
 }
 void enable_compatibility_hole(void)
 {
     u8 cfg;
     pci_dev_t art = PCI_BDF(0,0,0);
     pci_read_config_byte(art, 0x54, &cfg);
     /* cfg |= 0x08; */
     cfg |= 0x20;
     pci_write_config_byte(art, 0x54, cfg);
 }
 void disable_compatibility_hole(void)
 {
     u8 cfg;
     pci_dev_t art = PCI_BDF(0,0,0);
     pci_read_config_byte(art, 0x54, &cfg);
     /* cfg &= ~0x08; */
     cfg &= ~0x20;
     pci_write_config_byte(art, 0x54, cfg);
 }
 void map_rom(pci_dev_t dev, u32 address)
 {
     pci_write_config_dword(dev, PCI_ROM_ADDRESS, address|PCI_ROM_ADDRESS_ENABLE);
 }
 void unmap_rom(pci_dev_t dev)
 {
     pci_write_config_dword(dev, PCI_ROM_ADDRESS, 0);
 }
 void bat_map(u8 batnum, u32 address, u32 length)
 {
     u32 temp = address;
     address &= 0xFFFE0000;
     temp    &= 0x0001FFFF;
     length = (length - 1 ) >> 17;
     length <<= 2;
     switch (batnum)
     {
     case 0:
 	__asm volatile ("mtdbatu 0, %0" : : "r" (address | length | 3));
 	__asm volatile ("mtdbatl 0, %0" : : "r" (address | 0x22));
 	break;
     case 1:
 	__asm volatile ("mtdbatu 1, %0" : : "r" (address | length | 3));
 	__asm volatile ("mtdbatl 1, %0" : : "r" (address | 0x22));
 	break;
     case 2:
 	__asm volatile ("mtdbatu 2, %0" : : "r" (address | length | 3));
 	__asm volatile ("mtdbatl 2, %0" : : "r" (address | 0x22));
 	break;
     case 3:
 	__asm volatile ("mtdbatu 3, %0" : : "r" (address | length | 3));
 	__asm volatile ("mtdbatl 3, %0" : : "r" (address | 0x22));
 	break;
     }
 }
 int find_image(u32 rom_address, u32 rom_size, void **image, u32 *image_size);
 int attempt_map_rom(pci_dev_t dev, void *copy_address)
 {
     u32 rom_size      = 0;
     u32 rom_address   = 0;
     u32 bar_size      = 0;
     u32 bar_backup    = 0;
     int i,j;
     void *image       = 0;
     u32 image_size    = 0;
     int did_correct   = 0;
     u32 prefetch_addr = 0;
     u32 prefetch_size = 0;
     u32 prefetch_idx  = 0;
     /*  Get the size of the expansion rom */
     pci_write_config_dword(dev, PCI_ROM_ADDRESS, 0xFFFFFFFF);
     pci_read_config_dword(dev, PCI_ROM_ADDRESS, &rom_size);
     if ((rom_size & 0x01) == 0)
     {
 	PRINTF("No ROM\n");
 	return 0;
     }
     rom_size &= 0xFFFFF800;
     rom_size = (~rom_size)+1;
     PRINTF("ROM Size is %dK\n", rom_size/1024);
     /*
      * Try to find a place for the ROM. We always attempt to use
      * one of the card's bases for this, as this will be in any
      * bridge's resource range as well as being free of conflicts
      * with other cards. In a graphics card it is very unlikely
      * that there won't be any base address that is large enough to
      * hold the rom.
      *
      * FIXME: To work around this, theoretically the largest base
      * could be used if none is found in the loop below.
      */
     for (i = PCI_BASE_ADDRESS_0; i <= PCI_BASE_ADDRESS_5; i += 4)
     {
 	bar_size = get_bar_size(dev, i);
 	PRINTF("PCI_BASE_ADDRESS_%d is %dK large\n",
 	       (i - PCI_BASE_ADDRESS_0)/4,
 	       bar_size/1024);
 	if (bar_size != 0xFFFFFFFF && bar_size >= rom_size)
 	{
 	    PRINTF("Found a match for rom size\n");
 	    pci_read_config_dword(dev, i, &rom_address);
 	    rom_address &= 0xFFFFFFF0;
 	    if (rom_address != 0 && rom_address != 0xFFFFFFF0) break;
 	}
     }
     if (rom_address == 0 || rom_address == 0xFFFFFFF0)
     {
 	PRINTF("No suitable rom address found\n");
 	return 0;
     }
     /*  Disable the BAR */
     pci_read_config_dword(dev, i, &bar_backup);
     pci_write_config_dword(dev, i, 0);
     /*  Map ROM */
     pci_write_config_dword(dev, PCI_ROM_ADDRESS, rom_address | PCI_ROM_ADDRESS_ENABLE);
     /*  Copy the rom to a place in the emulator space */
     PRINTF("Claiming BAT 2\n");
     bat_map(2, rom_address, rom_size);
     /* show_bat_mapping(); */
     if (0 == find_image(rom_address, rom_size, &image, &image_size))
     {
 	PRINTF("No x86 BIOS image found\n");
 	return 0;
     }
     PRINTF("Copying %ld bytes from 0x%lx to 0x%lx\n", (long)image_size, (long)image, (long)copy_address);
     /* memcpy(copy_address, rom_address, rom_size); */
     {
 	unsigned char *from = (unsigned char *)image; /* rom_address; */
 	unsigned char *to = (unsigned char *)copy_address;
 	for (j=0; j<image_size /*rom_size*/; j++)
 	{
 	    *to++ = *from++;
 	}
     }
     PRINTF("Copy is done\n");
     /*  Unmap the ROM and restore the BAR */
     pci_write_config_dword(dev, PCI_ROM_ADDRESS, 0);
     pci_write_config_dword(dev, i, bar_backup);
-    /*  FIXME: */
+    /*  FIXME: Shouldn't be needed anymore*/
-    bat_map(2, 0x80000000, 256*1024*1024);
+    /* bat_map(2, 0x80000000, 256*1024*1024);
-    show_bat_mapping();
+       show_bat_mapping(); */
     /*
      * Since most cards can probably only do 16 bit IO addressing, we
      * correct their IO base into an appropriate value.
      * This should do for most.
      */
     for (i = PCI_BASE_ADDRESS_0; i <= PCI_BASE_ADDRESS_5; i += 4)
     {
 	unsigned long value;
 	pci_read_config_dword(dev, i, &value);
 	if (value & 0x01) /*  IO */
 	{
 	    did_correct = 1;
 	    pci_write_config_dword(dev, i, 0x1001);
 	    break;
 	}
 	if (value & PCI_BASE_ADDRESS_MEM_PREFETCH)
 	{
 	    prefetch_idx = i;
 	    prefetch_addr = value & PCI_BASE_ADDRESS_MEM_MASK;
 	    prefetch_size = get_bar_size(dev, i);
 	}
     }
     if (1) /* did_correct) */
     {
 	extern pci_dev_t pci_find_bridge_for_bus(struct pci_controller *hose, int busnr);
 	int busnr = PCI_BUS(dev);
 	if (busnr)
 	{
 	    pci_dev_t bridge;
 	    PRINTF("Need to correct bridge device for IO range change\n");
 	    bridge = pci_find_bridge_for_bus(NULL, busnr);
 	    if (bridge == PCI_ANY_ID)
 	    {
 		PRINTF("Didn't find bridge. Hope that's OK\n");
 	    }
 	    else
 	    {
 		/*
 		 * Set upper I/O base/limit to 0
 		 */
 		pci_write_config_byte(bridge, 0x30, 0x00);
 		pci_write_config_byte(bridge, 0x31, 0x00);
 		pci_write_config_byte(bridge, 0x32, 0x00);
 		pci_write_config_byte(bridge, 0x33, 0x00);
 		if (did_correct)
 		{
 		    /*
 		     * set lower I/O base to 1000
 		     * That is, bits 0:3 are set to 0001 by default.
 		     * bits 7:4 contain I/O address bits 15:12
 		     * all others are assumed 0.
 		     */
 		    pci_write_config_byte(bridge, 0x1C, 0x11);
 		    /*
 		     * Set lower I/O limit to 1FFF
 		     * That is, bits 0:3 are reserved and always 0000
 		     * Bits 7:4 contain I/O address bits 15:12
 		     * All others are assumed F.
 		     */
 		    pci_write_config_byte(bridge, 0x1D, 0x10);
 		    pci_write_config_byte(bridge, 0x0D, 0x20);
 		    PRINTF("Corrected bridge resource range of bridge at %02x:%02x:%02x\n",
 			   PCI_BUS(bridge), PCI_DEV(bridge), PCI_FUNC(bridge));
 		}
 		else
 		{
 		    /*
 		     * This card doesn't have I/O, we disable I/O forwarding
 		     */
 		    pci_write_config_byte(bridge, 0x1C, 0x11);
 		    pci_write_config_byte(bridge, 0x1D, 0x00);
 		    pci_write_config_byte(bridge, PCI_INTERRUPT_LINE, 0);
 		    pci_write_config_byte(bridge, PCI_INTERRUPT_PIN, 0);
 		    pci_write_config_dword(bridge, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_IO);
 		    PRINTF("Disabled bridge resource range of bridge at %02x:%02x:%02x\n",
 			   PCI_BUS(bridge), PCI_DEV(bridge), PCI_FUNC(bridge));
 		}
 	    }
 	    /*
 	     * Correct the prefetchable memory base, which is not set correctly by
 	     * the U-Boot autoconfig stuff
 	     */
 	    if (prefetch_idx)
 	    {
 /* 		PRINTF("Setting prefetchable range to %x, %x (%x and %x)\n", */
 /* 		       prefetch_addr, prefetch_addr+prefetch_size, */
 /* 		       prefetch_addr>>16, (prefetch_addr+prefetch_size)>>16); */
 /* 		pci_write_config_word(bridge, PCI_PREF_MEMORY_BASE, (prefetch_addr>>16)); */
 /* 		pci_write_config_word(bridge, PCI_PREF_MEMORY_LIMIT, (prefetch_addr+prefetch_size)>>16); */
 	    }
 	    pci_write_config_word(bridge, PCI_PREF_MEMORY_BASE, 0x1000);
 	    pci_write_config_word(bridge, PCI_PREF_MEMORY_LIMIT, 0x0000);
 	    pci_write_config_byte(bridge, 0xD0, 0x0A);
 	    pci_write_config_byte(bridge, 0xD3, 0x04);
 	    /*
 	     * Set the interrupt pin to 0
 	     */
 #if 0
 	    pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 0);
 	    pci_write_config_byte(dev, PCI_INTERRUPT_PIN, 0);
 #endif
 	    pci_write_config_byte(bridge, PCI_INTERRUPT_LINE, 0);
 	    pci_write_config_byte(bridge, PCI_INTERRUPT_PIN, 0);
 	}
     }
     /* Finally, enable the card's IO and memory response */
     pci_write_config_dword(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
     pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0);
     pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0);
     return 1;
 }
 int find_image(u32 rom_address, u32 rom_size, void **image, u32 *image_size)
 {
     int i = 0;
     unsigned char *rom = (unsigned char *)rom_address;
     /* if (*rom != 0x55 || *(rom+1) != 0xAA) return 0; // No bios rom this is, yes. */
     for (;;)
     {
 	unsigned short pci_data_offset = *(rom+0x18) + 256 * *(rom+0x19);
 	unsigned short pci_image_length = (*(rom+pci_data_offset+0x10) + 256 * *(rom+pci_data_offset+0x11)) * 512;
 	unsigned char pci_image_type = *(rom+pci_data_offset+0x14);
 	if (*rom != 0x55 || *(rom+1) != 0xAA)
 	{
 	    PRINTF("Invalid header this is\n");
 	    return 0;
 	}
 	PRINTF("Image %i: Type %d (%s)\n", i++, pci_image_type,
 	       pci_image_type==0 ? "x86" :
 	       pci_image_type==1 ? "OpenFirmware" :
 	       "Unknown");
 	if (pci_image_type == 0)
 	{
 	    *image = rom;
 	    *image_size = pci_image_length;
 	    return 1;
 	}
 	if (*(rom+pci_data_offset+0x15) & 0x80)
 	{
 	    PRINTF("LAST image encountered, no image found\n");
 	    return 0;
 	}
 	rom += pci_image_length;
     }
 }
 void show_bat_mapping(void)
 {
-#ifdef DEBUG
     u32 dbat0u, dbat0l, ibat0u, ibat0l;
     u32 dbat1u, dbat1l, ibat1u, ibat1l;
     u32 dbat2u, dbat2l, ibat2u, ibat2l;
     u32 dbat3u, dbat3l, ibat3u, ibat3l;
     u32 msr, hid0, l2cr_reg;
     __asm volatile ("mfdbatu %0,0" : "=r" (dbat0u));
     __asm volatile ("mfdbatl %0,0" : "=r" (dbat0l));
     __asm volatile ("mfibatu %0,0" : "=r" (ibat0u));
     __asm volatile ("mfibatl %0,0" : "=r" (ibat0l));
     __asm volatile ("mfdbatu %0,1" : "=r" (dbat1u));
     __asm volatile ("mfdbatl %0,1" : "=r" (dbat1l));
     __asm volatile ("mfibatu %0,1" : "=r" (ibat1u));
     __asm volatile ("mfibatl %0,1" : "=r" (ibat1l));
     __asm volatile ("mfdbatu %0,2" : "=r" (dbat2u));
     __asm volatile ("mfdbatl %0,2" : "=r" (dbat2l));
     __asm volatile ("mfibatu %0,2" : "=r" (ibat2u));
     __asm volatile ("mfibatl %0,2" : "=r" (ibat2l));
     __asm volatile ("mfdbatu %0,3" : "=r" (dbat3u));
     __asm volatile ("mfdbatl %0,3" : "=r" (dbat3l));
     __asm volatile ("mfibatu %0,3" : "=r" (ibat3u));
     __asm volatile ("mfibatl %0,3" : "=r" (ibat3l));
     __asm volatile ("mfmsr %0"     : "=r" (msr));
     __asm volatile ("mfspr %0,1008": "=r" (hid0));
     __asm volatile ("mfspr %0,1017": "=r" (l2cr_reg));
     printf("dbat0u: %08x dbat0l: %08x ibat0u: %08x ibat0l: %08x\n",
 	   dbat0u, dbat0l, ibat0u, ibat0l);
     printf("dbat1u: %08x dbat1l: %08x ibat1u: %08x ibat1l: %08x\n",
 	   dbat1u, dbat1l, ibat1u, ibat1l);
     printf("dbat2u: %08x dbat2l: %08x ibat2u: %08x ibat2l: %08x\n",
 	   dbat2u, dbat2l, ibat2u, ibat2l);
     printf("dbat3u: %08x dbat3l: %08x ibat3u: %08x ibat3l: %08x\n",
 	   dbat3u, dbat3l, ibat3u, ibat3l);
     printf("\nMSR: %08x   HID0: %08x   L2CR: %08x \n", msr,hid0, l2cr_reg);
-#endif
 }
 void remove_init_data(void)
 {
     char *s;
-    u32 batl = ((CFG_SDRAM_BASE+0x100000) | BATL_PP_RW);
-    u32 batu =((CFG_SDRAM_BASE+0x100000) | BATU_BL_256M | BATU_VS | BATU_VP);
-#if 0	/* already done in board_init_r() */
-    void *data = (void *)(CFG_INIT_RAM_ADDR+CFG_INIT_DATA_OFFSET);
-    unsigned char data2[CFG_INIT_DATA_SIZE];
-    /*  Make a copy of the data */
-    memcpy(data2, data, CFG_INIT_DATA_SIZE);
-#endif /* 0 */
     /*  Invalidate and disable data cache */
     invalidate_l1_data_cache();
     dcache_disable();
-#if 0
-    /*  Copy to the real RAM address */
-    memcpy(data, data2, CFG_INIT_DATA_SIZE);
-#endif
-    /*printf("Before ICache enable\n");
-      show_bat_mapping();*/
-    __asm volatile ("isync        \n"
-		    "mtdbatu 2,%2 \n"
-		    "mtdbatl 2,%2 \n"
-	            "mtdbatu 1,%0 \n"
-		    "mtdbatl 1,%1 \n"
-		    "sync         \n"
-		    "isync        \n"
-		    : : "r" (batu), "r" (batl), "r" (0));
-    /* show_bat_mapping(); */
     s = getenv("x86_cache");
-    if (!s || (s && strcmp(s, "on")==0))
+    if (!s)
     {
 	icache_enable();
 	dcache_enable();
     }
+    else if (s)
+    {
+        if (strcmp(s, "dcache")==0)

board/MAI/bios_emulator/scitech/src/x86emu/makefile.uboot

Diff comments View file @ 7c7a23b

File was created	1	#############################################################################
	2	#
	3	# Realmode X86 Emulator Library
	4	#
	5	# Copyright (C) 1996-1999 SciTech Software, Inc.
	6	#
	7	# ========================================================================
	8	#
	9	# Permission to use, copy, modify, distribute, and sell this software and
	10	# its documentation for any purpose is hereby granted without fee,
	11	# provided that the above copyright notice appear in all copies and that
	12	# both that copyright notice and this permission notice appear in
	13	# supporting documentation, and that the name of the authors not be used
	14	# in advertising or publicity pertaining to distribution of the software
	15	# without specific, written prior permission. The authors makes no
	16	# representations about the suitability of this software for any purpose.
	17	# It is provided "as is" without express or implied warranty.
	18	#
	19	# THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
	20	# INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
	21	# EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
	22	# CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
	23	# USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
	24	# OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
	25	# PERFORMANCE OF THIS SOFTWARE.
	26	#
	27	# ========================================================================
	28	#
	29	# Descripton: Linux specific makefile for the x86emu library.
	30	#
	31	#############################################################################
	32	CC = $(CROSS_COMPILE)gcc
	33	AR = $(CROSS_COMPILE)ar
	34	TARGETLIB = libx86emu.a
	35	TARGETDEBUGLIB =libx86emud.a
	36
	37	OBJS=\
	38	decode.o \
	39	fpu.o \
	40	ops.o \
	41	ops2.o \
	42	prim_ops.o \
	43	sys.o
	44
	45	DEBUGOBJS=debug.d \
	46	decode.d \
	47	fpu.d \
	48	ops.d \
	49	ops2.d \
	50	prim_ops.d \
	51	sys.d
	52
	53	.SUFFIXES: .d
	54
	55	all: $(TARGETLIB) $(TARGETDEBUGLIB)
	56
	57	$(TARGETLIB): $(OBJS)
	58	$(AR) rv $(TARGETLIB) $(OBJS)
	59
	60	$(TARGETDEBUGLIB): $(DEBUGOBJS)
	61	$(AR) rv $(TARGETDEBUGLIB) $(DEBUGOBJS)
	62
	63	INCS = -I. -Ix86emu -I../../include
	64	CFLAGS = -D__DRIVER__ -DFORCE_POST -D_CEXPORT= -DNO_LONG_LONG -Dprintk=printf -fsigned-char -fomit-frame-pointer -mrelocatable -ffixed-r14 -meabi -mrelocatable -ffixed-r14 -meabi
	65	CDEBUGFLAGS = -DDEBUG
	66
	67	.c.o:
	68	$(CC) -g -O2 -Wall -c $(CFLAGS) $(INCS) $*.c
	69
	70	.c.d:
	71	$(CC) -g -O2 -Wall -c -o$.d $(CFLAGS) $(CDEBUGFLAGS) $(INCS) $.c
	72
	73	.cpp.o:
	74	$(CC) -c $(CFLAGS) $(INCS) $*.cpp
	75
	76	clean:
	77	rm -f .a .o *.d
	78
	79	validate: validate.o libx86emu.a
	80	$(CC) -o validate validate.o -lx86emu -L.
	81

board/MAI/bios_emulator/x86interface.c

Diff comments View file @ 7c7a23b

 #include "x86emu.h"
 #include "glue.h"
 /*
  * This isn't nice, but there are a lot of incompatibilities in the U-Boot and scitech include
  * files that this is the only really workable solution.
  * Might be cleaned out later.
  */
 #ifdef DEBUG
 #undef DEBUG
 #endif
 #undef IO_LOGGING
 #undef MEM_LOGGING
 #ifdef IO_LOGGING
 #define LOGIO(port, format, args...) if (dolog(port)) _printf(format , ## args)
 #else
 #define LOGIO(port, format, args...)
 #endif
 #ifdef MEM_LOGGIN
 #define LOGMEM(format, args...) _printf(format , ## args)
 #else
 #define LOGMEM(format, args...)
 #endif
 #ifdef DEBUG
 #define PRINTF(format, args...) _printf(format , ## args)
 #else
 #define PRINTF(format, argc...)
 #endif
 typedef unsigned char UBYTE;
 typedef unsigned short UWORD;
 typedef unsigned long ULONG;
 typedef char BYTE;
 typedef short WORT;
 typedef long LONG;
 #define EMULATOR_MEM_SIZE       (1024*1024)
 #define EMULATOR_BIOS_OFFSET    0xC0000
 #define EMULATOR_STRAP_OFFSET   0x30000
 #define EMULATOR_STACK_OFFSET   0x20000
 #define EMULATOR_LOGO_OFFSET    0x40000 // If you change this, change the strap code, too
 #define VIDEO_BASE (void *)0xFD0B8000
 extern char *getenv(char *);
 extern int tstc(void);
 extern int getc(void);
 extern unsigned char video_get_attr(void);
 int atoi(char *string)
 {
     int res = 0;
     while (*string>='0' && *string <='9')
     {
 	res *= 10;
 	res += *string-'0';
 	string++;
     }
     return res;
 }
 void cons_gets(char *buffer)
 {
     int i = 0;
     char c = 0;
     buffer[0] = 0;
     if (getenv("x86_runthru")) return; //FIXME:
     while (c != 0x0D && c != 0x0A)
     {
 	while (!tstc());
 	c = getc();
 	if (c>=32 && c < 127)
 	{
 	    buffer[i] = c;
 	    i++;
 	    buffer[i] = 0;
 	    putc(c);
 	}
 	else
 	{
 	    if (c == 0x08)
 	    {
 		if (i>0) i--;
 		buffer[i] = 0;
 	    }
 	}
     }
     buffer[i] = '\n';
     buffer[i+1] = 0;
 }
 char *bios_date = "08/14/02";
 UBYTE model = 0xFC;
 UBYTE submodel = 0x00;
 static inline UBYTE read_byte(volatile UBYTE* from)
 {
     int x;
     asm volatile ("lbz %0,%1\n eieio" : "=r" (x) : "m" (*from));
     return (UBYTE)x;
 }
 static inline void write_byte(volatile UBYTE *to, int x)
 {
     asm volatile ("stb %1,%0\n eieio" : "=m" (*to) : "r" (x));
 }
 static inline UWORD read_word_little(volatile UWORD *from)
 {
     int x;
     asm volatile ("lhbrx %0,0,%1\n eieio" : "=r" (x) : "r" (from), "m" (*from));
     return (UWORD)x;
 }
 static inline UWORD read_word_big(volatile UWORD *from)
 {
     int x;
     asm volatile ("lhz %0,%1\n eieio" : "=r" (x) : "m" (*from));
     return (UWORD)x;
 }
 static inline void write_word_little(volatile UWORD *to, int x)
 {
     asm volatile ("sthbrx %1,0,%2\n eieio" : "=m" (*to) : "r" (x), "r" (to));
 }
 static inline void write_word_big(volatile UWORD *to, int x)
 {
     asm volatile ("sth %1,%0\n eieio" : "=m" (*to) : "r" (x));
 }
 static inline ULONG read_long_little(volatile ULONG *from)
 {
     unsigned long x;
     asm volatile ("lwbrx %0,0,%1\n eieio" : "=r" (x) : "r" (from), "m"(*from));
     return (ULONG)x;
 }
 static inline ULONG read_long_big(volatile ULONG *from)
 {
     unsigned long x;
     asm volatile ("lwz %0,%1\n eieio" : "=r" (x) : "m" (*from));
     return (ULONG)x;
 }
 static inline void write_long_little(volatile ULONG *to, ULONG x)
 {
     asm volatile ("stwbrx %1,0,%2\n eieio" : "=m" (*to) : "r" (x), "r" (to));
 }
 static inline void write_long_big(volatile ULONG *to, ULONG x)
 {
     asm volatile ("stw %1,%0\n eieio" : "=m" (*to) : "r" (x));
 }
 static int log_init = 0;
 static int log_do = 0;
 static int log_low = 0;
 int dolog(int port)
 {
     if (log_init && log_do)
     {
 	if (log_low && port > 0x400) return 0;
 	return 1;
     }
     if (!log_init)
     {
 	log_init = 1;
 	log_do = (getenv("x86_logio") != (char *)0);
 	log_low = (getenv("x86_loglow") != (char *)0);
 	if (log_do)
 	{
 	    if (log_low && port > 0x400) return 0;
 	    return 1;
 	}
     }
     return 0;
 }
 // Converts an emulator address to a physical address.
 // Handles all special cases (bios date, model etc), and might need work
 u32 memaddr(u32 addr)
 {
 //    if (addr >= 0xF0000 && addr < 0xFFFFF) printf("WARNING: Segment F access (0x%x)\n", addr);
 //    printf("MemAddr=%p\n", addr);
     if (addr >= 0xA0000 && addr < 0xC0000)
 	return 0xFD000000 + addr;
     else if (addr >= 0xFFFF5 && addr < 0xFFFFE)
     {
 	return (u32)bios_date+addr-0xFFFF5;
     }
     else if (addr == 0xFFFFE)
 	return (u32)&model;
     else if (addr == 0xFFFFF)
 	return (u32)&submodel;
     else if (addr >= 0x80000000)
     {
 	//printf("Warning: High memory access at 0x%x\n", addr);
 	return addr;
     }
     else
 	return (u32)M.mem_base+addr;
 }
 u8 A1_rdb(u32 addr)
 {
     u8 a = read_byte((UBYTE *)memaddr(addr));
     LOGMEM("rdb: %x -> %x\n", addr, a);
     return a;
 }
 u16 A1_rdw(u32 addr)
 {
     u16 a = read_word_little((UWORD *)memaddr(addr));
     LOGMEM("rdw: %x -> %x\n", addr, a);
     return a;
 }
 u32 A1_rdl(u32 addr)
 {
     u32 a = read_long_little((ULONG *)memaddr(addr));
     LOGMEM("rdl: %x -> %x\n", addr, a);
     return a;
 }
 void A1_wrb(u32 addr, u8 val)
 {
     LOGMEM("wrb: %x <- %x\n", addr, val);
     write_byte((UBYTE *)memaddr(addr), val);
 }
 void A1_wrw(u32 addr, u16 val)
 {
     LOGMEM("wrw: %x <- %x\n", addr, val);
     write_word_little((UWORD *)memaddr(addr), val);
 }
 void A1_wrl(u32 addr, u32 val)
 {
     LOGMEM("wrl: %x <- %x\n", addr, val);
     write_long_little((ULONG *)memaddr(addr), val);
 }
 X86EMU_memFuncs _A1_mem =
 {
     A1_rdb,
     A1_rdw,
     A1_rdl,
     A1_wrb,
     A1_wrw,
     A1_wrl,
 };
 #define ARTICIAS_PCI_CFGADDR  0xfec00cf8
 #define ARTICIAS_PCI_CFGDATA  0xfee00cfc
 #define IOBASE                0xFE000000
 #define in_byte(from) read_byte( (UBYTE *)port_to_mem(from))
 #define in_word(from) read_word_little((UWORD *)port_to_mem(from))
 #define in_long(from) read_long_little((ULONG *)port_to_mem(from))
 #define out_byte(to, val) write_byte((UBYTE *)port_to_mem(to), val)
 #define out_word(to, val) write_word_little((UWORD *)port_to_mem(to), val)
 #define out_long(to, val) write_long_little((ULONG *)port_to_mem(to), val)
 u32 port_to_mem(int port)
 {
     if (port >= 0xCFC && port <= 0xCFF) return 0xFEE00000+port;
     else if (port >= 0xCF8 && port <= 0xCFB) return 0xFEC00000+port;
     else return IOBASE + port;
 }
 u8 A1_inb(int port)
 {
     u8 a;
     //if (port == 0x3BA) return 0;
     a = in_byte(port);
     LOGIO(port, "inb: %Xh -> %d (%Xh)\n", port, a, a);
     return a;
 }
 u16 A1_inw(int port)
 {
     u16 a = in_word(port);
     LOGIO(port, "inw: %Xh -> %d (%Xh)\n", port, a, a);
     return a;
 }
 u32 A1_inl(int port)
 {
     u32 a = in_long(port);
     LOGIO(port, "inl: %Xh -> %d (%Xh)\n", port, a, a);
     return a;
 }
 void A1_outb(int port, u8 val)
 {
     LOGIO(port, "outb: %Xh <- %d (%Xh)\n", port, val, val);
 /*    if (port == 0xCF8) port = 0xCFB;
     else if (port == 0xCF9) port = 0xCFA;
     else if (port == 0xCFA) port = 0xCF9;
     else if (port == 0xCFB) port = 0xCF8;*/
     out_byte(port, val);
 }
 void A1_outw(int port, u16 val)
 {
     LOGIO(port, "outw: %Xh <- %d (%Xh)\n", port, val, val);
     out_word(port, val);
 }
 void A1_outl(int port, u32 val)
 {
     LOGIO(port, "outl: %Xh <- %d (%Xh)\n", port, val, val);
     out_long(port, val);
 }
 X86EMU_pioFuncs _A1_pio =
 {
     A1_inb,
     A1_inw,
     A1_inl,
     A1_outb,
     A1_outw,
     A1_outl,
 };
 static int reloced_ops = 0;
 void reloc_ops(void *reloc_addr)
 {
     extern void (*x86emu_optab[256])(u8);
     extern void (*x86emu_optab2[256])(u8);
     extern void tables_relocate(unsigned int offset);
     int i;
     unsigned long delta;
     if (reloced_ops == 1) return;
     reloced_ops = 1;
     delta = TEXT_BASE - (unsigned long)reloc_addr;
     for (i=0; i<256; i++)
     {
 	x86emu_optab[i] -= delta;
 	x86emu_optab2[i] -= delta;
     }
     _A1_mem.rdb = A1_rdb;
     _A1_mem.rdw = A1_rdw;
     _A1_mem.rdl = A1_rdl;
     _A1_mem.wrb = A1_wrb;
     _A1_mem.wrw = A1_wrw;
     _A1_mem.wrl = A1_wrl;
     _A1_pio.inb = A1_inb;
     _A1_pio.inw = A1_inw;
     _A1_pio.inl = A1_inl;
     _A1_pio.outb = A1_outb;
     _A1_pio.outw = A1_outw;
     _A1_pio.outl = A1_outl;
     tables_relocate(delta);
 }
 #define ANY_KEY(text)				\
     printf(text);				\
     while (!tstc());
 unsigned char more_strap[] = {
         0xb4, 0x0, 0xb0, 0x2, 0xcd, 0x10,
 };
 #define MORE_STRAP_BYTES 6 // Additional bytes of strap code
 unsigned char *done_msg="VGA Initialized\0";
 int execute_bios(pci_dev_t gr_dev, void *reloc_addr)
 {
     extern void bios_init(void);
     extern void remove_init_data(void);
     extern int video_rows(void);
     extern int video_cols(void);
     extern int video_size(int, int);
     u8 *strap;
     unsigned char *logo;
     u8 cfg;
     int i;
     char c;
-#ifdef DEBUG
     char *s;
-#endif
 #ifdef EASTEREGG
     int easteregg_active = 0;
 #endif
     char *pal_reset;
     u8 *fb;
     unsigned char *msg;
     unsigned char current_attr;
+    PRINTF("Trying to remove init data\n");
     remove_init_data();
     PRINTF("Removed init data from cache, now in RAM\n");
     reloc_ops(reloc_addr);
     PRINTF("Attempting to run emulator on %02x:%02x:%02x\n",
 	   PCI_BUS(gr_dev), PCI_DEV(gr_dev), PCI_FUNC(gr_dev));
     // Enable compatibility hole for emulator access to frame buffer
     PRINTF("Enabling compatibility hole\n");
     enable_compatibility_hole();
     // Allocate memory
     // FIXME: We shouldn't use this much memory really.
     memset(&M, 0, sizeof(X86EMU_sysEnv));
     M.mem_base = malloc(EMULATOR_MEM_SIZE);
     M.mem_size = EMULATOR_MEM_SIZE;
     if (!M.mem_base)
     {
 	PRINTF("Unable to allocate one megabyte for emulator\n");
 	return 0;
     }
     if (attempt_map_rom(gr_dev, M.mem_base + EMULATOR_BIOS_OFFSET) == 0)
     {
 	PRINTF("Error mapping rom. Emulation terminated\n");
 	return 0;
     }
-#ifdef DEBUG
+#if 1 /*def DEBUG*/
     s = getenv("x86_ask_start");
     if (s)
     {
 	printf("Press 'q' to skip initialization, 'd' for dry init\n'i' for i/o session");
 	while (!tstc());
 	c = getc();
 	if (c == 'q') return 0;
 	if (c == 'd')
 	{
 	    extern void bios_set_mode(int mode);
 	    bios_set_mode(0x03);
 	    return 0;
 	}
 	if (c == 'i') do_inout();
     }
 #endif
 #ifdef EASTEREGG
 /*    if (tstc())
     {
 	if (getc() == 'c')
 	{
 	    easteregg_active = 1;
 	}
     }
 */
     if (getenv("easteregg"))
     {
 	easteregg_active = 1;
     }
     if (easteregg_active)
     {
 	// Yay!
 	setenv("x86_mode", "1");
 	setenv("vga_fg_color", "11");
 	setenv("vga_bg_color", "1");
 	easteregg_active = 1;
     }
 #endif
     strap = (u8*)M.mem_base + EMULATOR_STRAP_OFFSET;
     {
 	char *m = getenv("x86_mode");
 	if (m)
 	{
 	    more_strap[3] = atoi(m);
 	    if (more_strap[3] == 1) video_size(40, 25);
 	    else                    video_size(80, 25);
 	}
     }
     /*
      * Poke the strap routine. This might need a bit of extending
      * if there is a mode switch involved, i.e. we want to int10
      * afterwards to set a different graphics mode, or alternatively
      * there might be a different start address requirement if the
      * ROM doesn't have an x86 image in its first image.
      */
     PRINTF("Poking strap...\n");
     // FAR CALL c000:0003
     *strap++ = 0x9A; *strap++ = 0x03; *strap++ = 0x00;
     *strap++ = 0x00; *strap++ = 0xC0;
 #if 1
     // insert additional strap code
     for (i=0; i < MORE_STRAP_BYTES; i++)
     {
 	*strap++ = more_strap[i];
     }
 #endif
     // HALT
     *strap++ = 0xF4;
     PRINTF("Setting up logo data\n");
     logo = (unsigned char *)M.mem_base + EMULATOR_LOGO_OFFSET;
     for (i=0; i<16; i++)
     {
 	*logo++ = 0xFF;
     }
     /*
      * Setup the init parameters.
      * Per PCI specs, AH must contain the bus and AL
      * must contain the devfn, encoded as (dev<<3)|fn
      */
     // Execution starts here
     M.x86.R_CS = SEG(EMULATOR_STRAP_OFFSET);
     M.x86.R_IP = OFF(EMULATOR_STRAP_OFFSET);
     // Stack at top of ram
     M.x86.R_SS = SEG(EMULATOR_STACK_OFFSET);
     M.x86.R_SP = OFF(EMULATOR_STACK_OFFSET);
     // Input parameters
     M.x86.R_AH = PCI_BUS(gr_dev);
     M.x86.R_AL = (PCI_DEV(gr_dev)<<3) | PCI_FUNC(gr_dev);
     // Set the I/O and memory access functions
     X86EMU_setupMemFuncs(&_A1_mem);
     X86EMU_setupPioFuncs(&_A1_pio);
     // Enable timer 2
     cfg = in_byte(0x61); // Get Misc control
     cfg |= 0x01;         // Enable timer 2
     out_byte(0x61, cfg); // output again
     // Set up the timers
     out_byte(0x43, 0x54);
     out_byte(0x41, 0x18);
     out_byte(0x43, 0x36);
     out_byte(0x40, 0x00);
     out_byte(0x40, 0x00);
     out_byte(0x43, 0xb6);
     out_byte(0x42, 0x31);
     out_byte(0x42, 0x13);
     // Init the "BIOS".
     bios_init();
     // Video Card Reset
     out_byte(0x3D8, 0);
     out_byte(0x3B8, 1);
     (void)in_byte(0x3BA);
     (void)in_byte(0x3DA);
     out_byte(0x3C0, 0);
     out_byte(0x61, 0xFC);
 #ifdef DEBUG
     s = _getenv("x86_singlestep");
     if (s && strcmp(s, "on")==0)
     {
 	PRINTF("Enabling single stepping for debug\n");
 	X86EMU_trace_on();
     }
 #endif
     // Ready set go...
     PRINTF("Running emulator\n");
     X86EMU_exec();
     PRINTF("Done running emulator\n");
 /* FIXME: Remove me */
     pal_reset = getenv("x86_palette_reset");
     if (pal_reset && strcmp(pal_reset, "on") == 0)
     {
 	PRINTF("Palette reset\n");
 	//(void)in_byte(0x3da);
 	//out_byte(0x3c0, 0);
 	out_byte(0x3C8, 0);
 	out_byte(0x3C9, 0);
 	out_byte(0x3C9, 0);
 	out_byte(0x3C9, 0);
 	for (i=0; i<254; i++)
 	{
 	    out_byte(0x3C9, 63);
 	    out_byte(0x3C9, 63);
 	    out_byte(0x3C9, 63);
 	}
 	out_byte(0x3c0, 0x20);
     }
 /* FIXME: remove me */
 #ifdef EASTEREGG
     if (easteregg_active)
     {
 	extern void video_easteregg(void);
 	video_easteregg();
     }
 #endif
 /*
     current_attr = video_get_attr();
     fb = (u8 *)VIDEO_BASE;
     for (i=0; i<video_rows()*video_cols()*2; i+=2)
     {
 	*(fb+i) = ' ';
 	*(fb+i+1) = current_attr;
     }
     fb = (u8 *)VIDEO_BASE + (video_rows())-1*(video_cols()*2);
     for (i=0; i<video_cols(); i++)
     {
 	*(fb + 2*i)     = 32;
 	*(fb + 2*i + 1) = 0x17;
     }
     msg = done_msg;
     while (*msg)
     {
 	*fb = *msg;
 	fb  += 2;
 	msg ++;
     }
 */
 #ifdef DEBUG
     if (getenv("x86_do_inout")) do_inout();
 #endif
-    dcache_disable();
+//FIXME:    dcache_disable();
     return 1;
 }
 // Clean up the x86 mess
 void shutdown_bios(void)
 {
 //    disable_compatibility_hole();
     // Free the memory associated
     free(M.mem_base);
 }
 int to_int(char *buffer)
 {
     int base = 0;
     int res  = 0;
     if (*buffer == '$')
     {
 	base = 16;
 	buffer++;
     }
     else base = 10;
     for (;;)
     {
 	switch(*buffer)
 	{
 	case '0' ... '9':
 	    res *= base;
 	    res += *buffer - '0';
 	    break;
 	case 'A':
 	case 'a':
 	    res *= base;
 	    res += 10;
 	    break;
 	case 'B':
 	case 'b':
 	    res *= base;
 	    res += 11;
 	    break;
 	case 'C':
 	case 'c':
 	    res *= base;
 	    res += 12;
 	    break;
 	case 'D':
 	case 'd':
 	    res *= base;
 	    res += 13;
 	    break;
 	case 'E':
 	case 'e':
 	    res *= base;
 	    res += 14;
 	    break;
 	case 'F':
 	case 'f':
 	    res *= base;
 	    res += 15;
 	    break;
 	default:
 	    return res;
 	}
 	buffer++;
     }
     return res;
 }
 void one_arg(char *buffer, int *a)
 {
     while (*buffer && *buffer != '\n')
     {
 	if (*buffer == ' ') buffer++;
 	else break;
     }
     *a = to_int(buffer);
 }
 void two_args(char *buffer, int *a, int *b)
 {
     while (*buffer && *buffer != '\n')
     {
 	if (*buffer == ' ') buffer++;
 	else break;
     }
     *a = to_int(buffer);
     while (*buffer && *buffer != '\n')
     {
 	if (*buffer != ' ') buffer++;
 	else break;
     }
     while (*buffer && *buffer != '\n')
     {
 	if (*buffer == ' ') buffer++;
 	else break;
     }
     *b = to_int(buffer);
 }
 void do_inout(void)
 {
     char buffer[256];
     char *arg1, *arg2;
     int a,b;
     printf("In/Out Session\nUse 'i[bwl]' for in, 'o[bwl]' for out and 'q' to quit\n");
     do
     {
 	cons_gets(buffer);
 	printf("\n");
 	*arg1 = buffer;
 	while (*arg1 != ' ' ) arg1++;
 	while (*arg1 == ' ') arg1++;
 	if (buffer[0] == 'i')
 	{
 	    one_arg(buffer+2, &a);
 	    switch (buffer[1])
 	    {
 	    case 'b':
 		printf("in_byte(%xh) = %xh\n", a, A1_inb(a));
 		break;
 	    case 'w':
 		printf("in_word(%xh) = %xh\n", a, A1_inw(a));
 		break;
 	    case 'l':
 		printf("in_dword(%xh) = %xh\n", a, A1_inl(a));
 		break;
 	    default:
 		printf("Invalid length '%c'\n", buffer[1]);
 		break;
 	    }
 	}
 	else if (buffer[0] == 'o')
 	{
 	    two_args(buffer+2, &a, &b);
 	    switch (buffer[1])
 	    {
 	    case 'b':
 		printf("out_byte(%d, %d)\n", a, b);
 		A1_outb(a,b);
 		break;
 	    case 'w':
 		printf("out_word(%d, %d)\n", a, b);
 		A1_outw(a, b);
 		break;
 	    case 'l':
 		printf("out_long(%d, %d)\n", a, b);
 		A1_outl(a, b);
 		break;
 	    default:
 		printf("Invalid length '%c'\n", buffer[1]);
 		break;
 	    }
 	} else if (buffer[0] == 'q') return;
     } while (1);
 }

board/MAI/menu/cmd_menu.c

Diff comments View file @ 7c7a23b

1	#include <common.h>	1	#include <common.h>
2	#include <command.h>	2	#include <command.h>
3	#include <cmd_menu.h>	3	#include <cmd_menu.h>
4		4
5	int do_menu( cmd_tbl_t cmdtp, bd_t bd, int flag, int argc, char *argv[] )	5	int do_menu( cmd_tbl_t cmdtp, /bd_t bd,/ int flag, int argc, char *argv[] )
6	{	6	{
7	// printf("<NOT YET IMPLEMENTED>\n");	7	// printf("<NOT YET IMPLEMENTED>\n");
8	return 0;	8	return 0;
9	}	9	}
10		10

board/hermes/u-boot.lds

Diff comments View file @ 7c7a23b

 /*
  * (C) Copyright 2000
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 OUTPUT_ARCH(powerpc)
 SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
 /* Do we need any of these for elf?
    __DYNAMIC = 0;    */
 SECTIONS
 {
   /* Read-only sections, merged into text segment: */
   . = + SIZEOF_HEADERS;
   .interp : { *(.interp) }
   .hash          : { *(.hash)		}
   .dynsym        : { *(.dynsym)		}
   .dynstr        : { *(.dynstr)		}
   .rel.text      : { *(.rel.text)		}
   .rela.text     : { *(.rela.text) 	}
   .rel.data      : { *(.rel.data)		}
   .rela.data     : { *(.rela.data) 	}
   .rel.rodata    : { *(.rel.rodata) 	}
   .rela.rodata   : { *(.rela.rodata) 	}
   .rel.got       : { *(.rel.got)		}
   .rela.got      : { *(.rela.got)		}
   .rel.ctors     : { *(.rel.ctors)	}
   .rela.ctors    : { *(.rela.ctors)	}
   .rel.dtors     : { *(.rel.dtors)	}
   .rela.dtors    : { *(.rela.dtors)	}
   .rel.bss       : { *(.rel.bss)		}
   .rela.bss      : { *(.rela.bss)		}
   .rel.plt       : { *(.rel.plt)		}
   .rela.plt      : { *(.rela.plt)		}
   .init          : { *(.init)	}
   .plt : { *(.plt) }
   .text      :
   {
     /* WARNING - the following is hand-optimized to fit within	*/
     /* the sector layout of our flash chips!	XXX FIXME XXX	*/
-    cpu/mpc8xx/start.o	(.text)
+    cpu/mpc8xx/start.o		(.text)
-    common/dlmalloc.o	(.text)
+    common/dlmalloc.o		(.text)
-    lib_ppc/ppcstring.o	(.text)
+    cpu/mpc8xx/interrupts.o	(.text)
-    cpu/mpc8xx/interrupts.o (.text)
     lib_ppc/time.o		(.text)
+    lib_ppc/ticks.o		(.text)
+    lib_ppc/cache.o		(.text)
+    lib_generic/crc32.o		(.text)
     . = env_offset;
     common/environment.o(.text)
     *(.text)
     *(.fixup)
     *(.got1)
   }
   _etext = .;
   PROVIDE (etext = .);
   .rodata    :
   {
     *(.rodata)
     *(.rodata1)
   }
   .fini      : { *(.fini)    } =0
   .ctors     : { *(.ctors)   }
   .dtors     : { *(.dtors)   }
   /* Read-write section, merged into data segment: */
   . = (. + 0x00FF) & 0xFFFFFF00;
   _erotext = .;
   PROVIDE (erotext = .);
   .reloc   :
   {
     *(.got)
     _GOT2_TABLE_ = .;
     *(.got2)
     _FIXUP_TABLE_ = .;
     *(.fixup)
   }
   __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
   __fixup_entries = (. - _FIXUP_TABLE_)>>2;
   .data    :
   {
     *(.data)
     *(.data1)
     *(.sdata)
     *(.sdata2)
     *(.dynamic)
     CONSTRUCTORS
   }
   _edata  =  .;
   PROVIDE (edata = .);
   __start___ex_table = .;
   __ex_table : { *(__ex_table) }
   __stop___ex_table = .;
   . = ALIGN(256);
   __init_begin = .;
   .text.init : { *(.text.init) }
   .data.init : { *(.data.init) }
   . = ALIGN(256);
   __init_end = .;
   __bss_start = .;
   .bss       :
   {
    *(.sbss) *(.scommon)
    *(.dynbss)
    *(.bss)
    *(COMMON)
   }
   _end = . ;
   PROVIDE (end = .);
 }

board/tqm8260/tqm8260.c

Diff comments View file @ 7c7a23b

board/trab/vfd.c

Diff comments View file @ 7c7a23b

1	/*	1	/*
2	* (C) Copyright 2001	2	* (C) Copyright 2001
3	* Wolfgang Denk, DENX Software Engineering -- wd@denx.de	3	* Wolfgang Denk, DENX Software Engineering -- wd@denx.de
4	*	4	*
5	* See file CREDITS for list of people who contributed to this	5	* See file CREDITS for list of people who contributed to this
6	* project.	6	* project.
7	*	7	*
8	* This program is free software; you can redistribute it and/or	8	* This program is free software; you can redistribute it and/or
9	* modify it under the terms of the GNU General Public License as	9	* modify it under the terms of the GNU General Public License as
10	* published by the Free Software Foundation; either version 2 of	10	* published by the Free Software Foundation; either version 2 of
11	* the License, or (at your option) any later version.	11	* the License, or (at your option) any later version.
12	*	12	*
13	* This program is distributed in the hope that it will be useful,	13	* This program is distributed in the hope that it will be useful,
14	* but WITHOUT ANY WARRANTY; without even the implied warranty of	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16	* GNU General Public License for more details.	16	* GNU General Public License for more details.
17	*	17	*
18	* You should have received a copy of the GNU General Public License	18	* You should have received a copy of the GNU General Public License
19	* along with this program; if not, write to the Free Software	19	* along with this program; if not, write to the Free Software
20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21	* MA 02111-1307 USA	21	* MA 02111-1307 USA
22	*/	22	*/
23		23
24	/************************************************************************/	24	/************************************************************************/
25	/* ** DEBUG SETTINGS */	25	/* ** DEBUG SETTINGS */
26	/************************************************************************/	26	/************************************************************************/
27		27
28	/* #define DEBUG */	28	/* #define DEBUG */
29		29
30	/************************************************************************/	30	/************************************************************************/
31	/* ** HEADER FILES */	31	/* ** HEADER FILES */
32	/************************************************************************/	32	/************************************************************************/
33		33
34	#include <config.h>	34	#include <config.h>
35	#include <common.h>	35	#include <common.h>
36	#include <version.h>	36	#include <version.h>
37	#include <stdarg.h>	37	#include <stdarg.h>
38	#include <linux/types.h>	38	#include <linux/types.h>
39	#include <devices.h>	39	#include <devices.h>
40	#include <s3c2400.h>	40	#include <s3c2400.h>
41		41
42	#ifdef CONFIG_VFD	42	#ifdef CONFIG_VFD
43		43
44	/************************************************************************/	44	/************************************************************************/
45	/* ** CONFIG STUFF -- should be moved to board config file */	45	/* ** CONFIG STUFF -- should be moved to board config file */
46	/************************************************************************/	46	/************************************************************************/
47		47
48	/************************************************************************/	48	/************************************************************************/
49		49
50	#ifndef PAGE_SIZE	50	#ifndef PAGE_SIZE
51	#define PAGE_SIZE 4096	51	#define PAGE_SIZE 4096
52	#endif	52	#endif
53		53
54	#define ROT 0x09	54	#define ROT 0x09
55	#define BLAU 0x0C	55	#define BLAU 0x0C
56	#define VIOLETT 0X0D	56	#define VIOLETT 0X0D
57		57
58	ulong vfdbase;	58	ulong vfdbase;
59	ulong frame_buf_size;	59	ulong frame_buf_size;
60	#define frame_buf_offs 4	60	#define frame_buf_offs 4
61		61
62	/* taken from armboot/common/vfd.c */	62	/* taken from armboot/common/vfd.c */
63	ulong adr_vfd_table[112][18][2][4][2];	63	ulong adr_vfd_table[112][18][2][4][2];
64	unsigned char bit_vfd_table[112][18][2][4][2];	64	unsigned char bit_vfd_table[112][18][2][4][2];
65		65
66	/*	66	/*
67	* initialize the values for the VFD-grid-control in the framebuffer	67	* initialize the values for the VFD-grid-control in the framebuffer
68	*/	68	*/
69	void init_grid_ctrl(void)	69	void init_grid_ctrl(void)
70	{	70	{
71	ulong adr, grid_cycle;	71	ulong adr, grid_cycle;
72	unsigned int bit, display;	72	unsigned int bit, display;
73	unsigned char temp, bit_nr;	73	unsigned char temp, bit_nr;
74		74
75	for (adr=vfdbase; adr<=(vfdbase+7168); adr+=4) /clear frame buffer /	75	for (adr=vfdbase; adr<=(vfdbase+7168); adr+=4) /clear frame buffer /
76	((volatile ulong)(adr))=0;	76	((volatile ulong)(adr))=0;
77		77
78	for(display=0;display<=3;display++)	78	for(display=0;display<=3;display++)
79	{	79	{
80	for(grid_cycle=0;grid_cycle<=55;grid_cycle++)	80	for(grid_cycle=0;grid_cycle<=55;grid_cycle++)
81	{	81	{
82	bit = grid_cycle2564+(grid_cycle+200)*4+frame_buf_offs+display;	82	bit = grid_cycle2564+(grid_cycle+200)*4+frame_buf_offs+display;
83	/* wrap arround if offset (see manual S3C2400) */	83	/* wrap arround if offset (see manual S3C2400) */
84	if (bit>=frame_buf_size*8)	84	if (bit>=frame_buf_size*8)
85	bit = bit-(frame_buf_size*8);	85	bit = bit-(frame_buf_size*8);
86	adr = vfdbase+(bit/32)*4+(3-(bit%32)/8);	86	adr = vfdbase+(bit/32)*4+(3-(bit%32)/8);
87	bit_nr = bit%8;	87	bit_nr = bit%8;
88	bit_nr = (bit_nr>3)?bit_nr-4:bit_nr+4;	88	bit_nr = (bit_nr>3)?bit_nr-4:bit_nr+4;
89	temp=((volatile unsigned char)(adr));	89	temp=((volatile unsigned char)(adr));
90	temp\|=(1<<bit_nr);	90	temp\|=(1<<bit_nr);
91	((volatile unsigned char)(adr))=temp;	91	((volatile unsigned char)(adr))=temp;
92		92
93	if(grid_cycle<55)	93	if(grid_cycle<55)
94	bit = grid_cycle2564+(grid_cycle+201)*4+frame_buf_offs+display;	94	bit = grid_cycle2564+(grid_cycle+201)*4+frame_buf_offs+display;
95	else	95	else
96	bit = grid_cycle2564+2004+frame_buf_offs+display-4; / grid nr. 0 */	96	bit = grid_cycle2564+2004+frame_buf_offs+display-4; / grid nr. 0 */
97	/* wrap arround if offset (see manual S3C2400) */	97	/* wrap arround if offset (see manual S3C2400) */
98	if (bit>=frame_buf_size*8)	98	if (bit>=frame_buf_size*8)
99	bit = bit-(frame_buf_size*8);	99	bit = bit-(frame_buf_size*8);
100	adr = vfdbase+(bit/32)*4+(3-(bit%32)/8);	100	adr = vfdbase+(bit/32)*4+(3-(bit%32)/8);
101	bit_nr = bit%8;	101	bit_nr = bit%8;
102	bit_nr = (bit_nr>3)?bit_nr-4:bit_nr+4;	102	bit_nr = (bit_nr>3)?bit_nr-4:bit_nr+4;
103	temp=((volatile unsigned char)(adr));	103	temp=((volatile unsigned char)(adr));
104	temp\|=(1<<bit_nr);	104	temp\|=(1<<bit_nr);
105	((volatile unsigned char)(adr))=temp;	105	((volatile unsigned char)(adr))=temp;
106	}	106	}
107	}	107	}
108	}	108	}
109		109
110	/*	110	/*
111	*create translation table for getting easy the right position in the	111	*create translation table for getting easy the right position in the
112	*physical framebuffer for some x/y-coordinates of the VFDs	112	*physical framebuffer for some x/y-coordinates of the VFDs
113	*/	113	*/
114	void create_vfd_table(void)	114	void create_vfd_table(void)
115	{	115	{
116	unsigned int vfd_table[112][18][2][4][2];	116	unsigned int vfd_table[112][18][2][4][2];
117	ulong adr;	117	ulong adr;
118	unsigned int x, y, color, display, entry, pixel, bit_nr;	118	unsigned int x, y, color, display, entry, pixel, bit_nr;
119		119
120	/*	120	/*
121	* Create translation table for Noritake-T119C-VFD-specific	121	* Create translation table for Noritake-T119C-VFD-specific
122	* organized frame-buffer.	122	* organized frame-buffer.
123	* Created is the number of the bit in the framebuffer (the	123	* Created is the number of the bit in the framebuffer (the
124	* first transferred pixel of each frame is bit 0).	124	* first transferred pixel of each frame is bit 0).
125	*/	125	*/
126	for(y=0;y<=17;y++) /* Zeile */	126	for(y=0;y<=17;y++) /* Zeile */
127	{	127	{
128	for(x=0;x<=111;x++) /* Spalten */	128	for(x=0;x<=111;x++) /* Spalten */
129	{	129	{
130	/Display 0 blaue Pixel Eintrag 1 /	130	/Display 0 blaue Pixel Eintrag 1 /
131	vfd_table[x][y][0][0][0]=((x%4)4+y16+(x/4)*2048);	131	vfd_table[x][y][0][0][0]=((x%4)4+y16+(x/4)*2048);
132	/Display 0 rote Pixel Eintrag 1 /	132	/Display 0 rote Pixel Eintrag 1 /
133	vfd_table[x][y][1][0][0]=((x%4)4+y16+(x/4)*2048+512);	133	vfd_table[x][y][1][0][0]=((x%4)4+y16+(x/4)*2048+512);
134	if(x<=1)	134	if(x<=1)
135	{	135	{
136	/Display 0 blaue Pixel Eintrag 2 /	136	/Display 0 blaue Pixel Eintrag 2 /
137	vfd_table[x][y][0][0][1]=(((x+112)%4)4+y16+((x+110)/4)*2048+1024);	137	vfd_table[x][y][0][0][1]=(((x+112)%4)4+y16+((x+110)/4)*2048+1024);
138	/Display 0 rote Pixel Eintrag 2 /	138	/Display 0 rote Pixel Eintrag 2 /
139	vfd_table[x][y][1][0][1]=(((x+112)%4)4+y16+((x+110)/4)*2048+512+1024);	139	vfd_table[x][y][1][0][1]=(((x+112)%4)4+y16+((x+110)/4)*2048+512+1024);
140	}	140	}
141	else	141	else
142	{	142	{
143	/Display 0 blaue Pixel Eintrag 2 /	143	/Display 0 blaue Pixel Eintrag 2 /
144	vfd_table[x][y][0][0][1]=((x%4)4+y16+((x-2)/4)*2048+1024);	144	vfd_table[x][y][0][0][1]=((x%4)4+y16+((x-2)/4)*2048+1024);
145	/Display 0 rote Pixel Eintrag 2 /	145	/Display 0 rote Pixel Eintrag 2 /
146	vfd_table[x][y][1][0][1]=((x%4)4+y16+((x-2)/4)*2048+512+1024);	146	vfd_table[x][y][1][0][1]=((x%4)4+y16+((x-2)/4)*2048+512+1024);
147	}	147	}
148	/Display 1 blaue Pixel Eintrag 1 /	148	/Display 1 blaue Pixel Eintrag 1 /
149	vfd_table[x][y][0][1][0]=((x%4)4+y16+(x/4)*2048+1);	149	vfd_table[x][y][0][1][0]=((x%4)4+y16+(x/4)*2048+1);
150	/Display 1 rote Pixel Eintrag 1 /	150	/Display 1 rote Pixel Eintrag 1 /
151	vfd_table[x][y][1][1][0]=((x%4)4+y16+(x/4)*2048+512+1);	151	vfd_table[x][y][1][1][0]=((x%4)4+y16+(x/4)*2048+512+1);
152	if(x<=1)	152	if(x<=1)
153	{	153	{
154	/Display 1 blaue Pixel Eintrag 2 /	154	/Display 1 blaue Pixel Eintrag 2 /
155	vfd_table[x][y][0][1][1]=(((x+112)%4)4+y16+((x+110)/4)*2048+1+1024);	155	vfd_table[x][y][0][1][1]=(((x+112)%4)4+y16+((x+110)/4)*2048+1+1024);
156	/Display 1 rote Pixel Eintrag 2 /	156	/Display 1 rote Pixel Eintrag 2 /
157	vfd_table[x][y][1][1][1]=(((x+112)%4)4+y16+((x+110)/4)*2048+512+1+1024);	157	vfd_table[x][y][1][1][1]=(((x+112)%4)4+y16+((x+110)/4)*2048+512+1+1024);
158	}	158	}
159	else	159	else
160	{	160	{
161	/Display 1 blaue Pixel Eintrag 2 /	161	/Display 1 blaue Pixel Eintrag 2 /
162	vfd_table[x][y][0][1][1]=((x%4)4+y16+((x-2)/4)*2048+1+1024);	162	vfd_table[x][y][0][1][1]=((x%4)4+y16+((x-2)/4)*2048+1+1024);
163	/Display 1 rote Pixel Eintrag 2 /	163	/Display 1 rote Pixel Eintrag 2 /
164	vfd_table[x][y][1][1][1]=((x%4)4+y16+((x-2)/4)*2048+512+1+1024);	164	vfd_table[x][y][1][1][1]=((x%4)4+y16+((x-2)/4)*2048+512+1+1024);
165	}	165	}
166	/Display 2 blaue Pixel Eintrag 1 /	166	/Display 2 blaue Pixel Eintrag 1 /
167	vfd_table[x][y][0][2][0]=((x%4)4+y16+(x/4)*2048+2);	167	vfd_table[x][y][0][2][0]=((x%4)4+y16+(x/4)*2048+2);
168	/Display 2 rote Pixel Eintrag 1 /	168	/Display 2 rote Pixel Eintrag 1 /
169	vfd_table[x][y][1][2][0]=((x%4)4+y16+(x/4)*2048+512+2);	169	vfd_table[x][y][1][2][0]=((x%4)4+y16+(x/4)*2048+512+2);
170	if(x<=1)	170	if(x<=1)
171	{	171	{
172	/Display 2 blaue Pixel Eintrag 2 /	172	/Display 2 blaue Pixel Eintrag 2 /
173	vfd_table[x][y][0][2][1]=(((x+112)%4)4+y16+((x+110)/4)*2048+2+1024);	173	vfd_table[x][y][0][2][1]=(((x+112)%4)4+y16+((x+110)/4)*2048+2+1024);
174	/Display 2 rote Pixel Eintrag 2 /	174	/Display 2 rote Pixel Eintrag 2 /
175	vfd_table[x][y][1][2][1]=(((x+112)%4)4+y16+((x+110)/4)*2048+512+2+1024);	175	vfd_table[x][y][1][2][1]=(((x+112)%4)4+y16+((x+110)/4)*2048+512+2+1024);
176	}	176	}
177	else	177	else
178	{	178	{
179	/Display 2 blaue Pixel Eintrag 2 /	179	/Display 2 blaue Pixel Eintrag 2 /
180	vfd_table[x][y][0][2][1]=((x%4)4+y16+((x-2)/4)*2048+2+1024);	180	vfd_table[x][y][0][2][1]=((x%4)4+y16+((x-2)/4)*2048+2+1024);
181	/Display 2 rote Pixel Eintrag 2 /	181	/Display 2 rote Pixel Eintrag 2 /
182	vfd_table[x][y][1][2][1]=((x%4)4+y16+((x-2)/4)*2048+512+2+1024);	182	vfd_table[x][y][1][2][1]=((x%4)4+y16+((x-2)/4)*2048+512+2+1024);
183	}	183	}
184	/Display 3 blaue Pixel Eintrag 1 /	184	/Display 3 blaue Pixel Eintrag 1 /
185	vfd_table[x][y][0][3][0]=((x%4)4+y16+(x/4)*2048+3);	185	vfd_table[x][y][0][3][0]=((x%4)4+y16+(x/4)*2048+3);
186	/Display 3 rote Pixel Eintrag 1 /	186	/Display 3 rote Pixel Eintrag 1 /
187	vfd_table[x][y][1][3][0]=((x%4)4+y16+(x/4)*2048+512+3);	187	vfd_table[x][y][1][3][0]=((x%4)4+y16+(x/4)*2048+512+3);
188	if(x<=1)	188	if(x<=1)
189	{	189	{
190	/Display 3 blaue Pixel Eintrag 2 /	190	/Display 3 blaue Pixel Eintrag 2 /
191	vfd_table[x][y][0][3][1]=(((x+112)%4)4+y16+((x+110)/4)*2048+3+1024);	191	vfd_table[x][y][0][3][1]=(((x+112)%4)4+y16+((x+110)/4)*2048+3+1024);
192	/Display 3 rote Pixel Eintrag 2 /	192	/Display 3 rote Pixel Eintrag 2 /
193	vfd_table[x][y][1][3][1]=(((x+112)%4)4+y16+((x+110)/4)*2048+512+3+1024);	193	vfd_table[x][y][1][3][1]=(((x+112)%4)4+y16+((x+110)/4)*2048+512+3+1024);
194	}	194	}
195	else	195	else
196	{	196	{
197	/Display 3 blaue Pixel Eintrag 2 /	197	/Display 3 blaue Pixel Eintrag 2 /
198	vfd_table[x][y][0][3][1]=((x%4)4+y16+((x-2)/4)*2048+3+1024);	198	vfd_table[x][y][0][3][1]=((x%4)4+y16+((x-2)/4)*2048+3+1024);
199	/Display 3 rote Pixel Eintrag 2 /	199	/Display 3 rote Pixel Eintrag 2 /
200	vfd_table[x][y][1][3][1]=((x%4)4+y16+((x-2)/4)*2048+512+3+1024);	200	vfd_table[x][y][1][3][1]=((x%4)4+y16+((x-2)/4)*2048+512+3+1024);
201	}	201	}
202	}	202	}
203	}	203	}
204		204
205	/*	205	/*
206	* Create translation table for Noritake-T119C-VFD-specific	206	* Create translation table for Noritake-T119C-VFD-specific
207	* organized frame-buffer	207	* organized frame-buffer
208	* Create table with entries for physical byte adresses and	208	* Create table with entries for physical byte adresses and
209	* bit-number within the byte	209	* bit-number within the byte
210	* from table with bit-numbers within the total framebuffer	210	* from table with bit-numbers within the total framebuffer
211	*/	211	*/
212	for(y=0;y<=17;y++)	212	for(y=0;y<=17;y++)
213	{	213	{
214	for(x=0;x<=111;x++)	214	for(x=0;x<=111;x++)
215	{	215	{
216	for(color=0;color<=1;color++)	216	for(color=0;color<=1;color++)
217	{	217	{
218	for(display=0;display<=3;display++)	218	for(display=0;display<=3;display++)
219	{	219	{
220	for(entry=0;entry<=1;entry++)	220	for(entry=0;entry<=1;entry++)
221	{	221	{
222	pixel = vfd_table[x][y][color][display][entry] + frame_buf_offs;	222	pixel = vfd_table[x][y][color][display][entry] + frame_buf_offs;
223	/*	223	/*
224	* wrap arround if offset	224	* wrap arround if offset
225	* (see manual S3C2400)	225	* (see manual S3C2400)
226	*/	226	*/
227	if (pixel>=frame_buf_size*8)	227	if (pixel>=frame_buf_size*8)
228	pixel = pixel-(frame_buf_size*8);	228	pixel = pixel-(frame_buf_size*8);
229	adr = vfdbase+(pixel/32)*4+(3-(pixel%32)/8);	229	adr = vfdbase+(pixel/32)*4+(3-(pixel%32)/8);
230	bit_nr = pixel%8;	230	bit_nr = pixel%8;
231	bit_nr = (bit_nr>3)?bit_nr-4:bit_nr+4;	231	bit_nr = (bit_nr>3)?bit_nr-4:bit_nr+4;
232	adr_vfd_table[x][y][color][display][entry] = adr;	232	adr_vfd_table[x][y][color][display][entry] = adr;
233	bit_vfd_table[x][y][color][display][entry] = bit_nr;	233	bit_vfd_table[x][y][color][display][entry] = bit_nr;
234	}	234	}
235	}	235	}
236	}	236	}
237	}	237	}
238	}	238	}
239	}	239	}
240		240
241	/*	241	/*
242	* Set/clear pixel of the VFDs	242	* Set/clear pixel of the VFDs
243	*/	243	*/
244	void set_vfd_pixel(unsigned char x, unsigned char y, unsigned char color, unsigned char display, unsigned char value)	244	void set_vfd_pixel(unsigned char x, unsigned char y, unsigned char color, unsigned char display, unsigned char value)
245	{	245	{
246	ulong adr;	246	ulong adr;
247	unsigned char bit_nr, temp;	247	unsigned char bit_nr, temp;
248		248
249	if (value!=0)	249	if (value!=0)
250	{	250	{
251	/* Pixel-Eintrag Nr. 1 */	251	/* Pixel-Eintrag Nr. 1 */
252	adr = adr_vfd_table[x][y][color][display][0];	252	adr = adr_vfd_table[x][y][color][display][0];
253	/* Pixel-Eintrag Nr. 1 */	253	/* Pixel-Eintrag Nr. 1 */
254	bit_nr = bit_vfd_table[x][y][color][display][0];	254	bit_nr = bit_vfd_table[x][y][color][display][0];
255	temp=((volatile unsigned char)(adr));	255	temp=((volatile unsigned char)(adr));
256	temp\|=1<<bit_nr;	256	temp\|=1<<bit_nr;
257	((volatile unsigned char)(adr))=temp;	257	((volatile unsigned char)(adr))=temp;
258		258
259	/* Pixel-Eintrag Nr. 2 */	259	/* Pixel-Eintrag Nr. 2 */
260	adr = adr_vfd_table[x][y][color][display][1];	260	adr = adr_vfd_table[x][y][color][display][1];
261	/* Pixel-Eintrag Nr. 2 */	261	/* Pixel-Eintrag Nr. 2 */
262	bit_nr = bit_vfd_table[x][y][color][display][1];	262	bit_nr = bit_vfd_table[x][y][color][display][1];
263	temp=((volatile unsigned char)(adr));	263	temp=((volatile unsigned char)(adr));
264	temp\|=1<<bit_nr;	264	temp\|=1<<bit_nr;
265	((volatile unsigned char)(adr))=temp;	265	((volatile unsigned char)(adr))=temp;
266	}	266	}
267	else	267	else
268	{	268	{
269	/* Pixel-Eintrag Nr. 1 */	269	/* Pixel-Eintrag Nr. 1 */
270	adr = adr_vfd_table[x][y][color][display][0];	270	adr = adr_vfd_table[x][y][color][display][0];
271	/* Pixel-Eintrag Nr. 1 */	271	/* Pixel-Eintrag Nr. 1 */
272	bit_nr = bit_vfd_table[x][y][color][display][0];	272	bit_nr = bit_vfd_table[x][y][color][display][0];
273	temp=((volatile unsigned char)(adr));	273	temp=((volatile unsigned char)(adr));
274	temp&=~(1<<bit_nr);	274	temp&=~(1<<bit_nr);
275	((volatile unsigned char)(adr))=temp;	275	((volatile unsigned char)(adr))=temp;
276		276
277	/* Pixel-Eintrag Nr. 2 */	277	/* Pixel-Eintrag Nr. 2 */
278	adr = adr_vfd_table[x][y][color][display][1];	278	adr = adr_vfd_table[x][y][color][display][1];
279	/* Pixel-Eintrag Nr. 2 */	279	/* Pixel-Eintrag Nr. 2 */
280	bit_nr = bit_vfd_table[x][y][color][display][1];	280	bit_nr = bit_vfd_table[x][y][color][display][1];
281	temp=((volatile unsigned char)(adr));	281	temp=((volatile unsigned char)(adr));
282	temp&=~(1<<bit_nr);	282	temp&=~(1<<bit_nr);
283	((volatile unsigned char)(adr))=temp;	283	((volatile unsigned char)(adr))=temp;
284	}	284	}
285	}	285	}
286		286
287	/*	287	/*
288	* transfer image from BMP-File	288	* transfer image from BMP-File
289	*/	289	*/
290	void transfer_pic(int display, unsigned char *adr, int height, int width)	290	void transfer_pic(int display, unsigned char *adr, int height, int width)
291	{	291	{
292	int x, y;	292	int x, y;
293	unsigned char temp;	293	unsigned char temp;
294		294
295	for (; height > 0; height -= 18)	295	for (; height > 0; height -= 18)
296	{	296	{
297	if (height > 18)	297	if (height > 18)
298	y = 18;	298	y = 18;
299	else	299	else
300	y = height;	300	y = height;
301	for (; y > 0; y--)	301	for (; y > 0; y--)
302	{	302	{
303	for (x = 0; x < width; x += 2)	303	for (x = 0; x < width; x += 2)
304	{	304	{
305	temp = *adr++;	305	temp = *adr++;
306	set_vfd_pixel(x, y-1, 0, display, 0);	306	set_vfd_pixel(x, y-1, 0, display, 0);
307	set_vfd_pixel(x, y-1, 1, display, 0);	307	set_vfd_pixel(x, y-1, 1, display, 0);
308	if ((temp >> 4) == BLAU)	308	if ((temp >> 4) == BLAU)
309	set_vfd_pixel(x, y-1, 0, display, 1);	309	set_vfd_pixel(x, y-1, 0, display, 1);
310	else if ((temp >> 4) == ROT)	310	else if ((temp >> 4) == ROT)
311	set_vfd_pixel(x, y-1, 1, display, 1);	311	set_vfd_pixel(x, y-1, 1, display, 1);
312	else if ((temp >> 4) == VIOLETT)	312	else if ((temp >> 4) == VIOLETT)
313	{	313	{
314	set_vfd_pixel(x, y-1, 0, display, 1);	314	set_vfd_pixel(x, y-1, 0, display, 1);
315	set_vfd_pixel(x, y-1, 1, display, 1);	315	set_vfd_pixel(x, y-1, 1, display, 1);
316	}	316	}
317	set_vfd_pixel(x+1, y-1, 0, display, 0);	317	set_vfd_pixel(x+1, y-1, 0, display, 0);
318	set_vfd_pixel(x+1, y-1, 1, display, 0);	318	set_vfd_pixel(x+1, y-1, 1, display, 0);
319	if ((temp & 0x0F) == BLAU)	319	if ((temp & 0x0F) == BLAU)
320	set_vfd_pixel(x+1, y-1, 0, display, 1);	320	set_vfd_pixel(x+1, y-1, 0, display, 1);
321	else if ((temp & 0x0F) == ROT)	321	else if ((temp & 0x0F) == ROT)
322	set_vfd_pixel(x+1, y-1, 1, display, 1);	322	set_vfd_pixel(x+1, y-1, 1, display, 1);
323	else if ((temp & 0x0F) == VIOLETT)	323	else if ((temp & 0x0F) == VIOLETT)
324	{	324	{
325	set_vfd_pixel(x+1, y-1, 0, display, 1);	325	set_vfd_pixel(x+1, y-1, 0, display, 1);
326	set_vfd_pixel(x+1, y-1, 1, display, 1);	326	set_vfd_pixel(x+1, y-1, 1, display, 1);
327	}	327	}
328	}	328	}
329	}	329	}
330	display++;	330	display++;
331	if (display > 3)	331	if (display > 3)
332	display = 0;	332	display = 0;
333	}	333	}
334	}	334	}
335		335
336	/*	336	/*
337	* initialize LCD-Controller of the S3C2400 for using VFDs	337	* initialize LCD-Controller of the S3C2400 for using VFDs
338	*/	338	*/
339	int drv_vfd_init(void)	339	int drv_vfd_init(void)
340	{	340	{
341	ulong palette;	341	ulong palette;
342	static int vfd_init_done = 0;	342	static int vfd_init_done = 0;
343		343
344	DECLARE_GLOBAL_DATA_PTR;	344	DECLARE_GLOBAL_DATA_PTR;
345		345
346	if (vfd_init_done != 0)	346	if (vfd_init_done != 0)
347	return;	347	return (0);
348	vfd_init_done = 1;	348	vfd_init_done = 1;
349		349
350	vfdbase = gd->fb_base;	350	vfdbase = gd->fb_base;
351	create_vfd_table();	351	create_vfd_table();
352	init_grid_ctrl();	352	init_grid_ctrl();
353		353
354	/*	354	/*
355	* Hinweis: Der Framebuffer ist um genau ein Nibble verschoben	355	* Hinweis: Der Framebuffer ist um genau ein Nibble verschoben
356	* Das erste angezeigte Pixel wird aus dem zweiten Nibble geholt	356	* Das erste angezeigte Pixel wird aus dem zweiten Nibble geholt
357	* das letzte angezeigte Pixel wird aus dem ersten Nibble geholt	357	* das letzte angezeigte Pixel wird aus dem ersten Nibble geholt
358	* (wrap around)	358	* (wrap around)
359	* see manual S3C2400	359	* see manual S3C2400
360	*/	360	*/
361	/* frame buffer startadr */	361	/* frame buffer startadr */
362	rLCDSADDR1 = vfdbase >> 1;	362	rLCDSADDR1 = vfdbase >> 1;
363	/* frame buffer endadr */	363	/* frame buffer endadr */
364	rLCDSADDR2 = (vfdbase + frame_buf_size) >> 1;	364	rLCDSADDR2 = (vfdbase + frame_buf_size) >> 1;
365	rLCDSADDR3 = ((256/4));	365	rLCDSADDR3 = ((256/4));
366		366
367	/* Port-Pins als LCD-Ausgang */	367	/* Port-Pins als LCD-Ausgang */
368	rPCCON = (rPCCON & 0xFFFFFF00)\| 0x000000AA;	368	rPCCON = (rPCCON & 0xFFFFFF00)\| 0x000000AA;
369	/* Port-Pins als LCD-Ausgang */	369	/* Port-Pins als LCD-Ausgang */
370	rPDCON = (rPDCON & 0xFFFFFF03)\| 0x000000A8;	370	rPDCON = (rPDCON & 0xFFFFFF03)\| 0x000000A8;
371	#ifdef WITH_VFRAME	371	#ifdef WITH_VFRAME
372	/* mit VFRAME zum Messen */	372	/* mit VFRAME zum Messen */
373	rPDCON = (rPDCON & 0xFFFFFF00)\| 0x000000AA;	373	rPDCON = (rPDCON & 0xFFFFFF00)\| 0x000000AA;
374	#endif	374	#endif
375		375
376	rLCDCON2 = 0x000DC000;	376	rLCDCON2 = 0x000DC000;
377	rLCDCON3 = 0x0051000A;	377	rLCDCON3 = 0x0051000A;
378	rLCDCON4 = 0x00000001;	378	rLCDCON4 = 0x00000001;
379	rLCDCON5 = 0x00000440;	379	rLCDCON5 = 0x00000440;
380	rLCDCON1 = 0x00000B75;	380	rLCDCON1 = 0x00000B75;
381		381
382	debug ("LCDSADDR1: %lX\n", rLCDSADDR1);	382	debug ("LCDSADDR1: %lX\n", rLCDSADDR1);
383	debug ("LCDSADDR2: %lX\n", rLCDSADDR2);	383	debug ("LCDSADDR2: %lX\n", rLCDSADDR2);
384	debug ("LCDSADDR3: %lX\n", rLCDSADDR3);	384	debug ("LCDSADDR3: %lX\n", rLCDSADDR3);
385		385
386	for(palette=0;palette<=15;palette++)	386	for(palette=0;palette<=15;palette++)
387	((volatile unsigned int)(PALETTE+(palette*4)))=palette;	387	((volatile unsigned int)(PALETTE+(palette*4)))=palette;
388	for(palette=16;palette<=255;palette++)	388	for(palette=16;palette<=255;palette++)
389	((volatile unsigned int)(PALETTE+(palette*4)))=0x00;	389	((volatile unsigned int)(PALETTE+(palette*4)))=0x00;
390		390
391	return 0;	391	return 0;
392	}	392	}
393		393
394	/************************************************************************/	394	/************************************************************************/
395	/* ** ROM capable initialization part - needed to reserve FB memory */	395	/* ** ROM capable initialization part - needed to reserve FB memory */
396	/************************************************************************/	396	/************************************************************************/
397		397
398	/*	398	/*
399	* This is called early in the system initialization to grab memory	399	* This is called early in the system initialization to grab memory
400	* for the VFD controller.	400	* for the VFD controller.
401	*	401	*
402	* Note that this is running from ROM, so no write access to global data.	402	* Note that this is running from ROM, so no write access to global data.
403	*/	403	*/
404	ulong vfd_setmem (ulong addr)	404	ulong vfd_setmem (ulong addr)
405	{	405	{
406	ulong size;	406	ulong size;
407		407
408	/* MAGIC */	408	/* MAGIC */
409	frame_buf_size = (256456)/8;	409	frame_buf_size = (256456)/8;
410		410
411	/* Round up to nearest full page */	411	/* Round up to nearest full page */
412	size = (frame_buf_size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);	412	size = (frame_buf_size + (PAGE_SIZE - 1)) & ~(PAGE_SIZE - 1);
413		413
414	debug ("Reserving %ldk for VFD Framebuffer at: %08lx\n", size>>10, addr);	414	debug ("Reserving %ldk for VFD Framebuffer at: %08lx\n", size>>10, addr);
415		415
416	return (size);	416	return (size);
417	}	417	}
418		418
419	#endif /* CONFIG_VFD */	419	#endif /* CONFIG_VFD */
420		420

common/cmd_pci.c

Diff comments View file @ 7c7a23b

1	/*	1	/*
2	* (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>	2	* (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
3	* Andreas Heppel <aheppel@sysgo.de>	3	* Andreas Heppel <aheppel@sysgo.de>
4	*	4	*
5	* (C) Copyright 2002	5	* (C) Copyright 2002
6	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.	6	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7	* Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.	7	* Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
8	*	8	*
9	* See file CREDITS for list of people who contributed to this	9	* See file CREDITS for list of people who contributed to this
10	* project.	10	* project.
11	*	11	*
12	* This program is free software; you can redistribute it and/or	12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License as	13	* modify it under the terms of the GNU General Public License as
14	* published by the Free Software Foundation; either version 2 of	14	* published by the Free Software Foundation; either version 2 of
15	* the License, or (at your option) any later version.	15	* the License, or (at your option) any later version.
16	*	16	*
17	* This program is distributed in the hope that it will be useful,	17	* This program is distributed in the hope that it will be useful,
18	* but WITHOUT ANY WARRANTY; without even the implied warranty of	18	* but WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the	19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20	* GNU General Public License for more details.	20	* GNU General Public License for more details.
21	*	21	*
22	* You should have received a copy of the GNU General Public License	22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, write to the Free Software	23	* along with this program; if not, write to the Free Software
24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,	24	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25	* MA 02111-1307 USA	25	* MA 02111-1307 USA
26	*/	26	*/
27		27
28	/*	28	/*
29	* PCI routines	29	* PCI routines
30	*/	30	*/
31		31
32	#include <common.h>	32	#include <common.h>
33		33
34	#ifdef CONFIG_PCI	34	#ifdef CONFIG_PCI
35		35
36	#include <command.h>	36	#include <command.h>
37	#include <cmd_boot.h>	37	#include <cmd_boot.h>
38	#include <asm/processor.h>	38	#include <asm/processor.h>
39	#include <asm/io.h>	39	#include <asm/io.h>
40	#include <cmd_pci.h>	40	#include <cmd_pci.h>
41	#include <pci.h>	41	#include <pci.h>
42		42
43	#if (CONFIG_COMMANDS & CFG_CMD_PCI)	43	#if (CONFIG_COMMANDS & CFG_CMD_PCI)
44		44
45	extern int cmd_get_data_size(char* arg, int default_size);	45	extern int cmd_get_data_size(char* arg, int default_size);
46		46
47	unsigned char ShortPCIListing = 1;	47	unsigned char ShortPCIListing = 1;
48		48
49	/*	49	/*
50	* Follows routines for the output of infos about devices on PCI bus.	50	* Follows routines for the output of infos about devices on PCI bus.
51	*/	51	*/
52		52
53	void pci_header_show(pci_dev_t dev);	53	void pci_header_show(pci_dev_t dev);
54	void pci_header_show_brief(pci_dev_t dev);	54	void pci_header_show_brief(pci_dev_t dev);
55		55
56	/*	56	/*
57	* Subroutine: pciinfo	57	* Subroutine: pciinfo
58	*	58	*
59	* Description: Show information about devices on PCI bus.	59	* Description: Show information about devices on PCI bus.
60	* Depending on the define CFG_SHORT_PCI_LISTING	60	* Depending on the define CFG_SHORT_PCI_LISTING
61	* the output will be more or less exhaustive.	61	* the output will be more or less exhaustive.
62	*	62	*
63	* Inputs: bus_no the number of the bus to be scanned.	63	* Inputs: bus_no the number of the bus to be scanned.
64	*	64	*
65	* Return: None	65	* Return: None
66	*	66	*
67	*/	67	*/
68	void pciinfo(int BusNum, int ShortPCIListing)	68	void pciinfo(int BusNum, int ShortPCIListing)
69	{	69	{
70	int Device;	70	int Device;
71	int Function;	71	int Function;
72	unsigned char HeaderType;	72	unsigned char HeaderType;
73	unsigned short VendorID;	73	unsigned short VendorID;
74	pci_dev_t dev;	74	pci_dev_t dev;
75		75
76	printf("Scanning PCI devices on bus %d\n", BusNum);	76	printf("Scanning PCI devices on bus %d\n", BusNum);
77		77
78	if (ShortPCIListing) {	78	if (ShortPCIListing) {
79	printf("BusDevFun VendorId DeviceId Device Class Sub-Class\n");	79	printf("BusDevFun VendorId DeviceId Device Class Sub-Class\n");
80	printf("_____________________________________________________________\n");	80	printf("_____________________________________________________________\n");
81	}	81	}
82		82
83	for (Device = 0; Device < PCI_MAX_PCI_DEVICES; Device++) {	83	for (Device = 0; Device < PCI_MAX_PCI_DEVICES; Device++) {
84	HeaderType = 0;	84	HeaderType = 0;
85	VendorID = 0;	85	VendorID = 0;
86	for (Function = 0; Function < PCI_MAX_PCI_FUNCTIONS; Function++) {	86	for (Function = 0; Function < PCI_MAX_PCI_FUNCTIONS; Function++) {
87	/*	87	/*
88	* If this is not a multi-function device, we skip the rest.	88	* If this is not a multi-function device, we skip the rest.
89	*/	89	*/
90	if (Function && !(HeaderType & 0x80))	90	if (Function && !(HeaderType & 0x80))
91	break;	91	break;
92		92
93	dev = PCI_BDF(BusNum, Device, Function);	93	dev = PCI_BDF(BusNum, Device, Function);
94		94
95	pci_read_config_word(dev, PCI_VENDOR_ID, &VendorID);	95	pci_read_config_word(dev, PCI_VENDOR_ID, &VendorID);
96	if ((VendorID == 0xFFFF) \|\| (VendorID == 0x0000))	96	if ((VendorID == 0xFFFF) \|\| (VendorID == 0x0000))
97	continue;	97	continue;
98		98
99	if (!Function) pci_read_config_byte(dev, PCI_HEADER_TYPE, &HeaderType);	99	if (!Function) pci_read_config_byte(dev, PCI_HEADER_TYPE, &HeaderType);
100		100
101	if (ShortPCIListing)	101	if (ShortPCIListing)
102	{	102	{
103	printf("%02x.%02x.%02x ", BusNum, Device, Function);	103	printf("%02x.%02x.%02x ", BusNum, Device, Function);
104	pci_header_show_brief(dev);	104	pci_header_show_brief(dev);
105	}	105	}
106	else	106	else
107	{	107	{
108	printf("\nFound PCI device %02x.%02x.%02x:\n",	108	printf("\nFound PCI device %02x.%02x.%02x:\n",
109	BusNum, Device, Function);	109	BusNum, Device, Function);
110	pci_header_show(dev);	110	pci_header_show(dev);
111	}	111	}
112	}	112	}
113	}	113	}
114	}	114	}
115		115
116	char* pci_classes_str(u8 class)	116	char* pci_classes_str(u8 class)
117	{	117	{
118	static char *pci_classes[] = {	118	static char *pci_classes[] = {
119	"Build before PCI Rev2.0",	119	"Build before PCI Rev2.0",
120	"Mass storage controller",	120	"Mass storage controller",
121	"Network controller ",	121	"Network controller ",
122	"Display controller ",	122	"Display controller ",
123	"Multimedia device ",	123	"Multimedia device ",
124	"Memory controller ",	124	"Memory controller ",
125	"Bridge device ",	125	"Bridge device ",
126	"Simple comm. controller",	126	"Simple comm. controller",
127	"Base system peripheral ",	127	"Base system peripheral ",
128	"Input device ",	128	"Input device ",
129	"Docking station ",	129	"Docking station ",
130	"Processor ",	130	"Processor ",
131	"Serial bus controller ",	131	"Serial bus controller ",
132	"Reserved entry ",	132	"Reserved entry ",
133	"Does not fit any class "	133	"Does not fit any class "
134	};	134	};
135		135
136	if (class < (sizeof pci_classes / sizeof *pci_classes))	136	if (class < (sizeof pci_classes / sizeof *pci_classes))
137	return pci_classes[(int) class];	137	return pci_classes[(int) class];
138		138
139	return "??? ";	139	return "??? ";
140	}	140	}
141		141
142	/*	142	/*
143	* Subroutine: pci_header_show_brief	143	* Subroutine: pci_header_show_brief
144	*	144	*
145	* Description: Reads and prints the header of the	145	* Description: Reads and prints the header of the
146	* specified PCI device in short form.	146	* specified PCI device in short form.
147	*	147	*
148	* Inputs: dev Bus+Device+Function number	148	* Inputs: dev Bus+Device+Function number
149	*	149	*
150	* Return: None	150	* Return: None
151	*	151	*
152	*/	152	*/
153	void pci_header_show_brief(pci_dev_t dev)	153	void pci_header_show_brief(pci_dev_t dev)
154	{	154	{
155	u16 vendor, device;	155	u16 vendor, device;
156	u8 class, subclass;	156	u8 class, subclass;
157		157
158	pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);	158	pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);
159	pci_read_config_word(dev, PCI_DEVICE_ID, &device);	159	pci_read_config_word(dev, PCI_DEVICE_ID, &device);
160	pci_read_config_byte(dev, PCI_CLASS_CODE, &class);	160	pci_read_config_byte(dev, PCI_CLASS_CODE, &class);
161	pci_read_config_byte(dev, PCI_CLASS_SUB_CODE, &subclass);	161	pci_read_config_byte(dev, PCI_CLASS_SUB_CODE, &subclass);
162		162
163	printf("0x%.4x 0x%.4x %s 0x%.2x\n",	163	printf("0x%.4x 0x%.4x %s 0x%.2x\n",
164	vendor, device,	164	vendor, device,
165	pci_classes_str(class), subclass);	165	pci_classes_str(class), subclass);
166	}	166	}
167		167
168	/*	168	/*
169	* Subroutine: PCI_Header_Show	169	* Subroutine: PCI_Header_Show
170	*	170	*
171	* Description: Reads the header of the specified PCI device.	171	* Description: Reads the header of the specified PCI device.
172	*	172	*
173	* Inputs: BusDevFunc Bus+Device+Function number	173	* Inputs: BusDevFunc Bus+Device+Function number
174	*	174	*
175	* Return: None	175	* Return: None
176	*	176	*
177	*/	177	*/
178	void pci_header_show(pci_dev_t dev)	178	void pci_header_show(pci_dev_t dev)
179	{	179	{
180	u8 _byte, header_type;	180	u8 _byte, header_type;
181	u16 _word;	181	u16 _word;
182	u32 _dword;	182	u32 _dword;
183		183
184	#define PRINT(msg, type, reg) \	184	#define PRINT(msg, type, reg) \
185	pci_read_config_##type(dev, reg, &_##type); \	185	pci_read_config_##type(dev, reg, &_##type); \
186	printf(msg, _##type)	186	printf(msg, _##type)
187		187
188	#define PRINT2(msg, type, reg, func) \	188	#define PRINT2(msg, type, reg, func) \
189	pci_read_config_##type(dev, reg, &_##type); \	189	pci_read_config_##type(dev, reg, &_##type); \
190	printf(msg, _##type, func(_##type))	190	printf(msg, _##type, func(_##type))
191		191
192	pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type);	192	pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type);
193		193
194	PRINT (" vendor ID = 0x%.4x\n", word, PCI_VENDOR_ID);	194	PRINT (" vendor ID = 0x%.4x\n", word, PCI_VENDOR_ID);
195	PRINT (" device ID = 0x%.4x\n", word, PCI_DEVICE_ID);	195	PRINT (" device ID = 0x%.4x\n", word, PCI_DEVICE_ID);
196	PRINT (" command register = 0x%.4x\n", word, PCI_COMMAND);	196	PRINT (" command register = 0x%.4x\n", word, PCI_COMMAND);
197	PRINT (" status register = 0x%.4x\n", word, PCI_STATUS);	197	PRINT (" status register = 0x%.4x\n", word, PCI_STATUS);
198	PRINT (" revision ID = 0x%.2x\n", byte, PCI_REVISION_ID);	198	PRINT (" revision ID = 0x%.2x\n", byte, PCI_REVISION_ID);
199	PRINT2(" class code = 0x%.2x (%s)\n", byte, PCI_CLASS_CODE,	199	PRINT2(" class code = 0x%.2x (%s)\n", byte, PCI_CLASS_CODE,
200	pci_classes_str);	200	pci_classes_str);
201	PRINT (" sub class code = 0x%.2x\n", byte, PCI_CLASS_SUB_CODE);	201	PRINT (" sub class code = 0x%.2x\n", byte, PCI_CLASS_SUB_CODE);
202	PRINT (" programming interface = 0x%.2x\n", byte, PCI_CLASS_PROG);	202	PRINT (" programming interface = 0x%.2x\n", byte, PCI_CLASS_PROG);
203	PRINT (" cache line = 0x%.2x\n", byte, PCI_CACHE_LINE_SIZE);	203	PRINT (" cache line = 0x%.2x\n", byte, PCI_CACHE_LINE_SIZE);
204	PRINT (" latency time = 0x%.2x\n", byte, PCI_LATENCY_TIMER);	204	PRINT (" latency time = 0x%.2x\n", byte, PCI_LATENCY_TIMER);
205	PRINT (" header type = 0x%.2x\n", byte, PCI_HEADER_TYPE);	205	PRINT (" header type = 0x%.2x\n", byte, PCI_HEADER_TYPE);
206	PRINT (" BIST = 0x%.2x\n", byte, PCI_BIST);	206	PRINT (" BIST = 0x%.2x\n", byte, PCI_BIST);
207	PRINT (" base address 0 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_0);	207	PRINT (" base address 0 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_0);
208	PRINT (" base address 1 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_1);
209		208
210	if (header_type & 0x01) { /* PCI-to-PCI bridge */	209	switch (header_type & 0x03) {
		210	case PCI_HEADER_TYPE_NORMAL: /* "normal" PCI device */
		211	PRINT (" base address 1 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_1);
		212	PRINT (" base address 2 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_2);
		213	PRINT (" base address 3 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_3);
		214	PRINT (" base address 4 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_4);
		215	PRINT (" base address 5 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_5);
		216	PRINT (" cardBus CIS pointer = 0x%.8x\n", dword, PCI_CARDBUS_CIS);
		217	PRINT (" sub system vendor ID = 0x%.4x\n", word, PCI_SUBSYSTEM_VENDOR_ID);
		218	PRINT (" sub system ID = 0x%.4x\n", word, PCI_SUBSYSTEM_ID);
		219	PRINT (" expansion ROM base address = 0x%.8x\n", dword, PCI_ROM_ADDRESS);
		220	PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
		221	PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
		222	PRINT (" min Grant = 0x%.2x\n", byte, PCI_MIN_GNT);
		223	PRINT (" max Latency = 0x%.2x\n", byte, PCI_MAX_LAT);
		224	break;
		225
		226	case PCI_HEADER_TYPE_BRIDGE: /* PCI-to-PCI bridge */
		227
		228	PRINT (" base address 1 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_1);
211	PRINT (" primary bus number = 0x%.2x\n", byte, PCI_PRIMARY_BUS);	229	PRINT (" primary bus number = 0x%.2x\n", byte, PCI_PRIMARY_BUS);
212	PRINT (" secondary bus number = 0x%.2x\n", byte, PCI_SECONDARY_BUS);	230	PRINT (" secondary bus number = 0x%.2x\n", byte, PCI_SECONDARY_BUS);
213	PRINT (" subordinate bus number = 0x%.2x\n", byte, PCI_SUBORDINATE_BUS);	231	PRINT (" subordinate bus number = 0x%.2x\n", byte, PCI_SUBORDINATE_BUS);
214	PRINT (" secondary latency timer = 0x%.2x\n", byte, PCI_SEC_LATENCY_TIMER);	232	PRINT (" secondary latency timer = 0x%.2x\n", byte, PCI_SEC_LATENCY_TIMER);
215	PRINT (" IO base = 0x%.2x\n", byte, PCI_IO_BASE);	233	PRINT (" IO base = 0x%.2x\n", byte, PCI_IO_BASE);
216	PRINT (" IO limit = 0x%.2x\n", byte, PCI_IO_LIMIT);	234	PRINT (" IO limit = 0x%.2x\n", byte, PCI_IO_LIMIT);
217	PRINT (" secondary status = 0x%.4x\n", word, PCI_SEC_STATUS);	235	PRINT (" secondary status = 0x%.4x\n", word, PCI_SEC_STATUS);
218	PRINT (" memory base = 0x%.4x\n", word, PCI_MEMORY_BASE);	236	PRINT (" memory base = 0x%.4x\n", word, PCI_MEMORY_BASE);
219	PRINT (" memory limit = 0x%.4x\n", word, PCI_MEMORY_LIMIT);	237	PRINT (" memory limit = 0x%.4x\n", word, PCI_MEMORY_LIMIT);
220	PRINT (" prefetch memory base = 0x%.4x\n", word, PCI_PREF_MEMORY_BASE);	238	PRINT (" prefetch memory base = 0x%.4x\n", word, PCI_PREF_MEMORY_BASE);
221	PRINT (" prefetch memory limit = 0x%.4x\n", word, PCI_PREF_MEMORY_LIMIT);	239	PRINT (" prefetch memory limit = 0x%.4x\n", word, PCI_PREF_MEMORY_LIMIT);
222	PRINT (" prefetch memory base upper = 0x%.8x\n", dword, PCI_PREF_BASE_UPPER32);	240	PRINT (" prefetch memory base upper = 0x%.8x\n", dword, PCI_PREF_BASE_UPPER32);
223	PRINT (" prefetch memory limit upper = 0x%.8x\n", dword, PCI_PREF_LIMIT_UPPER32);	241	PRINT (" prefetch memory limit upper = 0x%.8x\n", dword, PCI_PREF_LIMIT_UPPER32);
224	PRINT (" IO base upper 16 bits = 0x%.4x\n", word, PCI_IO_BASE_UPPER16);	242	PRINT (" IO base upper 16 bits = 0x%.4x\n", word, PCI_IO_BASE_UPPER16);
225	PRINT (" IO limit upper 16 bits = 0x%.4x\n", word, PCI_IO_LIMIT_UPPER16);	243	PRINT (" IO limit upper 16 bits = 0x%.4x\n", word, PCI_IO_LIMIT_UPPER16);
226	PRINT (" expansion ROM base address = 0x%.8x\n", dword, PCI_ROM_ADDRESS1);	244	PRINT (" expansion ROM base address = 0x%.8x\n", dword, PCI_ROM_ADDRESS1);
227	PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);	245	PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
228	PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);	246	PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
229	PRINT (" bridge control = 0x%.4x\n", word, PCI_BRIDGE_CONTROL);	247	PRINT (" bridge control = 0x%.4x\n", word, PCI_BRIDGE_CONTROL);
230	} else { /* PCI device */	248	break;
231	PRINT(" base address 2 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_2);	249
232	PRINT(" base address 3 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_3);	250	case PCI_HEADER_TYPE_CARDBUS: /* PCI-to-CardBus bridge */
233	PRINT(" base address 4 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_4);	251
234	PRINT(" base address 5 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_5);	252	PRINT (" capabilities = 0x%.2x\n", byte, PCI_CB_CAPABILITY_LIST);
235	PRINT(" cardBus CIS pointer = 0x%.8x\n", dword, PCI_CARDBUS_CIS);	253	PRINT (" secondary status = 0x%.4x\n", word, PCI_CB_SEC_STATUS);
236	PRINT(" sub system vendor ID = 0x%.4x\n", word, PCI_SUBSYSTEM_VENDOR_ID);	254	PRINT (" primary bus number = 0x%.2x\n", byte, PCI_CB_PRIMARY_BUS);
237	PRINT(" sub system ID = 0x%.4x\n", word, PCI_SUBSYSTEM_ID);	255	PRINT (" CardBus number = 0x%.2x\n", byte, PCI_CB_CARD_BUS);
238	PRINT(" expansion ROM base address = 0x%.8x\n", dword, PCI_ROM_ADDRESS);	256	PRINT (" subordinate bus number = 0x%.2x\n", byte, PCI_CB_SUBORDINATE_BUS);
239	PRINT(" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);	257	PRINT (" CardBus latency timer = 0x%.2x\n", byte, PCI_CB_LATENCY_TIMER);
240	PRINT(" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);	258	PRINT (" CardBus memory base 0 = 0x%.8x\n", dword, PCI_CB_MEMORY_BASE_0);
241	PRINT(" min Grant = 0x%.2x\n", byte, PCI_MIN_GNT);	259	PRINT (" CardBus memory limit 0 = 0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_0);
242	PRINT(" max Latency = 0x%.2x\n", byte, PCI_MAX_LAT);	260	PRINT (" CardBus memory base 1 = 0x%.8x\n", dword, PCI_CB_MEMORY_BASE_1);
		261	PRINT (" CardBus memory limit 1 = 0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_1);
		262	PRINT (" CardBus IO base 0 = 0x%.4x\n", word, PCI_CB_IO_BASE_0);
		263	PRINT (" CardBus IO base high 0 = 0x%.4x\n", word, PCI_CB_IO_BASE_0_HI);
		264	PRINT (" CardBus IO limit 0 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_0);
		265	PRINT (" CardBus IO limit high 0 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_0_HI);
		266	PRINT (" CardBus IO base 1 = 0x%.4x\n", word, PCI_CB_IO_BASE_1);
		267	PRINT (" CardBus IO base high 1 = 0x%.4x\n", word, PCI_CB_IO_BASE_1_HI);
		268	PRINT (" CardBus IO limit 1 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_1);
		269	PRINT (" CardBus IO limit high 1 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_1_HI);
		270	PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
		271	PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
		272	PRINT (" bridge control = 0x%.4x\n", word, PCI_CB_BRIDGE_CONTROL);
		273	PRINT (" subvendor ID = 0x%.4x\n", word, PCI_CB_SUBSYSTEM_VENDOR_ID);
		274	PRINT (" subdevice ID = 0x%.4x\n", word, PCI_CB_SUBSYSTEM_ID);
		275	PRINT (" PC Card 16bit base address = 0x%.8x\n", dword, PCI_CB_LEGACY_MODE_BASE);
		276	break;
		277
		278	default:
		279	printf("unknown header\n");
		280	break;
243	}	281	}
244		282
245	#undef PRINT	283	#undef PRINT
246	#undef PRINT2	284	#undef PRINT2
247	}	285	}
248		286
249	/* Convert the "bus.device.function" identifier into a number.	287	/* Convert the "bus.device.function" identifier into a number.
250	*/	288	*/
251	static pci_dev_t get_pci_dev(char* name)	289	static pci_dev_t get_pci_dev(char* name)
252	{	290	{
253	char cnum[12];	291	char cnum[12];
254	int len, i, iold, n;	292	int len, i, iold, n;
255	int bdfs[3] = {0,0,0};	293	int bdfs[3] = {0,0,0};
256		294
257	len = strlen(name);	295	len = strlen(name);
258	if (len > 8)	296	if (len > 8)
259	return -1;	297	return -1;
260	for (i = 0, iold = 0, n = 0; i < len; i++) {	298	for (i = 0, iold = 0, n = 0; i < len; i++) {
261	if (name[i] == '.') {	299	if (name[i] == '.') {
262	memcpy(cnum, &name[iold], i - iold);	300	memcpy(cnum, &name[iold], i - iold);
263	cnum[i - iold] = '\0';	301	cnum[i - iold] = '\0';
264	bdfs[n++] = simple_strtoul(cnum, NULL, 16);	302	bdfs[n++] = simple_strtoul(cnum, NULL, 16);
265	iold = i + 1;	303	iold = i + 1;
266	}	304	}
267	}	305	}
268	strcpy(cnum, &name[iold]);	306	strcpy(cnum, &name[iold]);
269	if (n == 0)	307	if (n == 0)
270	n = 1;	308	n = 1;
271	bdfs[n] = simple_strtoul(cnum, NULL, 16);	309	bdfs[n] = simple_strtoul(cnum, NULL, 16);
272	return PCI_BDF(bdfs[0], bdfs[1], bdfs[2]);	310	return PCI_BDF(bdfs[0], bdfs[1], bdfs[2]);
273	}	311	}
274		312
275	static int pci_cfg_display(pci_dev_t bdf, ulong addr, ulong size, ulong length)	313	static int pci_cfg_display(pci_dev_t bdf, ulong addr, ulong size, ulong length)
276	{	314	{
277	#define DISP_LINE_LEN 16	315	#define DISP_LINE_LEN 16
278	ulong i, nbytes, linebytes;	316	ulong i, nbytes, linebytes;
279	int rc = 0;	317	int rc = 0;
280		318
281	if (length == 0)	319	if (length == 0)
282	length = 0x40 / size; /* Standard PCI configuration space */	320	length = 0x40 / size; /* Standard PCI configuration space */
283		321
284	/* Print the lines.	322	/* Print the lines.
285	* once, and all accesses are with the specified bus width.	323	* once, and all accesses are with the specified bus width.
286	*/	324	*/
287	nbytes = length * size;	325	nbytes = length * size;
288	do {	326	do {
289	uint val4;	327	uint val4;
290	ushort val2;	328	ushort val2;
291	u_char val1;	329	u_char val1;
292		330
293	printf("%08lx:", addr);	331	printf("%08lx:", addr);
294	linebytes = (nbytes>DISP_LINE_LEN)?DISP_LINE_LEN:nbytes;	332	linebytes = (nbytes>DISP_LINE_LEN)?DISP_LINE_LEN:nbytes;
295	for (i=0; i<linebytes; i+= size) {	333	for (i=0; i<linebytes; i+= size) {
296	if (size == 4) {	334	if (size == 4) {
297	pci_read_config_dword(bdf, addr, &val4);	335	pci_read_config_dword(bdf, addr, &val4);
298	printf(" %08x", val4);	336	printf(" %08x", val4);
299	} else if (size == 2) {	337	} else if (size == 2) {
300	pci_read_config_word(bdf, addr, &val2);	338	pci_read_config_word(bdf, addr, &val2);
301	printf(" %04x", val2);	339	printf(" %04x", val2);
302	} else {	340	} else {
303	pci_read_config_byte(bdf, addr, &val1);	341	pci_read_config_byte(bdf, addr, &val1);
304	printf(" %02x", val1);	342	printf(" %02x", val1);
305	}	343	}
306	addr += size;	344	addr += size;
307	}	345	}
308	printf("\n");	346	printf("\n");
309	nbytes -= linebytes;	347	nbytes -= linebytes;
310	if (ctrlc()) {	348	if (ctrlc()) {
311	rc = 1;	349	rc = 1;
312	break;	350	break;
313	}	351	}
314	} while (nbytes > 0);	352	} while (nbytes > 0);
315		353
316	return (rc);	354	return (rc);
317	}	355	}
318		356
319	static int pci_cfg_write (pci_dev_t bdf, ulong addr, ulong size, ulong value)	357	static int pci_cfg_write (pci_dev_t bdf, ulong addr, ulong size, ulong value)
320	{	358	{
321	if (size == 4) {	359	if (size == 4) {
322	pci_write_config_dword(bdf, addr, value);	360	pci_write_config_dword(bdf, addr, value);
323	}	361	}
324	else if (size == 2) {	362	else if (size == 2) {
325	ushort val = value & 0xffff;	363	ushort val = value & 0xffff;
326	pci_write_config_word(bdf, addr, val);	364	pci_write_config_word(bdf, addr, val);
327	}	365	}
328	else {	366	else {
329	u_char val = value & 0xff;	367	u_char val = value & 0xff;
330	pci_write_config_byte(bdf, addr, val);	368	pci_write_config_byte(bdf, addr, val);
331	}	369	}
332	return 0;	370	return 0;
333	}	371	}
334		372
335	static int	373	static int
336	pci_cfg_modify (pci_dev_t bdf, ulong addr, ulong size, ulong value, int incrflag)	374	pci_cfg_modify (pci_dev_t bdf, ulong addr, ulong size, ulong value, int incrflag)
337	{	375	{
338	ulong i;	376	ulong i;
339	int nbytes;	377	int nbytes;
340	extern char console_buffer[];	378	extern char console_buffer[];
341	uint val4;	379	uint val4;
342	ushort val2;	380	ushort val2;
343	u_char val1;	381	u_char val1;
344		382
345	/* Print the address, followed by value. Then accept input for	383	/* Print the address, followed by value. Then accept input for
346	* the next value. A non-converted value exits.	384	* the next value. A non-converted value exits.
347	*/	385	*/
348	do {	386	do {
349	printf("%08lx:", addr);	387	printf("%08lx:", addr);
350	if (size == 4) {	388	if (size == 4) {
351	pci_read_config_dword(bdf, addr, &val4);	389	pci_read_config_dword(bdf, addr, &val4);
352	printf(" %08x", val4);	390	printf(" %08x", val4);
353	}	391	}
354	else if (size == 2) {	392	else if (size == 2) {
355	pci_read_config_word(bdf, addr, &val2);	393	pci_read_config_word(bdf, addr, &val2);
356	printf(" %04x", val2);	394	printf(" %04x", val2);
357	}	395	}
358	else {	396	else {
359	pci_read_config_byte(bdf, addr, &val1);	397	pci_read_config_byte(bdf, addr, &val1);
360	printf(" %02x", val1);	398	printf(" %02x", val1);
361	}	399	}
362		400
363	nbytes = readline (" ? ");	401	nbytes = readline (" ? ");
364	if (nbytes == 0 \|\| (nbytes == 1 && console_buffer[0] == '-')) {	402	if (nbytes == 0 \|\| (nbytes == 1 && console_buffer[0] == '-')) {
365	/* <CR> pressed as only input, don't modify current	403	/* <CR> pressed as only input, don't modify current
366	* location and move to next. "-" pressed will go back.	404	* location and move to next. "-" pressed will go back.
367	*/	405	*/
368	if (incrflag)	406	if (incrflag)
369	addr += nbytes ? -size : size;	407	addr += nbytes ? -size : size;
370	nbytes = 1;	408	nbytes = 1;
371	#ifdef CONFIG_BOOT_RETRY_TIME	409	#ifdef CONFIG_BOOT_RETRY_TIME
372	reset_cmd_timeout(); /* good enough to not time out */	410	reset_cmd_timeout(); /* good enough to not time out */
373	#endif	411	#endif
374	}	412	}
375	#ifdef CONFIG_BOOT_RETRY_TIME	413	#ifdef CONFIG_BOOT_RETRY_TIME
376	else if (nbytes == -2) {	414	else if (nbytes == -2) {
377	break; /* timed out, exit the command */	415	break; /* timed out, exit the command */
378	}	416	}
379	#endif	417	#endif
380	else {	418	else {
381	char *endp;	419	char *endp;
382	i = simple_strtoul(console_buffer, &endp, 16);	420	i = simple_strtoul(console_buffer, &endp, 16);
383	nbytes = endp - console_buffer;	421	nbytes = endp - console_buffer;
384	if (nbytes) {	422	if (nbytes) {
385	#ifdef CONFIG_BOOT_RETRY_TIME	423	#ifdef CONFIG_BOOT_RETRY_TIME
386	/* good enough to not time out	424	/* good enough to not time out
387	*/	425	*/
388	reset_cmd_timeout();	426	reset_cmd_timeout();
389	#endif	427	#endif
390	pci_cfg_write (bdf, addr, size, i);	428	pci_cfg_write (bdf, addr, size, i);
391	if (incrflag)	429	if (incrflag)
392	addr += size;	430	addr += size;
393	}	431	}
394	}	432	}
395	} while (nbytes);	433	} while (nbytes);
396		434
397	return 0;	435	return 0;
398	}	436	}
399		437
400	/* PCI Configuration Space access commands	438	/* PCI Configuration Space access commands
401	*	439	*
402	* Syntax:	440	* Syntax:
403	* pci display[.b, .w, .l] bus.device.function} [addr] [len]	441	* pci display[.b, .w, .l] bus.device.function} [addr] [len]
404	* pci next[.b, .w, .l] bus.device.function [addr]	442	* pci next[.b, .w, .l] bus.device.function [addr]
405	* pci modify[.b, .w, .l] bus.device.function [addr]	443	* pci modify[.b, .w, .l] bus.device.function [addr]
406	* pci write[.b, .w, .l] bus.device.function addr value	444	* pci write[.b, .w, .l] bus.device.function addr value
407	*/	445	*/
408	int do_pci (cmd_tbl_t cmdtp, int flag, int argc, char argv[])	446	int do_pci (cmd_tbl_t cmdtp, int flag, int argc, char argv[])
409	{	447	{
410	ulong addr = 0, value = 0, size = 0;	448	ulong addr = 0, value = 0, size = 0;
411	pci_dev_t bdf = 0;	449	pci_dev_t bdf = 0;
412	char cmd = 's';	450	char cmd = 's';
413		451
414	if (argc > 1)	452	if (argc > 1)
415	cmd = argv[1][0];	453	cmd = argv[1][0];
416		454
417	switch (cmd) {	455	switch (cmd) {
418	case 'd': /* display */	456	case 'd': /* display */
419	case 'n': /* next */	457	case 'n': /* next */
420	case 'm': /* modify */	458	case 'm': /* modify */
421	case 'w': /* write */	459	case 'w': /* write */
422	/* Check for a size specification. */	460	/* Check for a size specification. */
423	size = cmd_get_data_size(argv[1], 4);	461	size = cmd_get_data_size(argv[1], 4);
424	if (argc > 3)	462	if (argc > 3)
425	addr = simple_strtoul(argv[3], NULL, 16);	463	addr = simple_strtoul(argv[3], NULL, 16);
426	if (argc > 4)	464	if (argc > 4)
427	value = simple_strtoul(argv[4], NULL, 16);	465	value = simple_strtoul(argv[4], NULL, 16);
428	case 'h': /* header */	466	case 'h': /* header */
429	if (argc < 3)	467	if (argc < 3)
430	goto usage;	468	goto usage;
431	if ((bdf = get_pci_dev(argv[2])) == -1)	469	if ((bdf = get_pci_dev(argv[2])) == -1)
432	return 1;	470	return 1;
433	break;	471	break;
434	default: /* scan bus */	472	default: /* scan bus */
435	value = 1; /* short listing */	473	value = 1; /* short listing */
436	bdf = 0; /* bus number */	474	bdf = 0; /* bus number */
437	if (argc > 1) {	475	if (argc > 1) {
438	if (argv[argc-1][0] == 'l') {	476	if (argv[argc-1][0] == 'l') {
439	value = 0;	477	value = 0;
440	argc--;	478	argc--;
441	}	479	}
442	if (argc > 1)	480	if (argc > 1)
443	bdf = simple_strtoul(argv[1], NULL, 16);	481	bdf = simple_strtoul(argv[1], NULL, 16);
444	}	482	}
445	pciinfo(bdf, value);	483	pciinfo(bdf, value);
446	return 0;	484	return 0;
447	}	485	}
448		486
449	switch (argv[1][0]) {	487	switch (argv[1][0]) {
450	case 'h': /* header */	488	case 'h': /* header */
451	pci_header_show(bdf);	489	pci_header_show(bdf);
452	return 0;	490	return 0;
453	case 'd': /* display */	491	case 'd': /* display */
454	return pci_cfg_display(bdf, addr, size, value);	492	return pci_cfg_display(bdf, addr, size, value);
455	case 'n': /* next */	493	case 'n': /* next */
456	if (argc < 4)	494	if (argc < 4)
457	goto usage;	495	goto usage;
458	return pci_cfg_modify(bdf, addr, size, value, 0);	496	return pci_cfg_modify(bdf, addr, size, value, 0);
459	case 'm': /* modify */	497	case 'm': /* modify */
460	if (argc < 4)	498	if (argc < 4)
461	goto usage;	499	goto usage;
462	return pci_cfg_modify(bdf, addr, size, value, 1);	500	return pci_cfg_modify(bdf, addr, size, value, 1);
463	case 'w': /* write */	501	case 'w': /* write */
464	if (argc < 5)	502	if (argc < 5)
465	goto usage;	503	goto usage;
466	return pci_cfg_write(bdf, addr, size, value);	504	return pci_cfg_write(bdf, addr, size, value);
467	}	505	}
468		506
469	return 1;	507	return 1;
470	usage:	508	usage:
471	printf ("Usage:\n%s\n", cmdtp->usage);	509	printf ("Usage:\n%s\n", cmdtp->usage);
472	return 1;	510	return 1;
473	}	511	}
474		512
475	#endif /* (CONFIG_COMMANDS & CFG_CMD_PCI) */	513	#endif /* (CONFIG_COMMANDS & CFG_CMD_PCI) */
476		514
477	#endif /* CONFIG_PCI */	515	#endif /* CONFIG_PCI */

common/env_common.c

Diff comments View file @ 7c7a23b

 /*
  * (C) Copyright 2000-2002
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  * Andreas Heppel <aheppel@sysgo.de>
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 #include <common.h>
 #include <command.h>
 #include <environment.h>
 #include <cmd_nvedit.h>
 #include <linux/stddef.h>
 #include <malloc.h>
 #ifdef CONFIG_SHOW_BOOT_PROGRESS
 # include <status_led.h>
 # define SHOW_BOOT_PROGRESS(arg)	show_boot_progress(arg)
 #else
 # define SHOW_BOOT_PROGRESS(arg)
 #endif
 #ifdef CONFIG_AMIGAONEG3SE
 	extern void enable_nvram(void);
 	extern void disable_nvram(void);
 #endif
 #undef DEBUG_ENV
 #ifdef DEBUG_ENV
 #define DEBUGF(fmt,args...) printf(fmt ,##args)
 #else
 #define DEBUGF(fmt,args...)
 #endif
 extern env_t *env_ptr;
 extern void env_relocate_spec (void);
 extern uchar env_get_char_spec(int);
 static uchar env_get_char_init (int index);
 uchar (*env_get_char)(int) = env_get_char_init;
 /************************************************************************
  * Default settings to be used when no valid environment is found
  */
 #define XMK_STR(x)	#x
 #define MK_STR(x)	XMK_STR(x)
 uchar default_environment[] = {
 #ifdef	CONFIG_BOOTARGS
 	"bootargs="	CONFIG_BOOTARGS			"\0"
 #endif
 #ifdef	CONFIG_BOOTCOMMAND
 	"bootcmd="	CONFIG_BOOTCOMMAND		"\0"
 #endif
 #ifdef	CONFIG_RAMBOOTCOMMAND
 	"ramboot="	CONFIG_RAMBOOTCOMMAND		"\0"
 #endif
 #ifdef	CONFIG_NFSBOOTCOMMAND
 	"nfsboot="	CONFIG_NFSBOOTCOMMAND		"\0"
 #endif
 #if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0)
 	"bootdelay="	MK_STR(CONFIG_BOOTDELAY)	"\0"
 #endif
 #if defined(CONFIG_BAUDRATE) && (CONFIG_BAUDRATE >= 0)
 	"baudrate="	MK_STR(CONFIG_BAUDRATE)		"\0"
 #endif
 #ifdef	CONFIG_LOADS_ECHO
 	"loads_echo="	MK_STR(CONFIG_LOADS_ECHO)	"\0"
 #endif
 #ifdef	CONFIG_ETHADDR
 	"ethaddr="	MK_STR(CONFIG_ETHADDR)		"\0"
 #endif
 #ifdef	CONFIG_ETH1ADDR
 	"eth1addr="	MK_STR(CONFIG_ETH1ADDR)		"\0"
 #endif
 #ifdef	CONFIG_ETH2ADDR
 	"eth2addr="	MK_STR(CONFIG_ETH2ADDR)		"\0"
 #endif
 #ifdef	CONFIG_IPADDR
 	"ipaddr="	MK_STR(CONFIG_IPADDR)		"\0"
 #endif
 #ifdef	CONFIG_SERVERIP
 	"serverip="	MK_STR(CONFIG_SERVERIP)		"\0"
 #endif
 #ifdef	CFG_AUTOLOAD
 	"autoload="	CFG_AUTOLOAD			"\0"
 #endif
 #ifdef	CONFIG_PREBOOT
 	"preboot="	CONFIG_PREBOOT			"\0"
 #endif
 #ifdef	CONFIG_ROOTPATH
 	"rootpath="	MK_STR(CONFIG_ROOTPATH)		"\0"
 #endif
 #ifdef	CONFIG_GATEWAYIP
 	"gatewayip="	MK_STR(CONFIG_GATEWAYIP)	"\0"
 #endif
 #ifdef	CONFIG_NETMASK
 	"netmask="	MK_STR(CONFIG_NETMASK)		"\0"
 #endif
 #ifdef	CONFIG_HOSTNAME
 	"hostname="	MK_STR(CONFIG_HOSTNAME)		"\0"
 #endif
 #ifdef	CONFIG_BOOTFILE
 	"bootfile="	MK_STR(CONFIG_BOOTFILE)		"\0"
 #endif
 #ifdef	CONFIG_LOADADDR
 	"loadaddr="	MK_STR(CONFIG_LOADADDR)		"\0"
 #endif
 #ifdef  CONFIG_CLOCKS_IN_MHZ
 	"clocks_in_mhz=1\0"
 #endif
 #ifdef  CONFIG_EXTRA_ENV_SETTINGS
 	CONFIG_EXTRA_ENV_SETTINGS
 #endif
 	"\0"
 };
 void env_crc_update (void)
 {
 	env_ptr->crc = crc32(0, env_ptr->data, ENV_SIZE);
 }
 static uchar env_get_char_init (int index)
 {
 	DECLARE_GLOBAL_DATA_PTR;
 	uchar c;
 	/* if crc was bad, use the default environment */
 	if (gd->env_valid)
 	{
 		c = env_get_char_spec(index);
 	} else {
 		c = default_environment[index];
 	}
 	return (c);
 }
+#ifdef CONFIG_AMIGAONEG3SE
 uchar env_get_char_memory (int index)
 {
 	DECLARE_GLOBAL_DATA_PTR;
+	uchar retval;
+	enable_nvram();
+	if (gd->env_valid) {
+		retval = ( *((uchar *)(gd->env_addr + index)) );
+	} else {
+		retval = ( default_environment[index] );
+	}
+	disable_nvram();
+	return retval;
+}
+#else
+uchar env_get_char_memory (int index)
+{
+	DECLARE_GLOBAL_DATA_PTR;
 	if (gd->env_valid) {
 		return ( *((uchar *)(gd->env_addr + index)) );
 	} else {
 		return ( default_environment[index] );
 	}
 }
+#endif
 uchar *env_get_addr (int index)
 {
 	DECLARE_GLOBAL_DATA_PTR;
 	if (gd->env_valid) {
 		return ( ((uchar *)(gd->env_addr + index)) );
 	} else {
 		return (&default_environment[index]);
 	}
 }
 void env_relocate (void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
 	DEBUGF ("%s[%d] offset = 0x%lx\n", __FUNCTION__,__LINE__,
 		gd->reloc_off);
 #ifdef CONFIG_AMIGAONEG3SE
 	enable_nvram();
 #endif
 #ifdef ENV_IS_EMBEDDED
 	/*
 	 * The environment buffer is embedded with the text segment,
 	 * just relocate the environment pointer
 	 */
 	env_ptr = (env_t *)((ulong)env_ptr + gd->reloc_off);
 	DEBUGF ("%s[%d] embedded ENV at %p\n", __FUNCTION__,__LINE__,env_ptr);
 #else
 	/*
 	 * We must allocate a buffer for the environment
 	 */
 	env_ptr = (env_t *)malloc (CFG_ENV_SIZE);
 	DEBUGF ("%s[%d] malloced ENV at %p\n", __FUNCTION__,__LINE__,env_ptr);
 #endif
 	/*
 	 * After relocation to RAM, we can always use the "memory" functions
 	 */
 	env_get_char = env_get_char_memory;
 	if (gd->env_valid == 0) {
 #if defined(CONFIG_GTH)	|| defined(CFG_ENV_IS_NOWHERE)	/* Environment not changable */
 		puts ("Using default environment\n\n");
 #else
 		puts ("*** Warning - bad CRC, using default environment\n\n");
 		SHOW_BOOT_PROGRESS (-1);
 #endif
 		if (sizeof(default_environment) > ENV_SIZE)
 		{
 			puts ("*** Error - default environment is too large\n\n");
 			return;
 		}
 		memset (env_ptr, 0, sizeof(env_t));
 		memcpy (env_ptr->data,
 			default_environment,
 			sizeof(default_environment));
 #ifdef CFG_REDUNDAND_ENVIRONMENT
 		env_ptr->flags = 0xFF;
 #endif
 		env_crc_update ();
 		gd->env_valid = 1;
 	}
 	else {
 		env_relocate_spec ();
 	}
 	gd->env_addr = (ulong)&(env_ptr->data);
 #ifdef CONFIG_AMIGAONEG3SE
 	disable_nvram();
 #endif
 }

common/env_nvram.c

Diff comments View file @ 7c7a23b

1	/*	1	/*
2	* (C) Copyright 2000-2002	2	* (C) Copyright 2000-2002
3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4	*	4	*
5	* (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>	5	* (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
6	* Andreas Heppel <aheppel@sysgo.de>	6	* Andreas Heppel <aheppel@sysgo.de>
7		7
8	* See file CREDITS for list of people who contributed to this	8	* See file CREDITS for list of people who contributed to this
9	* project.	9	* project.
10	*	10	*
11	* This program is free software; you can redistribute it and/or	11	* This program is free software; you can redistribute it and/or
12	* modify it under the terms of the GNU General Public License as	12	* modify it under the terms of the GNU General Public License as
13	* published by the Free Software Foundation; either version 2 of	13	* published by the Free Software Foundation; either version 2 of
14	* the License, or (at your option) any later version.	14	* the License, or (at your option) any later version.
15	*	15	*
16	* This program is distributed in the hope that it will be useful,	16	* This program is distributed in the hope that it will be useful,
17	* but WITHOUT ANY WARRANTY; without even the implied warranty of	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19	* GNU General Public License for more details.	19	* GNU General Public License for more details.
20	*	20	*
21	* You should have received a copy of the GNU General Public License	21	* You should have received a copy of the GNU General Public License
22	* along with this program; if not, write to the Free Software	22	* along with this program; if not, write to the Free Software
23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24	* MA 02111-1307 USA	24	* MA 02111-1307 USA
25	*/	25	*/
26		26
27	/*	27	/*
28	* 09-18-2001 Andreas Heppel, Sysgo RTS GmbH <aheppel@sysgo.de>	28	* 09-18-2001 Andreas Heppel, Sysgo RTS GmbH <aheppel@sysgo.de>
29	*	29	*
30	* It might not be possible in all cases to use 'memcpy()' to copy	30	* It might not be possible in all cases to use 'memcpy()' to copy
31	* the environment to NVRAM, as the NVRAM might not be mapped into	31	* the environment to NVRAM, as the NVRAM might not be mapped into
32	* the memory space. (I.e. this is the case for the BAB750). In those	32	* the memory space. (I.e. this is the case for the BAB750). In those
33	* cases it might be possible to access the NVRAM using a different	33	* cases it might be possible to access the NVRAM using a different
34	* method. For example, the RTC on the BAB750 is accessible in IO	34	* method. For example, the RTC on the BAB750 is accessible in IO
35	* space using its address and data registers. To enable usage of	35	* space using its address and data registers. To enable usage of
36	* NVRAM in those cases I invented the functions 'nvram_read()' and	36	* NVRAM in those cases I invented the functions 'nvram_read()' and
37	* 'nvram_write()', which will be activated upon the configuration	37	* 'nvram_write()', which will be activated upon the configuration
38	* #define CFG_NVRAM_ACCESS_ROUTINE. Note, that those functions are	38	* #define CFG_NVRAM_ACCESS_ROUTINE. Note, that those functions are
39	* strongly dependent on the used HW, and must be redefined for each	39	* strongly dependent on the used HW, and must be redefined for each
40	* board that wants to use them.	40	* board that wants to use them.
41	*/	41	*/
42		42
43	#include <common.h>	43	#include <common.h>
44		44
45	#ifdef CFG_ENV_IS_IN_NVRAM /* Environment is in NVRAM */	45	#ifdef CFG_ENV_IS_IN_NVRAM /* Environment is in NVRAM */
46		46
47	#include <command.h>	47	#include <command.h>
48	#include <environment.h>	48	#include <environment.h>
49	#include <cmd_nvedit.h>	49	#include <cmd_nvedit.h>
50	#include <linux/stddef.h>	50	#include <linux/stddef.h>
51	#include <malloc.h>	51	#include <malloc.h>
52		52
53	#ifdef CFG_NVRAM_ACCESS_ROUTINE	53	#ifdef CFG_NVRAM_ACCESS_ROUTINE
54	extern void nvram_read(void dest, const long src, size_t count);	54	extern void nvram_read(void dest, const long src, size_t count);
55	extern void nvram_write(long dest, const void *src, size_t count);	55	extern void nvram_write(long dest, const void *src, size_t count);
56	env_t *env_ptr = NULL;	56	env_t *env_ptr = NULL;
57	#else	57	#else
58	env_t env_ptr = (env_t )CFG_ENV_ADDR;	58	env_t env_ptr = (env_t )CFG_ENV_ADDR;
59	#endif	59	#endif
60		60
61	char * env_name_spec = "NVRAM";	61	char * env_name_spec = "NVRAM";
62		62
63	extern uchar default_environment[];	63	extern uchar default_environment[];
64	extern int default_environment_size;	64	extern int default_environment_size;
65		65
66	extern uchar (*env_get_char)(int);	66	extern uchar (*env_get_char)(int);
67	extern uchar env_get_char_memory (int index);	67	extern uchar env_get_char_memory (int index);
68		68
		69	#ifdef CONFIG_AMIGAONEG3SE
		70	uchar env_get_char_spec (int index)
		71	{
		72	#ifdef CFG_NVRAM_ACCESS_ROUTINE
		73	uchar c;
69		74
		75	nvram_read(&c, CFG_ENV_ADDR+index, 1);
		76
		77	return c;
		78	#else
		79	DECLARE_GLOBAL_DATA_PTR;
		80	uchar retval;
		81	enable_nvram();
		82	retval = ((uchar )(gd->env_addr + index));
		83	disable_nvram();
		84	return retval;
		85	#endif
		86	}
		87	#else
70	uchar env_get_char_spec (int index)	88	uchar env_get_char_spec (int index)
71	{	89	{
72	#ifdef CFG_NVRAM_ACCESS_ROUTINE	90	#ifdef CFG_NVRAM_ACCESS_ROUTINE
73	uchar c;	91	uchar c;
74		92
75	nvram_read(&c, CFG_ENV_ADDR+index, 1);	93	nvram_read(&c, CFG_ENV_ADDR+index, 1);
76		94
77	return c;	95	return c;
78	#else	96	#else
79	DECLARE_GLOBAL_DATA_PTR;	97	DECLARE_GLOBAL_DATA_PTR;
80		98
81	return ((uchar )(gd->env_addr + index));	99	return ((uchar )(gd->env_addr + index));
82	#endif	100	#endif
83	}	101	}
		102	#endif
84		103
85	void env_relocate_spec (void)	104	void env_relocate_spec (void)
86	{	105	{
87	#if defined(CFG_NVRAM_ACCESS_ROUTINE)	106	#if defined(CFG_NVRAM_ACCESS_ROUTINE)
88	nvram_read(env_ptr, CFG_ENV_ADDR, CFG_ENV_SIZE);	107	nvram_read(env_ptr, CFG_ENV_ADDR, CFG_ENV_SIZE);
89	#else	108	#else
90	memcpy (env_ptr, (void*)CFG_ENV_ADDR, CFG_ENV_SIZE);	109	memcpy (env_ptr, (void*)CFG_ENV_ADDR, CFG_ENV_SIZE);
91	#endif	110	#endif
92	}	111	}
93		112
94	int saveenv (void)	113	int saveenv (void)
95	{	114	{
96	int rcode = 0;	115	int rcode = 0;
97		116	#ifdef CONFIG_AMIGAONEG3SE
		117	enable_nvram();
		118	#endif
98	#ifdef CFG_NVRAM_ACCESS_ROUTINE	119	#ifdef CFG_NVRAM_ACCESS_ROUTINE
99	nvram_write(CFG_ENV_ADDR, env_ptr, CFG_ENV_SIZE);	120	nvram_write(CFG_ENV_ADDR, env_ptr, CFG_ENV_SIZE);
100	#else	121	#else
101	if (memcpy ((char *)CFG_ENV_ADDR, env_ptr, CFG_ENV_SIZE) == NULL)	122	if (memcpy ((char *)CFG_ENV_ADDR, env_ptr, CFG_ENV_SIZE) == NULL)
102	rcode = 1 ;	123	rcode = 1 ;
103	#endif	124	#endif
		125	#ifdef CONFIG_AMIGAONEG3SE
		126	udelay(10000);
		127	disable_nvram();
		128	#endif
104	return rcode;	129	return rcode;
105	}	130	}
106		131
107		132
108	/************************************************************************	133	/************************************************************************
109	* Initialize Environment use	134	* Initialize Environment use
110	*	135	*
111	* We are still running from ROM, so data use is limited	136	* We are still running from ROM, so data use is limited
112	*/	137	*/
113	int env_init (void)	138	int env_init (void)
114	{	139	{
115	DECLARE_GLOBAL_DATA_PTR;	140	DECLARE_GLOBAL_DATA_PTR;
116		141	#ifdef CONFIG_AMIGAONEG3SE
		142	enable_nvram();
		143	#endif
117	#if defined(CFG_NVRAM_ACCESS_ROUTINE)	144	#if defined(CFG_NVRAM_ACCESS_ROUTINE)
118	ulong crc;	145	ulong crc;
119	uchar data[ENV_SIZE];	146	uchar data[ENV_SIZE];
120	nvram_read (&crc, CFG_ENV_ADDR, sizeof(ulong));	147	nvram_read (&crc, CFG_ENV_ADDR, sizeof(ulong));
121	nvram_read (data, CFG_ENV_ADDR+sizeof(ulong), ENV_SIZE);	148	nvram_read (data, CFG_ENV_ADDR+sizeof(ulong), ENV_SIZE);
122		149
123	if (crc32(0, data, ENV_SIZE) == crc) {	150	if (crc32(0, data, ENV_SIZE) == crc) {
124	gd->env_addr = (ulong)CFG_ENV_ADDR + sizeof(long);	151	gd->env_addr = (ulong)CFG_ENV_ADDR + sizeof(long);
125	#else	152	#else
126	if (crc32(0, env_ptr->data, ENV_SIZE) == env_ptr->crc) {	153	if (crc32(0, env_ptr->data, ENV_SIZE) == env_ptr->crc) {
127	gd->env_addr = (ulong)&(env_ptr->data);	154	gd->env_addr = (ulong)&(env_ptr->data);
128	#endif	155	#endif
129	gd->env_valid = 1;	156	gd->env_valid = 1;
130	} else {	157	} else {
131	gd->env_addr = (ulong)&default_environment[0];	158	gd->env_addr = (ulong)&default_environment[0];
132	gd->env_valid = 0;	159	gd->env_valid = 0;
133	}	160	}
134		161	#ifdef CONFIG_AMIGAONEG3SE
		162	disable_nvram();
		163	#endif
135	return (0);	164	return (0);
136	}	165	}
137		166
138	#endif /* CFG_ENV_IS_IN_NVRAM */	167	#endif /* CFG_ENV_IS_IN_NVRAM */
139		168

cpu/74xx_7xx/start.S

Diff comments View file @ 7c7a23b

 /*
  *  Copyright (C) 1998	Dan Malek <dmalek@jlc.net>
  *  Copyright (C) 1999	Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
  *  Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
  *  Copyright (C) 2001  Josh Huber <huber@mclx.com>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 /*  U-Boot - Startup Code for PowerPC based Embedded Boards
  *
  *
  *  The processor starts at 0xfff00100 and the code is executed
  *  from flash. The code is organized to be at an other address
  *  in memory, but as long we don't jump around before relocating.
  *  board_init lies at a quite high address and when the cpu has
  *  jumped there, everything is ok.
  */
 #include <config.h>
 #include <74xx_7xx.h>
 #include <version.h>
 #include <ppc_asm.tmpl>
 #include <ppc_defs.h>
 #include <asm/cache.h>
 #include <asm/mmu.h>
 #include <galileo/gt64260R.h>
 #ifndef  CONFIG_IDENT_STRING
 #define  CONFIG_IDENT_STRING ""
 #endif
 /* We don't want the  MMU yet.
 */
 #undef	MSR_KERNEL
 /* Machine Check and Recoverable Interr. */
 #define MSR_KERNEL ( MSR_ME | MSR_RI )
 /*
  * Set up GOT: Global Offset Table
  *
  * Use r14 to access the GOT
  */
 	START_GOT
 	GOT_ENTRY(_GOT2_TABLE_)
 	GOT_ENTRY(_FIXUP_TABLE_)
 	GOT_ENTRY(_start)
 	GOT_ENTRY(_start_of_vectors)
 	GOT_ENTRY(_end_of_vectors)
 	GOT_ENTRY(transfer_to_handler)
 	GOT_ENTRY(_end)
 	GOT_ENTRY(.bss)
 	END_GOT
 /*
  * r3 - 1st arg to board_init(): IMMP pointer
  * r4 - 2nd arg to board_init(): boot flag
  */
 	.text
 	.long	0x27051956		/* U-Boot Magic Number		*/
 	.globl	version_string
 version_string:
 	.ascii	U_BOOT_VERSION
 	.ascii	" (", __DATE__, " - ", __TIME__, ")"
 	.ascii	CONFIG_IDENT_STRING, "\0"
 	. = EXC_OFF_SYS_RESET
 	.globl	_start
 _start:
 	li	r21, BOOTFLAG_COLD	/* Normal Power-On: Boot from FLASH */
 	b	boot_cold
 	sync
 	. = EXC_OFF_SYS_RESET + 0x10
 	.globl	_start_warm
 _start_warm:
 	li	r21, BOOTFLAG_WARM	/* Software reboot		*/
 	b	boot_warm
 	sync
 	/* the boot code is located below the exception table */
 	.globl	_start_of_vectors
 _start_of_vectors:
 /* Machine check */
 	STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
 /* Data Storage exception.  "Never" generated on the 860. */
 	STD_EXCEPTION(0x300, DataStorage, UnknownException)
 /* Instruction Storage exception.  "Never" generated on the 860. */
 	STD_EXCEPTION(0x400, InstStorage, UnknownException)
 /* External Interrupt exception. */
 	STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
 /* Alignment exception. */
 	. = 0x600
 Alignment:
 	EXCEPTION_PROLOG
 	mfspr	r4,DAR
 	stw	r4,_DAR(r21)
 	mfspr	r5,DSISR
 	stw	r5,_DSISR(r21)
 	addi	r3,r1,STACK_FRAME_OVERHEAD
 	li	r20,MSR_KERNEL
 	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
 	lwz	r6,GOT(transfer_to_handler)
 	mtlr	r6
 	blrl
 .L_Alignment:
 	.long	AlignmentException - _start + EXC_OFF_SYS_RESET
 	.long	int_return - _start + EXC_OFF_SYS_RESET
 /* Program check exception */
 	. = 0x700
 ProgramCheck:
 	EXCEPTION_PROLOG
 	addi	r3,r1,STACK_FRAME_OVERHEAD
 	li	r20,MSR_KERNEL
 	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
 	lwz	r6,GOT(transfer_to_handler)
 	mtlr	r6
 	blrl
 .L_ProgramCheck:
 	.long	ProgramCheckException - _start + EXC_OFF_SYS_RESET
 	.long	int_return - _start + EXC_OFF_SYS_RESET
 	/* No FPU on MPC8xx.  This exception is not supposed to happen.
 	*/
 	STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
 	/* I guess we could implement decrementer, and may have
 	 * to someday for timekeeping.
 	 */
 	STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
 	STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
 	STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
 	. = 0xc00
 /*
  * r0 - SYSCALL number
  * r3-... arguments
  */
 SystemCall:
 	addis	r11,r0,0		/* get functions table addr */
 	ori	r11,r11,0		/* Note: this code is patched in trap_init */
 	addis	r12,r0,0		/* get number of functions */
 	ori	r12,r12,0
 	cmplw	0, r0, r12
 	bge	1f
 	rlwinm	r0,r0,2,0,31		/* fn_addr = fn_tbl[r0] */
 	add	r11,r11,r0
 	lwz	r11,0(r11)
-	li	r12,0xd00-4*3		/* save LR & SRRx */
+	li	r20,0xd00-4		/* Get stack pointer */
+	lwz	r12,0(r20)
+	subi	r12,r12,12		/* Adjust stack pointer */
+	li	r0,0xc00+_end_back-SystemCall
+	cmplw	0, r0, r12		/* Check stack overflow */
+	bgt	1f
+	stw	r12,0(r20)
 	mflr	r0
 	stw	r0,0(r12)
 	mfspr	r0,SRR0
 	stw	r0,4(r12)
 	mfspr	r0,SRR1
 	stw	r0,8(r12)
 	li	r12,0xc00+_back-SystemCall
 	mtlr	r12
 	mtspr	SRR0,r11
 1:	SYNC
 	rfi
 _back:
 	mfmsr	r11			/* Disable interrupts */
 	li	r12,0
 	ori	r12,r12,MSR_EE
 	andc	r11,r11,r12
 	SYNC				/* Some chip revs need this... */
 	mtmsr	r11
 	SYNC
-	li	r12,0xd00-4*3		/* restore regs */
+	li	r12,0xd00-4		/* restore regs */
+	lwz	r12,0(r12)
 	lwz	r11,0(r12)
 	mtlr	r11
 	lwz	r11,4(r12)
 	mtspr	SRR0,r11
 	lwz	r11,8(r12)
 	mtspr	SRR1,r11
+	addi	r12,r12,12		/* Adjust stack pointer */
+	li	r20,0xd00-4
+	stw	r12,0(r20)
 	SYNC
 	rfi
+_end_back:
 	STD_EXCEPTION(0xd00, SingleStep, UnknownException)
 	STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
 	STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
         /*
          * On the MPC8xx, this is a software emulation interrupt. It
          * occurs for all unimplemented and illegal instructions.
 	 */
 	STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
 	STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
 	STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
 	STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
 	STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
 	STD_EXCEPTION(0x1500, Reserved5, UnknownException)
 	STD_EXCEPTION(0x1600, Reserved6, UnknownException)
 	STD_EXCEPTION(0x1700, Reserved7, UnknownException)
 	STD_EXCEPTION(0x1800, Reserved8, UnknownException)
 	STD_EXCEPTION(0x1900, Reserved9, UnknownException)
 	STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
 	STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
 	STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
 	STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException)
 	STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
 	STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
 	.globl	_end_of_vectors
 _end_of_vectors:
 	. = 0x2000
 boot_cold:
 boot_warm:
 	/* disable everything */
 	li	r0, 0
 	mtspr	HID0, r0
 	sync
 	mtmsr	0
 	bl	invalidate_bats
 	sync
 #ifdef CFG_L2
 	/* init the L2 cache */
 	addis	r3, r0, L2_INIT@h
 	ori	r3, r3, L2_INIT@l
 	sync
 	mtspr	l2cr, r3
 #endif
 #if defined(CONFIG_ALTIVEC) && defined(CONFIG_74xx)
 	.long	0x7e00066c
 		/*
                  * dssall instruction, gas doesn't have it yet
                  * ...for altivec, data stream stop all this probably
                  * isn't needed unless we warm (software) reboot U-Boot
 		 */
 #endif
 #ifdef CFG_L2
 	/* invalidate the L2 cache */
 	bl	l2cache_invalidate
 	sync
 #endif
 #ifdef CFG_BOARD_ASM_INIT
 	/* do early init */
 	bl	board_asm_init
 #endif
 	/*
 	 * Calculate absolute address in FLASH and jump there
 	 *------------------------------------------------------*/
 	lis	r3, CFG_MONITOR_BASE@h
 	ori	r3, r3, CFG_MONITOR_BASE@l
 	addi	r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
 	mtlr	r3
 	blr
 in_flash:
 	/* let the C-code set up the rest			*/
 	/*							*/
 	/* Be careful to keep code relocatable !		*/
 	/*------------------------------------------------------*/
 	/* perform low-level init */
 	/* sdram init, galileo init, etc */
 	/* r3:	NHR bit from HID0 */
 	/* setup the bats */
 	bl	setup_bats
 	sync
 	/*
 	 * Cache must be enabled here for stack-in-cache trick.
 	 * This means we need to enable the BATS.
 	 * This means:
          *   1) for the EVB, original gt regs need to be mapped
 	 *   2) need to have an IBAT for the 0xf region,
 	 *      we are running there!
          * Cache should be turned on after BATs, since by default
          * everything is write-through.
          * The init-mem BAT can be reused after reloc. The old
          * gt-regs BAT can be reused after board_init_f calls
          * board_pre_init (EVB only).
          */
 #if !defined(CONFIG_BAB7xx) && !defined(CONFIG_ELPPC)
 	/* enable address translation */
 	bl	enable_addr_trans
 	sync
 	/* enable and invalidate the data cache */
 	bl	l1dcache_enable
 	sync
 #endif
 #ifdef CFG_INIT_RAM_LOCK
 	bl	lock_ram_in_cache
 	sync
 #endif
 	/* set up the stack pointer in our newly created
 	 * cache-ram (r1) */
 	lis	r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@h
 	ori	r1, r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@l
 	li	r0, 0		/* Make room for stack frame header and	*/
 	stwu	r0, -4(r1)	/* clear final stack frame so that	*/
 	stwu	r0, -4(r1)	/* stack backtraces terminate cleanly	*/
 	GET_GOT			/* initialize GOT access	*/
 	/* run low-level CPU init code     (from Flash)	*/
 	bl	cpu_init_f
 	sync
 	mr	r3, r21
 	/* r3: BOOTFLAG */
 	/* run 1st part of board init code (from Flash)   */
 	bl	board_init_f
 	sync
 	/* NOTREACHED */
 	.globl	invalidate_bats
 invalidate_bats:
 	/* invalidate BATs */
 	mtspr	IBAT0U, r0
 	mtspr	IBAT1U, r0
 	mtspr	IBAT2U, r0
 	mtspr	IBAT3U, r0
 	isync
 	mtspr	DBAT0U, r0
 	mtspr	DBAT1U, r0
 	mtspr	DBAT2U, r0
 	mtspr	DBAT3U, r0
 	isync
 	sync
 	blr
 	/* setup_bats - set them up to some initial state */
 	.globl	setup_bats
 setup_bats:
 	addis	r0, r0, 0x0000
 	/* IBAT 0 */
 	addis	r4, r0, CFG_IBAT0L@h
 	ori	r4, r4, CFG_IBAT0L@l
 	addis	r3, r0, CFG_IBAT0U@h
 	ori	r3, r3, CFG_IBAT0U@l
 	mtspr	IBAT0L, r4
 	mtspr	IBAT0U, r3
 	isync
 	/* DBAT 0 */
 	addis	r4, r0, CFG_DBAT0L@h
 	ori	r4, r4, CFG_DBAT0L@l
 	addis	r3, r0, CFG_DBAT0U@h
 	ori	r3, r3, CFG_DBAT0U@l
 	mtspr	DBAT0L, r4
 	mtspr	DBAT0U, r3
 	isync
 	/* IBAT 1 */
 	addis	r4, r0, CFG_IBAT1L@h
 	ori	r4, r4, CFG_IBAT1L@l
 	addis	r3, r0, CFG_IBAT1U@h
 	ori	r3, r3, CFG_IBAT1U@l
 	mtspr	IBAT1L, r4
 	mtspr	IBAT1U, r3
 	isync
 	/* DBAT 1 */
 	addis	r4, r0, CFG_DBAT1L@h
 	ori	r4, r4, CFG_DBAT1L@l
 	addis	r3, r0, CFG_DBAT1U@h
 	ori	r3, r3, CFG_DBAT1U@l
 	mtspr	DBAT1L, r4
 	mtspr	DBAT1U, r3
 	isync
 	/* IBAT 2 */
 	addis	r4, r0, CFG_IBAT2L@h
 	ori	r4, r4, CFG_IBAT2L@l
 	addis	r3, r0, CFG_IBAT2U@h
 	ori	r3, r3, CFG_IBAT2U@l
 	mtspr	IBAT2L, r4
 	mtspr	IBAT2U, r3
 	isync
 	/* DBAT 2 */
 	addis	r4, r0, CFG_DBAT2L@h
 	ori	r4, r4, CFG_DBAT2L@l
 	addis	r3, r0, CFG_DBAT2U@h
 	ori	r3, r3, CFG_DBAT2U@l
 	mtspr	DBAT2L, r4
 	mtspr	DBAT2U, r3
 	isync
 	/* IBAT 3 */
 	addis	r4, r0, CFG_IBAT3L@h
 	ori	r4, r4, CFG_IBAT3L@l
 	addis	r3, r0, CFG_IBAT3U@h
 	ori	r3, r3, CFG_IBAT3U@l
 	mtspr	IBAT3L, r4
 	mtspr	IBAT3U, r3
 	isync
 	/* DBAT 3 */
 	addis	r4, r0, CFG_DBAT3L@h
 	ori	r4, r4, CFG_DBAT3L@l
 	addis	r3, r0, CFG_DBAT3U@h
 	ori	r3, r3, CFG_DBAT3U@l
 	mtspr	DBAT3L, r4
 	mtspr	DBAT3U, r3
 	isync
 	/* bats are done, now invalidate the TLBs */
 	addis	r3, 0, 0x0000
 	addis	r5, 0, 0x4    /* upper bound of 0x00040000 for 7400/750 */
 	isync
 tlblp:
 	tlbie	r3
 	sync
 	addi	r3, r3, 0x1000
 	cmp	0, 0, r3, r5
 	blt tlblp
 	blr
 	.globl enable_addr_trans
 enable_addr_trans:
 	/* enable address translation */
 	mfmsr	r5
 	ori	r5, r5, (MSR_IR | MSR_DR)
 	mtmsr	r5
 	isync
 	blr
 	.globl disable_addr_trans
 disable_addr_trans:
 	/* disable address translation */
 	mflr	r4
 	mfmsr	r3
 	andi.	r0, r3, (MSR_IR | MSR_DR)
 	beqlr
 	andc	r3, r3, r0
 	mtspr	SRR0, r4
 	mtspr	SRR1, r3
 	rfi
 /*
  * This code finishes saving the registers to the exception frame
  * and jumps to the appropriate handler for the exception.
  * Register r21 is pointer into trap frame, r1 has new stack pointer.
  */
 	.globl	transfer_to_handler
 transfer_to_handler:
 	stw	r22,_NIP(r21)
 	lis	r22,MSR_POW@h
 	andc	r23,r23,r22
 	stw	r23,_MSR(r21)
 	SAVE_GPR(7, r21)
 	SAVE_4GPRS(8, r21)
 	SAVE_8GPRS(12, r21)
 	SAVE_8GPRS(24, r21)
 	mflr	r23
 	andi.	r24,r23,0x3f00		/* get vector offset */
 	stw	r24,TRAP(r21)
 	li	r22,0
 	stw	r22,RESULT(r21)
 	mtspr	SPRG2,r22		/* r1 is now kernel sp */
 	lwz	r24,0(r23)		/* virtual address of handler */
 	lwz	r23,4(r23)		/* where to go when done */
 	mtspr	SRR0,r24
 	mtspr	SRR1,r20
 	mtlr	r23
 	SYNC
 	rfi				/* jump to handler, enable MMU */
 int_return:
 	mfmsr	r28		/* Disable interrupts */
 	li	r4,0
 	ori	r4,r4,MSR_EE
 	andc	r28,r28,r4
 	SYNC			/* Some chip revs need this... */
 	mtmsr	r28
 	SYNC
 	lwz	r2,_CTR(r1)
 	lwz	r0,_LINK(r1)
 	mtctr	r2
 	mtlr	r0
 	lwz	r2,_XER(r1)
 	lwz	r0,_CCR(r1)
 	mtspr	XER,r2
 	mtcrf	0xFF,r0
 	REST_10GPRS(3, r1)
 	REST_10GPRS(13, r1)
 	REST_8GPRS(23, r1)
 	REST_GPR(31, r1)
 	lwz	r2,_NIP(r1)	/* Restore environment */
 	lwz	r0,_MSR(r1)
 	mtspr	SRR0,r2
 	mtspr	SRR1,r0
 	lwz	r0,GPR0(r1)
 	lwz	r2,GPR2(r1)
 	lwz	r1,GPR1(r1)
 	SYNC
 	rfi
 	.globl	dc_read
 dc_read:
 	blr
 	.globl get_pvr
 get_pvr:
 	mfspr	r3, PVR
 	blr
 /*-----------------------------------------------------------------------*/
 /*
  * void relocate_code (addr_sp, gd, addr_moni)
  *
  * This "function" does not return, instead it continues in RAM
  * after relocating the monitor code.
  *
  * r3 = dest
  * r4 = src
  * r5 = length in bytes
  * r6 = cachelinesize
  */
 	.globl	relocate_code
 relocate_code:
 	mr	r1,  r3		/* Set new stack pointer		*/
 	mr	r9,  r4		/* Save copy of Global Data pointer	*/
 	mr	r10, r5		/* Save copy of Destination Address	*/
 	mr	r3,  r5				/* Destination Address	*/
 	lis	r4, CFG_MONITOR_BASE@h		/* Source      Address	*/
 	ori	r4, r4, CFG_MONITOR_BASE@l
 	lis	r5, CFG_MONITOR_LEN@h		/* Length in Bytes	*/
 	ori	r5, r5, CFG_MONITOR_LEN@l
 	li	r6, CFG_CACHELINE_SIZE		/* Cache Line Size	*/
 	/*
 	 * Fix GOT pointer:
 	 *
 	 * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
 	 *
 	 * Offset:
 	 */
 	sub	r15, r10, r4
 	/* First our own GOT */
 	add	r14, r14, r15
 	/* then the one used by the C code */
 	add	r30, r30, r15
 	/*
 	 * Now relocate code
 	 */
 #ifdef CONFIG_ECC
 	bl	board_relocate_rom
 	sync
 	mr	r3, r10				/* Destination Address	*/
 	lis	r4, CFG_MONITOR_BASE@h		/* Source      Address	*/
 	ori	r4, r4, CFG_MONITOR_BASE@l
 	lis	r5, CFG_MONITOR_LEN@h		/* Length in Bytes	*/
 	ori	r5, r5, CFG_MONITOR_LEN@l
 	li	r6, CFG_CACHELINE_SIZE		/* Cache Line Size	*/
 #else
 	cmplw	cr1,r3,r4
 	addi	r0,r5,3
 	srwi.	r0,r0,2
 	beq	cr1,4f		/* In place copy is not necessary	*/
 	beq	7f		/* Protect against 0 count		*/
 	mtctr	r0
 	bge	cr1,2f
 	la	r8,-4(r4)
 	la	r7,-4(r3)
 1:	lwzu	r0,4(r8)
 	stwu	r0,4(r7)
 	bdnz	1b
 	b	4f
 2:	slwi	r0,r0,2
 	add	r8,r4,r0
 	add	r7,r3,r0
 3:	lwzu	r0,-4(r8)
 	stwu	r0,-4(r7)
 	bdnz	3b
 #endif
 /*
  * Now flush the cache: note that we must start from a cache aligned
  * address. Otherwise we might miss one cache line.
  */
 4:	cmpwi	r6,0
 	add	r5,r3,r5
 	beq	7f		/* Always flush prefetch queue in any case */
 	subi	r0,r6,1
 	andc	r3,r3,r0
 	mr	r4,r3
 5:	dcbst	0,r4
 	add	r4,r4,r6
 	cmplw	r4,r5
 	blt	5b
 	sync			/* Wait for all dcbst to complete on bus */
 	mr	r4,r3
 6:	icbi	0,r4
 	add	r4,r4,r6
 	cmplw	r4,r5
 	blt	6b
 7:	sync			/* Wait for all icbi to complete on bus	*/
 	isync
 /*
  * We are done. Do not return, instead branch to second part of board
  * initialization, now running from RAM.
  */
 	addi	r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
 	mtlr	r0
 	blr
 in_ram:
 #ifdef CONFIG_ECC
 	bl	board_init_ecc
 #endif
 	/*
 	 * Relocation Function, r14 point to got2+0x8000
 	 *
          * Adjust got2 pointers, no need to check for 0, this code
          * already puts a few entries in the table.
 	 */
 	li	r0,__got2_entries@sectoff@l
 	la	r3,GOT(_GOT2_TABLE_)
 	lwz	r11,GOT(_GOT2_TABLE_)
 	mtctr	r0
 	sub	r11,r3,r11
 	addi	r3,r3,-4
 1:	lwzu	r0,4(r3)
 	add	r0,r0,r11
 	stw	r0,0(r3)
 	bdnz	1b
 	/*
          * Now adjust the fixups and the pointers to the fixups
 	 * in case we need to move ourselves again.
 	 */
 2:	li	r0,__fixup_entries@sectoff@l
 	lwz	r3,GOT(_FIXUP_TABLE_)
 	cmpwi	r0,0
 	mtctr	r0
 	addi	r3,r3,-4
 	beq	4f
 3:	lwzu	r4,4(r3)
 	lwzux	r0,r4,r11
 	add	r0,r0,r11
 	stw	r10,0(r3)
 	stw	r0,0(r4)
 	bdnz	3b
 4:
 /* clear_bss: */
 	/*
 	 * Now clear BSS segment
 	 */
 	lwz	r3,GOT(.bss)
 	lwz	r4,GOT(_end)
 	cmplw	0, r3, r4
 	beq	6f
 	li	r0, 0
 5:
 	stw	r0, 0(r3)
 	addi	r3, r3, 4
 	cmplw	0, r3, r4
 	bne	5b
 6:
 	mr	r3, r10		/* Destination Address		*/
+#ifdef CONFIG_AMIGAONEG3SE
+	mr	r4, r9		/* Use RAM copy of the global data */
+#endif
 	bl	after_reloc
 	/* not reached - end relocate_code */
 /*-----------------------------------------------------------------------*/
 	/* Problems accessing "end" in C, so do it here */
 	.globl	get_endaddr
 get_endaddr:
 	lwz	r3,GOT(_end)
 	blr
 	/*
 	 * Copy exception vector code to low memory
 	 *
 	 * r3: dest_addr
 	 * r7: source address, r8: end address, r9: target address
 	 */
 	.globl	trap_init
 trap_init:
 	lwz	r7, GOT(_start)
 	lwz	r8, GOT(_end_of_vectors)
 	rlwinm	r9, r7, 0, 18, 31	/* _start & 0x3FFF	*/
 	cmplw	0, r7, r8
 	bgelr				/* return if r7>=r8 - just in case */
 	mflr	r4			/* save link register		*/
 1:
 	lwz	r0, 0(r7)
 	stw	r0, 0(r9)
 	addi	r7, r7, 4
 	addi	r9, r9, 4
 	cmplw	0, r7, r8
 	bne	1b
 	/*
 	 * relocate `hdlr' and `int_return' entries
 	 */
 	li	r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
 	li	r8, Alignment - _start + EXC_OFF_SYS_RESET
 2:
 	bl	trap_reloc
 	addi	r7, r7, 0x100		/* next exception vector	*/
 	cmplw	0, r7, r8
 	blt	2b
 	li	r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
 	bl	trap_reloc
 	li	r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
 	bl	trap_reloc
 	li	r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
 	li	r8, SystemCall - _start + EXC_OFF_SYS_RESET
 3:
 	bl	trap_reloc
 	addi	r7, r7, 0x100		/* next exception vector	*/
 	cmplw	0, r7, r8
 	blt	3b
 	li	r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
 	li	r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
 4:
 	bl	trap_reloc
 	addi	r7, r7, 0x100		/* next exception vector	*/
 	cmplw	0, r7, r8
 	blt	4b
 	/* enable execptions from RAM vectors */
 	mfmsr	r7
 	li	r8,MSR_IP
 	andc	r7,r7,r8
 	mtmsr	r7
 	mtlr	r4			/* restore link register	*/
 	blr
 	/*
 	 * Function: relocate entries for one exception vector
 	 */
 trap_reloc:
 	lwz	r0, 0(r7)		/* hdlr ...			*/
 	add	r0, r0, r3		/*  ... += dest_addr		*/
 	stw	r0, 0(r7)
 	lwz	r0, 4(r7)		/* int_return ...		*/
 	add	r0, r0, r3		/*  ... += dest_addr		*/
 	stw	r0, 4(r7)
 	sync
 	isync
 	blr
 #ifdef CFG_INIT_RAM_LOCK
 lock_ram_in_cache:
 	/* Allocate Initial RAM in data cache.
 	 */
 	lis	r3, (CFG_INIT_RAM_ADDR & ~31)@h
 	ori	r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
 	li	r2, ((CFG_INIT_RAM_END & ~31) + \
 		     (CFG_INIT_RAM_ADDR & 31) + 31) / 32
 	mtctr	r2
 1:
 	dcbz	r0, r3
 	addi	r3, r3, 32
 	bdnz	1b
 	/* Lock the data cache */
 	mfspr	r0, HID0
 	ori	r0, r0, 0x1000
 	sync
 	mtspr	HID0, r0
 	sync
 	blr
 .globl unlock_ram_in_cache
 unlock_ram_in_cache:
 	/* invalidate the INIT_RAM section */
 	lis	r3, (CFG_INIT_RAM_ADDR & ~31)@h
 	ori	r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l
 	li	r2, ((CFG_INIT_RAM_END & ~31) + \
 		     (CFG_INIT_RAM_ADDR & 31) + 31) / 32
 	mtctr	r2
 1:	icbi	r0, r3
 	addi	r3, r3, 32
 	bdnz	1b
 	sync			/* Wait for all icbi to complete on bus	*/
 	isync
 	/* Unlock the data cache and invalidate it */
 	mfspr   r0, HID0
 	li      r3,0x1000
 	andc    r0,r0,r3
 	li	r3,0x0400
 	or	r0,r0,r3
 	sync
 	mtspr   HID0, r0
 	sync
 	blr
 #endif

cpu/mpc824x/drivers/epic/epic.h

Diff comments View file @ 7c7a23b

 /*********************************************************************
  * mpc8240epic.h - EPIC module of the MPC8240 micro-controller
  *
  * Copyrigh 1999  Motorola Inc.
  *
  * Modification History:
  * =====================
  * 01a,04Feb99,My  Created.
  * 15Nov200, robt -modified to use in U-Boot
  *
 */
 #ifndef __INCEPICh
 #define __INCEPICh
 #define ULONG unsigned long
 #define MAXVEC             20
 #define MAXIRQ        5 /* IRQs */
 #define EPIC_DIRECT_IRQ     0 /* Direct interrupt type */
 /* EPIC register addresses */
 #define EPIC_EUMBBAR      0x40000     /* EUMBBAR of EPIC  */
 #define EPIC_FEATURES_REG (EPIC_EUMBBAR + 0x01000)/* Feature reporting */
 #define EPIC_GLOBAL_REG   (EPIC_EUMBBAR + 0x01020)/* Global config.  */
 #define EPIC_INT_CONF_REG (EPIC_EUMBBAR + 0x01030)/* Interrupt config. */
 #define EPIC_VENDOR_ID_REG  (EPIC_EUMBBAR + 0x01080)/* Vendor id */
 #define EPIC_PROC_INIT_REG  (EPIC_EUMBBAR + 0x01090)/* Processor init. */
 #define EPIC_SPUR_VEC_REG (EPIC_EUMBBAR + 0x010e0)/* Spurious vector */
 #define EPIC_TM_FREQ_REG  (EPIC_EUMBBAR + 0x010f0)/* Timer Frequency */
 #define EPIC_TM0_CUR_COUNT_REG  (EPIC_EUMBBAR + 0x01100)/* Gbl TM0 Cur. Count*/
 #define EPIC_TM0_BASE_COUNT_REG (EPIC_EUMBBAR + 0x01110)/* Gbl TM0 Base Count*/
 #define EPIC_TM0_VEC_REG  (EPIC_EUMBBAR + 0x01120)/* Gbl TM0 Vector Pri*/
 #define EPIC_TM0_DES_REG  (EPIC_EUMBBAR + 0x01130)/* Gbl TM0 Dest. */
 #define EPIC_TM1_CUR_COUNT_REG  (EPIC_EUMBBAR + 0x01140)/* Gbl TM1 Cur. Count*/
 #define EPIC_TM1_BASE_COUNT_REG (EPIC_EUMBBAR + 0x01150)/* Gbl TM1 Base Count*/
 #define EPIC_TM1_VEC_REG  (EPIC_EUMBBAR + 0x01160)/* Gbl TM1 Vector Pri*/
 #define EPIC_TM1_DES_REG  (EPIC_EUMBBAR + 0x01170)/* Gbl TM1 Dest. */
 #define EPIC_TM2_CUR_COUNT_REG  (EPIC_EUMBBAR + 0x01180)/* Gbl TM2 Cur. Count*/
 #define EPIC_TM2_BASE_COUNT_REG (EPIC_EUMBBAR + 0x01190)/* Gbl TM2 Base Count*/
 #define EPIC_TM2_VEC_REG  (EPIC_EUMBBAR + 0x011a0)/* Gbl TM2 Vector Pri*/
 #define EPIC_TM2_DES_REG  (EPIC_EUMBBAR + 0x011b0)/* Gbl TM2 Dest */
 #define EPIC_TM3_CUR_COUNT_REG  (EPIC_EUMBBAR + 0x011c0)/* Gbl TM3 Cur. Count*/
 #define EPIC_TM3_BASE_COUNT_REG (EPIC_EUMBBAR + 0x011d0)/* Gbl TM3 Base Count*/
 #define EPIC_TM3_VEC_REG  (EPIC_EUMBBAR + 0x011e0)/* Gbl TM3 Vector Pri*/
 #define EPIC_TM3_DES_REG  (EPIC_EUMBBAR + 0x011f0)/* Gbl TM3 Dest. */
 #define EPIC_EX_INT0_VEC_REG  (EPIC_EUMBBAR + 0x10200)/* Ext. Int. Sr0 Des */
 #define EPIC_EX_INT0_DES_REG  (EPIC_EUMBBAR + 0x10210)/* Ext. Int. Sr0 Vect*/
 #define EPIC_EX_INT1_VEC_REG  (EPIC_EUMBBAR + 0x10220)/* Ext. Int. Sr1 Des */
 #define EPIC_EX_INT1_DES_REG  (EPIC_EUMBBAR + 0x10230)/* Ext. Int. Sr1 Vect*/
 #define EPIC_EX_INT2_VEC_REG  (EPIC_EUMBBAR + 0x10240)/* Ext. Int. Sr2 Des */
 #define EPIC_EX_INT2_DES_REG  (EPIC_EUMBBAR + 0x10250)/* Ext. Int. Sr2 Vect*/
 #define EPIC_EX_INT3_VEC_REG  (EPIC_EUMBBAR + 0x10260)/* Ext. Int. Sr3 Des */
 #define EPIC_EX_INT3_DES_REG  (EPIC_EUMBBAR + 0x10270)/* Ext. Int. Sr3 Vect*/
 #define EPIC_EX_INT4_VEC_REG  (EPIC_EUMBBAR + 0x10280)/* Ext. Int. Sr4 Des */
 #define EPIC_EX_INT4_DES_REG  (EPIC_EUMBBAR + 0x10290)/* Ext. Int. Sr4 Vect*/
 #define EPIC_SR_INT0_VEC_REG  (EPIC_EUMBBAR + 0x10200)/* Sr. Int. Sr0 Des */
 #define EPIC_SR_INT0_DES_REG  (EPIC_EUMBBAR + 0x10210)/* Sr. Int. Sr0 Vect */
 #define EPIC_SR_INT1_VEC_REG  (EPIC_EUMBBAR + 0x10220)/* Sr. Int. Sr1 Des */
 #define EPIC_SR_INT1_DES_REG  (EPIC_EUMBBAR + 0x10230)/* Sr. Int. Sr1 Vect.*/
 #define EPIC_SR_INT2_VEC_REG  (EPIC_EUMBBAR + 0x10240)/* Sr. Int. Sr2 Des */
 #define EPIC_SR_INT2_DES_REG  (EPIC_EUMBBAR + 0x10250)/* Sr. Int. Sr2 Vect.*/
 #define EPIC_SR_INT3_VEC_REG  (EPIC_EUMBBAR + 0x10260)/* Sr. Int. Sr3 Des */
 #define EPIC_SR_INT3_DES_REG  (EPIC_EUMBBAR + 0x10270)/* Sr. Int. Sr3 Vect.*/
 #define EPIC_SR_INT4_VEC_REG  (EPIC_EUMBBAR + 0x10280)/* Sr. Int. Sr4 Des */
 #define EPIC_SR_INT4_DES_REG  (EPIC_EUMBBAR + 0x10290)/* Sr. Int. Sr4 Vect.*/
 #define EPIC_SR_INT5_VEC_REG  (EPIC_EUMBBAR + 0x102a0)/* Sr. Int. Sr5 Des */
 #define EPIC_SR_INT5_DES_REG  (EPIC_EUMBBAR + 0x102b0)/* Sr. Int. Sr5 Vect.*/
 #define EPIC_SR_INT6_VEC_REG  (EPIC_EUMBBAR + 0x102c0)/* Sr. Int. Sr6 Des */
 #define EPIC_SR_INT6_DES_REG  (EPIC_EUMBBAR + 0x102d0)/* Sr. Int. Sr6 Vect.*/
 #define EPIC_SR_INT7_VEC_REG  (EPIC_EUMBBAR + 0x102e0)/* Sr. Int. Sr7 Des */
 #define EPIC_SR_INT7_DES_REG  (EPIC_EUMBBAR + 0x102f0)/* Sr. Int. Sr7 Vect.*/
 #define EPIC_SR_INT8_VEC_REG  (EPIC_EUMBBAR + 0x10300)/* Sr. Int. Sr8 Des */
 #define EPIC_SR_INT8_DES_REG  (EPIC_EUMBBAR + 0x10310)/* Sr. Int. Sr8 Vect.*/
 #define EPIC_SR_INT9_VEC_REG  (EPIC_EUMBBAR + 0x10320)/* Sr. Int. Sr9 Des */
 #define EPIC_SR_INT9_DES_REG  (EPIC_EUMBBAR + 0x10330)/* Sr. Int. Sr9 Vect.*/
 #define EPIC_SR_INT10_VEC_REG (EPIC_EUMBBAR + 0x10340)/* Sr. Int. Sr10 Des */
 #define EPIC_SR_INT10_DES_REG (EPIC_EUMBBAR + 0x10350)/* Sr. Int. Sr10 Vect*/
 #define EPIC_SR_INT11_VEC_REG (EPIC_EUMBBAR + 0x10360)/* Sr. Int. Sr11 Des */
 #define EPIC_SR_INT11_DES_REG (EPIC_EUMBBAR + 0x10370)/* Sr. Int. Sr11 Vect*/
 #define EPIC_SR_INT12_VEC_REG (EPIC_EUMBBAR + 0x10380)/* Sr. Int. Sr12 Des */
 #define EPIC_SR_INT12_DES_REG (EPIC_EUMBBAR + 0x10390)/* Sr. Int. Sr12 Vect*/
 #define EPIC_SR_INT13_VEC_REG (EPIC_EUMBBAR + 0x103a0)/* Sr. Int. Sr13 Des */
 #define EPIC_SR_INT13_DES_REG (EPIC_EUMBBAR + 0x103b0)/* Sr. Int. Sr13 Vect*/
 #define EPIC_SR_INT14_VEC_REG (EPIC_EUMBBAR + 0x103c0)/* Sr. Int. Sr14 Des */
 #define EPIC_SR_INT14_DES_REG (EPIC_EUMBBAR + 0x103d0)/* Sr. Int. Sr14 Vect*/
 #define EPIC_SR_INT15_VEC_REG (EPIC_EUMBBAR + 0x103e0)/* Sr. Int. Sr15 Des */
 #define EPIC_SR_INT15_DES_REG (EPIC_EUMBBAR + 0x103f0)/* Sr. Int. Sr15 Vect*/
 #define EPIC_I2C_INT_VEC_REG  (EPIC_EUMBBAR + 0x11020)/* I2C Int. Vect Pri.*/
 #define EPIC_I2C_INT_DES_REG  (EPIC_EUMBBAR + 0x11030)/* I2C Int. Dest */
 #define EPIC_DMA0_INT_VEC_REG (EPIC_EUMBBAR + 0x11040)/* DMA0 Int. Vect Pri*/
 #define EPIC_DMA0_INT_DES_REG (EPIC_EUMBBAR + 0x11050)/* DMA0 Int. Dest */
 #define EPIC_DMA1_INT_VEC_REG (EPIC_EUMBBAR + 0x11060)/* DMA1 Int. Vect Pri*/
 #define EPIC_DMA1_INT_DES_REG (EPIC_EUMBBAR + 0x11070)/* DMA1 Int. Dest */
 #define EPIC_MSG_INT_VEC_REG  (EPIC_EUMBBAR + 0x110c0)/* Msg Int. Vect Pri*/
 #define EPIC_MSG_INT_DES_REG  (EPIC_EUMBBAR + 0x110d0)/* Msg Int. Dest  */
 #define EPIC_PROC_CTASK_PRI_REG (EPIC_EUMBBAR + 0x20080)/* Proc. current task*/
 #define EPIC_PROC_INT_ACK_REG (EPIC_EUMBBAR + 0x200a0)/* Int. acknowledge */
 #define EPIC_PROC_EOI_REG (EPIC_EUMBBAR + 0x200b0)/* End of interrupt */
+#define EPIC_VEC_PRI_MASK      0x80000000 /* Mask Interrupt bit in IVPR */
+#define EPIC_VEC_PRI_DFLT_PRI  8          /* Interrupt Priority in IVPR */
 /* Error code */
 #define OK       0
 #define ERROR    -1
 /* function prototypes */
 void epicVendorId( unsigned int *step,
        unsigned int *devId,
        unsigned int *venId
      );
 void epicFeatures( unsigned int *noIRQs,
              unsigned int *noCPUs,
        unsigned int *VerId );
 extern void epicInit( unsigned int IRQType, unsigned int clkRatio);
 ULONG sysEUMBBARRead ( ULONG regNum );
 void sysEUMBBARWrite ( ULONG regNum, ULONG regVal);
 extern void epicTmFrequencySet( unsigned int frq );
 extern unsigned int epicTmFrequencyGet(void);
 extern unsigned int epicTmBaseSet( ULONG srcAddr,
                  unsigned int cnt,
                  unsigned int inhibit );
 extern unsigned int epicTmBaseGet ( ULONG srcAddr, unsigned int *val );
 extern unsigned int epicTmCountGet( ULONG srcAddr, unsigned int *val );
 extern unsigned int epicTmInhibit( unsigned int timer );
 extern unsigned int epicTmEnable( ULONG srcAdr );
 extern void CoreExtIntEnable(void);  /* Enable 603e external interrupts */
 extern void CoreExtIntDisable(void); /* Disable 603e external interrupts */
 extern unsigned char epicIntTaskGet(void);
 extern void epicIntTaskSet( unsigned char val );
 extern unsigned int epicIntAck(void);
 extern void epicSprSet( unsigned int eumbbar, unsigned char );
 extern void epicConfigGet( unsigned int *clkRatio,
                unsigned int *serEnable );
 extern void SrcVecTableInit(void);
 extern unsigned int  epicModeGet(void);
 extern void epicIntEnable(int Vect);
 extern void epicIntDisable(int Vect);
 extern int epicIntSourceConfig(int Vect, int Polarity, int Sense, int Prio);
 extern unsigned int epicIntAck(void);
 extern void epicEOI(void);
 extern int epicCurTaskPrioSet(int Vect);
 struct SrcVecTable
     {
      ULONG srcAddr;
      char  srcName[40];
     };
 #endif   /*  EPIC_H */

cpu/mpc824x/drivers/epic/epic1.c

Diff comments View file @ 7c7a23b

 /**************************************************
  *
  * copyright @ motorola, 1999
  *
  *************************************************/
 #include <mpc824x.h>
 #include <common.h>
 #include "epic.h"
 #define PRINT(format, args...) printf(format , ## args)
 typedef void (*VOIDFUNCPTR)  (void);  /* ptr to function returning void */
 struct SrcVecTable SrcVecTable[MAXVEC] = /* Addr/Vector cross-reference tbl */
     {
     { EPIC_EX_INT0_VEC_REG,  "External Direct/Serial Source 0"},
     { EPIC_EX_INT1_VEC_REG,  "External Direct/Serial Source 1"},
     { EPIC_EX_INT2_VEC_REG,  "External Direct/Serial Source 2"},
     { EPIC_EX_INT3_VEC_REG,  "External Direct/Serial Source 3"},
     { EPIC_EX_INT4_VEC_REG,  "External Direct/Serial Source 4"},
     { EPIC_SR_INT5_VEC_REG,  "External Serial Source 5"},
     { EPIC_SR_INT6_VEC_REG,  "External Serial Source 6"},
     { EPIC_SR_INT7_VEC_REG,  "External Serial Source 7"},
     { EPIC_SR_INT8_VEC_REG,  "External Serial Source 8"},
     { EPIC_SR_INT9_VEC_REG,  "External Serial Source 9"},
     { EPIC_SR_INT10_VEC_REG, "External Serial Source 10"},
     { EPIC_SR_INT11_VEC_REG, "External Serial Source 11"},
     { EPIC_SR_INT12_VEC_REG, "External Serial Source 12"},
     { EPIC_SR_INT13_VEC_REG, "External Serial Source 13"},
     { EPIC_SR_INT14_VEC_REG, "External Serial Source 14"},
     { EPIC_SR_INT15_VEC_REG, "External Serial Source 15"},
     { EPIC_I2C_INT_VEC_REG,  "Internal I2C Source"},
     { EPIC_DMA0_INT_VEC_REG, "Internal DMA0 Source"},
     { EPIC_DMA1_INT_VEC_REG, "Internal DMA1 Source"},
     { EPIC_MSG_INT_VEC_REG,  "Internal Message Source"},
     };
 VOIDFUNCPTR intVecTbl[MAXVEC];    /* Interrupt vector table */
 /****************************************************************************
 *  epicInit - Initialize the EPIC registers
 *
 *  This routine resets the Global Configuration Register, thus it:
 *     -  Disables all interrupts
 *     -  Sets epic registers to reset values
 *     -  Sets the value of the Processor Current Task Priority to the
 *        highest priority (0xF).
 *  epicInit then sets the EPIC operation mode to Mixed Mode (vs. Pass
 *  Through or 8259 compatible mode).
 *
 *  If IRQType (input) is Direct IRQs:
 *     - IRQType is written to the SIE bit of the EPIC Interrupt
 *       Configuration register (ICR).
 *     - clkRatio is ignored.
 *  If IRQType is Serial IRQs:
 *     - both IRQType and clkRatio will be written to the ICR register
 */
 void epicInit
     (
     unsigned int IRQType,      /* Direct or Serial */
     unsigned int clkRatio      /* Clk Ratio for Serial IRQs */
     )
     {
     ULONG tmp;
     tmp = sysEUMBBARRead(EPIC_GLOBAL_REG);
     tmp |= 0xa0000000;                  /* Set the Global Conf. register */
     sysEUMBBARWrite(EPIC_GLOBAL_REG, tmp);
+	/*
+	 * Wait for EPIC to reset - CLH
+	 */
+    while( (sysEUMBBARRead(EPIC_GLOBAL_REG) & 0x80000000) == 1);
     sysEUMBBARWrite(EPIC_GLOBAL_REG, 0x20000000);
     tmp = sysEUMBBARRead(EPIC_INT_CONF_REG);    /* Read interrupt conf. reg */
     if (IRQType == EPIC_DIRECT_IRQ)             /* direct mode */
         sysEUMBBARWrite(EPIC_INT_CONF_REG, tmp & 0xf7ffffff);
     else                                        /* Serial mode */
         {
         tmp = (clkRatio << 28) | 0x08000000;    /* Set clock ratio */
         sysEUMBBARWrite(EPIC_INT_CONF_REG, tmp);
         }
-    while (epicIntAck() != 0xff);       /* Clear all pending interrupts */
+    while (epicIntAck() != 0xff)       /* Clear all pending interrupts */
+		epicEOI();
 }
 /****************************************************************************
  *  epicIntEnable - Enable an interrupt source
  *
  *  This routine clears the mask bit of an external, an internal or
  *  a Timer register to enable the interrupt.
  *
  *  RETURNS:  None
  */
-void epicIntEnable
+void epicIntEnable(int intVec)
-    (
+{
-    int intVec        /* Interrupt Vector Number */
-    )
-    {
     ULONG tmp;
     ULONG srAddr;
     srAddr = SrcVecTable[intVec].srcAddr;  /* Retrieve src Vec/Prio register */
     tmp = sysEUMBBARRead(srAddr);
-    tmp &= 0x7fffffff;             /* Clear the mask bit */
+    tmp &= ~EPIC_VEC_PRI_MASK;             /* Clear the mask bit */
+    tmp |= (EPIC_VEC_PRI_DFLT_PRI << 16);   /* Set priority to Default - CLH */
+    tmp |= intVec;				           /* Set Vector number */
     sysEUMBBARWrite(srAddr, tmp);
     return;
     }
 /****************************************************************************
  *  epicIntDisable - Disable an interrupt source
  *
  *  This routine sets the mask bit of an external, an internal or
  *  a Timer register to disable the interrupt.
  *
  *  RETURNS:  OK or ERROR
  *
  */
 void epicIntDisable
     (
     int intVec        /* Interrupt vector number */
     )
     {
     ULONG tmp, srAddr;
     srAddr = SrcVecTable[intVec].srcAddr;
     tmp = sysEUMBBARRead(srAddr);
     tmp |= 0x80000000;                      /* Set the mask bit */
     sysEUMBBARWrite(srAddr, tmp);
     return;
     }
 /****************************************************************************
  * epicIntSourceConfig - Set properties of an interrupt source
  *
  * This function sets interrupt properites (Polarity, Sense, Interrupt
  * Prority, and Interrupt Vector) of an Interrupt Source.  The properties
  * can be set when the current source is not in-request or in-service,
  * which is determined by the Activity bit.  This routine return ERROR
  * if the the Activity bit is 1 (in-request or in-service).
  *
  * This function assumes that the Source Vector/Priority register (input)
  * is a valid address.
  *
  * RETURNS:  OK or ERROR
  */
 int epicIntSourceConfig
     (
     int   Vect,                         /* interrupt source vector number */
     int   Polarity,                     /* interrupt source polarity */
     int   Sense,                        /* interrupt source Sense */
     int   Prio                          /* interrupt source priority */
     )
     {
     ULONG tmp, newVal;
     ULONG actBit, srAddr;
     srAddr = SrcVecTable[Vect].srcAddr;
     tmp = sysEUMBBARRead(srAddr);
     actBit = (tmp & 40000000) >> 30;    /* retrieve activity bit - bit 30 */
     if (actBit == 1)
         return ERROR;
     tmp &= 0xff30ff00;     /* Erase previously set P,S,Prio,Vector bits */
     newVal = (Polarity << 23) | (Sense << 22) | (Prio << 16) | Vect;
     sysEUMBBARWrite(srAddr, tmp | newVal );
     return (OK);
     }
 /****************************************************************************
  * epicIntAck - acknowledge an interrupt
  *
  * This function reads the Interrupt acknowldge register and return
  * the vector number of the highest pending interrupt.
  *
  * RETURNS: Interrupt Vector number.
  */
 unsigned int epicIntAck(void)
 {
     return(sysEUMBBARRead( EPIC_PROC_INT_ACK_REG ));
 }
 /****************************************************************************
  * epicEOI - signal an end of interrupt
  *
  * This function writes 0x0 to the EOI register to signal end of interrupt.
  * It is usually called after an interrupt routine is served.
  *
  * RETURNS: None
  */
 void epicEOI(void)
     {
     sysEUMBBARWrite(EPIC_PROC_EOI_REG, 0x0);
     }
 /****************************************************************************
  *  epicCurTaskPrioSet - sets the priority of the Processor Current Task
  *
  *  This function should be called after epicInit() to lower the priority
  *  of the processor current task.
  *
  *  RETURNS:  OK or ERROR
  */
 int epicCurTaskPrioSet
     (
     int prioNum                 /* New priority value */
     )
     {
     if ( (prioNum < 0) || (prioNum > 0xF))
         return ERROR;
     sysEUMBBARWrite(EPIC_PROC_CTASK_PRI_REG, prioNum);
     return OK;
     }
 /************************************************************************
  * function: epicIntTaskGet
  *
  * description: Get value of processor current interrupt task priority register
  *
  * note:
  ***********************************************************************/
 unsigned char epicIntTaskGet()
 {
   /* get the interrupt task priority register */
     ULONG reg;
     unsigned char rec;
     reg = sysEUMBBARRead( EPIC_PROC_CTASK_PRI_REG );
     rec = ( reg & 0x0F );
     return rec;
 }
 /**************************************************************
  * function: epicISR
  *
  * description: EPIC service routine called by the core exception
  *              at 0x500
  *
  * note:
  **************************************************************/
 unsigned int epicISR(void)
 {
    return 0;
 }
 /************************************************************
  * function: epicModeGet
  *
  * description: query EPIC mode, return 0 if pass through mode
  *                               return 1 if mixed mode
  *
  * note:
  *************************************************************/
 unsigned int epicModeGet(void)
 {
     ULONG val;
     val = sysEUMBBARRead( EPIC_GLOBAL_REG );
     return (( val & 0x20000000 ) >> 29);
 }
 /*********************************************
  * function: epicConfigGet
  *
  * description: Get the EPIC interrupt Configuration
  *              return 0 if not error, otherwise return 1
  *
  * note:
  ********************************************/
 void epicConfigGet( unsigned int *clkRatio, unsigned int *serEnable)
 {
     ULONG val;
     val = sysEUMBBARRead( EPIC_INT_CONF_REG );
     *clkRatio = ( val & 0x70000000 ) >> 28;
     *serEnable = ( val & 0x8000000 ) >> 27;
 }
 /*******************************************************************
  *  sysEUMBBARRead - Read a 32-bit EUMBBAR register
  *
  *  This routine reads the content of a register in the Embedded
  *  Utilities Memory Block, and swaps to big endian before returning
  *  the value.
  *
  *  RETURNS:  The content of the specified EUMBBAR register.
  */
 ULONG sysEUMBBARRead
     (
     ULONG regNum
     )
     {
     ULONG temp;
     temp = *(ULONG *) (CFG_EUMB_ADDR + regNum);
     return ( LONGSWAP(temp));
     }
 /*******************************************************************
  *  sysEUMBBARWrite - Write a 32-bit EUMBBAR register
  *
  *  This routine swaps the value to little endian then writes it to
  *  a register in the Embedded Utilities Memory Block address space.
  *
  *  RETURNS: N/A
  */
 void sysEUMBBARWrite
     (
     ULONG regNum,               /* EUMBBAR register address */
     ULONG regVal                /* Value to be written */
     )
     {
     *(ULONG *) (CFG_EUMB_ADDR + regNum) = LONGSWAP(regVal);
     return ;
     }
 /********************************************************
  * function: epicVendorId
  *
  * description: return the EPIC Vendor Identification
  *              register:
  *
  *              siliccon version, device id, and vendor id
  *
  * note:
  ********************************************************/
 void epicVendorId
    (
     unsigned int *step,
     unsigned int *devId,
     unsigned int *venId
    )
    {
     ULONG val;
     val = sysEUMBBARRead( EPIC_VENDOR_ID_REG );
     *step  = ( val & 0x00FF0000 ) >> 16;
     *devId = ( val & 0x0000FF00 ) >> 8;
     *venId = ( val & 0x000000FF );
     }
 /**************************************************
  * function: epicFeatures
  *
  * description: return the number of IRQ supported,
  *              number of CPU, and the version of the
  *              OpenEPIC
  *
  * note:
  *************************************************/
 void epicFeatures
     (
     unsigned int *noIRQs,
     unsigned int *noCPUs,
     unsigned int *verId
     )
     {
     ULONG val;
     val = sysEUMBBARRead( EPIC_FEATURES_REG );
     *noIRQs  = ( val & 0x07FF0000 ) >> 16;
     *noCPUs  = ( val & 0x00001F00 ) >> 8;
     *verId   = ( val & 0x000000FF );
 }
 /*********************************************************
  * function: epciTmFrequncySet
  *
  * description: Set the timer frequency reporting register
  ********************************************************/
 void epicTmFrequencySet( unsigned int frq )
 {
     sysEUMBBARWrite(EPIC_TM_FREQ_REG, frq);
 }
 /*******************************************************
  * function: epicTmFrequncyGet
  *
  * description: Get the current value of the Timer Frequency
  * Reporting register
  *
  ******************************************************/
 unsigned int epicTmFrequencyGet(void)
 {
     return( sysEUMBBARRead(EPIC_TM_FREQ_REG)) ;
 }
 /****************************************************
  * function: epicTmBaseSet
  *
  * description: Set the #n global timer base count register
  *              return 0 if no error, otherwise return 1.
  *
  * note:
  ****************************************************/
 unsigned int epicTmBaseSet
     (
     ULONG srcAddr,         /* Address of the Timer Base register */
     unsigned int cnt,    /* Base count */
     unsigned int inhibit   /* 1 - count inhibit */
     )
 {
     unsigned int val = 0x80000000;
     /* First inhibit counting the timer */
     sysEUMBBARWrite(srcAddr, val) ;
     /* set the new value */
     val = (cnt & 0x7fffffff) | ((inhibit & 0x1) << 31);
     sysEUMBBARWrite(srcAddr, val) ;
     return 0;
 }
 /***********************************************************************
  * function: epicTmBaseGet
  *
  * description: Get the current value of the global timer base count register
  *              return 0 if no error, otherwise return 1.
  *
  * note:
  ***********************************************************************/
 unsigned int epicTmBaseGet( ULONG srcAddr, unsigned int *val )
 {
     *val = sysEUMBBARRead( srcAddr );
     *val = *val & 0x7fffffff;
     return 0;
 }
 /***********************************************************
  * function: epicTmCountGet
  *
  * description: Get the value of a given global timer
  *              current count register
  *              return 0 if no error, otherwise return 1
  * note:
  **********************************************************/
 unsigned int epicTmCountGet( ULONG srcAddr, unsigned int *val )
 {
     *val = sysEUMBBARRead( srcAddr );
     *val = *val & 0x7fffffff;
     return 0;
 }
 /***********************************************************
  * function: epicTmInhibit
  *
  * description: Stop counting of a given global timer
  *              return 0 if no error, otherwise return 1
  *
  * note:
  ***********************************************************/
 unsigned int epicTmInhibit( unsigned int srcAddr )
 {
     ULONG val;
     val = sysEUMBBARRead( srcAddr );
     val |= 0x80000000;
     sysEUMBBARWrite( srcAddr, val );
     return 0;
 }
 /******************************************************************
  * function: epicTmEnable
  *
  * description: Enable counting of a given global timer
  *              return 0 if no error, otherwise return 1
  *
  * note:
  *****************************************************************/
 unsigned int epicTmEnable( ULONG srcAddr )
 {
     ULONG val;
     val = sysEUMBBARRead( srcAddr );
     val &= 0x7fffffff;
     sysEUMBBARWrite( srcAddr, val );
     return 0;
 }
 void epicSourcePrint(int Vect)
     {
     ULONG srcVal;
     srcVal = sysEUMBBARRead(SrcVecTable[Vect].srcAddr);
     PRINT("%s\n", SrcVecTable[Vect].srcName);
     PRINT("Address   = 0x%lx\n", SrcVecTable[Vect].srcAddr);
     PRINT("Vector    = %ld\n", (srcVal & 0x000000FF) );
     PRINT("Mask      = %ld\n", srcVal >> 31);
     PRINT("Activitiy = %ld\n", (srcVal & 40000000) >> 30);
     PRINT("Polarity  = %ld\n", (srcVal & 0x00800000) >> 23);
     PRINT("Sense     = %ld\n", (srcVal & 0x00400000) >> 22);

cpu/mpc824x/interrupts.c

Diff comments View file @ 7c7a23b

 /*
  * (C) Copyright 2000-2002
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  * Rob Taylor, Flying Pig Systems. robt@flyingpig.com
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 #include <common.h>
 #include <mpc824x.h>
 #include <asm/processor.h>
 #include <asm/pci_io.h>
 #include <commproc.h>
 #include "drivers/epic.h"
 /****************************************************************************/
 unsigned decrementer_count;		/* count val for 1e6/HZ microseconds */
 static __inline__ unsigned long get_msr (void)
 {
 	unsigned long msr;
 	asm volatile ("mfmsr %0":"=r" (msr):);
 	return msr;
 }
 static __inline__ void set_msr (unsigned long msr)
 {
 	asm volatile ("mtmsr %0"::"r" (msr));
 }
 static __inline__ unsigned long get_dec (void)
 {
 	unsigned long val;
 	asm volatile ("mfdec %0":"=r" (val):);
 	return val;
 }
 static __inline__ void set_dec (unsigned long val)
 {
 	asm volatile ("mtdec %0"::"r" (val));
 }
 void enable_interrupts (void)
 {
 	set_msr (get_msr () | MSR_EE);
 }
 /* returns flag if MSR_EE was set before */
 int disable_interrupts (void)
 {
 	ulong msr = get_msr ();
 	set_msr (msr & ~MSR_EE);
 	return ((msr & MSR_EE) != 0);
 }
 /****************************************************************************/
 int interrupt_init (void)
 {
 	decrementer_count = (get_bus_freq (0) / 4) / CFG_HZ;
         /*
          * It's all broken at the moment and I currently don't need
          * interrupts. If you want to fix it, have a look at the epic
          * drivers in dink32 v12. They do everthing and Motorola said
          * I could use the dink source in this project as long as
          * copyright notices remain intact.
 	 */
 	epicInit (EPIC_DIRECT_IRQ, 0);
+	/* EPIC won't generate INT unless Current Task Pri < 15 */
+	epicCurTaskPrioSet(0);
 	set_dec (decrementer_count);
 	set_msr (get_msr () | MSR_EE);
 	return (0);
 }
 /****************************************************************************/
 /*
  * Handle external interrupts
  */
 void external_interrupt (struct pt_regs *regs)
 {
 	register unsigned long temp;
 	pci_readl (CFG_EUMB_ADDR + EPIC_PROC_INT_ACK_REG, temp);
 	sync ();					/* i'm not convinced this is needed, but dink source has it */
 	temp &= 0xff;				/*get vector */
 	/*TODO: handle them -... */
 	epicEOI ();
 }
 /****************************************************************************/
 /*
  * blank int handlers.
  */
 void
 irq_install_handler (int vec, interrupt_handler_t * handler, void *arg)
 {
 }
 void irq_free_handler (int vec)
 {
 }
 /*TODO: some handlers for winbond and 87308 interrupts
  and what about generic pci inteerupts?
  vga?
  */
 volatile ulong timestamp = 0;
 void timer_interrupt (struct pt_regs *regs)
 {
 	/* Restore Decrementer Count */
 	set_dec (decrementer_count);
 	timestamp++;
 #if defined(CONFIG_WATCHDOG)
 	if ((timestamp % (CFG_HZ / 2)) == 0) {
 #if defined(CONFIG_OXC)
 		{
 			extern void oxc_wdt_reset (void);
 			oxc_wdt_reset ();
 		}
 #endif
 	}
 #endif							/* CONFIG_WATCHDOG */
 #if defined(CONFIG_SHOW_ACTIVITY) && defined(CONFIG_OXC)
 	if ((timestamp % (CFG_HZ / 10)) == 0) {
 		{
 			extern void oxc_toggle_activeled (void);
 			oxc_toggle_activeled ();
 		}
 	}
 #endif
 }
 void reset_timer (void)
 {
 	timestamp = 0;
 }
 ulong get_timer (ulong base)
 {
 	return (timestamp - base);
 }
 void set_timer (ulong t)
 {
 	timestamp = t;
 }

cpu/mpc824x/start.S

Diff comments View file @ 7c7a23b

 /*
  *  Copyright (C) 1998	Dan Malek <dmalek@jlc.net>
  *  Copyright (C) 1999	Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
  *  Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 /* U-Boot - Startup Code for PowerPC based Embedded Boards
  *
  *
  * The processor starts at 0x00000100 and the code is executed
  * from flash. The code is organized to be at an other address
  * in memory, but as long we don't jump around before relocating.
  * board_init lies at a quite high address and when the cpu has
  * jumped there, everything is ok.
  * This works because the cpu gives the FLASH (CS0) the whole
  * address space at startup, and board_init lies as a echo of
  * the flash somewhere up there in the memorymap.
  *
  * board_init will change CS0 to be positioned at the correct
  * address and (s)dram will be positioned at address 0
  */
 #include <config.h>
 #include <mpc824x.h>
 #include <version.h>
 #define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
 #include <ppc_asm.tmpl>
 #include <ppc_defs.h>
 #include <asm/cache.h>
 #include <asm/mmu.h>
 #ifndef CONFIG_IDENT_STRING
 #define CONFIG_IDENT_STRING ""
 #endif
 /* We don't want the MMU yet.
 */
 #undef	MSR_KERNEL
 /* FP, Machine Check and Recoverable Interr. */
 #define MSR_KERNEL ( MSR_FP | MSR_ME | MSR_RI )
 /*
  * Set up GOT: Global Offset Table
  *
  * Use r14 to access the GOT
  */
 	START_GOT
 	GOT_ENTRY(_GOT2_TABLE_)
 	GOT_ENTRY(_FIXUP_TABLE_)
 	GOT_ENTRY(_start)
 	GOT_ENTRY(_start_of_vectors)
 	GOT_ENTRY(_end_of_vectors)
 	GOT_ENTRY(transfer_to_handler)
 	GOT_ENTRY(_end)
 	GOT_ENTRY(.bss)
 #if defined(CONFIG_FADS)
 	GOT_ENTRY(environment)
 #endif
 	END_GOT
 /*
  * r3 - 1st arg to board_init(): IMMP pointer
  * r4 - 2nd arg to board_init(): boot flag
  */
 	.text
 	.long	0x27051956		/* U-Boot Magic Number			*/
 	.globl	version_string
 version_string:
 	.ascii U_BOOT_VERSION
 	.ascii " (", __DATE__, " - ", __TIME__, ")"
 	.ascii CONFIG_IDENT_STRING, "\0"
 	. = EXC_OFF_SYS_RESET
 	.globl	_start
 _start:
 	li	r21, BOOTFLAG_COLD	/* Normal Power-On: Boot from FLASH	*/
 	b	boot_cold
 	. = EXC_OFF_SYS_RESET + 0x10
 	.globl	_start_warm
 _start_warm:
 	li	r21, BOOTFLAG_WARM	/* Software reboot			*/
 	b	boot_warm
 boot_cold:
 boot_warm:
 	/* Initialize machine status; enable machine check interrupt		*/
 	/*----------------------------------------------------------------------*/
 	li	r3, MSR_KERNEL		/* Set FP, ME, RI flags */
 	mtmsr	r3
 	mtspr	SRR1, r3		/* Make SRR1 match MSR */
 	addis	r0,0,0x0000		/* lets make sure that r0 is really 0 */
 	mtspr   HID0, r0		/* disable I and D caches */
 	mfspr	r3, ICR			/* clear Interrupt Cause Register */
 	mfmsr	r3			/* turn off address translation */
 	addis	r4,0,0xffff
 	ori	r4,r4,0xffcf
 	and	r3,r3,r4
 	mtmsr	r3
 	isync
 	sync				/* the MMU should be off... */
 in_flash:
 #if defined(CONFIG_BMW)
 	bl early_init_f /* Must be ASM: no stack yet! */
 #endif
 	/*
 	 * Setup BATs - cannot be done in C since we don't have a stack yet
 	 */
 	bl	setup_bats
 	/* Enable MMU.
 	 */
 	mfmsr	r3
 	ori	r3, r3, (MSR_IR | MSR_DR)
 	mtmsr	r3
 #if !defined(CONFIG_BMW)
 	/* Enable and invalidate data cache.
 	 */
 	mfspr	r3, HID0
 	mr	r2, r3
 	ori	r3, r3, HID0_DCE | HID0_DCI
 	ori	r2, r2, HID0_DCE
 	sync
 	mtspr	HID0, r3
 	mtspr	HID0, r2
 	sync
 	/* Allocate Initial RAM in data cache.
 	 */
 	lis	r3, CFG_INIT_RAM_ADDR@h
 	ori	r3, r3, CFG_INIT_RAM_ADDR@l
 	li	r2, 128
 	mtctr	r2
 1:
 	dcbz	r0, r3
 	addi	r3, r3, 32
 	bdnz	1b
 	/* Lock way0 in data cache.
 	 */
 	mfspr	r3, 1011
 	lis	r2, 0xffff
 	ori	r2, r2, 0xff1f
 	and	r3, r3, r2
 	ori	r3, r3, 0x0080
 	sync
 	mtspr	1011, r3
 #endif /* !CONFIG_BMW */
 	/*
 	 * Thisk the stack pointer *somewhere* sensible. Doesnt
 	 * matter much where as we'll move it when we relocate
 	 */
 	lis	r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@h
 	ori	r1, r1, (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET)@l
 	li	r0, 0			/* Make room for stack frame header and	*/
 	stwu	r0, -4(r1)		/* clear final stack frame so that	*/
 	stwu	r0, -4(r1)		/* stack backtraces terminate cleanly	*/
 	/* let the C-code set up the rest					*/
 	/*									*/
 	/* Be careful to keep code relocatable !				*/
 	/*----------------------------------------------------------------------*/
 	GET_GOT			/* initialize GOT access			*/
 	/* r3: IMMR */
 	bl	cpu_init_f	/* run low-level CPU init code     (from Flash)	*/
 	mr	r3, r21
 	/* r3: BOOTFLAG */
 	bl	board_init_f	/* run 1st part of board init code (from Flash) */
 	.globl	_start_of_vectors
 _start_of_vectors:
 /* Machine check */
 	STD_EXCEPTION(EXC_OFF_MACH_CHCK, MachineCheck, MachineCheckException)
 /* Data Storage exception.  "Never" generated on the 860. */
 	STD_EXCEPTION(EXC_OFF_DATA_STOR, DataStorage, UnknownException)
 /* Instruction Storage exception.  "Never" generated on the 860. */
 	STD_EXCEPTION(EXC_OFF_INS_STOR, InstStorage, UnknownException)
 /* External Interrupt exception. */
 	STD_EXCEPTION(EXC_OFF_EXTERNAL, ExtInterrupt, external_interrupt)
 /* Alignment exception. */
 	. = EXC_OFF_ALIGN
 Alignment:
 	EXCEPTION_PROLOG
 	mfspr	r4,DAR
 	stw	r4,_DAR(r21)
 	mfspr	r5,DSISR
 	stw	r5,_DSISR(r21)
 	addi	r3,r1,STACK_FRAME_OVERHEAD
 	li	r20,MSR_KERNEL
 	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
 	lwz	r6,GOT(transfer_to_handler)
 	mtlr	r6
 	blrl
 .L_Alignment:
 	.long	AlignmentException - _start + EXC_OFF_SYS_RESET
 	.long	int_return - _start + EXC_OFF_SYS_RESET
 /* Program check exception */
 	. = EXC_OFF_PROGRAM
 ProgramCheck:
 	EXCEPTION_PROLOG
 	addi	r3,r1,STACK_FRAME_OVERHEAD
 	li	r20,MSR_KERNEL
 	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
 	lwz	r6,GOT(transfer_to_handler)
 	mtlr	r6
 	blrl
 .L_ProgramCheck:
 	.long	ProgramCheckException - _start + EXC_OFF_SYS_RESET
 	.long	int_return - _start + EXC_OFF_SYS_RESET
 	/* No FPU on MPC8xx. This exception is not supposed to happen.
 	*/
 	STD_EXCEPTION(EXC_OFF_FPUNAVAIL, FPUnavailable, UnknownException)
 	/* I guess we could implement decrementer, and may have
 	 * to someday for timekeeping.
 	 */
 	STD_EXCEPTION(EXC_OFF_DECR, Decrementer, timer_interrupt)
 	STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
 	STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
 	. = 0xc00
 /*
  * r0 - SYSCALL number
  * r3-... arguments
  */
 SystemCall:
 	addis	r11,r0,0		/* get functions table addr */
 	ori	r11,r11,0		/* Note: this code is patched in trap_init */
 	addis	r12,r0,0		/* get number of functions */
 	ori	r12,r12,0
 	cmplw	0, r0, r12
 	bge	1f
 	rlwinm	r0,r0,2,0,31		/* fn_addr = fn_tbl[r0] */
 	add	r11,r11,r0
 	lwz	r11,0(r11)
-	li	r12,0xd00-4*3		/* save LR & SRRx */
+	li	r20,0xd00-4		/* Get stack pointer */
+	lwz	r12,0(r20)
+	subi	r12,r12,12		/* Adjust stack pointer */
+	li	r0,0xc00+_end_back-SystemCall
+	cmplw	0, r0, r12		/* Check stack overflow */
+	bgt	1f
+	stw	r12,0(r20)
 	mflr	r0
 	stw	r0,0(r12)
 	mfspr	r0,SRR0
 	stw	r0,4(r12)
 	mfspr	r0,SRR1
 	stw	r0,8(r12)
 	li	r12,0xc00+_back-SystemCall
 	mtlr	r12
 	mtspr	SRR0,r11
 1:	SYNC
 	rfi
 _back:
 	mfmsr	r11			/* Disable interrupts */
 	li	r12,0
 	ori	r12,r12,MSR_EE
 	andc	r11,r11,r12
 	SYNC				/* Some chip revs need this... */
 	mtmsr	r11
 	SYNC
-	li	r12,0xd00-4*3		/* restore regs */
+	li	r12,0xd00-4		/* restore regs */
+	lwz	r12,0(r12)
 	lwz	r11,0(r12)
 	mtlr	r11
 	lwz	r11,4(r12)
 	mtspr	SRR0,r11
 	lwz	r11,8(r12)
 	mtspr	SRR1,r11
+	addi	r12,r12,12		/* Adjust stack pointer */
+	li	r20,0xd00-4
+	stw	r12,0(r20)
 	SYNC
 	rfi
+_end_back:
 	STD_EXCEPTION(EXC_OFF_TRACE, SingleStep, UnknownException)
 	STD_EXCEPTION(EXC_OFF_FPUNASSIST, Trap_0e, UnknownException)
 	STD_EXCEPTION(EXC_OFF_PMI, Trap_0f, UnknownException)
 	STD_EXCEPTION(EXC_OFF_ITME, InstructionTransMiss, UnknownException)
 	STD_EXCEPTION(EXC_OFF_DLTME, DataLoadTransMiss, UnknownException)
 	STD_EXCEPTION(EXC_OFF_DSTME, DataStoreTransMiss, UnknownException)
 	STD_EXCEPTION(EXC_OFF_IABE, InstructionBreakpoint, UnknownException)
 	STD_EXCEPTION(EXC_OFF_SMIE, SysManageInt, UnknownException)
 	STD_EXCEPTION(0x1500, Reserved5, UnknownException)
 	STD_EXCEPTION(0x1600, Reserved6, UnknownException)
 	STD_EXCEPTION(0x1700, Reserved7, UnknownException)
 	STD_EXCEPTION(0x1800, Reserved8, UnknownException)
 	STD_EXCEPTION(0x1900, Reserved9, UnknownException)
 	STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
 	STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
 	STD_EXCEPTION(0x1c00, ReservedC, UnknownException)
 	STD_EXCEPTION(0x1d00, ReservedD, UnknownException)
 	STD_EXCEPTION(0x1e00, ReservedE, UnknownException)
 	STD_EXCEPTION(0x1f00, ReservedF, UnknownException)
 	STD_EXCEPTION(EXC_OFF_RMTE, RunModeTrace, UnknownException)
 	.globl	_end_of_vectors
 _end_of_vectors:
 	. = 0x3000
 /*
  * This code finishes saving the registers to the exception frame
  * and jumps to the appropriate handler for the exception.
  * Register r21 is pointer into trap frame, r1 has new stack pointer.
  */
 	.globl	transfer_to_handler
 transfer_to_handler:
 	stw	r22,_NIP(r21)
 	lis	r22,MSR_POW@h
 	andc	r23,r23,r22
 	stw	r23,_MSR(r21)
 	SAVE_GPR(7, r21)
 	SAVE_4GPRS(8, r21)
 	SAVE_8GPRS(12, r21)
 	SAVE_8GPRS(24, r21)
 #if 0
 	andi.	r23,r23,MSR_PR
 	mfspr	r23,SPRG3		/* if from user, fix up tss.regs */
 	beq	2f
 	addi	r24,r1,STACK_FRAME_OVERHEAD
 	stw	r24,PT_REGS(r23)
 2:	addi	r2,r23,-TSS		/* set r2 to current */
 	tovirt(r2,r2,r23)
 #endif
 	mflr	r23
 	andi.	r24,r23,0x3f00		/* get vector offset */
 	stw	r24,TRAP(r21)
 	li	r22,0
 	stw	r22,RESULT(r21)
 	mtspr	SPRG2,r22		/* r1 is now kernel sp */
 #if 0
 	addi	r24,r2,TASK_STRUCT_SIZE /* check for kernel stack overflow */
 	cmplw	0,r1,r2
 	cmplw	1,r1,r24
 	crand	1,1,4
 	bgt	stack_ovf		/* if r2 < r1 < r2+TASK_STRUCT_SIZE */
 #endif
 	lwz	r24,0(r23)		/* virtual address of handler */
 	lwz	r23,4(r23)		/* where to go when done */
 	mtspr	SRR0,r24
 	ori	r20,r20,0x30		/* enable IR, DR */
 	mtspr	SRR1,r20
 	mtlr	r23
 	SYNC
 	rfi				/* jump to handler, enable MMU */
 int_return:
 	mfmsr	r28		/* Disable interrupts */
 	li	r4,0
 	ori	r4,r4,MSR_EE
 	andc	r28,r28,r4
 	SYNC			/* Some chip revs need this... */
 	mtmsr	r28
 	SYNC
 	lwz	r2,_CTR(r1)
 	lwz	r0,_LINK(r1)
 	mtctr	r2
 	mtlr	r0
 	lwz	r2,_XER(r1)
 	lwz	r0,_CCR(r1)
 	mtspr	XER,r2
 	mtcrf	0xFF,r0
 	REST_10GPRS(3, r1)
 	REST_10GPRS(13, r1)
 	REST_8GPRS(23, r1)
 	REST_GPR(31, r1)
 	lwz	r2,_NIP(r1)	/* Restore environment */
 	lwz	r0,_MSR(r1)
 	mtspr	SRR0,r2
 	mtspr	SRR1,r0
 	lwz	r0,GPR0(r1)
 	lwz	r2,GPR2(r1)
 	lwz	r1,GPR1(r1)
 	SYNC
 	rfi
 /* Cache functions.
 */
 	.globl	icache_enable
 icache_enable:
 	mfspr	r5,HID0		/* turn on the I cache. */
 	ori	r5,r5,0x8800	/* Instruction cache only! */
 	addis	r6,0,0xFFFF
 	ori	r6,r6,0xF7FF
 	and	r6,r5,r6	/* clear the invalidate bit */
 	sync
 	mtspr	HID0,r5
 	mtspr	HID0,r6
 	isync
 	sync
 	blr
 	.globl	icache_disable
 icache_disable:
 	mfspr	r5,HID0
 	addis	r6,0,0xFFFF
 	ori	r6,r6,0x7FFF
 	and	r5,r5,r6
 	sync
 	mtspr	HID0,r5
 	isync
 	sync
 	blr
 	.globl	icache_status
 icache_status:
 	mfspr	r3, HID0
 	srwi	r3, r3, 15	/* >>15 & 1=> select bit 16 */
 	andi.	r3, r3, 1
 	blr
 	.globl	dcache_enable
 dcache_enable:
 	mfspr	r5,HID0		/* turn on the D cache. */
 	ori	r5,r5,0x4400	/* Data cache only! */
 	mfspr	r4, PVR		/* read PVR */
 	srawi	r3, r4, 16	/* shift off the least 16 bits */
 	cmpi	0, 0, r3, 0xC	/* Check for Max pvr */
 	bne	NotMax
 	ori	r5,r5,0x0040	/* setting the DCFA bit, for Max rev 1 errata */
 NotMax:
 	addis	r6,0,0xFFFF
 	ori	r6,r6,0xFBFF
 	and	r6,r5,r6	/* clear the invalidate bit */
 	sync
 	mtspr	HID0,r5
 	mtspr	HID0,r6
 	isync
 	sync
 	blr
 	.globl	dcache_disable
 dcache_disable:
 	mfspr	r5,HID0
 	addis	r6,0,0xFFFF
 	ori	r6,r6,0xBFFF
 	and	r5,r5,r6
 	sync
 	mtspr	HID0,r5
 	isync
 	sync
 	blr
 	.globl	dcache_status
 dcache_status:
 	mfspr	r3, HID0
 	srwi	r3, r3, 14	/* >>14 & 1=> select bit 17 */
 	andi.	r3, r3, 1
 	blr
 	.globl	dc_read
 dc_read:
 /*TODO : who uses this, what should it do?
 */
 	blr
 	.globl get_pvr
 get_pvr:
 	mfspr	r3, PVR
 	blr
 /*------------------------------------------------------------------------------*/
 /*
  * void relocate_code (addr_sp, gd, addr_moni)
  *
  * This "function" does not return, instead it continues in RAM
  * after relocating the monitor code.
  *
  * r3 = dest
  * r4 = src
  * r5 = length in bytes
  * r6 = cachelinesize
  */
 	.globl	relocate_code
 relocate_code:
 	mr	r1,  r3		/* Set new stack pointer		*/
 	mr	r9,  r4		/* Save copy of Global Data pointer	*/
 	mr	r10, r5		/* Save copy of Destination Address	*/
 	mr	r3,  r5				/* Destination Address	*/
 #ifdef DEBUG
 	lis	r4, CFG_SDRAM_BASE@h		/* Source      Address	*/
 	ori	r4, r4, CFG_SDRAM_BASE@l
 #else
 	lis	r4, CFG_MONITOR_BASE@h		/* Source      Address	*/
 	ori	r4, r4, CFG_MONITOR_BASE@l
 #endif
 	lis	r5, CFG_MONITOR_LEN@h		/* Length in Bytes	*/
 	ori	r5, r5, CFG_MONITOR_LEN@l
 	li	r6, CFG_CACHELINE_SIZE		/* Cache Line Size	*/
 	/*
 	 * Fix GOT pointer:
 	 *
 	 * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
 	 *
 	 * Offset:
 	 */
 	sub	r15, r10, r4
 	/* First our own GOT */
 	add	r14, r14, r15
 	/* the the one used by the C code */
 	add	r30, r30, r15
 	/*
 	 * Now relocate code
 	 */
 	cmplw	cr1,r3,r4
 	addi	r0,r5,3
 	srwi.	r0,r0,2
 	beq	cr1,4f		/* In place copy is not necessary	*/
 	beq	7f		/* Protect against 0 count		*/
 	mtctr	r0
 	bge	cr1,2f
 	la	r8,-4(r4)
 	la	r7,-4(r3)
 1:	lwzu	r0,4(r8)
 	stwu	r0,4(r7)
 	bdnz	1b
 	b	4f
 2:	slwi	r0,r0,2
 	add	r8,r4,r0
 	add	r7,r3,r0
 3:	lwzu	r0,-4(r8)
 	stwu	r0,-4(r7)
 	bdnz	3b
 /*
  * Now flush the cache: note that we must start from a cache aligned
  * address. Otherwise we might miss one cache line.
  */
 4:	cmpwi	r6,0
 	add	r5,r3,r5
 	beq	7f		/* Always flush prefetch queue in any case */
 	subi	r0,r6,1
 	andc	r3,r3,r0
 	mr	r4,r3
 5:	dcbst	0,r4
 	add	r4,r4,r6
 	cmplw	r4,r5
 	blt	5b
 	sync			/* Wait for all dcbst to complete on bus */
 	mr	r4,r3
 6:	icbi	0,r4
 	add	r4,r4,r6
 	cmplw	r4,r5
 	blt	6b
 7:	sync			/* Wait for all icbi to complete on bus	*/
 	isync
 /*
  * We are done. Do not return, instead branch to second part of board
  * initialization, now running from RAM.
  */
 	addi	r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
 	mtlr	r0
 	blr
 in_ram:
 	/*
 	 * Relocation Function, r14 point to got2+0x8000
 	 *
 	 * Adjust got2 pointers, no need to check for 0, this code
 	 * already puts a few entries in the table.
 	 */
 	li	r0,__got2_entries@sectoff@l
 	la	r3,GOT(_GOT2_TABLE_)
 	lwz	r11,GOT(_GOT2_TABLE_)
 	mtctr	r0
 	sub	r11,r3,r11
 	addi	r3,r3,-4
 1:	lwzu	r0,4(r3)
 	add	r0,r0,r11
 	stw	r0,0(r3)
 	bdnz	1b
 	/*
 	 * Now adjust the fixups and the pointers to the fixups
 	 * in case we need to move ourselves again.
 	 */
 2:	li	r0,__fixup_entries@sectoff@l
 	lwz	r3,GOT(_FIXUP_TABLE_)
 	cmpwi	r0,0
 	mtctr	r0
 	addi	r3,r3,-4
 	beq	4f
 3:	lwzu	r4,4(r3)
 	lwzux	r0,r4,r11
 	add	r0,r0,r11
 	stw	r10,0(r3)
 	stw	r0,0(r4)
 	bdnz	3b
 4:
 clear_bss:
 	/*
 	 * Now clear BSS segment
 	 */
 	lwz	r3,GOT(.bss)
 	lwz	r4,GOT(_end)
 	cmplw	0, r3, r4
 	beq	6f
 	li	r0, 0
 5:
 	stw	r0, 0(r3)
 	addi	r3, r3, 4
 	cmplw	0, r3, r4
 	blt	5b
 6:
 	mr	r3, r9		/* Global Data pointer		*/
 	mr	r4, r10		/* Destination Address		*/
 	bl	board_init_r
 	/* Problems accessing "end" in C, so do it here */
 	.globl	get_endaddr
 get_endaddr:
 	lwz	r3,GOT(_end)
 	blr
 	/*
 	 * Copy exception vector code to low memory
 	 *
 	 * r3: dest_addr
 	 * r7: source address, r8: end address, r9: target address
 	 */
 	.globl	trap_init
 trap_init:
 	lwz	r7, GOT(_start)
 	lwz	r8, GOT(_end_of_vectors)
 	rlwinm	r9, r7, 0, 18, 31	/* _start & 0x3FFF	*/
 	cmplw	0, r7, r8
 	bgelr				/* return if r7>=r8 - just in case */
 	mflr	r4			/* save link register		*/
 1:
 	lwz	r0, 0(r7)
 	stw	r0, 0(r9)
 	addi	r7, r7, 4
 	addi	r9, r9, 4
 	cmplw	0, r7, r8
 	bne	1b
 	/*
 	 * relocate `hdlr' and `int_return' entries
 	 */
 	li	r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
 	li	r8, Alignment - _start + EXC_OFF_SYS_RESET
 2:
 	bl	trap_reloc
 	addi	r7, r7, 0x100		/* next exception vector	*/
 	cmplw	0, r7, r8
 	blt	2b
 	li	r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
 	bl	trap_reloc
 	li	r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
 	bl	trap_reloc
 	li	r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
 	li	r8, SystemCall - _start + EXC_OFF_SYS_RESET
 3:
 	bl	trap_reloc
 	addi	r7, r7, 0x100		/* next exception vector	*/
 	cmplw	0, r7, r8
 	blt	3b
 	li	r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
 	li	r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
 4:
 	bl	trap_reloc
 	addi	r7, r7, 0x100		/* next exception vector	*/
 	cmplw	0, r7, r8
 	blt	4b
 	mtlr	r4			/* restore link register	*/
 	blr
 	/*
 	 * Function: relocate entries for one exception vector
 	 */
 trap_reloc:
 	lwz	r0, 0(r7)		/* hdlr ...			*/
 	add	r0, r0, r3		/*  ... += dest_addr		*/
 	stw	r0, 0(r7)
 	lwz	r0, 4(r7)		/* int_return ...		*/
 	add	r0, r0, r3		/*  ... += dest_addr		*/
 	stw	r0, 4(r7)
 	blr
 	/* Setup the BAT registers.
 	 */
 setup_bats:
 	lis	r4, CFG_IBAT0L@h
 	ori	r4, r4, CFG_IBAT0L@l
 	lis	r3, CFG_IBAT0U@h
 	ori	r3, r3, CFG_IBAT0U@l
 	mtspr	IBAT0L, r4
 	mtspr	IBAT0U, r3
 	isync
 	lis	r4, CFG_DBAT0L@h
 	ori	r4, r4, CFG_DBAT0L@l
 	lis	r3, CFG_DBAT0U@h
 	ori	r3, r3, CFG_DBAT0U@l
 	mtspr	DBAT0L, r4
 	mtspr	DBAT0U, r3
 	isync
 	lis	r4, CFG_IBAT1L@h
 	ori	r4, r4, CFG_IBAT1L@l
 	lis	r3, CFG_IBAT1U@h
 	ori	r3, r3, CFG_IBAT1U@l
 	mtspr	IBAT1L, r4
 	mtspr	IBAT1U, r3
 	isync
 	lis	r4, CFG_DBAT1L@h
 	ori	r4, r4, CFG_DBAT1L@l
 	lis	r3, CFG_DBAT1U@h
 	ori	r3, r3, CFG_DBAT1U@l
 	mtspr	DBAT1L, r4
 	mtspr	DBAT1U, r3
 	isync
 	lis	r4, CFG_IBAT2L@h
 	ori	r4, r4, CFG_IBAT2L@l
 	lis	r3, CFG_IBAT2U@h
 	ori	r3, r3, CFG_IBAT2U@l
 	mtspr	IBAT2L, r4
 	mtspr	IBAT2U, r3
 	isync
 	lis	r4, CFG_DBAT2L@h
 	ori	r4, r4, CFG_DBAT2L@l
 	lis	r3, CFG_DBAT2U@h
 	ori	r3, r3, CFG_DBAT2U@l
 	mtspr	DBAT2L, r4
 	mtspr	DBAT2U, r3
 	isync
 	lis	r4, CFG_IBAT3L@h
 	ori	r4, r4, CFG_IBAT3L@l
 	lis	r3, CFG_IBAT3U@h
 	ori	r3, r3, CFG_IBAT3U@l
 	mtspr	IBAT3L, r4
 	mtspr	IBAT3U, r3
 	isync
 	lis	r4, CFG_DBAT3L@h
 	ori	r4, r4, CFG_DBAT3L@l
 	lis	r3, CFG_DBAT3U@h
 	ori	r3, r3, CFG_DBAT3U@l
 	mtspr	DBAT3L, r4
 	mtspr	DBAT3U, r3
 	isync
 	/* Invalidate TLBs.
 	 * -> for (val = 0; val < 0x20000; val+=0x1000)
 	 * ->   tlbie(val);
 	 */
 	lis	r3, 0
 	lis	r5, 2
 1:
 	tlbie	r3
 	addi	r3, r3, 0x1000
 	cmp	0, 0, r3, r5
 	blt	1b
 	blr

cpu/mpc8260/start.S

Diff comments View file @ 7c7a23b

 /*
  *  Copyright (C) 1998	Dan Malek <dmalek@jlc.net>
  *  Copyright (C) 1999	Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
  *  Copyright (C) 2000, 2001,2002 Wolfgang Denk <wd@denx.de>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 /*
  *  U-Boot - Startup Code for MPC8260 PowerPC based Embedded Boards
  */
 #include <config.h>
 #include <mpc8260.h>
 #include <version.h>
 #define CONFIG_8260 1		/* needed for Linux kernel header files */
 #define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
 #include <ppc_asm.tmpl>
 #include <ppc_defs.h>
 #include <asm/cache.h>
 #include <asm/mmu.h>
 #ifndef  CONFIG_IDENT_STRING
 #define  CONFIG_IDENT_STRING ""
 #endif
 /* We don't want the  MMU yet.
 */
 #undef	MSR_KERNEL
 /* Floating Point enable, Machine Check and Recoverable Interr. */
 #ifdef DEBUG
 #define MSR_KERNEL (MSR_FP|MSR_RI)
 #else
 #define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
 #endif
 /*
  * Set up GOT: Global Offset Table
  *
  * Use r14 to access the GOT
  */
 	START_GOT
 	GOT_ENTRY(_GOT2_TABLE_)
 	GOT_ENTRY(_FIXUP_TABLE_)
 	GOT_ENTRY(_start)
 	GOT_ENTRY(_start_of_vectors)
 	GOT_ENTRY(_end_of_vectors)
 	GOT_ENTRY(transfer_to_handler)
 	GOT_ENTRY(_end)
 	GOT_ENTRY(.bss)
 #if defined(CONFIG_HYMOD)
 	GOT_ENTRY(environment)
 #endif
 	END_GOT
 /*
  * Version string - must be in data segment because MPC8260 uses the first
  * 256 bytes for the Hard Reset Configuration Word table (see below).
  * Similarly, can't have the U-Boot Magic Number as the first thing in
  * the image - don't know how this will affect the image tools, but I guess
  * I'll find out soon
  */
 	.data
 	.globl	version_string
 version_string:
 	.ascii U_BOOT_VERSION
 	.ascii " (", __DATE__, " - ", __TIME__, ")"
 	.ascii CONFIG_IDENT_STRING, "\0"
 /*
  *  Hard Reset Configuration Word (HRCW) table
  *
  *  The Hard Reset Configuration Word (HRCW) sets a number of useful things
  *  such as whether there is an external memory controller, whether the
  *  PowerPC core is disabled (i.e. only the communications processor is
  *  active, accessed by another CPU on the bus), whether using external
  *  arbitration, external bus mode, boot port size, core initial prefix,
  *  internal space base, boot memory space, etc.
  *
  *  These things dictate where the processor begins execution, where the
  *  boot ROM appears in memory, the memory controller setup when access
  *  boot ROM, etc. The HRCW is *extremely* important.
  *
  *  The HRCW is read from the bus during reset. One CPU on the bus will
  *  be a hard reset configuration master, any others will be hard reset
  *  configuration slaves. The master reads eight HRCWs from flash during
  *  reset - the first it uses for itself, the other 7 it communicates to
  *  up to 7 configuration slaves by some complicated mechanism, which is
  *  not really important here.
  *
  *  The configuration master performs 32 successive reads starting at address
  *  0 and incrementing by 8 each read (i.e. on 64 bit boundaries) but only 8
  *  bits is read, and always from byte lane D[0-7] (so that port size of the
  *  boot device does not matter). The first four reads form the 32 bit HRCW
  *  for the master itself. The second four reads form the HRCW for the first
  *  slave, and so on, up to seven slaves. The 32 bit HRCW is formed by
  *  concatenating the four bytes, with the first read placed in byte 0 (the
  *  most significant byte), and so on with the fourth read placed in byte 3
  *  (the least significant byte).
  */
 #define _HRCW_TABLE_ENTRY(w)		\
 	.fill	8,1,(((w)>>24)&0xff);	\
 	.fill	8,1,(((w)>>16)&0xff);	\
 	.fill	8,1,(((w)>> 8)&0xff);	\
 	.fill	8,1,(((w)    )&0xff)
 	.text
 	.globl	_hrcw_table
 _hrcw_table:
 	_HRCW_TABLE_ENTRY(CFG_HRCW_MASTER)
 	_HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE1)
 	_HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE2)
 	_HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE3)
 	_HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE4)
 	_HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE5)
 	_HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE6)
 	_HRCW_TABLE_ENTRY(CFG_HRCW_SLAVE7)
 /*
  *  After configuration, a system reset exception is executed using the
  *  vector at offset 0x100 relative to the base set by MSR[IP]. If MSR[IP]
  *  is 0, the base address is 0x00000000. If MSR[IP] is 1, the base address
  *  is 0xfff00000. In the case of a Power On Reset or Hard Reset, the value
  *  of MSR[IP] is determined by the CIP field in the HRCW.
  *
  *  Other bits in the HRCW set up the Base Address and Port Size in BR0.
  *  This determines the location of the boot ROM (flash or EPROM) in the
  *  processor's address space at boot time. As long as the HRCW is set up
  *  so that we eventually end up executing the code below when the processor
  *  executes the reset exception, the actual values used should not matter.
  *
  *  Once we have got here, the address mask in OR0 is cleared so that the
  *  bottom 32K of the boot ROM is effectively repeated all throughout the
  *  processor's address space, after which we can jump to the absolute
  *  address at which the boot ROM was linked at compile time, and proceed
  *  to initialise the memory controller without worrying if the rug will be
  *  pulled out from under us, so to speak (it will be fine as long as we
  *  configure BR0 with the same boot ROM link address).
  */
 	. = EXC_OFF_SYS_RESET
 	.globl	_start
 _start:
 	li	r21, BOOTFLAG_COLD	/* Normal Power-On: Boot from FLASH*/
 	b	boot_cold
 	. = EXC_OFF_SYS_RESET + 0x10
 	.globl	_start_warm
 _start_warm:
 	li	r21, BOOTFLAG_WARM	/* Software reboot		*/
 	b	boot_warm
 boot_cold:
 boot_warm:
 	mfmsr	r5			/* save msr contents		*/
 #if defined(CONFIG_COGENT)
 	/* this is what the cogent EPROM does */
 	li	r0, 0
 	mtmsr	r0
 	isync
 	bl	cogent_init_8260
 #endif	/* CONFIG_COGENT */
 #if defined(CFG_DEFAULT_IMMR)
 	lis	r3, CFG_IMMR@h
 	ori	r3, r3, CFG_IMMR@l
 	lis	r4, CFG_DEFAULT_IMMR@h
 	stw	r3, 0x1A8(r4)
 #endif /* CFG_DEFAULT_IMMR */
 	/* Initialise the MPC8260 processor core			*/
 	/*--------------------------------------------------------------*/
 	bl	init_8260_core
 #ifndef CFG_RAMBOOT
 	/* When booting from ROM (Flash or EPROM), clear the		*/
 	/* Address Mask in OR0 so ROM appears everywhere		*/
 	/*--------------------------------------------------------------*/
 	lis	r3, (CFG_IMMR+IM_REGBASE)@h
 	lwz	r4, IM_OR0@l(r3)
 	li	r5, 0x7fff
 	and	r4, r4, r5
 	stw	r4, IM_OR0@l(r3)
 	/* Calculate absolute address in FLASH and jump there		*/
 	/*--------------------------------------------------------------*/
 	lis	r3, CFG_MONITOR_BASE@h
 	ori	r3, r3, CFG_MONITOR_BASE@l
 	addi	r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
 	mtlr	r3
 	blr
 in_flash:
 #endif	/* CFG_RAMBOOT */
 	/* initialize some things that are hard to access from C	*/
 	/*--------------------------------------------------------------*/
 	lis	r3, CFG_IMMR@h		/* set up stack in internal DPRAM */
 	ori	r1, r3, CFG_INIT_SP_OFFSET
 	li	r0, 0			/* Make room for stack frame header and	*/
 	stwu	r0, -4(r1)		/* clear final stack frame so that	*/
 	stwu	r0, -4(r1)		/* stack backtraces terminate cleanly	*/
 	/* let the C-code set up the rest				*/
 	/*								*/
 	/* Be careful to keep code relocatable !			*/
 	/*--------------------------------------------------------------*/
 	GET_GOT			/* initialize GOT access		*/
 	/* r3: IMMR */
 	bl	cpu_init_f	/* run low-level CPU init code (in Flash)*/
 #ifdef DEBUG
 	bl	init_debug	/* set up debugging stuff		*/
 #endif
 	mr	r3, r21
 	/* r3: BOOTFLAG */
 	bl	board_init_f	/* run 1st part of board init code (in Flash)*/
 /*
  * Vector Table
  */
 	.globl	_start_of_vectors
 _start_of_vectors:
 /* Machine check */
 	STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
 /* Data Storage exception. */
 	STD_EXCEPTION(0x300, DataStorage, UnknownException)
 /* Instruction Storage exception. */
 	STD_EXCEPTION(0x400, InstStorage, UnknownException)
 /* External Interrupt exception. */
 	STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
 /* Alignment exception. */
 	. = 0x600
 Alignment:
 	EXCEPTION_PROLOG
 	mfspr	r4,DAR
 	stw	r4,_DAR(r21)
 	mfspr	r5,DSISR
 	stw	r5,_DSISR(r21)
 	addi	r3,r1,STACK_FRAME_OVERHEAD
 	li	r20,MSR_KERNEL
 	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
 	rlwimi	r20,r23,0,25,25		/* copy IP bit from saved MSR */
 	lwz	r6,GOT(transfer_to_handler)
 	mtlr	r6
 	blrl
 .L_Alignment:
 	.long	AlignmentException - _start + EXC_OFF_SYS_RESET
 	.long	int_return - _start + EXC_OFF_SYS_RESET
 /* Program check exception */
 	. = 0x700
 ProgramCheck:
 	EXCEPTION_PROLOG
 	addi	r3,r1,STACK_FRAME_OVERHEAD
 	li	r20,MSR_KERNEL
 	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
 	rlwimi	r20,r23,0,25,25		/* copy IP bit from saved MSR */
 	lwz	r6,GOT(transfer_to_handler)
 	mtlr	r6
 	blrl
 .L_ProgramCheck:
 	.long	ProgramCheckException - _start + EXC_OFF_SYS_RESET
 	.long	int_return - _start + EXC_OFF_SYS_RESET
 	STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
 	/* I guess we could implement decrementer, and may have
 	 * to someday for timekeeping.
 	 */
 	STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
 	STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
 	STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
 	. = 0xc00
 /*
  * r0 - SYSCALL number
  * r3-... arguments
  */
 SystemCall:
 	addis	r11,r0,0		/* get functions table addr */
 	ori	r11,r11,0		/* Note: this code is patched in trap_init */
 	addis	r12,r0,0		/* get number of functions */
 	ori	r12,r12,0
 	cmplw	0, r0, r12
 	bge	1f
 	rlwinm	r0,r0,2,0,31		/* fn_addr = fn_tbl[r0] */
 	add	r11,r11,r0
 	lwz	r11,0(r11)
-	li	r12,0xd00-4*3		/* save LR & SRRx */
+	li	r20,0xd00-4		/* Get stack pointer */
+	lwz	r12,0(r20)
+	subi	r12,r12,12		/* Adjust stack pointer */
+	li	r0,0xc00+_end_back-SystemCall
+	cmplw	0, r0, r12		/* Check stack overflow */
+	bgt	1f
+	stw	r12,0(r20)
 	mflr	r0
 	stw	r0,0(r12)
 	mfspr	r0,SRR0
 	stw	r0,4(r12)
 	mfspr	r0,SRR1
 	stw	r0,8(r12)
 	li	r12,0xc00+_back-SystemCall
 	mtlr	r12
 	mtspr	SRR0,r11
 1:	SYNC
 	rfi
 _back:
 	mfmsr	r11			/* Disable interrupts */
 	li	r12,0
 	ori	r12,r12,MSR_EE
 	andc	r11,r11,r12
 	SYNC				/* Some chip revs need this... */
 	mtmsr	r11
 	SYNC
-	li	r12,0xd00-4*3		/* restore regs */
+	li	r12,0xd00-4		/* restore regs */
+	lwz	r12,0(r12)
 	lwz	r11,0(r12)
 	mtlr	r11
 	lwz	r11,4(r12)
 	mtspr	SRR0,r11
 	lwz	r11,8(r12)
 	mtspr	SRR1,r11
+	addi	r12,r12,12		/* Adjust stack pointer */
+	li	r20,0xd00-4
+	stw	r12,0(r20)
 	SYNC
 	rfi
+_end_back:
 	STD_EXCEPTION(0xd00, SingleStep, UnknownException)
 	STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
 	STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
 	STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
 	STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
 	STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
 #ifdef DEBUG
 	. = 0x1300
 	/*
 	 * This exception occurs when the program counter matches the
 	 * Instruction Address Breakpoint Register (IABR).
 	 *
 	 * I want the cpu to halt if this occurs so I can hunt around
 	 * with the debugger and look at things.
 	 *
 	 * When DEBUG is defined, both machine check enable (in the MSR)
 	 * and checkstop reset enable (in the reset mode register) are
 	 * turned off and so a checkstop condition will result in the cpu
 	 * halting.
 	 *
 	 * I force the cpu into a checkstop condition by putting an illegal
 	 * instruction here (at least this is the theory).
 	 *
 	 * well - that didnt work, so just do an infinite loop!
 	 */
 1:	b	1b
 #else
 	STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException)
 #endif
 	STD_EXCEPTION(0x1400, SMI, UnknownException)
 	STD_EXCEPTION(0x1500, Trap_15, UnknownException)
 	STD_EXCEPTION(0x1600, Trap_16, UnknownException)
 	STD_EXCEPTION(0x1700, Trap_17, UnknownException)
 	STD_EXCEPTION(0x1800, Trap_18, UnknownException)
 	STD_EXCEPTION(0x1900, Trap_19, UnknownException)
 	STD_EXCEPTION(0x1a00, Trap_1a, UnknownException)
 	STD_EXCEPTION(0x1b00, Trap_1b, UnknownException)
 	STD_EXCEPTION(0x1c00, Trap_1c, UnknownException)
 	STD_EXCEPTION(0x1d00, Trap_1d, UnknownException)
 	STD_EXCEPTION(0x1e00, Trap_1e, UnknownException)
 	STD_EXCEPTION(0x1f00, Trap_1f, UnknownException)
 	STD_EXCEPTION(0x2000, Trap_20, UnknownException)
 	STD_EXCEPTION(0x2100, Trap_21, UnknownException)
 	STD_EXCEPTION(0x2200, Trap_22, UnknownException)
 	STD_EXCEPTION(0x2300, Trap_23, UnknownException)
 	STD_EXCEPTION(0x2400, Trap_24, UnknownException)
 	STD_EXCEPTION(0x2500, Trap_25, UnknownException)
 	STD_EXCEPTION(0x2600, Trap_26, UnknownException)
 	STD_EXCEPTION(0x2700, Trap_27, UnknownException)
 	STD_EXCEPTION(0x2800, Trap_28, UnknownException)
 	STD_EXCEPTION(0x2900, Trap_29, UnknownException)
 	STD_EXCEPTION(0x2a00, Trap_2a, UnknownException)
 	STD_EXCEPTION(0x2b00, Trap_2b, UnknownException)
 	STD_EXCEPTION(0x2c00, Trap_2c, UnknownException)
 	STD_EXCEPTION(0x2d00, Trap_2d, UnknownException)
 	STD_EXCEPTION(0x2e00, Trap_2e, UnknownException)
 	STD_EXCEPTION(0x2f00, Trap_2f, UnknownException)
 	.globl	_end_of_vectors
 _end_of_vectors:
 	. = 0x3000
 /*
  * This code finishes saving the registers to the exception frame
  * and jumps to the appropriate handler for the exception.
  * Register r21 is pointer into trap frame, r1 has new stack pointer.
  */
 	.globl	transfer_to_handler
 transfer_to_handler:
 	stw	r22,_NIP(r21)
 	lis	r22,MSR_POW@h
 	andc	r23,r23,r22
 	stw	r23,_MSR(r21)
 	SAVE_GPR(7, r21)
 	SAVE_4GPRS(8, r21)
 	SAVE_8GPRS(12, r21)
 	SAVE_8GPRS(24, r21)
 	mflr	r23
 	andi.	r24,r23,0x3f00		/* get vector offset */
 	stw	r24,TRAP(r21)
 	li	r22,0
 	stw	r22,RESULT(r21)
 	lwz	r24,0(r23)		/* virtual address of handler */
 	lwz	r23,4(r23)		/* where to go when done */
 	mtspr	SRR0,r24
 	mtspr	SRR1,r20
 	mtlr	r23
 	SYNC
 	rfi				/* jump to handler, enable MMU */
 int_return:
 	mfmsr	r28		/* Disable interrupts */
 	li	r4,0
 	ori	r4,r4,MSR_EE
 	andc	r28,r28,r4
 	SYNC			/* Some chip revs need this... */
 	mtmsr	r28
 	SYNC
 	lwz	r2,_CTR(r1)
 	lwz	r0,_LINK(r1)
 	mtctr	r2
 	mtlr	r0
 	lwz	r2,_XER(r1)
 	lwz	r0,_CCR(r1)
 	mtspr	XER,r2
 	mtcrf	0xFF,r0
 	REST_10GPRS(3, r1)
 	REST_10GPRS(13, r1)
 	REST_8GPRS(23, r1)
 	REST_GPR(31, r1)
 	lwz	r2,_NIP(r1)	/* Restore environment */
 	lwz	r0,_MSR(r1)
 	mtspr	SRR0,r2
 	mtspr	SRR1,r0
 	lwz	r0,GPR0(r1)
 	lwz	r2,GPR2(r1)
 	lwz	r1,GPR1(r1)
 	SYNC
 	rfi
 #if defined(CONFIG_COGENT)
 /*
  * This code initialises the MPC8260 processor core
  * (conforms to PowerPC 603e spec)
  */
 	.globl	cogent_init_8260
 cogent_init_8260:
 	/* Taken from page 14 of CMA282 manual				*/
 	/*--------------------------------------------------------------*/
 	lis	r4, (CFG_IMMR+IM_REGBASE)@h
 	lis	r3, CFG_IMMR@h
 	stw	r3, IM_IMMR@l(r4)
 	lwz	r3, IM_IMMR@l(r4)
 	stw	r3, 0(r0)
 	lis	r3, CFG_SYPCR@h
 	ori	r3, r3, CFG_SYPCR@l
 	stw	r3, IM_SYPCR@l(r4)
 	lwz	r3, IM_SYPCR@l(r4)
 	stw	r3, 4(r0)
 	lis	r3, CFG_SCCR@h
 	ori	r3, r3, CFG_SCCR@l
 	stw	r3, IM_SCCR@l(r4)
 	lwz	r3, IM_SCCR@l(r4)
 	stw	r3, 8(r0)
 	/* the rest of this was disassembled from the			*/
 	/* EPROM code that came with my CMA282 CPU module		*/
 	/*--------------------------------------------------------------*/
 	lis	r1, 0x1234
 	ori	r1, r1, 0x5678
 	stw	r1, 0x20(r0)
 	lwz	r1, 0x20(r0)
 	stw	r1, 0x24(r0)
 	lwz	r1, 0x24(r0)
 	lis	r3, 0x0e80
 	ori	r3, r3, 0
 	stw	r1, 4(r3)
 	lwz	r1, 4(r3)
 	/* Done!							*/
 	/*--------------------------------------------------------------*/
 	blr
 #endif	/* CONFIG_COGENT */
 /*
  * This code initialises the MPC8260 processor core
  * (conforms to PowerPC 603e spec)
  * Note: expects original MSR contents to be in r5.
  */
 	.globl	init_8260_core
 init_8260_core:
 	/* Initialize machine status; enable machine check interrupt	*/
 	/*--------------------------------------------------------------*/
 	li	r3, MSR_KERNEL		/* Set ME and RI flags */
 	rlwimi	r3, r5, 0, 25, 25	/* preserve IP bit set by HRCW */
 #ifdef DEBUG
 	rlwimi	r3, r5, 0, 21, 22	/* debugger might set SE & BE bits */
 #endif
 	SYNC				/* Some chip revs need this... */
 	mtmsr	r3
 	SYNC
 	mtspr	SRR1, r3		/* Make SRR1 match MSR */
 	/* Initialise the SYPCR early, and reset the watchdog (if req)	*/
 	/*--------------------------------------------------------------*/
 	lis	r3, (CFG_IMMR+IM_REGBASE)@h
 #if !defined(CONFIG_COGENT)
 	lis	r4, CFG_SYPCR@h
 	ori	r4, r4, CFG_SYPCR@l
 	stw	r4, IM_SYPCR@l(r3)
 #endif /* !CONFIG_COGENT */
 #if defined(CONFIG_WATCHDOG)
 	li	r4, 21868		/* = 0x556c */
 	sth	r4, IM_SWSR@l(r3)
 	li	r4, -21959		/* = 0xaa39 */
 	sth	r4, IM_SWSR@l(r3)
 #endif /* CONFIG_WATCHDOG */
 	/* Initialize the Hardware Implementation-dependent Registers	*/
 	/* HID0 also contains cache control				*/
 	/*--------------------------------------------------------------*/
 	lis	r3, CFG_HID0_INIT@h
 	ori	r3, r3, CFG_HID0_INIT@l
 	SYNC
 	mtspr	HID0, r3
 	lis	r3, CFG_HID0_FINAL@h
 	ori	r3, r3, CFG_HID0_FINAL@l
 	SYNC
 	mtspr	HID0, r3
 	lis	r3, CFG_HID2@h
 	ori	r3, r3, CFG_HID2@l
 	mtspr	HID2, r3
 	/* clear all BAT's						*/
 	/*--------------------------------------------------------------*/
 	li	r0, 0
 	mtspr	DBAT0U, r0
 	mtspr	DBAT0L, r0
 	mtspr	DBAT1U, r0
 	mtspr	DBAT1L, r0
 	mtspr	DBAT2U, r0
 	mtspr	DBAT2L, r0
 	mtspr	DBAT3U, r0
 	mtspr	DBAT3L, r0
 	mtspr	IBAT0U, r0
 	mtspr	IBAT0L, r0
 	mtspr	IBAT1U, r0
 	mtspr	IBAT1L, r0
 	mtspr	IBAT2U, r0
 	mtspr	IBAT2L, r0
 	mtspr	IBAT3U, r0
 	mtspr	IBAT3L, r0
 	SYNC
 	/* invalidate all tlb's						*/
 	/*								*/
 	/* From the 603e User Manual: "The 603e provides the ability to	*/
 	/* invalidate a TLB entry. The TLB Invalidate Entry (tlbie)	*/
 	/* instruction invalidates the TLB entry indexed by the EA, and	*/
 	/* operates on both the instruction and data TLBs simultaneously*/
 	/* invalidating four TLB entries (both sets in each TLB). The	*/
 	/* index corresponds to bits 15-19 of the EA. To invalidate all	*/
 	/* entries within both TLBs, 32 tlbie instructions should be	*/
 	/* issued, incrementing this field by one each time."		*/
 	/*								*/
 	/* "Note that the tlbia instruction is not implemented on the	*/
 	/* 603e."							*/
 	/*								*/
 	/* bits 15-19 correspond to addresses 0x00000000 to 0x0001F000	*/
 	/* incrementing by 0x1000 each time. The code below is sort of	*/
 	/* based on code in "flush_tlbs" from arch/ppc/kernel/head.S	*/
 	/*								*/
 	/*--------------------------------------------------------------*/
 	li	r3, 32
 	mtctr	r3
 	li	r3, 0
 1:	tlbie	r3
 	addi	r3, r3, 0x1000
 	bdnz	1b
 	SYNC
 	/* Done!							*/
 	/*--------------------------------------------------------------*/
 	blr
 #ifdef DEBUG
 /*
  * initialise things related to debugging.
  *
  * must be called after the global offset table (GOT) is initialised
  * (GET_GOT) and after cpu_init_f() has executed.
  */
 	.globl	init_debug
 init_debug:
 	lis	r3, (CFG_IMMR+IM_REGBASE)@h
 	/* Quick and dirty hack to enable the RAM and copy the		*/
 	/* vectors so that we can take exceptions.			*/
 	/*--------------------------------------------------------------*/
 	/* write Memory Refresh Prescaler */
 	li	r4, CFG_MPTPR
 	sth	r4, IM_MPTPR@l(r3)
 	/* write 60x Refresh Timer */
 	li	r4, CFG_PSRT
 	stb	r4, IM_PSRT@l(r3)
 	/* init the 60x SDRAM Mode Register */
 	lis	r4, (CFG_PSDMR|PSDMR_OP_NORM)@h
 	ori	r4, r4, (CFG_PSDMR|PSDMR_OP_NORM)@l
 	stw	r4, IM_PSDMR@l(r3)
 	/* write Precharge All Banks command */
 	lis	r4, (CFG_PSDMR|PSDMR_OP_PREA)@h
 	ori	r4, r4, (CFG_PSDMR|PSDMR_OP_PREA)@l
 	stw	r4, IM_PSDMR@l(r3)
 	stb	r0, 0(0)
 	/* write eight CBR Refresh commands */
 	lis	r4, (CFG_PSDMR|PSDMR_OP_CBRR)@h
 	ori	r4, r4, (CFG_PSDMR|PSDMR_OP_CBRR)@l
 	stw	r4, IM_PSDMR@l(r3)
 	stb	r0, 0(0)
 	stb	r0, 0(0)
 	stb	r0, 0(0)
 	stb	r0, 0(0)
 	stb	r0, 0(0)
 	stb	r0, 0(0)
 	stb	r0, 0(0)
 	stb	r0, 0(0)
 	/* write Mode Register Write command */
 	lis	r4, (CFG_PSDMR|PSDMR_OP_MRW)@h
 	ori	r4, r4, (CFG_PSDMR|PSDMR_OP_MRW)@l
 	stw	r4, IM_PSDMR@l(r3)
 	stb	r0, 0(0)
 	/* write Normal Operation command and enable Refresh */
 	lis	r4, (CFG_PSDMR|PSDMR_OP_NORM|PSDMR_RFEN)@h
 	ori	r4, r4, (CFG_PSDMR|PSDMR_OP_NORM|PSDMR_RFEN)@l
 	stw	r4, IM_PSDMR@l(r3)
 	stb	r0, 0(0)
 	/* RAM should now be operational */
 #define VEC_WRD_CNT	((_end_of_vectors - _start + EXC_OFF_SYS_RESET) / 4)
 	lwz	r3, GOT(_end_of_vectors)
 	rlwinm	r4, r3, 0, 18, 31	/* _end_of_vectors & 0x3FFF	*/
 	lis	r5, VEC_WRD_CNT@h
 	ori	r5, r5, VEC_WRD_CNT@l
 	mtctr	r5
 1:
 	lwzu	r5, -4(r3)
 	stwu	r5, -4(r4)
 	bdnz	1b
 	/* Load the Instruction Address Breakpoint Register (IABR).	*/
 	/* 								*/
 	/* The address to load is stored in the first word of dual port	*/
 	/* ram and should be preserved while the power is on, so you	*/
 	/* can plug addresses into that location then reset the cpu and	*/
 	/* this code will load that address into the IABR after the	*/
 	/* reset.							*/
 	/* 								*/
 	/* When the program counter matches the contents of the IABR,	*/
 	/* an exception is generated (before the instruction at that	*/
 	/* location completes). The vector for this exception is 0x1300 */
 	/*--------------------------------------------------------------*/
 	lis	r3, CFG_IMMR@h
 	lwz	r3, 0(r3)
 	mtspr	IABR, r3
 	/* Set the entire dual port RAM (where the initial stack	*/
 	/* resides) to a known value - makes it easier to see where	*/
 	/* the stack has been written					*/
 	/*--------------------------------------------------------------*/
 	lis	r3, (CFG_IMMR + CFG_INIT_SP_OFFSET)@h
 	ori	r3, r3, (CFG_IMMR + CFG_INIT_SP_OFFSET)@l
 	li	r4, ((CFG_INIT_SP_OFFSET - 4) / 4)
 	mtctr	r4
 	lis	r4, 0xdeadbeaf@h
 	ori	r4, r4, 0xdeadbeaf@l
 1:
 	stwu	r4, -4(r3)
 	bdnz	1b
 	/* Done!							*/
 	/*--------------------------------------------------------------*/
 	blr
 #endif
 /* Cache functions.
  *
  * Note: requires that all cache bits in
  * HID0 are in the low half word.
  */
 	.globl	icache_enable
 icache_enable:
 	mfspr	r3, HID0
 	ori	r3, r3, HID0_ICE
 	lis	r4, 0
 	ori	r4, r4, HID0_ILOCK
 	andc	r3, r3, r4
 	ori	r4, r3, HID0_ICFI
 	isync
 	mtspr	HID0, r4	/* sets enable and invalidate, clears lock */
 	isync
 	mtspr	HID0, r3	/* clears invalidate */
 	blr
 	.globl	icache_disable
 icache_disable:
 	mfspr	r3, HID0
 	lis	r4, 0
 	ori	r4, r4, HID0_ICE|HID0_ILOCK
 	andc	r3, r3, r4
 	ori	r4, r3, HID0_ICFI
 	isync
 	mtspr	HID0, r4	/* sets invalidate, clears enable and lock */
 	isync
 	mtspr	HID0, r3	/* clears invalidate */
 	blr
 	.globl	icache_status
 icache_status:
 	mfspr	r3, HID0
 	rlwinm	r3, r3, HID0_ICE_BITPOS + 1, 31, 31
 	blr
 	.globl	dcache_enable
 dcache_enable:
 	mfspr	r3, HID0
 	ori	r3, r3, HID0_DCE
 	lis	r4, 0
 	ori	r4, r4, HID0_DLOCK
 	andc	r3, r3, r4
 	ori	r4, r3, HID0_DCI
 	sync
 	mtspr	HID0, r4	/* sets enable and invalidate, clears lock */
 	sync
 	mtspr	HID0, r3	/* clears invalidate */
 	blr
 	.globl	dcache_disable
 dcache_disable:
 	mfspr	r3, HID0
 	lis	r4, 0
 	ori	r4, r4, HID0_DCE|HID0_DLOCK
 	andc	r3, r3, r4
 	ori	r4, r3, HID0_DCI
 	sync
 	mtspr	HID0, r4	/* sets invalidate, clears enable and lock */
 	sync
 	mtspr	HID0, r3	/* clears invalidate */
 	blr
 	.globl	dcache_status
 dcache_status:
 	mfspr	r3, HID0
 	rlwinm	r3, r3, HID0_DCE_BITPOS + 1, 31, 31
 	blr
 	.globl get_pvr
 get_pvr:
 	mfspr	r3, PVR
 	blr
 /*------------------------------------------------------------------------------*/
 /*
  * void relocate_code (addr_sp, gd, addr_moni)
  *
  * This "function" does not return, instead it continues in RAM
  * after relocating the monitor code.
  *
  * r3 = dest
  * r4 = src
  * r5 = length in bytes
  * r6 = cachelinesize
  */
 	.globl	relocate_code
 relocate_code:
 	mr	r1,  r3		/* Set new stack pointer		*/
 	mr	r9,  r4		/* Save copy of Global Data pointer	*/
 	mr	r10, r5		/* Save copy of Destination Address	*/
 	mr	r3,  r5				/* Destination Address	*/
 	lis	r4, CFG_MONITOR_BASE@h		/* Source      Address	*/
 	ori	r4, r4, CFG_MONITOR_BASE@l
 	lis	r5, CFG_MONITOR_LEN@h		/* Length in Bytes	*/
 	ori	r5, r5, CFG_MONITOR_LEN@l
 	li	r6, CFG_CACHELINE_SIZE		/* Cache Line Size	*/
 	/*
 	 * Fix GOT pointer:
 	 *
 	 * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
 	 *
 	 * Offset:
 	 */
 	sub	r15, r10, r4
 	/* First our own GOT */
 	add	r14, r14, r15
 	/* then the one used by the C code */
 	add	r30, r30, r15
 	/*
 	 * Now relocate code
 	 */
 	cmplw	cr1,r3,r4
 	addi	r0,r5,3
 	srwi.	r0,r0,2
 	beq	cr1,4f		/* In place copy is not necessary	*/
 	beq	7f		/* Protect against 0 count		*/
 	mtctr	r0
 	bge	cr1,2f
 	la	r8,-4(r4)
 	la	r7,-4(r3)
 1:	lwzu	r0,4(r8)
 	stwu	r0,4(r7)
 	bdnz	1b
 	b	4f
 2:	slwi	r0,r0,2
 	add	r8,r4,r0
 	add	r7,r3,r0
 3:	lwzu	r0,-4(r8)
 	stwu	r0,-4(r7)
 	bdnz	3b
 /*
  * Now flush the cache: note that we must start from a cache aligned
  * address. Otherwise we might miss one cache line.
  */
 4:	cmpwi	r6,0
 	add	r5,r3,r5
 	beq	7f		/* Always flush prefetch queue in any case */
 	subi	r0,r6,1
 	andc	r3,r3,r0
 	mfspr	r7,HID0		/* don't do dcbst if dcache is disabled */
 	rlwinm	r7,r7,HID0_DCE_BITPOS+1,31,31
 	cmpwi	r7,0
 	beq	9f
 	mr	r4,r3
 5:	dcbst	0,r4
 	add	r4,r4,r6
 	cmplw	r4,r5
 	blt	5b
 	sync			/* Wait for all dcbst to complete on bus */
 9:	mfspr	r7,HID0		/* don't do icbi if icache is disabled */
 	rlwinm	r7,r7,HID0_ICE_BITPOS+1,31,31
 	cmpwi	r7,0
 	beq	7f
 	mr	r4,r3
 6:	icbi	0,r4
 	add	r4,r4,r6
 	cmplw	r4,r5
 	blt	6b
 7:	sync			/* Wait for all icbi to complete on bus	*/
 	isync
 /*
  * We are done. Do not return, instead branch to second part of board
  * initialization, now running from RAM.
  */
 	addi	r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
 	mtlr	r0
 	blr
 in_ram:
 	/*
 	 * Relocation Function, r14 point to got2+0x8000
 	 *
          * Adjust got2 pointers, no need to check for 0, this code
          * already puts a few entries in the table.
 	 */
 	li	r0,__got2_entries@sectoff@l
 	la	r3,GOT(_GOT2_TABLE_)
 	lwz	r11,GOT(_GOT2_TABLE_)
 	mtctr	r0
 	sub	r11,r3,r11
 	addi	r3,r3,-4
 1:	lwzu	r0,4(r3)
 	add	r0,r0,r11
 	stw	r0,0(r3)
 	bdnz	1b
 	/*
          * Now adjust the fixups and the pointers to the fixups
 	 * in case we need to move ourselves again.
 	 */
 2:	li	r0,__fixup_entries@sectoff@l
 	lwz	r3,GOT(_FIXUP_TABLE_)
 	cmpwi	r0,0
 	mtctr	r0
 	addi	r3,r3,-4
 	beq	4f
 3:	lwzu	r4,4(r3)
 	lwzux	r0,r4,r11
 	add	r0,r0,r11
 	stw	r10,0(r3)
 	stw	r0,0(r4)
 	bdnz	3b
 4:
 clear_bss:
 	/*
 	 * Now clear BSS segment
 	 */
 	lwz	r3,GOT(.bss)
 #if defined(CONFIG_HYMOD)
 	/*
 	 * For HYMOD - the environment is the very last item in flash.
 	 * The real .bss stops just before environment starts, so only
 	 * clear up to that point.
 	 *
 	 * taken from mods for FADS board
 	 */
 	lwz	r4,GOT(environment)
 #else
 	lwz	r4,GOT(_end)
 #endif
 	cmplw	0, r3, r4
 	beq	6f
 	li	r0, 0
 5:
 	stw	r0, 0(r3)
 	addi	r3, r3, 4
 	cmplw	0, r3, r4
 	bne	5b
 6:
 	mr	r3, r9		/* Global Data pointer		*/
 	mr	r4, r10		/* Destination Address		*/
 	bl	board_init_r
 	/* Problems accessing "end" in C, so do it here */
 	.globl	get_endaddr
 get_endaddr:
 	lwz	r3,GOT(_end)
 	blr
 	/*
 	 * Copy exception vector code to low memory
 	 *
 	 * r3: dest_addr
 	 * r7: source address, r8: end address, r9: target address
 	 */
 	.globl	trap_init
 trap_init:
 	lwz	r7, GOT(_start)
 	lwz	r8, GOT(_end_of_vectors)
 	rlwinm	r9, r7, 0, 18, 31	/* _start & 0x3FFF	*/
 	cmplw	0, r7, r8
 	bgelr				/* return if r7>=r8 - just in case */
 	mflr	r4			/* save link register		*/
 1:
 	lwz	r0, 0(r7)
 	stw	r0, 0(r9)
 	addi	r7, r7, 4
 	addi	r9, r9, 4
 	cmplw	0, r7, r8
 	bne	1b
 	/*
 	 * relocate `hdlr' and `int_return' entries
 	 */
 	li	r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
 	li	r8, Alignment - _start + EXC_OFF_SYS_RESET
 2:
 	bl	trap_reloc
 	addi	r7, r7, 0x100		/* next exception vector	*/
 	cmplw	0, r7, r8
 	blt	2b
 	li	r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
 	bl	trap_reloc
 	li	r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
 	bl	trap_reloc
 	li	r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
 	li	r8, SystemCall - _start + EXC_OFF_SYS_RESET
 3:
 	bl	trap_reloc
 	addi	r7, r7, 0x100		/* next exception vector	*/
 	cmplw	0, r7, r8
 	blt	3b
 	li	r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
 	li	r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
 4:
 	bl	trap_reloc
 	addi	r7, r7, 0x100		/* next exception vector	*/
 	cmplw	0, r7, r8
 	blt	4b
 	mfmsr	r3			/* now that the vectors have	*/
 	lis	r7, MSR_IP@h		/* relocated into low memory	*/
 	ori	r7, r7, MSR_IP@l	/* MSR[IP] can be turned off	*/
 	andc	r3, r3, r7		/* (if it was on)		*/
 	SYNC				/* Some chip revs need this... */
 	mtmsr	r3
 	SYNC
 	mtlr	r4			/* restore link register    */
 	blr
 	/*
 	 * Function: relocate entries for one exception vector
 	 */
 trap_reloc:
 	lwz	r0, 0(r7)		/* hdlr ...			*/
 	add	r0, r0, r3		/*  ... += dest_addr		*/
 	stw	r0, 0(r7)
 	lwz	r0, 4(r7)		/* int_return ...		*/
 	add	r0, r0, r3		/*  ... += dest_addr		*/
 	stw	r0, 4(r7)
 	blr

cpu/mpc8xx/interrupts.c

Diff comments View file @ 7c7a23b

1	/*	1	/*
2	* (C) Copyright 2000-2002	2	* (C) Copyright 2000-2002
3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4	*	4	*
5	* See file CREDITS for list of people who contributed to this	5	* See file CREDITS for list of people who contributed to this
6	* project.	6	* project.
7	*	7	*
8	* This program is free software; you can redistribute it and/or	8	* This program is free software; you can redistribute it and/or
9	* modify it under the terms of the GNU General Public License as	9	* modify it under the terms of the GNU General Public License as
10	* published by the Free Software Foundation; either version 2 of	10	* published by the Free Software Foundation; either version 2 of
11	* the License, or (at your option) any later version.	11	* the License, or (at your option) any later version.
12	*	12	*
13	* This program is distributed in the hope that it will be useful,	13	* This program is distributed in the hope that it will be useful,
14	* but WITHOUT ANY WARRANTY; without even the implied warranty of	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16	* GNU General Public License for more details.	16	* GNU General Public License for more details.
17	*	17	*
18	* You should have received a copy of the GNU General Public License	18	* You should have received a copy of the GNU General Public License
19	* along with this program; if not, write to the Free Software	19	* along with this program; if not, write to the Free Software
20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21	* MA 02111-1307 USA	21	* MA 02111-1307 USA
22	*/	22	*/
23		23
24	#include <common.h>	24	#include <common.h>
25	#include <watchdog.h>	25	#include <watchdog.h>
26	#include <mpc8xx.h>	26	#include <mpc8xx.h>
27	#include <mpc8xx_irq.h>	27	#include <mpc8xx_irq.h>
28	#include <asm/processor.h>	28	#include <asm/processor.h>
29	#include <commproc.h>	29	#include <commproc.h>
30		30
31	/****************************************************************************/	31	/************************************************************************/
32		32
33	unsigned decrementer_count; /* count value for 1e6/HZ microseconds */	33	unsigned decrementer_count; /* count value for 1e6/HZ microseconds */
34		34
35	/****************************************************************************/	35	/************************************************************************/
36		36
37	/*	37	/*
38	* CPM interrupt vector functions.	38	* CPM interrupt vector functions.
39	*/	39	*/
40	struct cpm_action {	40	struct interrupt_action {
41	interrupt_handler_t *handler;	41	interrupt_handler_t *handler;
42	void *arg;	42	void *arg;
43	};	43	};
44		44
45	static struct cpm_action cpm_vecs[CPMVEC_NR];	45	static struct interrupt_action cpm_vecs[CPMVEC_NR];
		46	static struct interrupt_action irq_vecs[NR_IRQS];
46		47
47	static void cpm_interrupt_init (void);	48	static void cpm_interrupt_init (void);
48	static void cpm_interrupt(int irq, struct pt_regs * regs);	49	static void cpm_interrupt (void *regs);
49		50
50	/****************************************************************************/	51	/************************************************************************/
51		52
52	static __inline__ unsigned long get_msr(void)	53	static __inline__ unsigned long get_msr (void)
53	{	54	{
54	unsigned long msr;	55	unsigned long msr;
55		56
56	asm volatile("mfmsr %0" : "=r" (msr) :);	57	asm volatile ("mfmsr %0":"=r" (msr):);
57	return msr;	58
		59	return msr;
58	}	60	}
59		61
60	static __inline__ void set_msr(unsigned long msr)	62	static __inline__ void set_msr (unsigned long msr)
61	{	63	{
62	asm volatile("mtmsr %0" : : "r" (msr));	64	asm volatile ("mtmsr %0"::"r" (msr));
63	}	65	}
64		66
65	static __inline__ unsigned long get_dec(void)	67	static __inline__ unsigned long get_dec (void)
66	{	68	{
67	unsigned long val;	69	unsigned long val;
68		70
69	asm volatile("mfdec %0" : "=r" (val) :);	71	asm volatile ("mfdec %0":"=r" (val):);
70	return val;	72
		73	return val;
71	}	74	}
72		75
73		76
74	static __inline__ void set_dec(unsigned long val)	77	static __inline__ void set_dec (unsigned long val)
75	{	78	{
76	asm volatile("mtdec %0" : : "r" (val));	79	asm volatile ("mtdec %0"::"r" (val));
77	}	80	}
78		81
79		82
80	void enable_interrupts (void)	83	void enable_interrupts (void)
81	{	84	{
82	set_msr (get_msr() \| MSR_EE);	85	set_msr (get_msr () \| MSR_EE);
83	}	86	}
84		87
85	/* returns flag if MSR_EE was set before */	88	/* returns flag if MSR_EE was set before */
86	int disable_interrupts (void)	89	int disable_interrupts (void)
87	{	90	{
88	ulong msr = get_msr();	91	ulong msr = get_msr ();
		92
89	set_msr (msr & ~MSR_EE);	93	set_msr (msr & ~MSR_EE);
90	return ((msr & MSR_EE) != 0);	94	return ((msr & MSR_EE) != 0);
91	}	95	}
92		96
93	/****************************************************************************/	97	/************************************************************************/
94		98
95	int interrupt_init(void)	99	int interrupt_init (void)
96	{	100	{
97	volatile immap_t immr = (immap_t )CFG_IMMR;	101	volatile immap_t immr = (immap_t ) CFG_IMMR;
98		102
99	decrementer_count = get_tbclk() / CFG_HZ;	103	decrementer_count = get_tbclk () / CFG_HZ;
100		104
101	cpm_interrupt_init();	105	/* disable all interrupts */
		106	immr->im_siu_conf.sc_simask = 0;
102		107
103	/* disable all interrupts except for the CPM interrupt */	108	/* Configure CPM interrupts */
104	immr->im_siu_conf.sc_simask = 1 << (31-CPM_INTERRUPT);	109	cpm_interrupt_init ();
105		110
106	set_dec (decrementer_count);	111	set_dec (decrementer_count);
107		112
108	set_msr (get_msr() \| MSR_EE);	113	set_msr (get_msr () \| MSR_EE);
109		114
110	return (0);	115	return (0);
111	}	116	}
112		117
113	/****************************************************************************/	118	/************************************************************************/
114		119
115	/*	120	/*
116	* Handle external interrupts	121	* Handle external interrupts
117	*/	122	*/
118	void external_interrupt(struct pt_regs *regs)	123	void external_interrupt (struct pt_regs *regs)
119	{	124	{
120	volatile immap_t immr = (immap_t )CFG_IMMR;	125	volatile immap_t immr = (immap_t ) CFG_IMMR;
121	int irq;	126	int irq;
122	ulong simask, newmask;	127	ulong simask, newmask;
123	ulong vec, v_bit;	128	ulong vec, v_bit;
124		129
125	/*	130	/*
126	* read the SIVEC register and shift the bits down	131	* read the SIVEC register and shift the bits down
127	* to get the irq number	132	* to get the irq number
128	*/	133	*/
129	vec = immr->im_siu_conf.sc_sivec;	134	vec = immr->im_siu_conf.sc_sivec;
130	irq = vec >> 26;	135	irq = vec >> 26;
131	v_bit = 0x80000000UL >> irq;	136	v_bit = 0x80000000UL >> irq;
132		137
133	/*	138	/*
134	* Read Interrupt Mask Register and Mask Interrupts	139	* Read Interrupt Mask Register and Mask Interrupts
135	*/	140	*/
136	simask = immr->im_siu_conf.sc_simask;	141	simask = immr->im_siu_conf.sc_simask;
137	newmask = simask & (~(0xFFFF0000 >> irq));	142	newmask = simask & (~(0xFFFF0000 >> irq));
138	immr->im_siu_conf.sc_simask = newmask;	143	immr->im_siu_conf.sc_simask = newmask;
139		144
140	if (!(irq & 0x1)) { /* External Interrupt ? */	145	if (!(irq & 0x1)) { /* External Interrupt ? */
141	ulong siel;	146	ulong siel;
		147
142	/*	148	/*
143	* Read Interrupt Edge/Level Register	149	* Read Interrupt Edge/Level Register
144	*/	150	*/
145	siel = immr->im_siu_conf.sc_siel;	151	siel = immr->im_siu_conf.sc_siel;
146		152
147	if (siel & v_bit) { /* edge triggered interrupt ? */	153	if (siel & v_bit) { /* edge triggered interrupt ? */
148	/*	154	/*
149	* Rewrite SIPEND Register to clear interrupt	155	* Rewrite SIPEND Register to clear interrupt
150	*/	156	*/
151	immr->im_siu_conf.sc_sipend = v_bit;	157	immr->im_siu_conf.sc_sipend = v_bit;
152	}	158	}
153	}	159	}
154		160
155	switch (irq) {	161	if (irq_vecs[irq].handler != NULL) {
156	case CPM_INTERRUPT:	162	irq_vecs[irq].handler (irq_vecs[irq].arg);
157	cpm_interrupt (irq, regs);	163	} else {
158	break;
159	default:
160	printf ("\nBogus External Interrupt IRQ %d Vector %ld\n",	164	printf ("\nBogus External Interrupt IRQ %d Vector %ld\n",
161	irq, vec);	165	irq, vec);
162	/* turn off the bogus interrupt to avoid it from now */	166	/* turn off the bogus interrupt to avoid it from now */
163	simask &= ~v_bit;	167	simask &= ~v_bit;
164	break;
165	}	168	}
166
167	/*	169	/*
168	* Re-Enable old Interrupt Mask	170	* Re-Enable old Interrupt Mask
169	*/	171	*/
170	immr->im_siu_conf.sc_simask = simask;	172	immr->im_siu_conf.sc_simask = simask;
171	}	173	}
172		174
173	/****************************************************************************/	175	/************************************************************************/
174		176
175	/*	177	/*
176	* CPM interrupt handler	178	* CPM interrupt handler
177	*/	179	*/
178	static void	180	static void cpm_interrupt (void *regs)
179	cpm_interrupt(int irq, struct pt_regs * regs)
180	{	181	{
181	volatile immap_t immr = (immap_t )CFG_IMMR;	182	volatile immap_t immr = (immap_t ) CFG_IMMR;
182	uint vec;	183	uint vec;
183		184
184	/*	185	/*
185	* Get the vector by setting the ACK bit	186	* Get the vector by setting the ACK bit
186	* and then reading the register.	187	* and then reading the register.
187	*/	188	*/
188	immr->im_cpic.cpic_civr = 1;	189	immr->im_cpic.cpic_civr = 1;
189	vec = immr->im_cpic.cpic_civr;	190	vec = immr->im_cpic.cpic_civr;
190	vec >>= 11;	191	vec >>= 11;
191		192
192	if (cpm_vecs[vec].handler != NULL) {	193	if (cpm_vecs[vec].handler != NULL) {
193	(*cpm_vecs[vec].handler)(cpm_vecs[vec].arg);	194	(*cpm_vecs[vec].handler) (cpm_vecs[vec].arg);
194	} else {	195	} else {
195	immr->im_cpic.cpic_cimr &= ~(1 << vec);	196	immr->im_cpic.cpic_cimr &= ~(1 << vec);
196	printf ("Masking bogus CPM interrupt vector 0x%x\n", vec);	197	printf ("Masking bogus CPM interrupt vector 0x%x\n", vec);
197	}	198	}
198	/*	199	/*
199	* After servicing the interrupt, we have to remove the status indicator.	200	* After servicing the interrupt,
		201	* we have to remove the status indicator.
200	*/	202	*/
201	immr->im_cpic.cpic_cisr \|= (1 << vec);	203	immr->im_cpic.cpic_cisr \|= (1 << vec);
202	}	204	}
203		205
204	/*	206	/*
205	* The CPM can generate the error interrupt when there is a race	207	* The CPM can generate the error interrupt when there is a race
206	* condition between generating and masking interrupts. All we have	208	* condition between generating and masking interrupts. All we have
207	* to do is ACK it and return. This is a no-op function so we don't	209	* to do is ACK it and return. This is a no-op function so we don't
208	* need any special tests in the interrupt handler.	210	* need any special tests in the interrupt handler.
209	*/	211	*/
210	static void	212	static void cpm_error_interrupt (void *dummy)
211	cpm_error_interrupt (void *dummy)
212	{	213	{
213	}	214	}
214		215
215	/****************************************************************************/	216	/************************************************************************/
216
217	/*	217	/*
218	* Install and free a CPM interrupt handler.	218	* Install and free an interrupt handler
219	*/	219	*/
220		220	void irq_install_handler (int vec, interrupt_handler_t * handler,
221	void	221	void *arg)
222	irq_install_handler(int vec, interrupt_handler_t handler, void arg)
223	{	222	{
224	volatile immap_t immr = (immap_t )CFG_IMMR;	223	volatile immap_t immr = (immap_t ) CFG_IMMR;
225		224
226	if (cpm_vecs[vec].handler != NULL) {	225	if ((vec & CPMVEC_OFFSET) != 0) {
227	printf ("CPM interrupt 0x%x replacing 0x%x\n",	226	/* CPM interrupt */
228	(uint)handler, (uint)cpm_vecs[vec].handler);	227	vec &= 0xffff;
229	}	228	if (cpm_vecs[vec].handler != NULL) {
230	cpm_vecs[vec].handler = handler;	229	printf ("CPM interrupt 0x%x replacing 0x%x\n",
231	cpm_vecs[vec].arg = arg;	230	(uint) handler,
232	immr->im_cpic.cpic_cimr \|= (1 << vec);	231	(uint) cpm_vecs[vec].handler);
		232	}
		233	cpm_vecs[vec].handler = handler;
		234	cpm_vecs[vec].arg = arg;
		235	immr->im_cpic.cpic_cimr \|= (1 << vec);
233	#if 0	236	#if 0
234	printf ("Install CPM interrupt for vector %d ==> %p\n", vec, handler);	237	printf ("Install CPM interrupt for vector %d ==> %p\n",
		238	vec, handler);
235	#endif	239	#endif
		240	} else {
		241	/* SIU interrupt */
		242	if (irq_vecs[vec].handler != NULL) {
		243	printf ("SIU interrupt %d 0x%x replacing 0x%x\n",
		244	vec,
		245	(uint) handler,
		246	(uint) cpm_vecs[vec].handler);
		247	}
		248	irq_vecs[vec].handler = handler;
		249	irq_vecs[vec].arg = arg;
		250	immr->im_siu_conf.sc_simask \|= 1 << (31 - vec);
		251	#if 0
		252	printf ("Install SIU interrupt for vector %d ==> %p\n",
		253	vec, handler);
		254	#endif
		255	}
236	}	256	}
237		257
238	void	258	void irq_free_handler (int vec)
239	irq_free_handler(int vec)
240	{	259	{
241	volatile immap_t immr = (immap_t )CFG_IMMR;	260	volatile immap_t immr = (immap_t ) CFG_IMMR;
		261
		262	if ((vec & CPMVEC_OFFSET) != 0) {
		263	/* CPM interrupt */
		264	vec &= 0xffff;
242	#if 0	265	#if 0
243	printf ("Free CPM interrupt for vector %d ==> %p\n",	266	printf ("Free CPM interrupt for vector %d ==> %p\n",
244	vec, cpm_vecs[vec].handler);	267	vec, cpm_vecs[vec].handler);
245	#endif	268	#endif
246	immr->im_cpic.cpic_cimr &= ~(1 << vec);	269	immr->im_cpic.cpic_cimr &= ~(1 << vec);
247	cpm_vecs[vec].handler = NULL;	270	cpm_vecs[vec].handler = NULL;
248	cpm_vecs[vec].arg = NULL;	271	cpm_vecs[vec].arg = NULL;
		272	} else {
		273	/* SIU interrupt */
		274	#if 0
		275	printf ("Free CPM interrupt for vector %d ==> %p\n",
		276	vec, cpm_vecs[vec].handler);
		277	#endif
		278	immr->im_siu_conf.sc_simask &= ~(1 << (31 - vec));
		279	irq_vecs[vec].handler = NULL;
		280	irq_vecs[vec].arg = NULL;
		281	}
249	}	282	}
250		283
251	/****************************************************************************/	284	/************************************************************************/
252		285
253	static void	286	static void cpm_interrupt_init (void)
254	cpm_interrupt_init (void)
255	{	287	{
256	volatile immap_t immr = (immap_t )CFG_IMMR;	288	volatile immap_t immr = (immap_t ) CFG_IMMR;
257		289
258	/*	290	/*
259	* Initialize the CPM interrupt controller.	291	* Initialize the CPM interrupt controller.
260	*/	292	*/
261		293
262	immr->im_cpic.cpic_cicr =	294	immr->im_cpic.cpic_cicr =
263	( CICR_SCD_SCC4 \|	295	(CICR_SCD_SCC4 \|
264	CICR_SCC_SCC3 \|	296	CICR_SCC_SCC3 \|
265	CICR_SCB_SCC2 \|	297	CICR_SCB_SCC2 \|
266	CICR_SCA_SCC1 ) \| ((CPM_INTERRUPT/2) << 13) \| CICR_HP_MASK;	298	CICR_SCA_SCC1) \| ((CPM_INTERRUPT / 2) << 13) \| CICR_HP_MASK;
267		299
268	immr->im_cpic.cpic_cimr = 0;	300	immr->im_cpic.cpic_cimr = 0;
269		301
270	/*	302	/*
271	* Install the error handler.	303	* Install the error handler.
272	*/	304	*/
273	irq_install_handler(CPMVEC_ERROR, cpm_error_interrupt, NULL);	305	irq_install_handler (CPMVEC_ERROR, cpm_error_interrupt, NULL);
274		306
275	immr->im_cpic.cpic_cicr \|= CICR_IEN;	307	immr->im_cpic.cpic_cicr \|= CICR_IEN;
		308
		309	/*
		310	* Install the cpm interrupt handler
		311	*/
		312	irq_install_handler (CPM_INTERRUPT, cpm_interrupt, NULL);
276	}	313	}
277		314
278	/****************************************************************************/	315	/************************************************************************/
279		316
280	volatile ulong timestamp = 0;	317	volatile ulong timestamp = 0;
281		318
282	/*	319	/*
283	* timer_interrupt - gets called when the decrementer overflows,	320	* timer_interrupt - gets called when the decrementer overflows,
284	* with interrupts disabled.	321	* with interrupts disabled.
285	* Trivial implementation - no need to be really accurate.	322	* Trivial implementation - no need to be really accurate.
286	*/	323	*/
287	void timer_interrupt(struct pt_regs *regs)	324	void timer_interrupt (struct pt_regs *regs)
288	{	325	{
289	volatile immap_t immr = (immap_t )CFG_IMMR;	326	volatile immap_t immr = (immap_t ) CFG_IMMR;
		327
290	#ifdef CONFIG_STATUS_LED	328	#ifdef CONFIG_STATUS_LED
291	extern void status_led_tick (ulong);	329	extern void status_led_tick (ulong);
292	#endif	330	#endif
293	#if 0	331	#if 0
294	printf ("* Timer Interrupt * ");	332	printf ("* Timer Interrupt * ");
295	#endif	333	#endif
296	/* Reset Timer Expired and Timers Interrupt Status */	334	/* Reset Timer Expired and Timers Interrupt Status */
297	immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;	335	immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
298	__asm__("nop");	336	__asm__ ("nop");
299	immr->im_clkrst.car_plprcr \|= PLPRCR_TEXPS \| PLPRCR_TMIST;	337	immr->im_clkrst.car_plprcr \|= PLPRCR_TEXPS \| PLPRCR_TMIST;
300	/* Restore Decrementer Count */	338	/* Restore Decrementer Count */
301	set_dec (decrementer_count);	339	set_dec (decrementer_count);
302		340
303	timestamp++;	341	timestamp++;
304		342
305	#ifdef CONFIG_STATUS_LED	343	#ifdef CONFIG_STATUS_LED
306	status_led_tick (timestamp);	344	status_led_tick (timestamp);
307	#endif /* CONFIG_STATUS_LED */	345	#endif /* CONFIG_STATUS_LED */
308		346
309	#if defined(CONFIG_WATCHDOG) \|\| defined(CFG_CMA_LCD_HEARTBEAT)	347	#if defined(CONFIG_WATCHDOG) \|\| defined(CFG_CMA_LCD_HEARTBEAT)
310		348
311
312	/*	349	/*
313	* The shortest watchdog period of all boards (except LWMON)	350	* The shortest watchdog period of all boards (except LWMON)
314	* is approx. 1 sec, thus re-trigger watchdog at least	351	* is approx. 1 sec, thus re-trigger watchdog at least
315	* every 500 ms = CFG_HZ / 2	352	* every 500 ms = CFG_HZ / 2
316	*/	353	*/
317	#ifndef CONFIG_LWMON	354	#ifndef CONFIG_LWMON
318	if ((timestamp % (CFG_HZ / 2)) == 0) {	355	if ((timestamp % (CFG_HZ / 2)) == 0) {
319	#else	356	#else
320	if ((timestamp % (CFG_HZ / 20)) == 0) {	357	if ((timestamp % (CFG_HZ / 20)) == 0) {
321	#endif	358	#endif
322		359
323	#if defined(CFG_CMA_LCD_HEARTBEAT)	360	#if defined(CFG_CMA_LCD_HEARTBEAT)
324	extern void lcd_heartbeat(void);	361	extern void lcd_heartbeat (void);
325	lcd_heartbeat();	362
		363	lcd_heartbeat ();
326	#endif /* CFG_CMA_LCD_HEARTBEAT */	364	#endif /* CFG_CMA_LCD_HEARTBEAT */
327		365
328	#if defined(CONFIG_WATCHDOG)	366	#if defined(CONFIG_WATCHDOG)
329	reset_8xx_watchdog(immr);	367	reset_8xx_watchdog (immr);
330	#endif /* CONFIG_WATCHDOG */	368	#endif /* CONFIG_WATCHDOG */
331		369
332	}	370	}
333
334	#endif /* CONFIG_WATCHDOG \|\| CFG_CMA_LCD_HEARTBEAT */	371	#endif /* CONFIG_WATCHDOG \|\| CFG_CMA_LCD_HEARTBEAT */
335	}	372	}
336		373
337	/****************************************************************************/	374	/************************************************************************/
338		375
339	void reset_timer (void)	376	void reset_timer (void)
340	{	377	{
341	timestamp = 0;	378	timestamp = 0;
342	}	379	}
343		380

cpu/mpc8xx/start.S

Diff comments View file @ 7c7a23b

 /*
  *  Copyright (C) 1998	Dan Malek <dmalek@jlc.net>
  *  Copyright (C) 1999	Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
  *  Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 /*  U-Boot - Startup Code for PowerPC based Embedded Boards
  *
  *
  *  The processor starts at 0x00000100 and the code is executed
  *  from flash. The code is organized to be at an other address
  *  in memory, but as long we don't jump around before relocating.
  *  board_init lies at a quite high address and when the cpu has
  *  jumped there, everything is ok.
  *  This works because the cpu gives the FLASH (CS0) the whole
  *  address space at startup, and board_init lies as a echo of
  *  the flash somewhere up there in the memorymap.
  *
  *  board_init will change CS0 to be positioned at the correct
  *  address and (s)dram will be positioned at address 0
  */
 #include <config.h>
 #include <mpc8xx.h>
 #include <version.h>
 #define CONFIG_8xx 1		/* needed for Linux kernel header files */
 #define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
 #include <ppc_asm.tmpl>
 #include <ppc_defs.h>
 #include <asm/cache.h>
 #include <asm/mmu.h>
 #ifndef  CONFIG_IDENT_STRING
 #define  CONFIG_IDENT_STRING ""
 #endif
 /* We don't want the  MMU yet.
 */
 #undef	MSR_KERNEL
 #define MSR_KERNEL ( MSR_ME | MSR_RI )	/* Machine Check and Recoverable Interr. */
 /*
  * Set up GOT: Global Offset Table
  *
  * Use r14 to access the GOT
  */
 	START_GOT
 	GOT_ENTRY(_GOT2_TABLE_)
 	GOT_ENTRY(_FIXUP_TABLE_)
 	GOT_ENTRY(_start)
 	GOT_ENTRY(_start_of_vectors)
 	GOT_ENTRY(_end_of_vectors)
 	GOT_ENTRY(transfer_to_handler)
 	GOT_ENTRY(_end)
 	GOT_ENTRY(.bss)
 #if defined(CONFIG_FADS) || defined(CONFIG_ICU862)
 	GOT_ENTRY(environment)
 #endif
 	END_GOT
 /*
  * r3 - 1st arg to board_init(): IMMP pointer
  * r4 - 2nd arg to board_init(): boot flag
  */
 	.text
 	.long	0x27051956		/* U-Boot Magic Number			*/
 	.globl	version_string
 version_string:
 	.ascii U_BOOT_VERSION
 	.ascii " (", __DATE__, " - ", __TIME__, ")"
 	.ascii CONFIG_IDENT_STRING, "\0"
 	. = EXC_OFF_SYS_RESET
 	.globl	_start
 _start:
 	lis	r3, CFG_IMMR@h		/* position IMMR */
 	mtspr	638, r3
 	li	r21, BOOTFLAG_COLD	/* Normal Power-On: Boot from FLASH	*/
 	b	boot_cold
 	. = EXC_OFF_SYS_RESET + 0x10
 	.globl	_start_warm
 _start_warm:
 	li	r21, BOOTFLAG_WARM	/* Software reboot			*/
 	b	boot_warm
 boot_cold:
 boot_warm:
 	/* Initialize machine status; enable machine check interrupt		*/
 	/*----------------------------------------------------------------------*/
 	li	r3, MSR_KERNEL		/* Set ME, RI flags */
 	mtmsr	r3
 	mtspr	SRR1, r3		/* Make SRR1 match MSR */
 	mfspr	r3, ICR			/* clear Interrupt Cause Register */
 	/* Initialize debug port registers					*/
 	/*----------------------------------------------------------------------*/
 	xor	r0, r0, r0		/* Clear R0 */
 	mtspr	LCTRL1, r0		/* Initialize debug port regs */
 	mtspr	LCTRL2, r0
 	mtspr	COUNTA, r0
 	mtspr	COUNTB, r0
 	/* Reset the caches							*/
 	/*----------------------------------------------------------------------*/
 	mfspr	r3, IC_CST		/* Clear error bits */
 	mfspr	r3, DC_CST
 	lis	r3, IDC_UNALL@h		/* Unlock all */
 	mtspr	IC_CST, r3
 	mtspr	DC_CST, r3
 	lis	r3, IDC_INVALL@h	/* Invalidate all */
 	mtspr	IC_CST, r3
 	mtspr	DC_CST, r3
 	lis	r3, IDC_DISABLE@h	/* Disable data cache */
 	mtspr	DC_CST, r3
 #if !(defined(CONFIG_IP860) || defined(CONFIG_PCU_E) || defined (CONFIG_FLAGADM))
 					/* On IP860 and PCU E,
 					 * we cannot enable IC yet
 					 */
 	lis	r3, IDC_ENABLE@h	/* Enable instruction cache */
 #endif
 	mtspr	IC_CST, r3
 	/* invalidate all tlb's							*/
 	/*----------------------------------------------------------------------*/
 	tlbia
 	isync
 	/*
 	 * Calculate absolute address in FLASH and jump there
 	 *----------------------------------------------------------------------*/
 	lis	r3, CFG_MONITOR_BASE@h
 	ori	r3, r3, CFG_MONITOR_BASE@l
 	addi	r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
 	mtlr	r3
 	blr
 in_flash:
 	/* initialize some SPRs that are hard to access from C			*/
 	/*----------------------------------------------------------------------*/
 	lis	r3, CFG_IMMR@h		/* pass IMMR as arg1 to C routine */
 	ori	r1, r3, CFG_INIT_SP_OFFSET /* set up the stack in internal DPRAM */
 	/* Note: R0 is still 0 here */
 	stwu	r0, -4(r1)		/* clear final stack frame so that	*/
 	stwu	r0, -4(r1)		/* stack backtraces terminate cleanly	*/
 	/*
 	 * Disable serialized ifetch and show cycles
 	 * (i.e. set processor to normal mode).
 	 * This is also a silicon bug workaround, see errata
 	 */
 	li	r2, 0x0007
 	mtspr	ICTRL, r2
 	/* Set up debug mode entry */
 	lis	r2, CFG_DER@h
 	ori	r2, r2, CFG_DER@l
 	mtspr	DER, r2
 	/* let the C-code set up the rest					*/
 	/*									*/
 	/* Be careful to keep code relocatable !				*/
 	/*----------------------------------------------------------------------*/
 	GET_GOT			/* initialize GOT access			*/
 	/* r3: IMMR */
 	bl	cpu_init_f	/* run low-level CPU init code     (from Flash)	*/
 	mr	r3, r21
 	/* r3: BOOTFLAG */
 	bl	board_init_f	/* run 1st part of board init code (from Flash) */
 	.globl	_start_of_vectors
 _start_of_vectors:
 /* Machine check */
 	STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
 /* Data Storage exception.  "Never" generated on the 860. */
 	STD_EXCEPTION(0x300, DataStorage, UnknownException)
 /* Instruction Storage exception.  "Never" generated on the 860. */
 	STD_EXCEPTION(0x400, InstStorage, UnknownException)
 /* External Interrupt exception. */
 	STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
 /* Alignment exception. */
 	. = 0x600
 Alignment:
 	EXCEPTION_PROLOG
 	mfspr	r4,DAR
 	stw	r4,_DAR(r21)
 	mfspr	r5,DSISR
 	stw	r5,_DSISR(r21)
 	addi	r3,r1,STACK_FRAME_OVERHEAD
 	li	r20,MSR_KERNEL
 	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
 	lwz	r6,GOT(transfer_to_handler)
 	mtlr	r6
 	blrl
 .L_Alignment:
 	.long	AlignmentException - _start + EXC_OFF_SYS_RESET
 	.long	int_return - _start + EXC_OFF_SYS_RESET
 /* Program check exception */
 	. = 0x700
 ProgramCheck:
 	EXCEPTION_PROLOG
 	addi	r3,r1,STACK_FRAME_OVERHEAD
 	li	r20,MSR_KERNEL
 	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
 	lwz	r6,GOT(transfer_to_handler)
 	mtlr	r6
 	blrl
 .L_ProgramCheck:
 	.long	ProgramCheckException - _start + EXC_OFF_SYS_RESET
 	.long	int_return - _start + EXC_OFF_SYS_RESET
 	/* No FPU on MPC8xx.  This exception is not supposed to happen.
 	*/
 	STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
 	/* I guess we could implement decrementer, and may have
 	 * to someday for timekeeping.
 	 */
 	STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
 	STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
 	STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
 	. = 0xc00
 /*
  * r0 - SYSCALL number
  * r3-... arguments
  */
 SystemCall:
 	addis	r11,r0,0		/* get functions table addr */
 	ori	r11,r11,0		/* Note: this code is patched in trap_init */
 	addis	r12,r0,0		/* get number of functions */
 	ori	r12,r12,0
 	cmplw	0, r0, r12
 	bge	1f
 	rlwinm	r0,r0,2,0,31		/* fn_addr = fn_tbl[r0] */
 	add	r11,r11,r0
 	lwz	r11,0(r11)
-	li	r12,0xd00-4*3		/* save LR & SRRx */
+	li	r20,0xd00-4		/* Get stack pointer */
+	lwz	r12,0(r20)
+	subi	r12,r12,12		/* Adjust stack pointer */
+	li	r0,0xc00+_end_back-SystemCall
+	cmplw	0, r0, r12		/* Check stack overflow */
+	bgt	1f
+	stw	r12,0(r20)
 	mflr	r0
 	stw	r0,0(r12)
 	mfspr	r0,SRR0
 	stw	r0,4(r12)
 	mfspr	r0,SRR1
 	stw	r0,8(r12)
 	li	r12,0xc00+_back-SystemCall
 	mtlr	r12
 	mtspr	SRR0,r11
 1:	SYNC
 	rfi
 _back:
 	mfmsr	r11			/* Disable interrupts */
 	li	r12,0
 	ori	r12,r12,MSR_EE
 	andc	r11,r11,r12
 	SYNC				/* Some chip revs need this... */
 	mtmsr	r11
 	SYNC
-	li	r12,0xd00-4*3		/* restore regs */
+	li	r12,0xd00-4		/* restore regs */
+	lwz	r12,0(r12)
 	lwz	r11,0(r12)
 	mtlr	r11
 	lwz	r11,4(r12)
 	mtspr	SRR0,r11
 	lwz	r11,8(r12)
 	mtspr	SRR1,r11
+	addi	r12,r12,12		/* Adjust stack pointer */
+	li	r20,0xd00-4
+	stw	r12,0(r20)
 	SYNC
 	rfi
+_end_back:
 	STD_EXCEPTION(0xd00, SingleStep, UnknownException)
 	STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
 	STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
 	/* On the MPC8xx, this is a software emulation interrupt.  It occurs
 	 * for all unimplemented and illegal instructions.
 	 */
 	STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
 	STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
 	STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
 	STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
 	STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
 	STD_EXCEPTION(0x1500, Reserved5, UnknownException)
 	STD_EXCEPTION(0x1600, Reserved6, UnknownException)
 	STD_EXCEPTION(0x1700, Reserved7, UnknownException)
 	STD_EXCEPTION(0x1800, Reserved8, UnknownException)
 	STD_EXCEPTION(0x1900, Reserved9, UnknownException)
 	STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
 	STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
 	STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
 	STD_EXCEPTION(0x1d00, InstructionBreakpoint, DebugException)
 	STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
 	STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
 	.globl	_end_of_vectors
 _end_of_vectors:
 	. = 0x2000
 /*
  * This code finishes saving the registers to the exception frame
  * and jumps to the appropriate handler for the exception.
  * Register r21 is pointer into trap frame, r1 has new stack pointer.
  */
 	.globl	transfer_to_handler
 transfer_to_handler:
 	stw	r22,_NIP(r21)
 	lis	r22,MSR_POW@h
 	andc	r23,r23,r22
 	stw	r23,_MSR(r21)
 	SAVE_GPR(7, r21)
 	SAVE_4GPRS(8, r21)
 	SAVE_8GPRS(12, r21)
 	SAVE_8GPRS(24, r21)
 	mflr	r23
 	andi.	r24,r23,0x3f00		/* get vector offset */
 	stw	r24,TRAP(r21)
 	li	r22,0
 	stw	r22,RESULT(r21)
 	mtspr	SPRG2,r22		/* r1 is now kernel sp */
 	lwz	r24,0(r23)		/* virtual address of handler */
 	lwz	r23,4(r23)		/* where to go when done */
 	mtspr	SRR0,r24
 	mtspr	SRR1,r20
 	mtlr	r23
 	SYNC
 	rfi				/* jump to handler, enable MMU */
 int_return:
 	mfmsr	r28			/* Disable interrupts */
 	li	r4,0
 	ori	r4,r4,MSR_EE
 	andc	r28,r28,r4
 	SYNC				/* Some chip revs need this... */
 	mtmsr	r28
 	SYNC
 	lwz	r2,_CTR(r1)
 	lwz	r0,_LINK(r1)
 	mtctr	r2
 	mtlr	r0
 	lwz	r2,_XER(r1)
 	lwz	r0,_CCR(r1)
 	mtspr	XER,r2
 	mtcrf	0xFF,r0
 	REST_10GPRS(3, r1)
 	REST_10GPRS(13, r1)
 	REST_8GPRS(23, r1)
 	REST_GPR(31, r1)
 	lwz	r2,_NIP(r1)		/* Restore environment */
 	lwz	r0,_MSR(r1)
 	mtspr	SRR0,r2
 	mtspr	SRR1,r0
 	lwz	r0,GPR0(r1)
 	lwz	r2,GPR2(r1)
 	lwz	r1,GPR1(r1)
 	SYNC
 	rfi
 /* Cache functions.
 */
 	.globl	icache_enable
 icache_enable:
 	SYNC
 	lis	r3, IDC_INVALL@h
 	mtspr	IC_CST, r3
 	lis	r3, IDC_ENABLE@h
 	mtspr	IC_CST, r3
 	blr
 	.globl	icache_disable
 icache_disable:
 	SYNC
 	lis	r3, IDC_DISABLE@h
 	mtspr	IC_CST, r3
 	blr
 	.globl	icache_status
 icache_status:
 	mfspr	r3, IC_CST
 	srwi	r3, r3, 31	/* >>31 => select bit 0 */
 	blr
 	.globl	dcache_enable
 dcache_enable:
 #if 0
 	SYNC
 #endif
 #if 1
 	lis	r3, 0x0400		/* Set cache mode with MMU off */
 	mtspr	MD_CTR, r3
 #endif
 	lis	r3, IDC_INVALL@h
 	mtspr	DC_CST, r3
 #if 0
 	lis	r3, DC_SFWT@h
 	mtspr	DC_CST, r3
 #endif
 	lis	r3, IDC_ENABLE@h
 	mtspr	DC_CST, r3
 	blr
 	.globl	dcache_disable
 dcache_disable:
 	SYNC
 	lis	r3, IDC_DISABLE@h
 	mtspr	DC_CST, r3
 	lis	r3, IDC_INVALL@h
 	mtspr	DC_CST, r3
 	blr
 	.globl	dcache_status
 dcache_status:
 	mfspr	r3, DC_CST
 	srwi	r3, r3, 31	/* >>31 => select bit 0 */
 	blr
 	.globl	dc_read
 dc_read:
 	mtspr	DC_ADR, r3
 	mfspr	r3, DC_DAT
 	blr
 /*
  * unsigned int get_immr (unsigned int mask)
  *
  * return (mask ? (IMMR & mask) : IMMR);
  */
 	.globl	get_immr
 get_immr:
 	mr	r4,r3		/* save mask */
 	mfspr	r3, IMMR	/* IMMR */
 	cmpwi	0,r4,0		/* mask != 0 ? */
 	beq	4f
 	and	r3,r3,r4	/* IMMR & mask */
 4:
 	blr
 	.globl get_pvr
 get_pvr:
 	mfspr	r3, PVR
 	blr
 	.globl wr_ic_cst
 wr_ic_cst:
 	mtspr	IC_CST, r3
 	blr
 	.globl rd_ic_cst
 rd_ic_cst:
 	mfspr	r3, IC_CST
 	blr
 	.globl wr_ic_adr
 wr_ic_adr:
 	mtspr	IC_ADR, r3
 	blr
 	.globl wr_dc_cst
 wr_dc_cst:
 	mtspr	DC_CST, r3
 	blr
 	.globl rd_dc_cst
 rd_dc_cst:
 	mfspr	r3, DC_CST
 	blr
 	.globl wr_dc_adr
 wr_dc_adr:
 	mtspr	DC_ADR, r3
 	blr
 /*------------------------------------------------------------------------------*/
 /*
  * void relocate_code (addr_sp, gd, addr_moni)
  *
  * This "function" does not return, instead it continues in RAM
  * after relocating the monitor code.
  *
  * r3 = dest
  * r4 = src
  * r5 = length in bytes
  * r6 = cachelinesize
  */
 	.globl	relocate_code
 relocate_code:
 	mr	r1,  r3		/* Set new stack pointer		*/
 	mr	r9,  r4		/* Save copy of Global Data pointer	*/
 	mr	r10, r5		/* Save copy of Destination Address	*/
 	mr	r3,  r5				/* Destination Address	*/
 	lis	r4, CFG_MONITOR_BASE@h		/* Source      Address	*/
 	ori	r4, r4, CFG_MONITOR_BASE@l
 	lis	r5, CFG_MONITOR_LEN@h		/* Length in Bytes	*/
 	ori	r5, r5, CFG_MONITOR_LEN@l
 	li	r6, CFG_CACHELINE_SIZE		/* Cache Line Size	*/
 	/*
 	 * Fix GOT pointer:
 	 *
 	 * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
 	 *
 	 * Offset:
 	 */
 	sub	r15, r10, r4
 	/* First our own GOT */
 	add	r14, r14, r15
 	/* the the one used by the C code */
 	add	r30, r30, r15
 	/*
 	 * Now relocate code
 	 */
 	cmplw	cr1,r3,r4
 	addi	r0,r5,3
 	srwi.	r0,r0,2
 	beq	cr1,4f		/* In place copy is not necessary	*/
 	beq	7f		/* Protect against 0 count		*/
 	mtctr	r0
 	bge	cr1,2f
 	la	r8,-4(r4)
 	la	r7,-4(r3)
 1:	lwzu	r0,4(r8)
 	stwu	r0,4(r7)
 	bdnz	1b
 	b	4f
 2:	slwi	r0,r0,2
 	add	r8,r4,r0
 	add	r7,r3,r0
 3:	lwzu	r0,-4(r8)
 	stwu	r0,-4(r7)
 	bdnz	3b
 /*
  * Now flush the cache: note that we must start from a cache aligned
  * address. Otherwise we might miss one cache line.
  */
 4:	cmpwi	r6,0
 	add	r5,r3,r5
 	beq	7f		/* Always flush prefetch queue in any case */
 	subi	r0,r6,1
 	andc	r3,r3,r0
 	mr	r4,r3
 5:	dcbst	0,r4
 	add	r4,r4,r6
 	cmplw	r4,r5
 	blt	5b
 	sync			/* Wait for all dcbst to complete on bus */
 	mr	r4,r3
 6:	icbi	0,r4
 	add	r4,r4,r6
 	cmplw	r4,r5
 	blt	6b
 7:	sync			/* Wait for all icbi to complete on bus	*/
 	isync
 /*
  * We are done. Do not return, instead branch to second part of board
  * initialization, now running from RAM.
  */
 	addi	r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
 	mtlr	r0
 	blr
 in_ram:
 	/*
 	 * Relocation Function, r14 point to got2+0x8000
 	 *
          * Adjust got2 pointers, no need to check for 0, this code
          * already puts a few entries in the table.
 	 */
 	li	r0,__got2_entries@sectoff@l
 	la	r3,GOT(_GOT2_TABLE_)
 	lwz	r11,GOT(_GOT2_TABLE_)
 	mtctr	r0
 	sub	r11,r3,r11
 	addi	r3,r3,-4
 1:	lwzu	r0,4(r3)
 	add	r0,r0,r11
 	stw	r0,0(r3)
 	bdnz	1b
 	/*
          * Now adjust the fixups and the pointers to the fixups
 	 * in case we need to move ourselves again.
 	 */
 2:	li	r0,__fixup_entries@sectoff@l
 	lwz	r3,GOT(_FIXUP_TABLE_)
 	cmpwi	r0,0
 	mtctr	r0
 	addi	r3,r3,-4
 	beq	4f
 3:	lwzu	r4,4(r3)
 	lwzux	r0,r4,r11
 	add	r0,r0,r11
 	stw	r10,0(r3)
 	stw	r0,0(r4)
 	bdnz	3b
 4:
 clear_bss:
 	/*
 	 * Now clear BSS segment
 	 */
 	lwz	r3,GOT(.bss)
 #if defined(CONFIG_FADS) || defined(CONFIG_ICU862)
 	/*
 	 * For the FADS - the environment is the very last item in flash.
 	 * The real .bss stops just before environment starts, so only
 	 * clear up to that point.
 	 */
 	lwz	r4,GOT(environment)
 #else
 	lwz	r4,GOT(_end)
 #endif
 	cmplw	0, r3, r4
 	beq	6f
 	li	r0, 0
 5:
 	stw	r0, 0(r3)
 	addi	r3, r3, 4
 	cmplw	0, r3, r4
 	bne	5b
 6:
 	mr	r3, r9		/* Global Data pointer		*/
 	mr	r4, r10		/* Destination Address		*/
 	bl	board_init_r
 	/* Problems accessing "end" in C, so do it here */
 	.globl	get_endaddr
 get_endaddr:
 	lwz	r3,GOT(_end)
 	blr
 	/*
 	 * Copy exception vector code to low memory
 	 *
 	 * r3: dest_addr
 	 * r7: source address, r8: end address, r9: target address
 	 */
 	.globl	trap_init
 trap_init:
 	lwz	r7, GOT(_start)
 	lwz	r8, GOT(_end_of_vectors)
 	rlwinm	r9, r7, 0, 22, 31	/* _start & 0x3FF	*/
 	cmplw	0, r7, r8
 	bgelr				/* return if r7>=r8 - just in case */
 	mflr	r4			/* save link register		*/
 1:
 	lwz	r0, 0(r7)
 	stw	r0, 0(r9)
 	addi	r7, r7, 4
 	addi	r9, r9, 4
 	cmplw	0, r7, r8
 	bne	1b
 	/*
 	 * relocate `hdlr' and `int_return' entries
 	 */
 	li	r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
 	li	r8, Alignment - _start + EXC_OFF_SYS_RESET
 2:
 	bl	trap_reloc
 	addi	r7, r7, 0x100		/* next exception vector	*/
 	cmplw	0, r7, r8
 	blt	2b
 	li	r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
 	bl	trap_reloc
 	li	r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
 	bl	trap_reloc
 	li	r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
 	li	r8, SystemCall - _start + EXC_OFF_SYS_RESET
 3:
 	bl	trap_reloc
 	addi	r7, r7, 0x100		/* next exception vector	*/
 	cmplw	0, r7, r8
 	blt	3b
 	li	r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
 	li	r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
 4:
 	bl	trap_reloc
 	addi	r7, r7, 0x100		/* next exception vector	*/
 	cmplw	0, r7, r8
 	blt	4b
 	mtlr	r4			/* restore link register	*/
 	blr
 	/*
 	 * Function: relocate entries for one exception vector
 	 */
 trap_reloc:
 	lwz	r0, 0(r7)		/* hdlr ...			*/
 	add	r0, r0, r3		/*  ... += dest_addr		*/
 	stw	r0, 0(r7)
 	lwz	r0, 4(r7)		/* int_return ...		*/
 	add	r0, r0, r3		/*  ... += dest_addr		*/
 	stw	r0, 4(r7)
 	sync
 	isync
 	blr

cpu/ppc4xx/start.S

Diff comments View file @ 7c7a23b

 /*
  *  Copyright (C) 1998	Dan Malek <dmalek@jlc.net>
  *  Copyright (C) 1999	Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
  *  Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 /*------------------------------------------------------------------------------+ */
 /* */
 /*	 This source code has been made available to you by IBM on an AS-IS */
 /*	 basis.	 Anyone receiving this source is licensed under IBM */
 /*	 copyrights to use it in any way he or she deems fit, including */
 /*	 copying it, modifying it, compiling it, and redistributing it either */
 /*	 with or without modifications.	 No license under IBM patents or */
 /*	 patent applications is to be implied by the copyright license. */
 /* */
 /*	 Any user of this software should understand that IBM cannot provide */
 /*	 technical support for this software and will not be responsible for */
 /*	 any consequences resulting from the use of this software. */
 /* */
 /*	 Any person who transfers this source code or any derivative work */
 /*	 must include the IBM copyright notice, this paragraph, and the */
 /*	 preceding two paragraphs in the transferred software. */
 /* */
 /*	 COPYRIGHT   I B M   CORPORATION 1995 */
 /*	 LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M */
 /*------------------------------------------------------------------------------- */
 /*  U-Boot - Startup Code for IBM 4xx PowerPC based Embedded Boards
  *
  *
  *  The processor starts at 0xfffffffc and the code is executed
  *  from flash/rom.
  *  in memory, but as long we don't jump around before relocating.
  *  board_init lies at a quite high address and when the cpu has
  *  jumped there, everything is ok.
  *  This works because the cpu gives the FLASH (CS0) the whole
  *  address space at startup, and board_init lies as a echo of
  *  the flash somewhere up there in the memorymap.
  *
  *  board_init will change CS0 to be positioned at the correct
  *  address and (s)dram will be positioned at address 0
  */
 #include <config.h>
 #include <mpc8xx.h>
 #include <ppc4xx.h>
 #include <version.h>
 #define _LINUX_CONFIG_H 1	/* avoid reading Linux autoconf.h file	*/
 #include <ppc_asm.tmpl>
 #include <ppc_defs.h>
 #include <asm/cache.h>
 #include <asm/mmu.h>
 #ifndef	 CONFIG_IDENT_STRING
 #define	 CONFIG_IDENT_STRING ""
 #endif
 #ifdef CFG_INIT_DCACHE_CS
 # if (CFG_INIT_DCACHE_CS == 0)
 #  define PBxAP pb0ap
 #  define PBxCR pb0cr
 # endif
 # if (CFG_INIT_DCACHE_CS == 1)
 #  define PBxAP pb1ap
 #  define PBxCR pb1cr
 # endif
 # if (CFG_INIT_DCACHE_CS == 2)
 #  define PBxAP pb2ap
 #  define PBxCR pb2cr
 # endif
 # if (CFG_INIT_DCACHE_CS == 3)
 #  define PBxAP pb3ap
 #  define PBxCR pb3cr
 # endif
 # if (CFG_INIT_DCACHE_CS == 4)
 #  define PBxAP pb4ap
 #  define PBxCR pb4cr
 # endif
 # if (CFG_INIT_DCACHE_CS == 5)
 #  define PBxAP pb5ap
 #  define PBxCR pb5cr
 # endif
 # if (CFG_INIT_DCACHE_CS == 6)
 #  define PBxAP pb6ap
 #  define PBxCR pb6cr
 # endif
 # if (CFG_INIT_DCACHE_CS == 7)
 #  define PBxAP pb7ap
 #  define PBxCR pb7cr
 # endif
 #endif /* CFG_INIT_DCACHE_CS */
 /* We don't want the  MMU yet.
 */
 #undef	MSR_KERNEL
 #define MSR_KERNEL ( MSR_ME  )	/* Machine Check */
 	.extern ext_bus_cntlr_init
 	.extern sdram_init
 /*
  * Set up GOT: Global Offset Table
  *
  * Use r14 to access the GOT
  */
 	START_GOT
 	GOT_ENTRY(_GOT2_TABLE_)
 	GOT_ENTRY(_FIXUP_TABLE_)
 	GOT_ENTRY(_start)
 	GOT_ENTRY(_start_of_vectors)
 	GOT_ENTRY(_end_of_vectors)
 	GOT_ENTRY(transfer_to_handler)
 	GOT_ENTRY(_end)
 	GOT_ENTRY(.bss)
 	END_GOT
 /*
  * 440 Startup -- on reset only the top 4k of the effective
  * address space is mapped in by an entry in the instruction
  * and data shadow TLB. The .bootpg section is located in the
  * top 4k & does only what's necessary to map in the the rest
  * of the boot rom. Once the boot rom is mapped in we can
  * proceed with normal startup.
  *
  * NOTE: CS0 only covers the top 2MB of the effective address
  * space after reset.
  */
 #if defined(CONFIG_440)
     .section .bootpg,"ax"
     .globl _start_440
 /**************************************************************************/
 _start_440:
 	/*----------------------------------------------------------------*/
 	/* Clear and set up some registers. */
 	/*----------------------------------------------------------------*/
 	iccci	r0,r0           /* NOTE: operands not used for 440 */
 	dccci	r0,r0           /* NOTE: operands not used for 440 */
 	sync
 	li	r0,0
 	mtspr	srr0,r0
 	mtspr	srr1,r0
 	mtspr	csrr0,r0
 	mtspr	csrr1,r0
 	/*----------------------------------------------------------------*/
 	/* Initialize debug */
 	/*----------------------------------------------------------------*/
 	mtspr	dbcr0,r0
 	mtspr	dbcr1,r0
 	mtspr	dbcr2,r0
 	mtspr	iac1,r0
 	mtspr	iac2,r0
 	mtspr	iac3,r0
 	mtspr	dac1,r0
 	mtspr	dac2,r0
 	mtspr	dvc1,r0
 	mtspr	dvc2,r0
 	mfspr	r1,dbsr
 	mtspr	dbsr,r1		/* Clear all valid bits */
 	/*----------------------------------------------------------------*/
 	/* CCR0 init */
 	/*----------------------------------------------------------------*/
 	/* Disable store gathering & broadcast, guarantee inst/data
 	* cache block touch, force load/store alignment
 	* (see errata 1.12: 440_33)
 	*/
 	lis	r1,0x0030	/* store gathering & broadcast disable */
 	ori	r1,r1,0x6000	/* cache touch */
 	mtspr	ccr0,r1
 	/*----------------------------------------------------------------*/
 	/* Setup interrupt vectors */
 	/*----------------------------------------------------------------*/
 	mtspr	ivpr,r0		/* Vectors start at 0x0000_0000 */
 	li      r1,0x0100
 	mtspr	ivor0,r1	/* Critical input */
 	li      r1,0x0200
 	mtspr	ivor1,r1	/* Machine check */
 	li      r1,0x0300
 	mtspr	ivor2,r1	/* Data storage */
 	li      r1,0x0400
 	mtspr	ivor3,r1	/* Instruction storage */
 	li	r1,0x0500
 	mtspr	ivor4,r1	/* External interrupt */
 	li	r1,0x0600
 	mtspr	ivor5,r1	/* Alignment */
 	li	r1,0x0700
 	mtspr	ivor6,r1	/* Program check */
 	li	r1,0x0800
 	mtspr	ivor7,r1	/* Floating point unavailable */
 	li	r1,0x0c00
 	mtspr	ivor8,r1	/* System call */
 	li	r1,0x1000
 	mtspr	ivor10,r1	/* Decrementer (PIT for 440) */
 	li	r1,0x1400
 	mtspr	ivor13,r1	/* Data TLB error */
 	li	r1,0x1300
 	mtspr	ivor14,r1	/* Instr TLB error */
 	li	r1,0x2000
 	mtspr	ivor15,r1	/* Debug */
 	/*----------------------------------------------------------------*/
 	/* Configure cache regions  */
 	/*----------------------------------------------------------------*/
 	mtspr	inv0,r0
 	mtspr	inv1,r0
 	mtspr	inv2,r0
 	mtspr	inv3,r0
 	mtspr	dnv0,r0
 	mtspr	dnv1,r0
 	mtspr	dnv2,r0
 	mtspr	dnv3,r0
 	mtspr	itv0,r0
 	mtspr	itv1,r0
 	mtspr	itv2,r0
 	mtspr	itv3,r0
 	mtspr	dtv0,r0
 	mtspr	dtv1,r0
 	mtspr	dtv2,r0
 	mtspr	dtv3,r0
 	/*----------------------------------------------------------------*/
 	/* Cache victim limits */
 	/*----------------------------------------------------------------*/
 	/* floors 0, ceiling max to use the entire cache -- nothing locked
 	*/
 	lis	r1,0x0001
 	ori	r1,r1,0xf800
 	mtspr	ivlim,r1
 	mtspr	dvlim,r1
 	/*----------------------------------------------------------------*/
 	/* Clear all TLB entries -- TID = 0, TS = 0 */
 	/*----------------------------------------------------------------*/
 	mtspr	mmucr,r0
 	li	r1,0x003f	/* 64 TLB entries */
 	mtctr	r1
 0:	tlbwe	r0,r1,0x0000	/* Invalidate all entries (V=0)*/
 	subi	r1,r1,0x0001
 	bdnz	0b
 	/*----------------------------------------------------------------*/
 	/* TLB entry setup -- step thru tlbtab */
 	/*----------------------------------------------------------------*/
 	bl	tlbtab		/* Get tlbtab pointer */
 	mr	r5,r0
 	li	r1,0x003f	/* 64 TLB entries max */
 	mtctr	r1
 	li	r4,0		/* TLB # */
 	addi	r5,r5,-4
 1:	lwzu	r0,4(r5)
 	cmpwi	r0,0
 	beq	2f		/* 0 marks end */
 	lwzu	r1,4(r5)
 	lwzu	r2,4(r5)
 	tlbwe	r0,r4,0		/* TLB Word 0 */
 	tlbwe	r1,r4,1		/* TLB Word 1 */
 	tlbwe	r2,r4,2		/* TLB Word 2 */
 	addi	r4,r4,1		/* Next TLB */
 	bdnz	1b
 	/*----------------------------------------------------------------*/
 	/* Continue from 'normal' start */
 	/*----------------------------------------------------------------*/
 2:	bl	3f
 	b	_start
 3:	li	r0,0
 	mtspr	srr1,r0		/* Keep things disabled for now */
 	mflr	r1
 	mtspr	srr0,r1
 	rfi
 #endif
 /*
  * r3 - 1st arg to board_init(): IMMP pointer
  * r4 - 2nd arg to board_init(): boot flag
  */
 	.text
 	.long	0x27051956		/* U-Boot Magic Number			*/
 	.globl	version_string
 version_string:
 	.ascii U_BOOT_VERSION
 	.ascii " (", __DATE__, " - ", __TIME__, ")"
 	.ascii CONFIG_IDENT_STRING, "\0"
 /*
  * Maybe this should be moved somewhere else because the current
  * location (0x100) is where the CriticalInput Execption should be.
  */
 	. = EXC_OFF_SYS_RESET
 	.globl	_start
 _start:
 /*****************************************************************************/
 #if defined(CONFIG_440)
 	/*----------------------------------------------------------------*/
 	/* Clear and set up some registers. */
 	/*----------------------------------------------------------------*/
 	li	r0,0x0000
 	lis	r1,0xffff
 	mtspr	dec,r0			/* prevent dec exceptions */
 	mtspr	tbl,r0			/* prevent fit & wdt exceptions */
 	mtspr	tbu,r0
 	mtspr	tsr,r1			/* clear all timer exception status */
 	mtspr	tcr,r0			/* disable all */
 	mtspr	esr,r0			/* clear exception syndrome register */
 	mtxer	r0			/* clear integer exception register */
 	lis	r1,0x0002		/* set CE bit (Critical Exceptions) */
 	ori	r1,r1,0x1000		/* set ME bit (Machine Exceptions) */
 	mtmsr	r1			/* change MSR */
 	/*----------------------------------------------------------------*/
 	/* Debug setup -- some (not very good) ice's need an event*/
 	/* to establish control :-( Define CFG_INIT_DBCR to the dbsr */
 	/* value you need in this case 0x8cff 0000 should do the trick */
 	/*----------------------------------------------------------------*/
 #if defined(CFG_INIT_DBCR)
 	lis	r1,0xffff
 	ori	r1,r1,0xffff
 	mtspr	dbsr,r1			/* Clear all status bits */
 	lis	r0,CFG_INIT_DBCR@h
 	ori	r0,r0,CFG_INIT_DBCR@l
 	mtspr	dbcr0,r0
 	isync
 #endif
 	/*----------------------------------------------------------------*/
 	/* Setup the internal SRAM */
 	/*----------------------------------------------------------------*/
 	li	r0,0
 	mtdcr	isram0_sb1cr,r0		/* Disable bank 1 */
 	li	r2,0x7fff
 	ori	r2,r2,0xffff
 	mfdcr	r1,isram0_dpc
 	and	r1,r1,r2		/* Disable parity check */
 	mtdcr	isram0_dpc,r1
 	mfdcr	r1,isram0_pmeg
 	andis.	r1,r1,r2		/* Disable pwr mgmt */
 	mtdcr	isram0_pmeg,r1
 	lis	r1,0x8000		/* BAS = 8000_0000 */
 	ori	r1,r1,0x0380		/* 8k rw */
 	mtdcr	isram0_sb0cr,r1
 	/*----------------------------------------------------------------*/
 	/* Setup the stack in internal SRAM */
 	/*----------------------------------------------------------------*/
 	lis	r1,CFG_INIT_RAM_ADDR@h
 	ori	r1,r1,CFG_INIT_SP_OFFSET@l
 	li	r0,0
 	stwu	r0,-4(r1)
 	stwu	r0,-4(r1)		/* Terminate call chain */
 	stwu	r1,-8(r1)		/* Save back chain and move SP */
 	lis	r0,RESET_VECTOR@h	/* Address of reset vector */
 	ori	r0,r0, RESET_VECTOR@l
 	stwu	r1,-8(r1)		/* Save back chain and move SP */
 	stw	r0,+12(r1)		/* Save return addr (underflow vect) */
 	GET_GOT
 	bl	board_init_f
 #endif /* CONFIG_440 */
 /*****************************************************************************/
 #ifdef CONFIG_IOP480
 	/*----------------------------------------------------------------------- */
 	/* Set up some machine state registers. */
 	/*----------------------------------------------------------------------- */
 	addi	r0,r0,0x0000		/* initialize r0 to zero */
 	mtspr	esr,r0			/* clear Exception Syndrome Reg */
 	mttcr	r0			/* timer control register */
 	mtexier r0			/* disable all interrupts */
 	addi	r4,r0,0x1000		/* set ME bit (Machine Exceptions) */
 	oris	r4,r4,0x2		/* set CE bit (Critical Exceptions) */
 	mtmsr	r4			/* change MSR */
 	addis	r4,r0,0xFFFF		/* set r4 to 0xFFFFFFFF (status in the */
 	ori	r4,r4,0xFFFF		/* dbsr is cleared by setting bits to 1) */
 	mtdbsr	r4			/* clear/reset the dbsr */
 	mtexisr r4			/* clear all pending interrupts */
 	addis	r4,r0,0x8000
 	mtexier r4			/* enable critical exceptions */
 	addis	r4,r0,0x0000		/* assume 403GCX - enable core clk */
 	ori	r4,r4,0x4020		/* dbling (no harm done on GA and GC */
 	mtiocr	r4			/* since bit not used) & DRC to latch */
 					/* data bus on rising edge of CAS */
 	/*----------------------------------------------------------------------- */
 	/* Clear XER. */
 	/*----------------------------------------------------------------------- */
 	mtxer	r0
 	/*----------------------------------------------------------------------- */
 	/* Invalidate i-cache and d-cache TAG arrays. */
 	/*----------------------------------------------------------------------- */
 	addi	r3,0,1024		/* 1/4 of I-cache size, half of D-cache */
 	addi	r4,0,1024		/* 1/4 of I-cache */
 ..cloop:
 	iccci	0,r3
 	iccci	r4,r3
 	dccci	0,r3
 	addic.	r3,r3,-16		/* move back one cache line */
 	bne	..cloop			/* loop back to do rest until r3 = 0 */
 	/* */
 	/* initialize IOP480 so it can read 1 MB code area for SRAM spaces */
 	/* this requires enabling MA[17..0], by default only MA[12..0] are enabled. */
 	/* */
 	/* first copy IOP480 register base address into r3 */
 	addis	r3,0,0x5000		/* IOP480 register base address hi */
 /*	ori	r3,r3,0x0000		/  IOP480 register base address lo */
 #ifdef CONFIG_ADCIOP
 	/* use r4 as the working variable */
 	/* turn on CS3 (LOCCTL.7) */
 	lwz	r4,0x84(r3)		/* LOCTL is at offset 0x84 */
 	andi.	r4,r4,0xff7f		/* make bit 7 = 0 -- CS3 mode */
 	stw	r4,0x84(r3)		/* LOCTL is at offset 0x84 */
 #endif
 #ifdef CONFIG_DASA_SIM
 	/* use r4 as the working variable */
 	/* turn on MA17 (LOCCTL.7) */
 	lwz	r4,0x84(r3)		/* LOCTL is at offset 0x84 */
 	ori	r4,r4,0x80		/* make bit 7 = 1 -- MA17 mode */
 	stw	r4,0x84(r3)		/* LOCTL is at offset 0x84 */
 #endif
 	/* turn on MA16..13 (LCS0BRD.12 = 0) */
 	lwz	r4,0x100(r3)		/* LCS0BRD is at offset 0x100 */
 	andi.	r4,r4,0xefff		/* make bit 12 = 0 */
 	stw	r4,0x100(r3)		/* LCS0BRD is at offset 0x100 */
 	/* make sure above stores all comlete before going on */
 	sync
 	/* last thing, set local init status done bit (DEVINIT.31) */
 	lwz	r4,0x80(r3)		/* DEVINIT is at offset 0x80 */
 	oris	r4,r4,0x8000		/* make bit 31 = 1 */
 	stw	r4,0x80(r3)		/* DEVINIT is at offset 0x80 */
 	/* clear all pending interrupts and disable all interrupts */
 	li	r4,-1			/* set p1 to 0xffffffff */
 	stw	r4,0x1b0(r3)		/* clear all pending interrupts */
 	stw	r4,0x1b8(r3)		/* clear all pending interrupts */
 	li	r4,0			/* set r4 to 0 */
 	stw	r4,0x1b4(r3)		/* disable all interrupts */
 	stw	r4,0x1bc(r3)		/* disable all interrupts */
 	/* make sure above stores all comlete before going on */
 	sync
 	/*----------------------------------------------------------------------- */
 	/* Enable two 128MB cachable regions. */
 	/*----------------------------------------------------------------------- */
 	addis	r1,r0,0x8000
 	addi	r1,r1,0x0001
 	mticcr	r1			/* instruction cache */
 	addis	r1,r0,0x0000
 	addi	r1,r1,0x0000
 	mtdccr	r1			/* data cache */
 	addis	r1,r0,CFG_INIT_RAM_ADDR@h
 	ori	r1,r1,CFG_INIT_SP_OFFSET	  /* set up the stack to SDRAM */
 	li	r0, 0			/* Make room for stack frame header and */
 	stwu	r0, -4(r1)		/* clear final stack frame so that	*/
 	stwu	r0, -4(r1)		/* stack backtraces terminate cleanly	*/
 	GET_GOT			/* initialize GOT access			*/
 	bl	board_init_f	/* run first part of init code (from Flash)	*/
 #endif	/* CONFIG_IOP480 */
 /*****************************************************************************/
 #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405)
 	/*----------------------------------------------------------------------- */
 	/* Clear and set up some registers. */
 	/*----------------------------------------------------------------------- */
 	addi	r4,r0,0x0000
 	mtspr	sgr,r4
 	mtspr	dcwr,r4
 	mtesr	r4			/* clear Exception Syndrome Reg */
 	mttcr	r4			/* clear Timer Control Reg */
 	mtxer	r4			/* clear Fixed-Point Exception Reg */
 	mtevpr	r4			/* clear Exception Vector Prefix Reg */
 	addi	r4,r0,0x1000		/* set ME bit (Machine Exceptions) */
 	oris	r4,r4,0x0002		/* set CE bit (Critical Exceptions) */
 	mtmsr	r4			/* change MSR */
 	addi	r4,r0,(0xFFFF-0x10000)		/* set r4 to 0xFFFFFFFF (status in the */
 					/* dbsr is cleared by setting bits to 1) */
 	mtdbsr	r4			/* clear/reset the dbsr */
 	/*----------------------------------------------------------------------- */
 	/* Invalidate I and D caches. Enable I cache for defined memory regions */
 	/* to speed things up. Leave the D cache disabled for now. It will be */
 	/* enabled/left disabled later based on user selected menu options. */
 	/* Be aware that the I cache may be disabled later based on the menu */
 	/* options as well. See miscLib/main.c. */
 	/*----------------------------------------------------------------------- */
 	bl	invalidate_icache
 	bl	invalidate_dcache
 	/*----------------------------------------------------------------------- */
 	/* Enable two 128MB cachable regions. */
 	/*----------------------------------------------------------------------- */
 	addis	r4,r0,0x8000
 	addi	r4,r4,0x0001
 	mticcr	r4			/* instruction cache */
 	isync
 	addis	r4,r0,0x0000
 	addi	r4,r4,0x0000
 	mtdccr	r4			/* data cache */
 #if !(defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR))
 	/*----------------------------------------------------------------------- */
 	/* Tune the speed and size for flash CS0  */
 	/*----------------------------------------------------------------------- */
 	bl	ext_bus_cntlr_init
 #endif
 #if defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE)
 	/********************************************************************
 	 * Setup OCM - On Chip Memory
 	 *******************************************************************/
 	/* Setup OCM */
  	lis	r0, 0x7FFF
  	ori	r0, r0, 0xFFFF
  	mfdcr	r3, ocmiscntl 		/* get instr-side IRAM config */
  	mfdcr	r4, ocmdscntl	/* get data-side IRAM config */
  	and	r3, r3, r0	/* disable data-side IRAM */
  	and	r4, r4, r0	/* disable data-side IRAM */
  	mtdcr	ocmiscntl, r3	/* set instr-side IRAM config */
  	mtdcr	ocmdscntl, r4	/* set data-side IRAM config */
  	isync
 	addis	r3, 0, CFG_OCM_DATA_ADDR@h /* OCM location */
 	mtdcr	ocmdsarc, r3
 	addis	r4, 0, 0xC000		/* OCM data area enabled */
 	mtdcr	ocmdscntl, r4
  	isync
 #endif
 	/*----------------------------------------------------------------------- */
 	/* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */
 	/*----------------------------------------------------------------------- */
 #ifdef CFG_INIT_DCACHE_CS
 	/*----------------------------------------------------------------------- */
 	/* Memory Bank x (nothingness) initialization 1GB+64MEG */
 	/* used as temporary stack pointer for stage0  */
 	/*----------------------------------------------------------------------- */
 	li	r4,PBxAP
 	mtdcr	ebccfga,r4
 	lis	r4,0x0380
 	ori	r4,r4,0x0480
 	mtdcr	ebccfgd,r4
 	addi	r4,0,PBxCR
 	mtdcr	ebccfga,r4
 	lis	r4,0x400D
 	ori	r4,r4,0xa000
 	mtdcr	ebccfgd,r4
 	/* turn on data chache for this region */
 	lis	r4,0x0080
 	mtdccr	r4
 	/* set stack pointer and clear stack to known value */
 	lis	r1,CFG_INIT_RAM_ADDR@h
 	ori     r1,r1,CFG_INIT_SP_OFFSET@l
 	li	r4,2048			/* we store 2048 words to stack */
 	mtctr	r4
 	lis	r2,CFG_INIT_RAM_ADDR@h		/* we also clear data area */
 	ori	r2,r2,CFG_INIT_RAM_END@l 	/* so cant copy value from r1 */
 	lis	r4,0xdead		/* we store 0xdeaddead in the stack */
 	ori	r4,r4,0xdead
 ..stackloop:
 	stwu	r4,-4(r2)
 	bdnz	..stackloop
 	li	r0, 0			/* Make room for stack frame header and */
 	stwu	r0, -4(r1)		/* clear final stack frame so that	*/
 	stwu	r0, -4(r1)		/* stack backtraces terminate cleanly	*/
 	/*
 	 * Set up a dummy frame to store reset vector as return address.
 	 * this causes stack underflow to reset board.
 	 */
 	stwu	r1, -8(r1)		/* Save back chain and move SP */
 	addis	r0, 0, RESET_VECTOR@h	/* Address of reset vector */
 	ori	r0, r0, RESET_VECTOR@l
 	stwu	r1, -8(r1)		/* Save back chain and move SP */
 	stw	r0, +12(r1)		/* Save return addr (underflow vect) */
 #elif defined(CFG_TEMP_STACK_OCM) && \
 	(defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE))
 	/*
 	 * Stack in OCM.
 	 */
 	/* Set up Stack at top of OCM */
 	lis	r1, (CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET)@h
 	ori	r1, r1, (CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET)@l
 	/* Set up a zeroized stack frame so that backtrace works right */
 	li	r0, 0
 	stwu	r0, -4(r1)
 	stwu	r0, -4(r1)
 	/*
 	 * Set up a dummy frame to store reset vector as return address.
 	 * this causes stack underflow to reset board.
 	 */
 	stwu	r1, -8(r1)		/* Save back chain and move SP */
 	lis	r0, RESET_VECTOR@h	/* Address of reset vector */
 	ori	r0, r0, RESET_VECTOR@l
 	stwu	r1, -8(r1)		/* Save back chain and move SP */
 	stw	r0, +12(r1)		/* Save return addr (underflow vect) */
 #endif /* CFG_INIT_DCACHE_CS */
 	/*----------------------------------------------------------------------- */
 	/* Initialize SDRAM Controller  */
 	/*----------------------------------------------------------------------- */
 	bl	sdram_init
 	/*
 	 * Setup temporary stack pointer only for boards
 	 * that do not use SDRAM SPD I2C stuff since it
 	 * is already initialized to use DCACHE or OCM
 	 * stacks.
 	 */
 #if !(defined(CFG_INIT_DCACHE_CS) || defined(CFG_TEMP_STACK_OCM))
 	lis	r1, CFG_INIT_RAM_ADDR@h
 	ori	r1,r1,CFG_INIT_SP_OFFSET /* set up the stack in SDRAM */
 	li	r0, 0			/* Make room for stack frame header and */
 	stwu	r0, -4(r1)		/* clear final stack frame so that	*/
 	stwu	r0, -4(r1)		/* stack backtraces terminate cleanly	*/
 	/*
 	 * Set up a dummy frame to store reset vector as return address.
 	 * this causes stack underflow to reset board.
 	 */
 	stwu	r1, -8(r1)		/* Save back chain and move SP */
 	lis	r0, RESET_VECTOR@h	/* Address of reset vector */
 	ori	r0, r0, RESET_VECTOR@l
 	stwu	r1, -8(r1)		/* Save back chain and move SP */
 	stw	r0, +12(r1)		/* Save return addr (underflow vect) */
 #endif /* !(CFG_INIT_DCACHE_CS  || !CFG_TEM_STACK_OCM) */
 	GET_GOT			/* initialize GOT access			*/
        	bl	cpu_init_f	/* run low-level CPU init code     (from Flash)	*/
 	/* NEVER RETURNS! */
 	bl	board_init_f	/* run first part of init code (from Flash)	*/
 #endif	/* CONFIG_405GP || CONFIG_405CR */
 	.globl	_start_of_vectors
 _start_of_vectors:
 #if 0
 /*TODO Fixup _start above so we can do this*/
 /* Critical input. */
 	CRIT_EXCEPTION(0x100, CritcalInput, CritcalInputException)
 #endif
 /* Machine check */
 	STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
 /* Data Storage exception. */
 	STD_EXCEPTION(0x300, DataStorage, UnknownException)
 /* Instruction Storage exception. */
 	STD_EXCEPTION(0x400, InstStorage, UnknownException)
 /* External Interrupt exception. */
 	STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
 /* Alignment exception. */
 	. = 0x600
 Alignment:
 	EXCEPTION_PROLOG
 	mfspr	r4,DAR
 	stw	r4,_DAR(r21)
 	mfspr	r5,DSISR
 	stw	r5,_DSISR(r21)
 	addi	r3,r1,STACK_FRAME_OVERHEAD
 	li	r20,MSR_KERNEL
 	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
 	lwz	r6,GOT(transfer_to_handler)
 	mtlr	r6
 	blrl
 .L_Alignment:
 	.long	AlignmentException - _start + EXC_OFF_SYS_RESET
 	.long	int_return - _start + EXC_OFF_SYS_RESET
 /* Program check exception */
 	. = 0x700
 ProgramCheck:
 	EXCEPTION_PROLOG
 	addi	r3,r1,STACK_FRAME_OVERHEAD
 	li	r20,MSR_KERNEL
 	rlwimi	r20,r23,0,16,16		/* copy EE bit from saved MSR */
 	lwz	r6,GOT(transfer_to_handler)
 	mtlr	r6
 	blrl
 .L_ProgramCheck:
 	.long	ProgramCheckException - _start + EXC_OFF_SYS_RESET
 	.long	int_return - _start + EXC_OFF_SYS_RESET
 	/* No FPU on MPC8xx.  This exception is not supposed to happen.
 	*/
 	STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
 	/* I guess we could implement decrementer, and may have
 	 * to someday for timekeeping.
 	 */
 	STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
 	STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
 	STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
 	. = 0xc00
 /*
  * r0 - SYSCALL number
  * r3-... arguments
  */
 SystemCall:
 	addis	r11,r0,0		/* get functions table addr */
 	ori	r11,r11,0		/* Note: this code is patched in trap_init */
 	addis	r12,r0,0		/* get number of functions */
 	ori	r12,r12,0
 	cmplw	0, r0, r12
 	bge	1f
 	rlwinm	r0,r0,2,0,31		/* fn_addr = fn_tbl[r0] */
 	add	r11,r11,r0
 	lwz	r11,0(r11)
-	li	r12,0xd00-4*3		/* save LR & SRRx */
+	li	r20,0xd00-4		/* Get stack pointer */
+	lwz	r12,0(r20)
+	subi	r12,r12,12		/* Adjust stack pointer */
+	li	r0,0xc00+_end_back-SystemCall
+	cmplw	0, r0, r12		/* Check stack overflow */
+	bgt	1f
+	stw	r12,0(r20)
 	mflr	r0
 	stw	r0,0(r12)
 	mfspr	r0,SRR0
 	stw	r0,4(r12)
 	mfspr	r0,SRR1
 	stw	r0,8(r12)
 	li	r12,0xc00+_back-SystemCall
 	mtlr	r12
 	mtspr	SRR0,r11
 1:	SYNC
 	rfi
 _back:
 	mfmsr	r11			/* Disable interrupts */
 	li	r12,0
 	ori	r12,r12,MSR_EE
 	andc	r11,r11,r12
 	SYNC				/* Some chip revs need this... */
 	mtmsr	r11
 	SYNC
-	li	r12,0xd00-4*3		/* restore regs */
+	li	r12,0xd00-4		/* restore regs */
+	lwz	r12,0(r12)
 	lwz	r11,0(r12)
 	mtlr	r11
 	lwz	r11,4(r12)
 	mtspr	SRR0,r11
 	lwz	r11,8(r12)
 	mtspr	SRR1,r11
+	addi	r12,r12,12		/* Adjust stack pointer */
+	li	r20,0xd00-4
+	stw	r12,0(r20)
 	SYNC
 	rfi
+_end_back:
 	STD_EXCEPTION(0xd00, SingleStep, UnknownException)
 	STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
 	STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
 	/* On the MPC8xx, this is a software emulation interrupt.  It occurs
 	 * for all unimplemented and illegal instructions.
 	 */
 	STD_EXCEPTION(0x1000, PIT, PITException)
 	STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
 	STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
 	STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
 	STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
 	STD_EXCEPTION(0x1500, Reserved5, UnknownException)
 	STD_EXCEPTION(0x1600, Reserved6, UnknownException)
 	STD_EXCEPTION(0x1700, Reserved7, UnknownException)
 	STD_EXCEPTION(0x1800, Reserved8, UnknownException)
 	STD_EXCEPTION(0x1900, Reserved9, UnknownException)
 	STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
 	STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
 	STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
 	STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException)
 	STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
 	STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
 	CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException )
 	.globl	_end_of_vectors
 _end_of_vectors:
 	. = 0x2100
 /*
  * This code finishes saving the registers to the exception frame
  * and jumps to the appropriate handler for the exception.
  * Register r21 is pointer into trap frame, r1 has new stack pointer.
  */
 	.globl	transfer_to_handler
 transfer_to_handler:
 	stw	r22,_NIP(r21)
 	lis	r22,MSR_POW@h
 	andc	r23,r23,r22
 	stw	r23,_MSR(r21)
 	SAVE_GPR(7, r21)
 	SAVE_4GPRS(8, r21)
 	SAVE_8GPRS(12, r21)
 	SAVE_8GPRS(24, r21)
 #if 0
 	andi.	r23,r23,MSR_PR
 	mfspr	r23,SPRG3		/* if from user, fix up tss.regs */
 	beq	2f
 	addi	r24,r1,STACK_FRAME_OVERHEAD
 	stw	r24,PT_REGS(r23)
 2:	addi	r2,r23,-TSS		/* set r2 to current */
 	tovirt(r2,r2,r23)
 #endif
 	mflr	r23
 	andi.	r24,r23,0x3f00		/* get vector offset */
 	stw	r24,TRAP(r21)
 	li	r22,0
 	stw	r22,RESULT(r21)
 	mtspr	SPRG2,r22		/* r1 is now kernel sp */
 #if 0
 	addi	r24,r2,TASK_STRUCT_SIZE /* check for kernel stack overflow */
 	cmplw	0,r1,r2
 	cmplw	1,r1,r24
 	crand	1,1,4
 	bgt	stack_ovf		/* if r2 < r1 < r2+TASK_STRUCT_SIZE */
 #endif
 	lwz	r24,0(r23)		/* virtual address of handler */
 	lwz	r23,4(r23)		/* where to go when done */
 	mtspr	SRR0,r24
 	mtspr	SRR1,r20
 	mtlr	r23
 	SYNC
 	rfi				/* jump to handler, enable MMU */
 int_return:
 	mfmsr	r28		/* Disable interrupts */
 	li	r4,0
 	ori	r4,r4,MSR_EE
 	andc	r28,r28,r4
 	SYNC			/* Some chip revs need this... */
 	mtmsr	r28
 	SYNC
 	lwz	r2,_CTR(r1)
 	lwz	r0,_LINK(r1)
 	mtctr	r2
 	mtlr	r0
 	lwz	r2,_XER(r1)
 	lwz	r0,_CCR(r1)
 	mtspr	XER,r2
 	mtcrf	0xFF,r0
 	REST_10GPRS(3, r1)
 	REST_10GPRS(13, r1)
 	REST_8GPRS(23, r1)
 	REST_GPR(31, r1)
 	lwz	r2,_NIP(r1)	/* Restore environment */
 	lwz	r0,_MSR(r1)
 	mtspr	SRR0,r2
 	mtspr	SRR1,r0
 	lwz	r0,GPR0(r1)
 	lwz	r2,GPR2(r1)
 	lwz	r1,GPR1(r1)
 	SYNC
 	rfi
 crit_return:
 	mfmsr	r28		/* Disable interrupts */
 	li	r4,0
 	ori	r4,r4,MSR_EE
 	andc	r28,r28,r4
 	SYNC			/* Some chip revs need this... */
 	mtmsr	r28
 	SYNC
 	lwz	r2,_CTR(r1)
 	lwz	r0,_LINK(r1)
 	mtctr	r2
 	mtlr	r0
 	lwz	r2,_XER(r1)
 	lwz	r0,_CCR(r1)
 	mtspr	XER,r2
 	mtcrf	0xFF,r0
 	REST_10GPRS(3, r1)
 	REST_10GPRS(13, r1)
 	REST_8GPRS(23, r1)
 	REST_GPR(31, r1)
 	lwz	r2,_NIP(r1)	/* Restore environment */
 	lwz	r0,_MSR(r1)
 	mtspr	990,r2		/* SRR2 */
 	mtspr	991,r0		/* SRR3 */
 	lwz	r0,GPR0(r1)
 	lwz	r2,GPR2(r1)
 	lwz	r1,GPR1(r1)
 	SYNC
 	rfci
 /* Cache functions.
 */
 invalidate_icache:
 	iccci	r0,r0			/* for 405, iccci invalidates the */
 	blr				/*   entire I cache */
 invalidate_dcache:
 	addi	r6,0,0x0000		/* clear GPR 6 */
 	/* Do loop for # of dcache congruence classes. */
 	addi	r7,r0, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)
 					/* NOTE: dccci invalidates both */
 	mtctr	r7			/* ways in the D cache */
 ..dcloop:
 	dccci	0,r6			/* invalidate line */
 	addi	r6,r6, CFG_CACHELINE_SIZE /* bump to next line */
 	bdnz	..dcloop
 	blr
 flush_dcache:
 	addis	r9,r0,0x0002		/* set mask for EE and CE msr bits */
 	ori	r9,r9,0x8000
 	mfmsr	r12			/* save msr */
 	andc	r9,r12,r9
 	mtmsr	r9			/* disable EE and CE */
 	addi	r10,r0,0x0001		/* enable data cache for unused memory */
 	mfdccr	r9			/* region 0xF8000000-0xFFFFFFFF via */
 	or	r10,r10,r9		/* bit 31 in dccr */
 	mtdccr	r10
 	/* do loop for # of congruence classes. */
 	addi	r10,r0,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)
 	addi	r11,r0,(CFG_DCACHE_SIZE / 2) /* D cache set size - 2 way sets */
 	mtctr	r10
 	addi	r10,r0,(0xE000-0x10000)	/* start at 0xFFFFE000 */
 	add	r11,r10,r11		/* add to get to other side of cache line */
 ..flush_dcache_loop:
 	lwz	r3,0(r10)		/* least recently used side */
 	lwz	r3,0(r11)		/* the other side */
 	dccci	r0,r11			/* invalidate both sides */
 	addi	r10,r10,CFG_CACHELINE_SIZE /* bump to next line */
 	addi	r11,r11,CFG_CACHELINE_SIZE /* bump to next line */
 	bdnz	..flush_dcache_loop
 	sync				/* allow memory access to complete */
 	mtdccr	r9			/* restore dccr */
 	mtmsr	r12			/* restore msr */
 	blr
 	.globl	icache_enable
 icache_enable:
 	mflr	r8
 	bl	invalidate_icache
 	mtlr	r8
 	isync
 	addis	r3,r0, 0x8000	      /* set bit 0 */
 	mticcr	r3
 	blr
 	.globl	icache_disable
 icache_disable:
 	addis	r3,r0, 0x0000	      /* clear bit 0 */
 	mticcr	r3
 	isync
 	blr
 	.globl	icache_status
 icache_status:
 	mficcr	r3
 	srwi	r3, r3, 31	/* >>31 => select bit 0 */
 	blr
 	.globl	dcache_enable
 dcache_enable:
 	mflr	r8
 	bl	invalidate_dcache
 	mtlr	r8
 	isync
 	addis	r3,r0, 0x8000	      /* set bit 0 */
 	mtdccr	r3
 	blr
 	.globl	dcache_disable
 dcache_disable:
 	mflr	r8
 	bl	flush_dcache
 	mtlr	r8
 	addis	r3,r0, 0x0000	      /* clear bit 0 */
 	mtdccr	r3
 	blr
 	.globl	dcache_status
 dcache_status:
 	mfdccr	r3
 	srwi	r3, r3, 31	/* >>31 => select bit 0 */
 	blr
 	.globl get_pvr
 get_pvr:
 	mfspr	r3, PVR
 	blr
 #if !defined(CONFIG_440)
 	.globl wr_pit
 wr_pit:
 	mtspr	pit, r3
 	blr
 #endif
 	.globl wr_tcr
 wr_tcr:
 	mtspr	tcr, r3
 	blr
 /*------------------------------------------------------------------------------- */
 /* Function:	 in8 */
 /* Description:	 Input 8 bits */
 /*------------------------------------------------------------------------------- */
 	.globl	in8
 in8:
 	lbz	r3,0x0000(r3)
 	blr
 /*------------------------------------------------------------------------------- */
 /* Function:	 out8 */
 /* Description:	 Output 8 bits */
 /*------------------------------------------------------------------------------- */
 	.globl	out8
 out8:
 	stb	r4,0x0000(r3)
 	blr
 /*------------------------------------------------------------------------------- */
 /* Function:	 out16 */
 /* Description:	 Output 16 bits */
 /*------------------------------------------------------------------------------- */
 	.globl	out16
 out16:
 	sth	r4,0x0000(r3)
 	blr
 /*------------------------------------------------------------------------------- */
 /* Function:	 out16r */
 /* Description:	 Byte reverse and output 16 bits */
 /*------------------------------------------------------------------------------- */
 	.globl	out16r
 out16r:
 	sthbrx	r4,r0,r3
 	blr
 /*------------------------------------------------------------------------------- */
 /* Function:	 out32 */
 /* Description:	 Output 32 bits */
 /*------------------------------------------------------------------------------- */
 	.globl	out32
 out32:
 	stw	r4,0x0000(r3)
 	blr
 /*------------------------------------------------------------------------------- */
 /* Function:	 out32r */
 /* Description:	 Byte reverse and output 32 bits */
 /*------------------------------------------------------------------------------- */
 	.globl	out32r
 out32r:
 	stwbrx	r4,r0,r3
 	blr
 /*------------------------------------------------------------------------------- */
 /* Function:	 in16 */
 /* Description:	 Input 16 bits */
 /*------------------------------------------------------------------------------- */
 	.globl	in16
 in16:
 	lhz	r3,0x0000(r3)
 	blr
 /*------------------------------------------------------------------------------- */
 /* Function:	 in16r */
 /* Description:	 Input 16 bits and byte reverse */
 /*------------------------------------------------------------------------------- */
 	.globl	in16r
 in16r:
 	lhbrx	r3,r0,r3
 	blr
 /*------------------------------------------------------------------------------- */
 /* Function:	 in32 */
 /* Description:	 Input 32 bits */
 /*------------------------------------------------------------------------------- */
 	.globl	in32
 in32:
 	lwz	3,0x0000(3)
 	blr
 /*------------------------------------------------------------------------------- */
 /* Function:	 in32r */
 /* Description:	 Input 32 bits and byte reverse */
 /*------------------------------------------------------------------------------- */
 	.globl	in32r
 in32r:
 	lwbrx	r3,r0,r3
 	blr
 /*------------------------------------------------------------------------------- */
 /* Function:	 ppcDcbf */
 /* Description:	 Data Cache block flush */
 /* Input:	 r3 = effective address */
 /* Output:	 none. */
 /*------------------------------------------------------------------------------- */
 	.globl	ppcDcbf
 ppcDcbf:
 	dcbf	r0,r3
 	blr
 /*------------------------------------------------------------------------------- */
 /* Function:	 ppcDcbi */
 /* Description:	 Data Cache block Invalidate */
 /* Input:	 r3 = effective address */
 /* Output:	 none. */
 /*------------------------------------------------------------------------------- */
 	.globl	ppcDcbi
 ppcDcbi:
 	dcbi	r0,r3
 	blr
 /*------------------------------------------------------------------------------- */
 /* Function:	 ppcSync */
 /* Description:	 Processor Synchronize */
 /* Input:	 none. */
 /* Output:	 none. */
 /*------------------------------------------------------------------------------- */
 	.globl	ppcSync
 ppcSync:
 	sync
 	blr
 /*------------------------------------------------------------------------------*/
 /*
  * void relocate_code (addr_sp, gd, addr_moni)
  *
  * This "function" does not return, instead it continues in RAM
  * after relocating the monitor code.
  *
  * r3 = dest
  * r4 = src
  * r5 = length in bytes
  * r6 = cachelinesize
  */
 	.globl	relocate_code
 relocate_code:
 	mr	r1,  r3		/* Set new stack pointer		*/
 	mr	r9,  r4		/* Save copy of Init Data pointer	*/
 	mr	r10, r5		/* Save copy of Destination Address	*/
 	mr	r3,  r5				/* Destination Address	*/
 	lis	r4, CFG_MONITOR_BASE@h		/* Source      Address	*/
 	ori	r4, r4, CFG_MONITOR_BASE@l
 	lis	r5, CFG_MONITOR_LEN@h		/* Length in Bytes	*/
 	ori	r5, r5, CFG_MONITOR_LEN@l
 	li	r6, CFG_CACHELINE_SIZE		/* Cache Line Size	*/
 	/*
 	 * Fix GOT pointer:
 	 *
 	 * New GOT-PTR = (old GOT-PTR - CFG_MONITOR_BASE) + Destination Address
 	 *
 	 * Offset:
 	 */
 	sub	r15, r10, r4
 	/* First our own GOT */
 	add	r14, r14, r15
 	/* the the one used by the C code */
 	add	r30, r30, r15
 	/*
 	 * Now relocate code
 	 */
 	cmplw	cr1,r3,r4
 	addi	r0,r5,3
 	srwi.	r0,r0,2
 	beq	cr1,4f		/* In place copy is not necessary	*/
 	beq	7f		/* Protect against 0 count		*/
 	mtctr	r0
 	bge	cr1,2f
 	la	r8,-4(r4)
 	la	r7,-4(r3)
 1:	lwzu	r0,4(r8)
 	stwu	r0,4(r7)
 	bdnz	1b
 	b	4f
 2:	slwi	r0,r0,2
 	add	r8,r4,r0
 	add	r7,r3,r0
 3:	lwzu	r0,-4(r8)
 	stwu	r0,-4(r7)
 	bdnz	3b
 /*
  * Now flush the cache: note that we must start from a cache aligned
  * address. Otherwise we might miss one cache line.
  */
 4:	cmpwi	r6,0
 	add	r5,r3,r5
 	beq	7f		/* Always flush prefetch queue in any case */
 	subi	r0,r6,1
 	andc	r3,r3,r0
 	mr	r4,r3
 5:	dcbst	0,r4
 	add	r4,r4,r6
 	cmplw	r4,r5
 	blt	5b
 	sync			/* Wait for all dcbst to complete on bus */
 	mr	r4,r3
 6:	icbi	0,r4
 	add	r4,r4,r6
 	cmplw	r4,r5
 	blt	6b
 7:	sync			/* Wait for all icbi to complete on bus */
 	isync
 /*
  * We are done. Do not return, instead branch to second part of board
  * initialization, now running from RAM.
  */
 	addi	r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
 	mtlr	r0
 	blr				/* NEVER RETURNS! */
 in_ram:
 	/*
 	 * Relocation Function, r14 point to got2+0x8000
 	 *
 	 * Adjust got2 pointers, no need to check for 0, this code
 	 * already puts a few entries in the table.
 	 */
 	li	r0,__got2_entries@sectoff@l
 	la	r3,GOT(_GOT2_TABLE_)
 	lwz	r11,GOT(_GOT2_TABLE_)
 	mtctr	r0
 	sub	r11,r3,r11
 	addi	r3,r3,-4
 1:	lwzu	r0,4(r3)
 	add	r0,r0,r11
 	stw	r0,0(r3)
 	bdnz	1b
 	/*
 	 * Now adjust the fixups and the pointers to the fixups
 	 * in case we need to move ourselves again.
 	 */
 2:	li	r0,__fixup_entries@sectoff@l
 	lwz	r3,GOT(_FIXUP_TABLE_)
 	cmpwi	r0,0
 	mtctr	r0
 	addi	r3,r3,-4
 	beq	4f
 3:	lwzu	r4,4(r3)
 	lwzux	r0,r4,r11
 	add	r0,r0,r11
 	stw	r10,0(r3)
 	stw	r0,0(r4)
 	bdnz	3b
 4:
 clear_bss:
 	/*
 	 * Now clear BSS segment
 	 */
 	lwz	r3,GOT(.bss)
 	lwz	r4,GOT(_end)
 	cmplw	0, r3, r4
 	beq	6f
 	li	r0, 0
 5:
 	stw	r0, 0(r3)
 	addi	r3, r3, 4
 	cmplw	0, r3, r4
 	bne	5b
 6:
 	mr	r3, r9		/* Init Data pointer		*/
 	mr	r4, r10		/* Destination Address		*/
 	bl	board_init_r
 	/* Problems accessing "end" in C, so do it here */
 	.globl	get_endaddr
 get_endaddr:
 	lwz	r3,GOT(_end)
 	blr
 	/*
 	 * Copy exception vector code to low memory
 	 *
 	 * r3: dest_addr
 	 * r7: source address, r8: end address, r9: target address
 	 */
 	.globl	trap_init
 trap_init:
 	lwz	r7, GOT(_start)
 	lwz	r8, GOT(_end_of_vectors)
 	rlwinm	r9, r7, 0, 18, 31	/* _start & 0x3FFF	*/
 	cmplw	0, r7, r8
 	bgelr				/* return if r7>=r8 - just in case */
 	mflr	r4			/* save link register		*/
 1:
 	lwz	r0, 0(r7)
 	stw	r0, 0(r9)
 	addi	r7, r7, 4
 	addi	r9, r9, 4
 	cmplw	0, r7, r8
 	bne	1b
 	/*
 	 * relocate `hdlr' and `int_return' entries
 	 */
 	li	r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
 	li	r8, Alignment - _start + EXC_OFF_SYS_RESET
 2:
 	bl	trap_reloc
 	addi	r7, r7, 0x100		/* next exception vector	*/
 	cmplw	0, r7, r8
 	blt	2b
 	li	r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
 	bl	trap_reloc
 	li	r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
 	bl	trap_reloc
 	li	r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
 	li	r8, SystemCall - _start + EXC_OFF_SYS_RESET
 3:
 	bl	trap_reloc
 	addi	r7, r7, 0x100		/* next exception vector	*/
 	cmplw	0, r7, r8
 	blt	3b
 	li	r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
 	li	r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
 4:
 	bl	trap_reloc
 	addi	r7, r7, 0x100		/* next exception vector	*/
 	cmplw	0, r7, r8
 	blt	4b
 	mtlr	r4			/* restore link register	*/
 	blr
 	/*
 	 * Function: relocate entries for one exception vector
 	 */
 trap_reloc:
 	lwz	r0, 0(r7)		/* hdlr ...			*/
 	add	r0, r0, r3		/*  ... += dest_addr		*/
 	stw	r0, 0(r7)
 	lwz	r0, 4(r7)		/* int_return ...		*/
 	add	r0, r0, r3		/*  ... += dest_addr		*/
 	stw	r0, 4(r7)
 	blr

examples/timer.c

Diff comments View file @ 7c7a23b

 /*
  * (C) Copyright 2000
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 #include <common.h>
 #include <commproc.h>
 #include <mpc8xx_irq.h>
 #include <syscall.h>
 #undef	DEBUG
 #define	TIMER_PERIOD	1000000		/* 1 second clock */
 static void timer_handler (void *arg);
 /* Access functions for the Machine State Register */
 static __inline__ unsigned long get_msr(void)
 {
     unsigned long msr;
     asm volatile("mfmsr %0" : "=r" (msr) :);
     return msr;
 }
 static __inline__ void set_msr(unsigned long msr)
 {
     asm volatile("mtmsr %0" : : "r" (msr));
 }
 /*
  * Definitions to access the CPM Timer registers
  * See 8xx_immap.h for Internal Memory Map layout,
  * and commproc.h for CPM Interrupt vectors (aka "IRQ"s)
  */
 typedef struct tid_8xx_cpmtimer_s {
   int		 cpm_vec;	/* CPM Interrupt Vector for this timer	*/
   ushort	*tgcrp;		/* Pointer to Timer Global Config Reg.	*/
   ushort	*tmrp;		/* Pointer to Timer Mode Register	*/
   ushort	*trrp;		/* Pointer to Timer Reference Register	*/
   ushort	*tcrp;		/* Pointer to Timer Capture Register	*/
   ushort	*tcnp;		/* Pointer to Timer Counter Register	*/
   ushort	*terp;		/* Pointer to Timer Event Register	*/
 } tid_8xx_cpmtimer_t;
 #ifndef CLOCKRATE
 #  define CLOCKRATE 64
 #endif
 #define	CPMT_CLOCK_DIV		16
 #define	CPMT_MAX_PRESCALER	256
 #define CPMT_MAX_REFERENCE	65535	/* max. unsigned short */
 #define	CPMT_MAX_TICKS		(CPMT_MAX_REFERENCE * CPMT_MAX_PRESCALER)
 #define	CPMT_MAX_TICKS_WITH_DIV	(CPMT_MAX_REFERENCE * CPMT_MAX_PRESCALER * CPMT_CLOCK_DIV)
 #define	CPMT_MAX_INTERVAL	(CPMT_MAX_TICKS_WITH_DIV / CLOCKRATE)
 /* For now: always use max. prescaler value */
 #define	CPMT_PRESCALER		(CPMT_MAX_PRESCALER)
 /* CPM Timer Event Register Bits */
 #define	CPMT_EVENT_CAP		0x0001	/* Capture Event		*/
 #define	CPMT_EVENT_REF		0x0002	/* Reference Counter Event	*/
 /* CPM Timer Global Config Register */
 #define	CPMT_GCR_RST		0x0001	/* Reset  Timer			*/
 #define	CPMT_GCR_STP		0x0002	/* Stop   Timer			*/
 #define	CPMT_GCR_FRZ		0x0004	/* Freeze Timer			*/
 #define	CPMT_GCR_GM_CAS		0x0008	/* Gate Mode / Cascade Timers	*/
 #define	CPMT_GCR_MASK		(CPMT_GCR_RST|CPMT_GCR_STP|CPMT_GCR_FRZ|CPMT_GCR_GM_CAS)
 /* CPM Timer Mode register */
 #define	CPMT_MR_GE		0x0001	/* Gate Enable			*/
 #define	CPMT_MR_ICLK_CASC	0x0000	/* Clock internally cascaded	*/
 #define	CPMT_MR_ICLK_CLK	0x0002	/* Clock = system clock		*/
 #define	CPMT_MR_ICLK_CLKDIV	0x0004	/* Clock = system clock / 16	*/
 #define	CPMT_MR_ICLK_TIN	0x0006	/* Clock = TINx signal		*/
 #define	CPMT_MR_FRR		0x0008	/* Free Run / Restart		*/
 #define	CPMT_MR_ORI		0x0010	/* Out. Reference Interrupt En.	*/
 #define	CPMT_MR_OM		0x0020	/* Output Mode			*/
 #define	CPMT_MR_CE_DIS		0x0000	/* Capture/Interrupt disabled	*/
 #define	CPMT_MR_CE_RISE		0x0040	/* Capt./Interr. on rising  TIN	*/
 #define CPMT_MR_CE_FALL		0x0080	/* Capt./Interr. on falling TIN	*/
 #define	CPMT_MR_CE_ANY		0x00C0	/* Capt./Interr. on any TIN edge*/
 /*
  * which CPM timer to use - index starts at 0 (= timer 1)
  */
 #define	TID_TIMER_ID	0	/* use CPM timer 1		*/
 void setPeriod (tid_8xx_cpmtimer_t *hwp, ulong interval);
 static char *usage = "\n[q, b, e, ?] ";
 int timer (int argc, char *argv[])
 {
 	DECLARE_GLOBAL_DATA_PTR;
 	cpmtimer8xx_t *cpmtimerp;	/* Pointer to the CPM Timer structure   */
 	tid_8xx_cpmtimer_t hw;
 	tid_8xx_cpmtimer_t *hwp = &hw;
 	int c;
+	int running;
 	/* Pointer to CPM Timer structure */
 	cpmtimerp = &((immap_t *) gd->bd->bi_immr_base)->im_cpmtimer;
 	mon_printf ("TIMERS=0x%x\n", (unsigned) cpmtimerp);
 	/* Initialize pointers depending on which timer we use */
 	switch (TID_TIMER_ID) {
 	case 0:
 		hwp->tmrp = &(cpmtimerp->cpmt_tmr1);
 		hwp->trrp = &(cpmtimerp->cpmt_trr1);
 		hwp->tcrp = &(cpmtimerp->cpmt_tcr1);
 		hwp->tcnp = &(cpmtimerp->cpmt_tcn1);
 		hwp->terp = &(cpmtimerp->cpmt_ter1);
 		hwp->cpm_vec = CPMVEC_TIMER1;
 		break;
 	case 1:
 		hwp->tmrp = &(cpmtimerp->cpmt_tmr2);
 		hwp->trrp = &(cpmtimerp->cpmt_trr2);
 		hwp->tcrp = &(cpmtimerp->cpmt_tcr2);
 		hwp->tcnp = &(cpmtimerp->cpmt_tcn2);
 		hwp->terp = &(cpmtimerp->cpmt_ter2);
 		hwp->cpm_vec = CPMVEC_TIMER2;
 		break;
 	case 2:
 		hwp->tmrp = &(cpmtimerp->cpmt_tmr3);
 		hwp->trrp = &(cpmtimerp->cpmt_trr3);
 		hwp->tcrp = &(cpmtimerp->cpmt_tcr3);
 		hwp->tcnp = &(cpmtimerp->cpmt_tcn3);
 		hwp->terp = &(cpmtimerp->cpmt_ter3);
 		hwp->cpm_vec = CPMVEC_TIMER3;
 		break;
 	case 3:
 		hwp->tmrp = &(cpmtimerp->cpmt_tmr4);
 		hwp->trrp = &(cpmtimerp->cpmt_trr4);
 		hwp->tcrp = &(cpmtimerp->cpmt_tcr4);
 		hwp->tcnp = &(cpmtimerp->cpmt_tcn4);
 		hwp->terp = &(cpmtimerp->cpmt_ter4);
 		hwp->cpm_vec = CPMVEC_TIMER4;
 		break;
 	}
 	hwp->tgcrp = &cpmtimerp->cpmt_tgcr;
 	mon_printf ("Using timer %d\n"
 			"tgcr @ 0x%x, tmr @ 0x%x, trr @ 0x%x,"
 			" tcr @ 0x%x, tcn @ 0x%x, ter @ 0x%x\n",
 			TID_TIMER_ID + 1,
 			(unsigned) hwp->tgcrp,
 			(unsigned) hwp->tmrp,
 			(unsigned) hwp->trrp,
 			(unsigned) hwp->tcrp,
 			(unsigned) hwp->tcnp,
 			(unsigned) hwp->terp
 			);
 	/* reset timer    */
 	*hwp->tgcrp &= ~(CPMT_GCR_MASK << TID_TIMER_ID);
 	/* clear all events */
 	*hwp->terp = (CPMT_EVENT_CAP | CPMT_EVENT_REF);
 	mon_printf (usage);
+	running = 0;
 	while ((c = mon_getc()) != 'q') {
 	    if (c == 'b') {
 		setPeriod (hwp, TIMER_PERIOD);	/* Set period and start ticking */
 		/* Install interrupt handler (enable timer in CIMR) */
 		mon_install_hdlr (hwp->cpm_vec, timer_handler, hwp);
 		mon_printf ("Enabling timer\n");
 		/* enable timer */
 		*hwp->tgcrp |= (CPMT_GCR_RST << TID_TIMER_ID);
+		running = 1;
 #ifdef	DEBUG
 		mon_printf ("tgcr=0x%x, tmr=0x%x, trr=0x%x,"
 			" tcr=0x%x, tcn=0x%x, ter=0x%x\n",
 				*hwp->tgcrp, *hwp->tmrp, *hwp->trrp,
 				*hwp->tcrp,  *hwp->tcnp, *hwp->terp
 				);
 #endif
 	    } else if (c == 'e') {
 		mon_printf ("Stopping timer\n");
 		*hwp->tgcrp &= ~(CPMT_GCR_MASK << TID_TIMER_ID);
+		running = 0;
 #ifdef	DEBUG
 		mon_printf ("tgcr=0x%x, tmr=0x%x, trr=0x%x,"
 			" tcr=0x%x, tcn=0x%x, ter=0x%x\n",
 				*hwp->tgcrp, *hwp->tmrp, *hwp->trrp,
 				*hwp->tcrp,  *hwp->tcnp, *hwp->terp
 			);
 #endif
 		/* Uninstall interrupt handler */
 		mon_free_hdlr (hwp->cpm_vec);
 	    } else if (c == '?') {
 #ifdef	DEBUG
 		cpic8xx_t *cpm_icp = &((immap_t *) gd->bd->bi_immr_base)->im_cpic;
 		sysconf8xx_t *siup = &((immap_t *) gd->bd->bi_immr_base)->im_siu_conf;
 #endif
 		mon_printf ("\ntgcr=0x%x, tmr=0x%x, trr=0x%x,"
 			" tcr=0x%x, tcn=0x%x, ter=0x%x\n",
 				*hwp->tgcrp, *hwp->tmrp, *hwp->trrp,
 				*hwp->tcrp,  *hwp->tcnp, *hwp->terp
 			);
 #ifdef	DEBUG
 		mon_printf ("SIUMCR=0x%08lx, SYPCR=0x%08lx,"
 			" SIMASK=0x%08lx, SIPEND=0x%08lx\n",
 				siup->sc_siumcr,
 				siup->sc_sypcr,
 				siup->sc_simask,
 				siup->sc_sipend
 			);
 		mon_printf ("CIMR=0x%08lx, CICR=0x%08lx, CIPR=0x%08lx\n",
 			cpm_icp->cpic_cimr,
 			cpm_icp->cpic_cicr,
 			cpm_icp->cpic_cipr
 			);
 #endif
 	    } else {
 	    	mon_printf ("\nEnter: q - quit, b - start timer, e - stop timer, ? - get status\n");
 	    }
 	    mon_printf (usage);
 	}
+	if (running) {
+		mon_printf ("Stopping timer\n");
+		*hwp->tgcrp &= ~(CPMT_GCR_MASK << TID_TIMER_ID);
+		mon_free_hdlr (hwp->cpm_vec);
+	}
 	return (0);
 }
 /* Set period in microseconds and start.
  * Truncate to maximum period if more than this is requested - but warn about it.
  */
 void setPeriod (tid_8xx_cpmtimer_t *hwp, ulong interval)
 {
 	unsigned short prescaler;
 	unsigned long ticks;
 	mon_printf ("Set interval %ld us\n", interval);
 	/* Warn if requesting longer period than possible */
 	if (interval > CPMT_MAX_INTERVAL) {
 		mon_printf ("Truncate interval %ld to maximum (%d)\n",
 				interval, CPMT_MAX_INTERVAL);
 		interval = CPMT_MAX_INTERVAL;
 	}
 	/*
 	 * Check if we want to use clock divider:
 	 * Since the reference counter can be incremented only in integer steps,
 	 * we try to keep it as big as possible to allow the resulting period to be
 	 * as precise as possible.
 	 */
 	/* prescaler, enable interrupt, restart after ref count is reached */
 	prescaler = (ushort) ((CPMT_PRESCALER - 1) << 8) |
 			CPMT_MR_ORI |
 			CPMT_MR_FRR;
 	ticks = ((ulong) CLOCKRATE * interval);
 	if (ticks > CPMT_MAX_TICKS) {
 		ticks /= CPMT_CLOCK_DIV;
 		prescaler |= CPMT_MR_ICLK_CLKDIV;	/* use system clock divided by 16 */
 	} else {
 		prescaler |= CPMT_MR_ICLK_CLK;	/* use system clock without divider */
 	}
 #ifdef	DEBUG
 	mon_printf ("clock/%d, prescale factor %d, reference %ld, ticks %ld\n",
 			(ticks > CPMT_MAX_TICKS) ? CPMT_CLOCK_DIV : 1,
 			CPMT_PRESCALER,
 			(ticks / CPMT_PRESCALER),
 			ticks
 			);
 #endif
 	/* set prescaler register */
 	*hwp->tmrp = prescaler;
 	/* clear timer counter */
 	*hwp->tcnp = 0;
 	/* set reference register */
 	*hwp->trrp = (unsigned short) (ticks / CPMT_PRESCALER);
 #ifdef	DEBUG
 	mon_printf ("tgcr=0x%x, tmr=0x%x, trr=0x%x,"
 		" tcr=0x%x, tcn=0x%x, ter=0x%x\n",
 			*hwp->tgcrp, *hwp->tmrp, *hwp->trrp,
 			*hwp->tcrp,  *hwp->tcnp, *hwp->terp
 		);
 #endif
 }
 /*
  * Handler for CPMVEC_TIMER1 interrupt
  */
 static
 void timer_handler (void *arg)
 {
 	tid_8xx_cpmtimer_t *hwp = (tid_8xx_cpmtimer_t *)arg;
 	/* printf ("** TER1=%04x ** ", *hwp->terp); */
 	/* just for demonstration */
 	mon_printf (".");
 	/* clear all possible events: Ref. and Cap. */
 	*hwp->terp = (CPMT_EVENT_CAP | CPMT_EVENT_REF);
 }

include/commproc.h

Diff comments View file @ 7c7a23b

 /*
  * MPC8xx Communication Processor Module.
  * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
  *
  * This file contains structures and information for the communication
  * processor channels.  Some CPM control and status is available
  * throught the MPC8xx internal memory map.  See immap.h for details.
  * This file only contains what I need for the moment, not the total
  * CPM capabilities.  I (or someone else) will add definitions as they
  * are needed.  -- Dan
  *
  * On the MBX board, EPPC-Bug loads CPM microcode into the first 512
  * bytes of the DP RAM and relocates the I2C parameter area to the
  * IDMA1 space.  The remaining DP RAM is available for buffer descriptors
  * or other use.
  */
 #ifndef __CPM_8XX__
 #define __CPM_8XX__
 #include <linux/config.h>
 #include <asm/8xx_immap.h>
 /* CPM Command register.
 */
-#define CPM_CR_RST	((ushort)0x8000)
+#define CPM_CR_RST		((ushort)0x8000)
-#define CPM_CR_OPCODE	((ushort)0x0f00)
+#define CPM_CR_OPCODE		((ushort)0x0f00)
-#define CPM_CR_CHAN	((ushort)0x00f0)
+#define CPM_CR_CHAN		((ushort)0x00f0)
-#define CPM_CR_FLG	((ushort)0x0001)
+#define CPM_CR_FLG		((ushort)0x0001)
 /* Some commands (there are more...later)
 */
 #define CPM_CR_INIT_TRX		((ushort)0x0000)
 #define CPM_CR_INIT_RX		((ushort)0x0001)
 #define CPM_CR_INIT_TX		((ushort)0x0002)
 #define CPM_CR_HUNT_MODE	((ushort)0x0003)
 #define CPM_CR_STOP_TX		((ushort)0x0004)
 #define CPM_CR_RESTART_TX	((ushort)0x0006)
 #define CPM_CR_SET_GADDR	((ushort)0x0008)
 /* Channel numbers.
 */
-#define CPM_CR_CH_SCC1	((ushort)0x0000)
+#define CPM_CR_CH_SCC1		((ushort)0x0000)
-#define CPM_CR_CH_I2C	((ushort)0x0001)	/* I2C and IDMA1 */
+#define CPM_CR_CH_I2C		((ushort)0x0001)    /* I2C and IDMA1 */
-#define CPM_CR_CH_SCC2	((ushort)0x0004)
+#define CPM_CR_CH_SCC2		((ushort)0x0004)
-#define CPM_CR_CH_SPI	((ushort)0x0005)	/* SPI / IDMA2 / Timers */
+#define CPM_CR_CH_SPI		((ushort)0x0005)    /* SPI/IDMA2/Timers */
-#define CPM_CR_CH_SCC3	((ushort)0x0008)
+#define CPM_CR_CH_SCC3		((ushort)0x0008)
-#define CPM_CR_CH_SMC1	((ushort)0x0009)	/* SMC1 / DSP1 */
+#define CPM_CR_CH_SMC1		((ushort)0x0009)    /* SMC1 / DSP1 */
-#define CPM_CR_CH_SCC4	((ushort)0x000c)
+#define CPM_CR_CH_SCC4		((ushort)0x000c)
-#define CPM_CR_CH_SMC2	((ushort)0x000d)	/* SMC2 / DSP2 */
+#define CPM_CR_CH_SMC2		((ushort)0x000d)    /* SMC2 / DSP2 */
 #define mk_cr_cmd(CH, CMD)	((CMD << 8) | (CH << 4))
 /*
  * DPRAM defines and allocation functions
  */
 /* The dual ported RAM is multi-functional.  Some areas can be (and are
  * being) used for microcode.  There is an area that can only be used
  * as data ram for buffer descriptors, which is all we use right now.
  * Currently the first 512 and last 256 bytes are used for microcode.
  */
 #ifdef  CFG_ALLOC_DPRAM
 #define CPM_DATAONLY_BASE	((uint)0x0800)
 #define CPM_DATAONLY_SIZE	((uint)0x0700)
 #define CPM_DP_NOSPACE		((uint)0x7fffffff)
 #else
 #define CPM_SERIAL_BASE		0x0800
 #define CPM_I2C_BASE		0x0820
 #define CPM_SPI_BASE		0x0840
 #define CPM_FEC_BASE		0x0860
 #define CPM_WLKBD_BASE		0x0880
 #define CPM_SCC_BASE		0x0900
 #define CPM_POST_BASE		0x0980
 #endif
 #ifndef CFG_CPM_POST_WORD_ADDR
 #define CPM_POST_WORD_ADDR	0x07FC
 #else
 #define CPM_POST_WORD_ADDR	CFG_CPM_POST_WORD_ADDR
 #endif
 #define BD_IIC_START	((uint) 0x0400) /* <- please use CPM_I2C_BASE !! */
 /* Export the base address of the communication processor registers
  * and dual port ram.
  */
 extern	cpm8xx_t	*cpmp;		/* Pointer to comm processor */
 /* Buffer descriptors used by many of the CPM protocols.
 */
 typedef struct cpm_buf_desc {
 	ushort	cbd_sc;		/* Status and Control */
 	ushort	cbd_datlen;	/* Data length in buffer */
 	uint	cbd_bufaddr;	/* Buffer address in host memory */
 } cbd_t;
 #define BD_SC_EMPTY	((ushort)0x8000)	/* Recieve is empty */
 #define BD_SC_READY	((ushort)0x8000)	/* Transmit is ready */
 #define BD_SC_WRAP	((ushort)0x2000)	/* Last buffer descriptor */
 #define BD_SC_INTRPT	((ushort)0x1000)	/* Interrupt on change */
 #define BD_SC_LAST	((ushort)0x0800)	/* Last buffer in frame */
 #define BD_SC_TC	((ushort)0x0400)	/* Transmit CRC */
 #define BD_SC_CM	((ushort)0x0200)	/* Continous mode */
 #define BD_SC_ID	((ushort)0x0100)	/* Rec'd too many idles */
 #define BD_SC_P		((ushort)0x0100)	/* xmt preamble */
 #define BD_SC_BR	((ushort)0x0020)	/* Break received */
 #define BD_SC_FR	((ushort)0x0010)	/* Framing error */
 #define BD_SC_PR	((ushort)0x0008)	/* Parity error */
 #define BD_SC_OV	((ushort)0x0002)	/* Overrun */
 #define BD_SC_CD	((ushort)0x0001)	/* Carrier Detect lost */
 /* Parameter RAM offsets.
 */
 #define PROFF_SCC1	((uint)0x0000)
 #define PROFF_IIC	((uint)0x0080)
 #define PROFF_SCC2	((uint)0x0100)
 #define PROFF_SPI	((uint)0x0180)
 #define PROFF_SCC3	((uint)0x0200)
 #define PROFF_SMC1	((uint)0x0280)
 #define PROFF_SCC4	((uint)0x0300)
 #define PROFF_SMC2	((uint)0x0380)
 /* Define enough so I can at least use the serial port as a UART.
  * The MBX uses SMC1 as the host serial port.
  */
 typedef struct smc_uart {
 	ushort	smc_rbase;	/* Rx Buffer descriptor base address */
 	ushort	smc_tbase;	/* Tx Buffer descriptor base address */
 	u_char	smc_rfcr;	/* Rx function code */
 	u_char	smc_tfcr;	/* Tx function code */
 	ushort	smc_mrblr;	/* Max receive buffer length */
 	uint	smc_rstate;	/* Internal */
 	uint	smc_idp;	/* Internal */
 	ushort	smc_rbptr;	/* Internal */
 	ushort	smc_ibc;	/* Internal */
 	uint	smc_rxtmp;	/* Internal */
 	uint	smc_tstate;	/* Internal */
 	uint	smc_tdp;	/* Internal */
 	ushort	smc_tbptr;	/* Internal */
 	ushort	smc_tbc;	/* Internal */
 	uint	smc_txtmp;	/* Internal */
 	ushort	smc_maxidl;	/* Maximum idle characters */
 	ushort	smc_tmpidl;	/* Temporary idle counter */
 	ushort	smc_brklen;	/* Last received break length */
 	ushort	smc_brkec;	/* rcv'd break condition counter */
 	ushort	smc_brkcr;	/* xmt break count register */
 	ushort	smc_rmask;	/* Temporary bit mask */
 } smc_uart_t;
 /* Function code bits.
 */
 #define SMC_EB	((u_char)0x10)	/* Set big endian byte order */
 /* SMC uart mode register.
 */
 #define	SMCMR_REN	((ushort)0x0001)
 #define SMCMR_TEN	((ushort)0x0002)
 #define SMCMR_DM	((ushort)0x000c)
 #define SMCMR_SM_GCI	((ushort)0x0000)
 #define SMCMR_SM_UART	((ushort)0x0020)
 #define SMCMR_SM_TRANS	((ushort)0x0030)
 #define SMCMR_SM_MASK	((ushort)0x0030)
 #define SMCMR_PM_EVEN	((ushort)0x0100)	/* Even parity, else odd */
 #define SMCMR_REVD	SMCMR_PM_EVEN
 #define SMCMR_PEN	((ushort)0x0200)	/* Parity enable */
 #define SMCMR_BS	SMCMR_PEN
 #define SMCMR_SL	((ushort)0x0400)	/* Two stops, else one */
 #define SMCR_CLEN_MASK	((ushort)0x7800)	/* Character length */
 #define smcr_mk_clen(C)	(((C) << 11) & SMCR_CLEN_MASK)
 /* SMC2 as Centronics parallel printer.  It is half duplex, in that
  * it can only receive or transmit.  The parameter ram values for
  * each direction are either unique or properly overlap, so we can
  * include them in one structure.
  */
 typedef struct smc_centronics {
 	ushort	scent_rbase;
 	ushort	scent_tbase;
 	u_char	scent_cfcr;
 	u_char	scent_smask;
 	ushort	scent_mrblr;
 	uint	scent_rstate;
 	uint	scent_r_ptr;
 	ushort	scent_rbptr;
 	ushort	scent_r_cnt;
 	uint	scent_rtemp;
 	uint	scent_tstate;
 	uint	scent_t_ptr;
 	ushort	scent_tbptr;
 	ushort	scent_t_cnt;
 	uint	scent_ttemp;
 	ushort	scent_max_sl;
 	ushort	scent_sl_cnt;
 	ushort	scent_character1;
 	ushort	scent_character2;
 	ushort	scent_character3;
 	ushort	scent_character4;
 	ushort	scent_character5;
 	ushort	scent_character6;
 	ushort	scent_character7;
 	ushort	scent_character8;
 	ushort	scent_rccm;
 	ushort	scent_rccr;
 } smc_cent_t;
 /* Centronics Status Mask Register.
 */
 #define SMC_CENT_F	((u_char)0x08)
 #define SMC_CENT_PE	((u_char)0x04)
 #define SMC_CENT_S	((u_char)0x02)
 /* SMC Event and Mask register.
 */
 #define	SMCM_BRKE	((unsigned char)0x40)	/* When in UART Mode */
 #define	SMCM_BRK	((unsigned char)0x10)	/* When in UART Mode */
 #define	SMCM_TXE	((unsigned char)0x10)	/* When in Transparent Mode */
 #define	SMCM_BSY	((unsigned char)0x04)
 #define	SMCM_TX		((unsigned char)0x02)
 #define	SMCM_RX		((unsigned char)0x01)
 /* Baud rate generators.
 */
 #define CPM_BRG_RST		((uint)0x00020000)
 #define CPM_BRG_EN		((uint)0x00010000)
 #define CPM_BRG_EXTC_INT	((uint)0x00000000)
 #define CPM_BRG_EXTC_CLK2	((uint)0x00004000)
 #define CPM_BRG_EXTC_CLK6	((uint)0x00008000)
 #define CPM_BRG_ATB		((uint)0x00002000)
 #define CPM_BRG_CD_MASK		((uint)0x00001ffe)
 #define CPM_BRG_DIV16		((uint)0x00000001)
 /* SI Clock Route Register
 */
 #define SICR_RCLK_SCC1_BRG1	((uint)0x00000000)
 #define SICR_TCLK_SCC1_BRG1	((uint)0x00000000)
 #define SICR_RCLK_SCC2_BRG2	((uint)0x00000800)
 #define SICR_TCLK_SCC2_BRG2	((uint)0x00000100)
 #define SICR_RCLK_SCC3_BRG3	((uint)0x00100000)
 #define SICR_TCLK_SCC3_BRG3	((uint)0x00020000)
 #define SICR_RCLK_SCC4_BRG4	((uint)0x18000000)
 #define SICR_TCLK_SCC4_BRG4	((uint)0x03000000)
 /* SCCs.
 */
 #define SCC_GSMRH_IRP		((uint)0x00040000)
 #define SCC_GSMRH_GDE		((uint)0x00010000)
 #define SCC_GSMRH_TCRC_CCITT	((uint)0x00008000)
 #define SCC_GSMRH_TCRC_BISYNC	((uint)0x00004000)
 #define SCC_GSMRH_TCRC_HDLC	((uint)0x00000000)
 #define SCC_GSMRH_REVD		((uint)0x00002000)
 #define SCC_GSMRH_TRX		((uint)0x00001000)
 #define SCC_GSMRH_TTX		((uint)0x00000800)
 #define SCC_GSMRH_CDP		((uint)0x00000400)
 #define SCC_GSMRH_CTSP		((uint)0x00000200)
 #define SCC_GSMRH_CDS		((uint)0x00000100)
 #define SCC_GSMRH_CTSS		((uint)0x00000080)
 #define SCC_GSMRH_TFL		((uint)0x00000040)
 #define SCC_GSMRH_RFW		((uint)0x00000020)
 #define SCC_GSMRH_TXSY		((uint)0x00000010)
 #define SCC_GSMRH_SYNL16	((uint)0x0000000c)
 #define SCC_GSMRH_SYNL8		((uint)0x00000008)
 #define SCC_GSMRH_SYNL4		((uint)0x00000004)
 #define SCC_GSMRH_RTSM		((uint)0x00000002)
 #define SCC_GSMRH_RSYN		((uint)0x00000001)
 #define SCC_GSMRL_SIR		((uint)0x80000000)	/* SCC2 only */
 #define SCC_GSMRL_EDGE_NONE	((uint)0x60000000)
 #define SCC_GSMRL_EDGE_NEG	((uint)0x40000000)
 #define SCC_GSMRL_EDGE_POS	((uint)0x20000000)
 #define SCC_GSMRL_EDGE_BOTH	((uint)0x00000000)
 #define SCC_GSMRL_TCI		((uint)0x10000000)
 #define SCC_GSMRL_TSNC_3	((uint)0x0c000000)
 #define SCC_GSMRL_TSNC_4	((uint)0x08000000)
 #define SCC_GSMRL_TSNC_14	((uint)0x04000000)
 #define SCC_GSMRL_TSNC_INF	((uint)0x00000000)
 #define SCC_GSMRL_RINV		((uint)0x02000000)
 #define SCC_GSMRL_TINV		((uint)0x01000000)
 #define SCC_GSMRL_TPL_128	((uint)0x00c00000)
 #define SCC_GSMRL_TPL_64	((uint)0x00a00000)
 #define SCC_GSMRL_TPL_48	((uint)0x00800000)
 #define SCC_GSMRL_TPL_32	((uint)0x00600000)
 #define SCC_GSMRL_TPL_16	((uint)0x00400000)
 #define SCC_GSMRL_TPL_8		((uint)0x00200000)
 #define SCC_GSMRL_TPL_NONE	((uint)0x00000000)
 #define SCC_GSMRL_TPP_ALL1	((uint)0x00180000)
 #define SCC_GSMRL_TPP_01	((uint)0x00100000)
 #define SCC_GSMRL_TPP_10	((uint)0x00080000)
 #define SCC_GSMRL_TPP_ZEROS	((uint)0x00000000)
 #define SCC_GSMRL_TEND		((uint)0x00040000)
 #define SCC_GSMRL_TDCR_32	((uint)0x00030000)
 #define SCC_GSMRL_TDCR_16	((uint)0x00020000)
 #define SCC_GSMRL_TDCR_8	((uint)0x00010000)
 #define SCC_GSMRL_TDCR_1	((uint)0x00000000)
 #define SCC_GSMRL_RDCR_32	((uint)0x0000c000)
 #define SCC_GSMRL_RDCR_16	((uint)0x00008000)
 #define SCC_GSMRL_RDCR_8	((uint)0x00004000)
 #define SCC_GSMRL_RDCR_1	((uint)0x00000000)
 #define SCC_GSMRL_RENC_DFMAN	((uint)0x00003000)
 #define SCC_GSMRL_RENC_MANCH	((uint)0x00002000)
 #define SCC_GSMRL_RENC_FM0	((uint)0x00001000)
 #define SCC_GSMRL_RENC_NRZI	((uint)0x00000800)
 #define SCC_GSMRL_RENC_NRZ	((uint)0x00000000)
 #define SCC_GSMRL_TENC_DFMAN	((uint)0x00000600)
 #define SCC_GSMRL_TENC_MANCH	((uint)0x00000400)
 #define SCC_GSMRL_TENC_FM0	((uint)0x00000200)
 #define SCC_GSMRL_TENC_NRZI	((uint)0x00000100)
 #define SCC_GSMRL_TENC_NRZ	((uint)0x00000000)
 #define SCC_GSMRL_DIAG_LE	((uint)0x000000c0)	/* Loop and echo */
 #define SCC_GSMRL_DIAG_ECHO	((uint)0x00000080)
 #define SCC_GSMRL_DIAG_LOOP	((uint)0x00000040)
 #define SCC_GSMRL_DIAG_NORM	((uint)0x00000000)
 #define SCC_GSMRL_ENR		((uint)0x00000020)
 #define SCC_GSMRL_ENT		((uint)0x00000010)
 #define SCC_GSMRL_MODE_ENET	((uint)0x0000000c)
 #define SCC_GSMRL_MODE_DDCMP	((uint)0x00000009)
 #define SCC_GSMRL_MODE_BISYNC	((uint)0x00000008)
 #define SCC_GSMRL_MODE_V14	((uint)0x00000007)
 #define SCC_GSMRL_MODE_AHDLC	((uint)0x00000006)
 #define SCC_GSMRL_MODE_PROFIBUS	((uint)0x00000005)
 #define SCC_GSMRL_MODE_UART	((uint)0x00000004)
 #define SCC_GSMRL_MODE_SS7	((uint)0x00000003)
 #define SCC_GSMRL_MODE_ATALK	((uint)0x00000002)
 #define SCC_GSMRL_MODE_HDLC	((uint)0x00000000)
 #define SCC_TODR_TOD		((ushort)0x8000)
 /* SCC Event and Mask register.
 */
 #define	SCCM_TXE	((unsigned char)0x10)
 #define	SCCM_BSY	((unsigned char)0x04)
 #define	SCCM_TX		((unsigned char)0x02)
 #define	SCCM_RX		((unsigned char)0x01)
 typedef struct scc_param {
 	ushort	scc_rbase;	/* Rx Buffer descriptor base address */
 	ushort	scc_tbase;	/* Tx Buffer descriptor base address */
 	u_char	scc_rfcr;	/* Rx function code */
 	u_char	scc_tfcr;	/* Tx function code */
 	ushort	scc_mrblr;	/* Max receive buffer length */
 	uint	scc_rstate;	/* Internal */
 	uint	scc_idp;	/* Internal */
 	ushort	scc_rbptr;	/* Internal */
 	ushort	scc_ibc;	/* Internal */
 	uint	scc_rxtmp;	/* Internal */
 	uint	scc_tstate;	/* Internal */
 	uint	scc_tdp;	/* Internal */
 	ushort	scc_tbptr;	/* Internal */
 	ushort	scc_tbc;	/* Internal */
 	uint	scc_txtmp;	/* Internal */
 	uint	scc_rcrc;	/* Internal */
 	uint	scc_tcrc;	/* Internal */
 } sccp_t;
 /* Function code bits.
 */
 #define SCC_EB	((u_char)0x10)	/* Set big endian byte order */
 /* CPM Ethernet through SCCx.
  */
 typedef struct scc_enet {
 	sccp_t	sen_genscc;
 	uint	sen_cpres;	/* Preset CRC */
 	uint	sen_cmask;	/* Constant mask for CRC */
 	uint	sen_crcec;	/* CRC Error counter */
 	uint	sen_alec;	/* alignment error counter */
 	uint	sen_disfc;	/* discard frame counter */
 	ushort	sen_pads;	/* Tx short frame pad character */
 	ushort	sen_retlim;	/* Retry limit threshold */
 	ushort	sen_retcnt;	/* Retry limit counter */
 	ushort	sen_maxflr;	/* maximum frame length register */
 	ushort	sen_minflr;	/* minimum frame length register */
 	ushort	sen_maxd1;	/* maximum DMA1 length */
 	ushort	sen_maxd2;	/* maximum DMA2 length */
 	ushort	sen_maxd;	/* Rx max DMA */
 	ushort	sen_dmacnt;	/* Rx DMA counter */
 	ushort	sen_maxb;	/* Max BD byte count */
 	ushort	sen_gaddr1;	/* Group address filter */
 	ushort	sen_gaddr2;
 	ushort	sen_gaddr3;
 	ushort	sen_gaddr4;
 	uint	sen_tbuf0data0;	/* Save area 0 - current frame */
 	uint	sen_tbuf0data1;	/* Save area 1 - current frame */
 	uint	sen_tbuf0rba;	/* Internal */
 	uint	sen_tbuf0crc;	/* Internal */
 	ushort	sen_tbuf0bcnt;	/* Internal */
 	ushort	sen_paddrh;	/* physical address (MSB) */
 	ushort	sen_paddrm;
 	ushort	sen_paddrl;	/* physical address (LSB) */
 	ushort	sen_pper;	/* persistence */
 	ushort	sen_rfbdptr;	/* Rx first BD pointer */
 	ushort	sen_tfbdptr;	/* Tx first BD pointer */
 	ushort	sen_tlbdptr;	/* Tx last BD pointer */
 	uint	sen_tbuf1data0;	/* Save area 0 - current frame */
 	uint	sen_tbuf1data1;	/* Save area 1 - current frame */
 	uint	sen_tbuf1rba;	/* Internal */
 	uint	sen_tbuf1crc;	/* Internal */
 	ushort	sen_tbuf1bcnt;	/* Internal */
 	ushort	sen_txlen;	/* Tx Frame length counter */
 	ushort	sen_iaddr1;	/* Individual address filter */
 	ushort	sen_iaddr2;
 	ushort	sen_iaddr3;
 	ushort	sen_iaddr4;
 	ushort	sen_boffcnt;	/* Backoff counter */
 	/* NOTE: Some versions of the manual have the following items
 	 * incorrectly documented.  Below is the proper order.
 	 */
 	ushort	sen_taddrh;	/* temp address (MSB) */
 	ushort	sen_taddrm;
 	ushort	sen_taddrl;	/* temp address (LSB) */
 } scc_enet_t;
 /**********************************************************************
  *
  * Board specific configuration settings.
  *
  * Please note that we use the presence of a #define SCC_ENET and/or
  * #define FEC_ENET to enable the SCC resp. FEC ethernet drivers.
  **********************************************************************/
 /***  ADS  *************************************************************/
 #if defined(CONFIG_MPC860) && defined(CONFIG_ADS)
 /* This ENET stuff is for the MPC860ADS with ethernet on SCC1.
  */
 #define	PROFF_ENET	PROFF_SCC1
 #define	CPM_CR_ENET	CPM_CR_CH_SCC1
 #define	SCC_ENET	0
 #define PA_ENET_RXD	((ushort)0x0001)
 #define PA_ENET_TXD	((ushort)0x0002)
 #define PA_ENET_TCLK	((ushort)0x0100)
 #define PA_ENET_RCLK	((ushort)0x0200)
 #define PB_ENET_TENA	((uint)0x00001000)
 #define PC_ENET_CLSN	((ushort)0x0010)
 #define PC_ENET_RENA	((ushort)0x0020)
 #define SICR_ENET_MASK	((uint)0x000000ff)
 #define SICR_ENET_CLKRT	((uint)0x0000002c)
 /* 68160 PHY control */
 #define PC_ENET_ETHLOOP ((ushort)0x0800)
 #define PC_ENET_TPFLDL	((ushort)0x0400)
 #define PC_ENET_TPSQEL  ((ushort)0x0200)
 #endif	/* MPC860ADS */
 /***  AMX860  **********************************************/
 #if defined(CONFIG_AMX860)
 /* This ENET stuff is for the AMX860 with ethernet on SCC1.
  */
 #define PROFF_ENET	PROFF_SCC1
 #define CPM_CR_ENET	CPM_CR_CH_SCC1
 #define SCC_ENET	0
 #define PA_ENET_RXD	((ushort)0x0001)
 #define PA_ENET_TXD	((ushort)0x0002)
 #define PA_ENET_TCLK	((ushort)0x0400)
 #define PA_ENET_RCLK	((ushort)0x0800)
 #define PB_ENET_TENA	((uint)0x00001000)
 #define PC_ENET_CLSN	((ushort)0x0010)
 #define PC_ENET_RENA	((ushort)0x0020)
 #define SICR_ENET_MASK	((uint)0x000000ff)
 #define SICR_ENET_CLKRT	((uint)0x0000003e)
 /* 68160 PHY control */
 #define PB_ENET_ETHLOOP	((uint)0x00020000)
 #define PB_ENET_TPFLDL	((uint)0x00010000)
 #define PB_ENET_TPSQEL	((uint)0x00008000)
 #define PD_ENET_ETH_EN	((ushort)0x0004)
 #endif	/* CONFIG_AMX860 */
 /***  BSEIP  **********************************************************/
 #ifdef CONFIG_BSEIP
 /* This ENET stuff is for the MPC823 with ethernet on SCC2.
  * This is unique to the BSE ip-Engine board.
  */
 #define	PROFF_ENET	PROFF_SCC2
 #define	CPM_CR_ENET	CPM_CR_CH_SCC2
 #define	SCC_ENET	1
 #define PA_ENET_RXD	((ushort)0x0004)
 #define PA_ENET_TXD	((ushort)0x0008)
 #define PA_ENET_TCLK	((ushort)0x0100)
 #define PA_ENET_RCLK	((ushort)0x0200)
 #define PB_ENET_TENA	((uint)0x00002000)
 #define PC_ENET_CLSN	((ushort)0x0040)
 #define PC_ENET_RENA	((ushort)0x0080)
 /* BSE uses port B and C bits for PHY control also.
 */
 #define PB_BSE_POWERUP	((uint)0x00000004)
 #define PB_BSE_FDXDIS	((uint)0x00008000)
 #define PC_BSE_LOOPBACK	((ushort)0x0800)
 #define SICR_ENET_MASK	((uint)0x0000ff00)
 #define SICR_ENET_CLKRT	((uint)0x00002c00)
 #endif	/* CONFIG_BSEIP */
 /***  BSEIP  **********************************************************/
 #ifdef CONFIG_FLAGADM
 /* Enet configuration for the FLAGADM */
 /* Enet on SCC2 */
 #define	PROFF_ENET	PROFF_SCC2
 #define	CPM_CR_ENET	CPM_CR_CH_SCC2
 #define	SCC_ENET	1
-#define PA_ENET_RXD		((ushort)0x0004)
+#define PA_ENET_RXD	((ushort)0x0004)
-#define PA_ENET_TXD		((ushort)0x0008)
+#define PA_ENET_TXD	((ushort)0x0008)
 #define PA_ENET_TCLK	((ushort)0x0100)
 #define PA_ENET_RCLK	((ushort)0x0400)
 #define PB_ENET_TENA	((uint)0x00002000)
 #define PC_ENET_CLSN	((ushort)0x0040)
 #define PC_ENET_RENA	((ushort)0x0080)
 #define SICR_ENET_MASK	((uint)0x0000ff00)
 #define SICR_ENET_CLKRT	((uint)0x00003400)
 #endif	/* CONFIG_FLAGADM */
 /***  C2MON  **********************************************************/
 #ifdef CONFIG_C2MON
 # ifndef CONFIG_FEC_ENET	/* use SCC for 10Mbps Ethernet	*/
 #  error "Ethernet on SCC not supported on C2MON Board!"
 # else				/* Use FEC for Fast Ethernet */
 #undef	SCC_ENET
 #define FEC_ENET
 #define PD_MII_TXD1	((ushort)0x1000)	/* PD  3 */
 #define PD_MII_TXD2	((ushort)0x0800)	/* PD  4 */
 #define PD_MII_TXD3	((ushort)0x0400)	/* PD  5 */
 #define PD_MII_RX_DV	((ushort)0x0200)	/* PD  6 */
 #define PD_MII_RX_ERR	((ushort)0x0100)	/* PD  7 */
 #define PD_MII_RX_CLK	((ushort)0x0080)	/* PD  8 */
 #define PD_MII_TXD0	((ushort)0x0040)	/* PD  9 */
 #define PD_MII_RXD0	((ushort)0x0020)	/* PD 10 */
 #define PD_MII_TX_ERR	((ushort)0x0010)	/* PD 11 */
 #define PD_MII_MDC	((ushort)0x0008)	/* PD 12 */
 #define PD_MII_RXD1	((ushort)0x0004)	/* PD 13 */
 #define PD_MII_RXD2	((ushort)0x0002)	/* PD 14 */
 #define PD_MII_RXD3	((ushort)0x0001)	/* PD 15 */
 #define PD_MII_MASK	((ushort)0x1FFF)	/* PD 3...15 */
 # endif	/* CONFIG_FEC_ENET */
 #endif	/* CONFIG_C2MON */
 /*********************************************************************/
 /***  CCM  and  PCU E  ***********************************************/
 /* The PCU E  and  CCM  use the FEC on a MPC860T for Ethernet */
 #if defined (CONFIG_PCU_E) || defined(CONFIG_CCM)
 #define	FEC_ENET	/* use FEC for EThernet */
 #undef	SCC_ENET
 #define PD_MII_TXD1	((ushort)0x1000)	/* PD  3 */
 #define PD_MII_TXD2	((ushort)0x0800)	/* PD  4 */
 #define PD_MII_TXD3	((ushort)0x0400)	/* PD  5 */
 #define PD_MII_RX_DV	((ushort)0x0200)	/* PD  6 */
 #define PD_MII_RX_ERR	((ushort)0x0100)	/* PD  7 */
 #define PD_MII_RX_CLK	((ushort)0x0080)	/* PD  8 */
 #define PD_MII_TXD0	((ushort)0x0040)	/* PD  9 */
 #define PD_MII_RXD0	((ushort)0x0020)	/* PD 10 */
 #define PD_MII_TX_ERR	((ushort)0x0010)	/* PD 11 */
 #define PD_MII_MDC	((ushort)0x0008)	/* PD 12 */
 #define PD_MII_RXD1	((ushort)0x0004)	/* PD 13 */
 #define PD_MII_RXD2	((ushort)0x0002)	/* PD 14 */
 #define PD_MII_RXD3	((ushort)0x0001)	/* PD 15 */
 #define PD_MII_MASK	((ushort)0x1FFF)	/* PD 3...15 */
 #endif	/* CONFIG_PCU_E, CONFIG_CCM */
 /***  ESTEEM 192E  **************************************************/
 #ifdef CONFIG_ESTEEM192E
 /* ESTEEM192E
  * This ENET stuff is for the MPC850 with ethernet on SCC2. This
  * is very similar to the RPX-Lite configuration.
  * Note TENA , LOOPBACK , FDPLEX_DIS on Port B.
  */
 #define	PROFF_ENET	PROFF_SCC2
 #define	CPM_CR_ENET	CPM_CR_CH_SCC2
 #define	SCC_ENET	1
 #define PA_ENET_RXD	((ushort)0x0004)
 #define PA_ENET_TXD	((ushort)0x0008)
 #define PA_ENET_TCLK	((ushort)0x0200)
 #define PA_ENET_RCLK	((ushort)0x0800)
 #define PB_ENET_TENA	((uint)0x00002000)
 #define PC_ENET_CLSN	((ushort)0x0040)
 #define PC_ENET_RENA	((ushort)0x0080)
 #define SICR_ENET_MASK	((uint)0x0000ff00)
 #define SICR_ENET_CLKRT	((uint)0x00003d00)
 #define PB_ENET_LOOPBACK ((uint)0x00004000)
 #define PB_ENET_FDPLEX_DIS ((uint)0x00008000)
 #endif
 /***  FADS823  ********************************************************/
 #if defined(CONFIG_MPC823FADS) && defined(CONFIG_FADS)
 /* This ENET stuff is for the MPC823FADS with ethernet on SCC2.
  */
 #ifdef CONFIG_SCC2_ENET
 #define	PROFF_ENET	PROFF_SCC2
 #define	CPM_CR_ENET	CPM_CR_CH_SCC2
 #define	SCC_ENET	1
 #define CPMVEC_ENET	CPMVEC_SCC2
 #endif
 #ifdef CONFIG_SCC1_ENET
 #define	PROFF_ENET	PROFF_SCC1
 #define	CPM_CR_ENET	CPM_CR_CH_SCC1
 #define	SCC_ENET	0
 #define CPMVEC_ENET	CPMVEC_SCC1
 #endif
 #define PA_ENET_RXD	((ushort)0x0004)
 #define PA_ENET_TXD	((ushort)0x0008)
 #define PA_ENET_TCLK	((ushort)0x0400)
 #define PA_ENET_RCLK	((ushort)0x0200)
 #define PB_ENET_TENA	((uint)0x00002000)
 #define PC_ENET_CLSN	((ushort)0x0040)
 #define PC_ENET_RENA	((ushort)0x0080)
 #define SICR_ENET_MASK	((uint)0x0000ff00)
 #define SICR_ENET_CLKRT	((uint)0x00002e00)
 #endif	/* CONFIG_FADS823FADS */
 /***  FADS850SAR  ********************************************************/
 #if defined(CONFIG_MPC850SAR) && defined(CONFIG_FADS)
 /* This ENET stuff is for the MPC850SAR with ethernet on SCC2.  Some of
  * this may be unique to the FADS850SAR configuration.
  * Note TENA is on Port B.
  */
 #define	PROFF_ENET	PROFF_SCC2
 #define	CPM_CR_ENET	CPM_CR_CH_SCC2
 #define	SCC_ENET	1
 #define PA_ENET_RXD	((ushort)0x0004)	/* PA 13 */
 #define PA_ENET_TXD	((ushort)0x0008)	/* PA 12 */
 #define PA_ENET_RCLK	((ushort)0x0200)	/* PA 6 */
 #define PA_ENET_TCLK	((ushort)0x0800)	/* PA 4 */
 #define PB_ENET_TENA	((uint)0x00002000)	/* PB 18 */
 #define PC_ENET_CLSN	((ushort)0x0040)	/* PC 9 */
 #define PC_ENET_RENA	((ushort)0x0080)	/* PC 8 */
 #define SICR_ENET_MASK	((uint)0x0000ff00)
 #define SICR_ENET_CLKRT	((uint)0x00002f00)	/* RCLK-CLK2, TCLK-CLK4 */
 #endif	/* CONFIG_FADS850SAR */
 /***  FADS860T********************************************************/
 #if defined(CONFIG_MPC860T) && defined(CONFIG_FADS)
 /* This ENET stuff is for the MPC860TFADS with ethernet on SCC1.
  */
 #ifdef CONFIG_SCC1_ENET
 #define	SCC_ENET	0
 #endif	/* CONFIG_SCC1_ETHERNET */
 #define	PROFF_ENET	PROFF_SCC1
 #define	CPM_CR_ENET	CPM_CR_CH_SCC1
 #define PA_ENET_RXD	((ushort)0x0001)
 #define PA_ENET_TXD	((ushort)0x0002)
 #define PA_ENET_TCLK	((ushort)0x0100)
 #define PA_ENET_RCLK	((ushort)0x0200)
 #define PB_ENET_TENA	((uint)0x00001000)
 #define PC_ENET_CLSN	((ushort)0x0010)
 #define PC_ENET_RENA	((ushort)0x0020)
 #define SICR_ENET_MASK	((uint)0x000000ff)
 #define SICR_ENET_CLKRT	((uint)0x0000002c)
 /* This ENET stuff is for the MPC860TFADS with ethernet on FEC.
  */
 #ifdef CONFIG_FEC_ENET
 #define	FEC_ENET	/* use FEC for EThernet */
 #endif	/* CONFIG_FEC_ETHERNET */
 #endif	/* CONFIG_FADS860T */
 /***  FPS850L, FPS860L  ************************************************/
 #if defined(CONFIG_FPS850L) || defined(CONFIG_FPS860L)
 /* Bits in parallel I/O port registers that have to be set/cleared
  * to configure the pins for SCC2 use.
  */
 #define	PROFF_ENET	PROFF_SCC2
 #define	CPM_CR_ENET	CPM_CR_CH_SCC2
 #define	SCC_ENET	1
 #define PA_ENET_RXD	((ushort)0x0004)	/* PA 13 */
 #define PA_ENET_TXD	((ushort)0x0008)	/* PA 12 */
 #define PA_ENET_RCLK	((ushort)0x0100)	/* PA  7 */
 #define PA_ENET_TCLK	((ushort)0x0400)	/* PA  5 */
 #define PC_ENET_TENA	((ushort)0x0002)	/* PC 14 */
 #define PC_ENET_CLSN	((ushort)0x0040)	/* PC  9 */
 #define PC_ENET_RENA	((ushort)0x0080)	/* PC  8 */
 /* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
  * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
  */
 #define SICR_ENET_MASK	((uint)0x0000ff00)
 #define SICR_ENET_CLKRT	((uint)0x00002600)
 #endif	/* CONFIG_FPS850L, CONFIG_FPS860L */
 /*** GEN860T **********************************************************/
 #if defined(CONFIG_GEN860T)
 #undef	SCC_ENET
 #define	FEC_ENET
 #define PD_MII_TXD1	((ushort)0x1000)	/* PD  3 	*/
 #define PD_MII_TXD2	((ushort)0x0800)	/* PD  4 	*/
 #define PD_MII_TXD3	((ushort)0x0400)	/* PD  5 	*/
 #define PD_MII_RX_DV	((ushort)0x0200)	/* PD  6 	*/
 #define PD_MII_RX_ERR	((ushort)0x0100)	/* PD  7 	*/
 #define PD_MII_RX_CLK	((ushort)0x0080)	/* PD  8 	*/
 #define PD_MII_TXD0	((ushort)0x0040)	/* PD  9 	*/
 #define PD_MII_RXD0	((ushort)0x0020)	/* PD 10 	*/
 #define PD_MII_TX_ERR	((ushort)0x0010)	/* PD 11 	*/
 #define PD_MII_MDC	((ushort)0x0008)	/* PD 12 	*/
 #define PD_MII_RXD1	((ushort)0x0004)	/* PD 13 	*/
 #define PD_MII_RXD2	((ushort)0x0002)	/* PD 14 	*/
 #define PD_MII_RXD3	((ushort)0x0001)	/* PD 15 	*/
 #define PD_MII_MASK	((ushort)0x1FFF)	/* PD 3-15	*/
 #endif	/* CONFIG_GEN860T */
 /***  GENIETV  ********************************************************/
 #if defined(CONFIG_GENIETV)
 /* Ethernet is only on SCC2 */
 #define CONFIG_SCC2_ENET
 #define	PROFF_ENET	PROFF_SCC2
 #define	CPM_CR_ENET	CPM_CR_CH_SCC2
 #define	SCC_ENET	1
 #define CPMVEC_ENET	CPMVEC_SCC2
 #define PA_ENET_RXD	((ushort)0x0004)	/* PA 13 */
 #define PA_ENET_TXD	((ushort)0x0008)	/* PA 12 */
 #define PA_ENET_TCLK	((ushort)0x0400)	/* PA  5 */
 #define PA_ENET_RCLK	((ushort)0x0200)	/* PA  6 */
 #define PB_ENET_TENA	((uint)0x00002000)	/* PB 18 */
 #define PC_ENET_CLSN	((ushort)0x0040)	/* PC  9 */
 #define PC_ENET_RENA	((ushort)0x0080)	/* PC  8 */
 #define SICR_ENET_MASK	((uint)0x0000ff00)
 #define SICR_ENET_CLKRT	((uint)0x00002e00)
 #endif	/* CONFIG_GENIETV */
 /*** GTH ******************************************************/
 #ifdef CONFIG_GTH
 #ifdef CONFIG_FEC_ENET
 #define	FEC_ENET	/* use FEC for EThernet */
 #endif	/* CONFIG_FEC_ETHERNET */
 /* This ENET stuff is for GTH 10 Mbit ( SCC ) */
 #define	PROFF_ENET	PROFF_SCC1
 #define	CPM_CR_ENET	CPM_CR_CH_SCC1
 #define	SCC_ENET	0
 #define PA_ENET_RXD	((ushort)0x0001) /* PA15 */
 #define PA_ENET_TXD	((ushort)0x0002) /* PA14 */
 #define PA_ENET_TCLK	((ushort)0x0800) /* PA4 */
 #define PA_ENET_RCLK	((ushort)0x0400) /* PA5 */
 #define PB_ENET_TENA	((uint)0x00001000) /* PB19 */
 #define PC_ENET_CLSN	((ushort)0x0010) /* PC11 */
 #define PC_ENET_RENA	((ushort)0x0020) /* PC10 */
 /* NOTE. This is reset for 10Mbit port only */
 #define PC_ENET_RESET	((ushort)0x0100)	/* PC 7 */
 #define SICR_ENET_MASK	((uint)0x000000ff)
 /* TCLK PA4 -->CLK4, RCLK PA5 -->CLK3 */
 #define SICR_ENET_CLKRT	((uint)0x00000037)
 #endif	/* CONFIG_GTH */
 /*** HERMES-PRO ******************************************************/
 /* The HERMES-PRO uses the FEC on a MPC860T for Ethernet */
 #ifdef CONFIG_HERMES
 #define	FEC_ENET	/* use FEC for EThernet */
 #undef	SCC_ENET
 #define PD_MII_TXD1	((ushort)0x1000)	/* PD  3 */
 #define PD_MII_TXD2	((ushort)0x0800)	/* PD  4 */
 #define PD_MII_TXD3	((ushort)0x0400)	/* PD  5 */
 #define PD_MII_RX_DV	((ushort)0x0200)	/* PD  6 */
 #define PD_MII_RX_ERR	((ushort)0x0100)	/* PD  7 */
 #define PD_MII_RX_CLK	((ushort)0x0080)	/* PD  8 */
 #define PD_MII_TXD0	((ushort)0x0040)	/* PD  9 */
 #define PD_MII_RXD0	((ushort)0x0020)	/* PD 10 */
 #define PD_MII_TX_ERR	((ushort)0x0010)	/* PD 11 */
 #define PD_MII_MDC	((ushort)0x0008)	/* PD 12 */
 #define PD_MII_RXD1	((ushort)0x0004)	/* PD 13 */
 #define PD_MII_RXD2	((ushort)0x0002)	/* PD 14 */
 #define PD_MII_RXD3	((ushort)0x0001)	/* PD 15 */
 #define PD_MII_MASK	((ushort)0x1FFF)	/* PD 3...15 */
 #endif	/* CONFIG_HERMES */
 /***  IAD210  **********************************************************/
 /* The IAD210 uses the FEC on a MPC860P for Ethernet */
 #if defined(CONFIG_IAD210)
 # define  FEC_ENET    /* use FEC for Ethernet */
 # undef   SCC_ENET
 # define PD_MII_TXD1    ((ushort) 0x1000 )	/* PD  3 */
 # define PD_MII_TXD2    ((ushort) 0x0800 )	/* PD  4 */
 # define PD_MII_TXD3    ((ushort) 0x0400 )	/* PD  5 */
 # define PD_MII_RX_DV   ((ushort) 0x0200 )	/* PD  6 */
 # define PD_MII_RX_ERR  ((ushort) 0x0100 )	/* PD  7 */
 # define PD_MII_RX_CLK  ((ushort) 0x0080 )	/* PD  8 */
 # define PD_MII_TXD0    ((ushort) 0x0040 )	/* PD  9 */
 # define PD_MII_RXD0    ((ushort) 0x0020 )	/* PD 10 */
 # define PD_MII_TX_ERR  ((ushort) 0x0010 )	/* PD 11 */
 # define PD_MII_MDC     ((ushort) 0x0008 )	/* PD 12 */
 # define PD_MII_RXD1    ((ushort) 0x0004 )	/* PD 13 */
 # define PD_MII_RXD2    ((ushort) 0x0002 )	/* PD 14 */
 # define PD_MII_RXD3    ((ushort) 0x0001 )	/* PD 15 */
 # define PD_MII_MASK    ((ushort) 0x1FFF )   /* PD 3...15 */
 #endif	/* CONFIG_IAD210 */
 /*** ICU862  **********************************************************/
 #if defined(CONFIG_ICU862)
 #ifdef CONFIG_FEC_ENET
 #define FEC_ENET	/* use FEC for EThernet */
 #endif  /* CONFIG_FEC_ETHERNET */
 #endif /* CONFIG_ICU862 */
 /***  IP860  **********************************************************/
 #if defined(CONFIG_IP860)
 /* Bits in parallel I/O port registers that have to be set/cleared
  * to configure the pins for SCC1 use.
  */
 #define	PROFF_ENET	PROFF_SCC1
 #define	CPM_CR_ENET	CPM_CR_CH_SCC1
 #define	SCC_ENET	0
 #define PA_ENET_RXD	((ushort)0x0001)	/* PA 15 */
 #define PA_ENET_TXD	((ushort)0x0002)	/* PA 14 */
 #define PA_ENET_RCLK	((ushort)0x0200)	/* PA  6 */
 #define PA_ENET_TCLK	((ushort)0x0100)	/* PA  7 */
 #define PC_ENET_TENA	((ushort)0x0001)	/* PC 15 */
 #define PC_ENET_CLSN	((ushort)0x0010)	/* PC 11 */
 #define PC_ENET_RENA	((ushort)0x0020)	/* PC 10 */
 #define PB_ENET_RESET	(uint)0x00000008	/* PB 28 */
 #define PB_ENET_JABD	(uint)0x00000004	/* PB 29 */
 /* Control bits in the SICR to route TCLK (CLK1) and RCLK (CLK2) to
  * SCC1.  Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
  */
 #define SICR_ENET_MASK	((uint)0x000000ff)
 #define SICR_ENET_CLKRT	((uint)0x0000002C)
 #endif	/* CONFIG_IP860 */
 /*** IVMS8  **********************************************************/
 /* The IVMS8 uses the FEC on a MPC860T for Ethernet */
 #if defined(CONFIG_IVMS8) || defined(CONFIG_IVML24)
 #define	FEC_ENET	/* use FEC for EThernet */
 #undef	SCC_ENET
 #define	PB_ENET_POWER	((uint)0x00010000)	/* PB 15 */
 #define PC_ENET_RESET	((ushort)0x0010)	/* PC 11 */
 #define PD_MII_TXD1	((ushort)0x1000)	/* PD  3 */
 #define PD_MII_TXD2	((ushort)0x0800)	/* PD  4 */
 #define PD_MII_TXD3	((ushort)0x0400)	/* PD  5 */
 #define PD_MII_RX_DV	((ushort)0x0200)	/* PD  6 */
 #define PD_MII_RX_ERR	((ushort)0x0100)	/* PD  7 */
 #define PD_MII_RX_CLK	((ushort)0x0080)	/* PD  8 */
 #define PD_MII_TXD0	((ushort)0x0040)	/* PD  9 */
 #define PD_MII_RXD0	((ushort)0x0020)	/* PD 10 */
 #define PD_MII_TX_ERR	((ushort)0x0010)	/* PD 11 */
 #define PD_MII_MDC	((ushort)0x0008)	/* PD 12 */
 #define PD_MII_RXD1	((ushort)0x0004)	/* PD 13 */
 #define PD_MII_RXD2	((ushort)0x0002)	/* PD 14 */
 #define PD_MII_RXD3	((ushort)0x0001)	/* PD 15 */
 #define PD_MII_MASK	((ushort)0x1FFF)	/* PD 3...15 */
 #endif	/* CONFIG_IVMS8, CONFIG_IVML24 */
 /***  KUP4K  *********************************************************/
 /* The KUP4K uses the FEC on a MPC855T for Ethernet */
 #if defined(CONFIG_KUP4K)
 #define	FEC_ENET	/* use FEC for EThernet */
 #undef	SCC_ENET
 #define	PB_ENET_POWER	((uint)0x00010000)	/* PB 15 */
 #define PC_ENET_RESET	((ushort)0x0010)	/* PC 11 */
 #define PD_MII_TXD1	((ushort)0x1000)	/* PD  3 */
 #define PD_MII_TXD2	((ushort)0x0800)	/* PD  4 */
 #define PD_MII_TXD3	((ushort)0x0400)	/* PD  5 */
 #define PD_MII_RX_DV	((ushort)0x0200)	/* PD  6 */
 #define PD_MII_RX_ERR	((ushort)0x0100)	/* PD  7 */
 #define PD_MII_RX_CLK	((ushort)0x0080)	/* PD  8 */
 #define PD_MII_TXD0	((ushort)0x0040)	/* PD  9 */
 #define PD_MII_RXD0	((ushort)0x0020)	/* PD 10 */
 #define PD_MII_TX_ERR	((ushort)0x0010)	/* PD 11 */
 #define PD_MII_MDC	((ushort)0x0008)	/* PD 12 */
 #define PD_MII_RXD1	((ushort)0x0004)	/* PD 13 */
 #define PD_MII_RXD2	((ushort)0x0002)	/* PD 14 */
 #define PD_MII_RXD3	((ushort)0x0001)	/* PD 15 */
 #define PD_MII_MASK	((ushort)0x1FFF)	/* PD 3...15 */
 #endif	/* CONFIG_KUP4K */
 /***  LANTEC  *********************************************************/
 #if defined(CONFIG_LANTEC) && CONFIG_LANTEC >= 2
 /* Bits in parallel I/O port registers that have to be set/cleared
  * to configure the pins for SCC2 use.
  */
 #define	PROFF_ENET	PROFF_SCC2
 #define	CPM_CR_ENET	CPM_CR_CH_SCC2
 #define	SCC_ENET	1
 #define PA_ENET_RXD	((ushort)0x0004)	/* PA 13 */
 #define PA_ENET_TXD	((ushort)0x0008)	/* PA 12 */
 #define PA_ENET_RCLK	((ushort)0x0200)	/* PA  6 */
 #define PA_ENET_TCLK	((ushort)0x0400)	/* PA  5 */
 #define PB_ENET_TENA	((uint)0x00002000)	/* PB 18 */
 #define PC_ENET_LBK	((ushort)0x0010)	/* PC 11 */
 #define PC_ENET_CLSN	((ushort)0x0040)	/* PC  9 */
 #define PC_ENET_RENA	((ushort)0x0080)	/* PC  8 */
 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK2) to
  * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
  */
 #define SICR_ENET_MASK	((uint)0x0000FF00)
 #define SICR_ENET_CLKRT	((uint)0x00002E00)
 #endif	/* CONFIG_LANTEC v2 */
 /***  LWMON  **********************************************************/
 #if defined(CONFIG_LWMON) && !defined(CONFIG_8xx_CONS_SCC2)
 /* Bits in parallel I/O port registers that have to be set/cleared
  * to configure the pins for SCC2 use.
  */
 #define	PROFF_ENET	PROFF_SCC2
 #define	CPM_CR_ENET	CPM_CR_CH_SCC2
 #define	SCC_ENET	1
 #define PA_ENET_RXD	((ushort)0x0004)	/* PA 13 */
 #define PA_ENET_TXD	((ushort)0x0008)	/* PA 12 */
 #define PA_ENET_RCLK	((ushort)0x0800)	/* PA  4 */
 #define PA_ENET_TCLK	((ushort)0x0400)	/* PA  5 */
 #define PB_ENET_TENA	((uint)0x00002000)	/* PB 18 */
 #define PC_ENET_CLSN	((ushort)0x0040)	/* PC  9 */
 #define PC_ENET_RENA	((ushort)0x0080)	/* PC  8 */
 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK4) to
  * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
  */
 #define SICR_ENET_MASK	((uint)0x0000ff00)
 #define SICR_ENET_CLKRT	((uint)0x00003E00)
 #endif	/* CONFIG_LWMON */
 /***  NX823  ***********************************************/
 #if defined(CONFIG_NX823)
 /* Bits in parallel I/O port registers that have to be set/cleared
  * to configure the pins for SCC1 use.
  */
 #define PROFF_ENET	PROFF_SCC2
 #define CPM_CR_ENET	CPM_CR_CH_SCC2
 #define SCC_ENET	1
-#define PA_ENET_RXD  ((ushort)0x0004)  /* PA 13 */
+#define PA_ENET_RXD	((ushort)0x0004)  /* PA 13 */
-#define PA_ENET_TXD  ((ushort)0x0008)  /* PA 12 */
+#define PA_ENET_TXD	((ushort)0x0008)  /* PA 12 */
-#define PA_ENET_RCLK ((ushort)0x0200)  /* PA  6 */
+#define PA_ENET_RCLK	((ushort)0x0200)  /* PA  6 */
-#define PA_ENET_TCLK ((ushort)0x0800)  /* PA  4 */
+#define PA_ENET_TCLK	((ushort)0x0800)  /* PA  4 */
-#define PB_ENET_TENA ((uint)0x00002000)   /* PB 18 */
+#define PB_ENET_TENA	((uint)0x00002000)   /* PB 18 */
-#define PC_ENET_CLSN ((ushort)0x0040)  /* PC  9 */
+#define PC_ENET_CLSN	((ushort)0x0040)  /* PC  9 */
-#define PC_ENET_RENA ((ushort)0x0080)  /* PC  8 */
+#define PC_ENET_RENA	((ushort)0x0080)  /* PC  8 */
 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
  * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
  */
-#define SICR_ENET_MASK  ((uint)0x0000ff00)
+#define SICR_ENET_MASK	((uint)0x0000ff00)
-#define SICR_ENET_CLKRT ((uint)0x00002f00)
+#define SICR_ENET_CLKRT	((uint)0x00002f00)
 #endif   /* CONFIG_NX823 */
 /***  MBX  ************************************************************/
 #ifdef CONFIG_MBX
 /* Bits in parallel I/O port registers that have to be set/cleared
  * to configure the pins for SCC1 use.  The TCLK and RCLK seem unique
  * to the MBX860 board.  Any two of the four available clocks could be
  * used, and the MPC860 cookbook manual has an example using different
  * clock pins.
  */
 #define	PROFF_ENET	PROFF_SCC1
 #define	CPM_CR_ENET	CPM_CR_CH_SCC1
 #define	SCC_ENET	0
 #define PA_ENET_RXD	((ushort)0x0001)
 #define PA_ENET_TXD	((ushort)0x0002)
 #define PA_ENET_TCLK	((ushort)0x0200)
 #define PA_ENET_RCLK	((ushort)0x0800)
 #define PC_ENET_TENA	((ushort)0x0001)
 #define PC_ENET_CLSN	((ushort)0x0010)
 #define PC_ENET_RENA	((ushort)0x0020)
 /* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
  * SCC1.  Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
  */
 #define SICR_ENET_MASK	((uint)0x000000ff)
 #define SICR_ENET_CLKRT	((uint)0x0000003d)
 #endif	/* CONFIG_MBX */
 /***  MHPC  ********************************************************/
 #if defined(CONFIG_MHPC)
 /* This ENET stuff is for the MHPC with ethernet on SCC2.
  * Note TENA is on Port B.
  */
 #define	PROFF_ENET	PROFF_SCC2
 #define	CPM_CR_ENET	CPM_CR_CH_SCC2
 #define	SCC_ENET	1
 #define PA_ENET_RXD	((ushort)0x0004)	/* PA 13 */
 #define PA_ENET_TXD	((ushort)0x0008)	/* PA 12 */
 #define PA_ENET_RCLK	((ushort)0x0200)	/* PA 6 */
 #define PA_ENET_TCLK	((ushort)0x0400)	/* PA 5 */
 #define PB_ENET_TENA	((uint)0x00002000)	/* PB 18 */
 #define PC_ENET_CLSN	((ushort)0x0040)	/* PC 9 */
 #define PC_ENET_RENA	((ushort)0x0080)	/* PC 8 */
 #define SICR_ENET_MASK	((uint)0x0000ff00)
 #define SICR_ENET_CLKRT	((uint)0x00002e00)	/* RCLK-CLK2, TCLK-CLK3 */
 #endif	/* CONFIG_MHPC */
 /***  RPXCLASSIC  *****************************************************/
 #ifdef CONFIG_RPXCLASSIC
 #ifdef CONFIG_FEC_ENET
 # define FEC_ENET				/* use FEC for EThernet */
 # undef SCC_ENET
 #else	/* ! CONFIG_FEC_ENET */
 /* Bits in parallel I/O port registers that have to be set/cleared
  * to configure the pins for SCC1 use.
  */
 #define	PROFF_ENET	PROFF_SCC1
 #define	CPM_CR_ENET	CPM_CR_CH_SCC1
 #define	SCC_ENET	0
 #define PA_ENET_RXD	((ushort)0x0001)
 #define PA_ENET_TXD	((ushort)0x0002)
 #define PA_ENET_TCLK	((ushort)0x0200)
 #define PA_ENET_RCLK	((ushort)0x0800)
 #define PB_ENET_TENA	((uint)0x00001000)
 #define PC_ENET_CLSN	((ushort)0x0010)
 #define PC_ENET_RENA	((ushort)0x0020)
 /* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
  * SCC1.  Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
  */
 #define SICR_ENET_MASK	((uint)0x000000ff)
 #define SICR_ENET_CLKRT	((uint)0x0000003d)
 #endif	/* CONFIG_FEC_ENET */
 #endif	/* CONFIG_RPXCLASSIC */
 /***  RPXLITE  ********************************************************/
 #ifdef CONFIG_RPXLITE
 /* This ENET stuff is for the MPC850 with ethernet on SCC2.  Some of
  * this may be unique to the RPX-Lite configuration.
  * Note TENA is on Port B.
  */
 #define	PROFF_ENET	PROFF_SCC2
 #define	CPM_CR_ENET	CPM_CR_CH_SCC2
 #define	SCC_ENET	1
 #define PA_ENET_RXD	((ushort)0x0004)
 #define PA_ENET_TXD	((ushort)0x0008)
 #define PA_ENET_TCLK	((ushort)0x0200)
 #define PA_ENET_RCLK	((ushort)0x0800)
 #define PB_ENET_TENA	((uint)0x00002000)
 #define PC_ENET_CLSN	((ushort)0x0040)
 #define PC_ENET_RENA	((ushort)0x0080)
 #define SICR_ENET_MASK	((uint)0x0000ff00)
 #define SICR_ENET_CLKRT	((uint)0x00003d00)
 #endif	/* CONFIG_RPXLITE */
 /***  SM850  *********************************************************/
 /* The SM850 Service Module uses SCC2 for IrDA and SCC3 for Ethernet */
 #ifdef CONFIG_SM850
 #define PROFF_ENET	PROFF_SCC3		/* Ethernet on SCC3 */
 #define CPM_CR_ENET	CPM_CR_CH_SCC3
 #define SCC_ENET	2
 #define PB_ENET_RXD	((uint)0x00000004)	/* PB 29 */
 #define PB_ENET_TXD	((uint)0x00000002)	/* PB 30 */
 #define PA_ENET_RCLK	((ushort)0x0100)	/* PA  7 */
 #define PA_ENET_TCLK	((ushort)0x0400)	/* PA  5 */
 #define PC_ENET_LBK	((ushort)0x0008)	/* PC 12 */
 #define PC_ENET_TENA	((ushort)0x0004)	/* PC 13 */
 #define PC_ENET_RENA	((ushort)0x0800)	/* PC  4 */
 #define PC_ENET_CLSN	((ushort)0x0400)	/* PC  5 */
 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
  * SCC3.  Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero.
  */
 #define SICR_ENET_MASK	((uint)0x00FF0000)
 #define SICR_ENET_CLKRT	((uint)0x00260000)
 #endif	/* CONFIG_SM850 */
 /***  SPD823TS  ******************************************************/
 #ifdef CONFIG_SPD823TS
 /* Bits in parallel I/O port registers that have to be set/cleared
  * to configure the pins for SCC2 use.
  */
 #define	PROFF_ENET	PROFF_SCC2		/* Ethernet on SCC2 */
 #define CPM_CR_ENET     CPM_CR_CH_SCC2
 #define	SCC_ENET	1
 #define PA_ENET_MDC	((ushort)0x0001)	/* PA 15 !!! */
 #define PA_ENET_MDIO	((ushort)0x0002)	/* PA 14 !!! */
 #define PA_ENET_RXD	((ushort)0x0004)	/* PA 13 */
 #define PA_ENET_TXD	((ushort)0x0008)	/* PA 12 */
 #define PA_ENET_RCLK	((ushort)0x0200)	/* PA  6 */
 #define PA_ENET_TCLK	((ushort)0x0400)	/* PA  5 */
 #define PB_ENET_TENA	((uint)0x00002000)	/* PB 18 */
 #define PC_ENET_CLSN	((ushort)0x0040)	/* PC  9 */
 #define PC_ENET_RENA	((ushort)0x0080)	/* PC  8 */
 #define	PC_ENET_RESET	((ushort)0x0100)	/* PC  7 !!! */
 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK2) to
  * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
  */
 #define SICR_ENET_MASK	((uint)0x0000ff00)
 #define SICR_ENET_CLKRT	((uint)0x00002E00)
 #endif	/* CONFIG_SPD823TS */
 /***  SXNI855T  ******************************************************/
 #if defined(CONFIG_SXNI855T)
 #ifdef CONFIG_FEC_ENET
 #define	FEC_ENET	/* use FEC for Ethernet */
 #endif	/* CONFIG_FEC_ETHERNET */
 #endif	/* CONFIG_SXNI855T */
 /***  MVS1, TQM823L, TQM850L, ETX094, R360MPI  ***********************/
 #if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \
     defined(CONFIG_R360MPI) || \
     defined(CONFIG_TQM823L) || \
     defined(CONFIG_TQM850L) || \
     defined(CONFIG_ETX094)  || \
     defined(CONFIG_RRVISION)|| \
    (defined(CONFIG_LANTEC) && CONFIG_LANTEC < 2)
 /* Bits in parallel I/O port registers that have to be set/cleared
  * to configure the pins for SCC2 use.
  */
 #define	PROFF_ENET	PROFF_SCC2
 #define	CPM_CR_ENET	CPM_CR_CH_SCC2
 #define	SCC_ENET	1
 #define PA_ENET_RXD	((ushort)0x0004)	/* PA 13 */
 #define PA_ENET_TXD	((ushort)0x0008)	/* PA 12 */
 #define PA_ENET_RCLK	((ushort)0x0100)	/* PA  7 */
 #define PA_ENET_TCLK	((ushort)0x0400)	/* PA  5 */
 #define PB_ENET_TENA	((uint)0x00002000)	/* PB 18 */
 #define PC_ENET_CLSN	((ushort)0x0040)	/* PC  9 */
 #define PC_ENET_RENA	((ushort)0x0080)	/* PC  8 */
 #if defined(CONFIG_R360MPI)
 #define PC_ENET_LBK	((ushort)0x0008)	/* PC 12 */
 #endif   /* CONFIG_R360MPI */
 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
  * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
  */
 #define SICR_ENET_MASK	((uint)0x0000ff00)
 #define SICR_ENET_CLKRT	((uint)0x00002600)
 #endif	/* CONFIG_MVS v1, CONFIG_TQM823L, CONFIG_TQM850L, etc. */
 /***  TQM860L, TQM855L ************************************************/
 #if (defined(CONFIG_TQM860L) || defined(CONFIG_TQM855L))
 # ifdef CONFIG_SCC1_ENET	/* use SCC for 10Mbps Ethernet	*/
 /* Bits in parallel I/O port registers that have to be set/cleared
  * to configure the pins for SCC1 use.
  */
 #define	PROFF_ENET	PROFF_SCC1
 #define	CPM_CR_ENET	CPM_CR_CH_SCC1
 #define	SCC_ENET	0
 #define PA_ENET_RXD	((ushort)0x0001)	/* PA 15 */
 #define PA_ENET_TXD	((ushort)0x0002)	/* PA 14 */
 #define PA_ENET_RCLK	((ushort)0x0100)	/* PA  7 */
 #define PA_ENET_TCLK	((ushort)0x0400)	/* PA  5 */
 #define PC_ENET_TENA	((ushort)0x0001)	/* PC 15 */
 #define PC_ENET_CLSN	((ushort)0x0010)	/* PC 11 */
 #define PC_ENET_RENA	((ushort)0x0020)	/* PC 10 */
 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
  * SCC1.  Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
  */
 #define SICR_ENET_MASK	((uint)0x000000ff)
 #define SICR_ENET_CLKRT	((uint)0x00000026)
 # endif	/* CONFIG_SCC1_ENET */
 # ifdef CONFIG_FEC_ENET		/* Use FEC for Fast Ethernet */
 #define FEC_ENET
 #define PD_MII_TXD1	((ushort)0x1000)	/* PD  3 */
 #define PD_MII_TXD2	((ushort)0x0800)	/* PD  4 */
 #define PD_MII_TXD3	((ushort)0x0400)	/* PD  5 */
 #define PD_MII_RX_DV	((ushort)0x0200)	/* PD  6 */
 #define PD_MII_RX_ERR	((ushort)0x0100)	/* PD  7 */
 #define PD_MII_RX_CLK	((ushort)0x0080)	/* PD  8 */
 #define PD_MII_TXD0	((ushort)0x0040)	/* PD  9 */
 #define PD_MII_RXD0	((ushort)0x0020)	/* PD 10 */
 #define PD_MII_TX_ERR	((ushort)0x0010)	/* PD 11 */
 #define PD_MII_MDC	((ushort)0x0008)	/* PD 12 */
 #define PD_MII_RXD1	((ushort)0x0004)	/* PD 13 */
 #define PD_MII_RXD2	((ushort)0x0002)	/* PD 14 */
 #define PD_MII_RXD3	((ushort)0x0001)	/* PD 15 */
 #define PD_MII_MASK	((ushort)0x1FFF)	/* PD 3...15 */
 # endif	/* CONFIG_FEC_ENET */
 #endif	/* CONFIG_TQM860L, CONFIG_TQM855L */
 #if defined(CONFIG_NETVIA)
 /* Bits in parallel I/O port registers that have to be set/cleared
  * to configure the pins for SCC2 use.
  */
 #define	PROFF_ENET	PROFF_SCC2
 #define	CPM_CR_ENET	CPM_CR_CH_SCC2
 #define	SCC_ENET	1
 #define PA_ENET_RXD	((ushort)0x0004)	/* PA 13 */
 #define PA_ENET_TXD	((ushort)0x0008)	/* PA 12 */
 #define PA_ENET_RCLK	((ushort)0x0200)	/* PA  6 */
 #define PA_ENET_TCLK	((ushort)0x0800)	/* PA  4 */
 #define PB_ENET_PDN	((ushort)0x4000)	/* PB 17 */
 #define PB_ENET_TENA	((ushort)0x2000)	/* PB 18 */
 #define PC_ENET_CLSN	((ushort)0x0040)	/* PC  9 */
 #define PC_ENET_RENA	((ushort)0x0080)	/* PC  8 */
 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
  * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
  */
 #define SICR_ENET_MASK	((uint)0x0000ff00)
 #define SICR_ENET_CLKRT	((uint)0x00002f00)
 #endif	/* CONFIG_NETVIA */
 /*********************************************************************/
 /* SCC Event register as used by Ethernet.
 */
 #define SCCE_ENET_GRA	((ushort)0x0080)	/* Graceful stop complete */
 #define SCCE_ENET_TXE	((ushort)0x0010)	/* Transmit Error */
 #define SCCE_ENET_RXF	((ushort)0x0008)	/* Full frame received */
 #define SCCE_ENET_BSY	((ushort)0x0004)	/* All incoming buffers full */
 #define SCCE_ENET_TXB	((ushort)0x0002)	/* A buffer was transmitted */
 #define SCCE_ENET_RXB	((ushort)0x0001)	/* A buffer was received */
 /* SCC Mode Register (PSMR) as used by Ethernet.
 */
 #define SCC_PSMR_HBC	((ushort)0x8000)	/* Enable heartbeat */
 #define SCC_PSMR_FC	((ushort)0x4000)	/* Force collision */
 #define SCC_PSMR_RSH	((ushort)0x2000)	/* Receive short frames */
 #define SCC_PSMR_IAM	((ushort)0x1000)	/* Check individual hash */
 #define SCC_PSMR_ENCRC	((ushort)0x0800)	/* Ethernet CRC mode */
 #define SCC_PSMR_PRO	((ushort)0x0200)	/* Promiscuous mode */
 #define SCC_PSMR_BRO	((ushort)0x0100)	/* Catch broadcast pkts */
 #define SCC_PSMR_SBT	((ushort)0x0080)	/* Special backoff timer */
 #define SCC_PSMR_LPB	((ushort)0x0040)	/* Set Loopback mode */
 #define SCC_PSMR_SIP	((ushort)0x0020)	/* Sample Input Pins */
 #define SCC_PSMR_LCW	((ushort)0x0010)	/* Late collision window */
 #define SCC_PSMR_NIB22	((ushort)0x000a)	/* Start frame search */
 #define SCC_PSMR_FDE	((ushort)0x0001)	/* Full duplex enable */
 /* Buffer descriptor control/status used by Ethernet receive.
 */
 #define BD_ENET_RX_EMPTY	((ushort)0x8000)
 #define BD_ENET_RX_WRAP		((ushort)0x2000)
 #define BD_ENET_RX_INTR		((ushort)0x1000)
 #define BD_ENET_RX_LAST		((ushort)0x0800)
 #define BD_ENET_RX_FIRST	((ushort)0x0400)
 #define BD_ENET_RX_MISS		((ushort)0x0100)
 #define BD_ENET_RX_LG		((ushort)0x0020)
 #define BD_ENET_RX_NO		((ushort)0x0010)
 #define BD_ENET_RX_SH		((ushort)0x0008)
 #define BD_ENET_RX_CR		((ushort)0x0004)
 #define BD_ENET_RX_OV		((ushort)0x0002)
 #define BD_ENET_RX_CL		((ushort)0x0001)
 #define BD_ENET_RX_STATS	((ushort)0x013f)	/* All status bits */
 /* Buffer descriptor control/status used by Ethernet transmit.
 */
 #define BD_ENET_TX_READY	((ushort)0x8000)
 #define BD_ENET_TX_PAD		((ushort)0x4000)
 #define BD_ENET_TX_WRAP		((ushort)0x2000)
 #define BD_ENET_TX_INTR		((ushort)0x1000)
 #define BD_ENET_TX_LAST		((ushort)0x0800)
 #define BD_ENET_TX_TC		((ushort)0x0400)
 #define BD_ENET_TX_DEF		((ushort)0x0200)
 #define BD_ENET_TX_HB		((ushort)0x0100)
 #define BD_ENET_TX_LC		((ushort)0x0080)
 #define BD_ENET_TX_RL		((ushort)0x0040)
 #define BD_ENET_TX_RCMASK	((ushort)0x003c)
 #define BD_ENET_TX_UN		((ushort)0x0002)
 #define BD_ENET_TX_CSL		((ushort)0x0001)
 #define BD_ENET_TX_STATS	((ushort)0x03ff)	/* All status bits */
 /* SCC as UART
 */
 typedef struct scc_uart {
 	sccp_t	scc_genscc;
 	uint	scc_res1;	/* Reserved */
 	uint	scc_res2;	/* Reserved */
 	ushort	scc_maxidl;	/* Maximum idle chars */
 	ushort	scc_idlc;	/* temp idle counter */
 	ushort	scc_brkcr;	/* Break count register */
 	ushort	scc_parec;	/* receive parity error counter */
 	ushort	scc_frmec;	/* receive framing error counter */
 	ushort	scc_nosec;	/* receive noise counter */
 	ushort	scc_brkec;	/* receive break condition counter */
 	ushort	scc_brkln;	/* last received break length */
 	ushort	scc_uaddr1;	/* UART address character 1 */
 	ushort	scc_uaddr2;	/* UART address character 2 */
 	ushort	scc_rtemp;	/* Temp storage */
 	ushort	scc_toseq;	/* Transmit out of sequence char */
 	ushort	scc_char1;	/* control character 1 */
 	ushort	scc_char2;	/* control character 2 */
 	ushort	scc_char3;	/* control character 3 */
 	ushort	scc_char4;	/* control character 4 */
 	ushort	scc_char5;	/* control character 5 */
 	ushort	scc_char6;	/* control character 6 */
 	ushort	scc_char7;	/* control character 7 */
 	ushort	scc_char8;	/* control character 8 */
 	ushort	scc_rccm;	/* receive control character mask */
 	ushort	scc_rccr;	/* receive control character register */
 	ushort	scc_rlbc;	/* receive last break character */
 } scc_uart_t;
 /* SCC Event and Mask registers when it is used as a UART.
 */
 #define UART_SCCM_GLR		((ushort)0x1000)
 #define UART_SCCM_GLT		((ushort)0x0800)
 #define UART_SCCM_AB		((ushort)0x0200)
 #define UART_SCCM_IDL		((ushort)0x0100)
 #define UART_SCCM_GRA		((ushort)0x0080)
 #define UART_SCCM_BRKE		((ushort)0x0040)
 #define UART_SCCM_BRKS		((ushort)0x0020)
 #define UART_SCCM_CCR		((ushort)0x0008)
 #define UART_SCCM_BSY		((ushort)0x0004)
 #define UART_SCCM_TX		((ushort)0x0002)
 #define UART_SCCM_RX		((ushort)0x0001)
 /* The SCC PSMR when used as a UART.
 */
 #define SCU_PSMR_FLC		((ushort)0x8000)
 #define SCU_PSMR_SL		((ushort)0x4000)
 #define SCU_PSMR_CL		((ushort)0x3000)
 #define SCU_PSMR_UM		((ushort)0x0c00)
 #define SCU_PSMR_FRZ		((ushort)0x0200)
 #define SCU_PSMR_RZS		((ushort)0x0100)
 #define SCU_PSMR_SYN		((ushort)0x0080)
 #define SCU_PSMR_DRT		((ushort)0x0040)
 #define SCU_PSMR_PEN		((ushort)0x0010)
 #define SCU_PSMR_RPM		((ushort)0x000c)
 #define SCU_PSMR_REVP		((ushort)0x0008)
 #define SCU_PSMR_TPM		((ushort)0x0003)
 #define SCU_PSMR_TEVP		((ushort)0x0003)
 /* CPM Transparent mode SCC.
  */
 typedef struct scc_trans {
 	sccp_t	st_genscc;
 	uint	st_cpres;	/* Preset CRC */
 	uint	st_cmask;	/* Constant mask for CRC */
 } scc_trans_t;
 #define BD_SCC_TX_LAST		((ushort)0x0800)
 /* IIC parameter RAM.
 */
 typedef struct iic {
 	ushort	iic_rbase;	/* Rx Buffer descriptor base address */
 	ushort	iic_tbase;	/* Tx Buffer descriptor base address */
 	u_char	iic_rfcr;	/* Rx function code */
 	u_char	iic_tfcr;	/* Tx function code */
 	ushort	iic_mrblr;	/* Max receive buffer length */
 	uint	iic_rstate;	/* Internal */
 	uint	iic_rdp;	/* Internal */
 	ushort	iic_rbptr;	/* Internal */
 	ushort	iic_rbc;	/* Internal */
 	uint	iic_rxtmp;	/* Internal */
 	uint	iic_tstate;	/* Internal */
 	uint	iic_tdp;	/* Internal */
 	ushort	iic_tbptr;	/* Internal */
 	ushort	iic_tbc;	/* Internal */
 	uint	iic_txtmp;	/* Internal */
 	uint	iic_res;	/* reserved */
 	ushort	iic_rpbase;	/* Relocation pointer */
 	ushort	iic_res2;	/* reserved */
 } iic_t;
 /* SPI parameter RAM.
 */
 typedef struct spi {
 	ushort	spi_rbase;	/* Rx Buffer descriptor base address */
 	ushort	spi_tbase;	/* Tx Buffer descriptor base address */
 	u_char	spi_rfcr;	/* Rx function code */
 	u_char	spi_tfcr;	/* Tx function code */
 	ushort	spi_mrblr;	/* Max receive buffer length */
 	uint	spi_rstate;	/* Internal */
 	uint	spi_rdp;	/* Internal */
 	ushort	spi_rbptr;	/* Internal */
 	ushort	spi_rbc;	/* Internal */
 	uint	spi_rxtmp;	/* Internal */
 	uint	spi_tstate;	/* Internal */
 	uint	spi_tdp;	/* Internal */
 	ushort	spi_tbptr;	/* Internal */
 	ushort	spi_tbc;	/* Internal */
 	uint	spi_txtmp;	/* Internal */
 	uint	spi_res;
 	ushort	spi_rpbase;	/* Relocation pointer */
 	ushort	spi_res2;
 } spi_t;
 /* SPI Mode register.
 */
 #define SPMODE_LOOP	((ushort)0x4000)	/* Loopback */
 #define SPMODE_CI	((ushort)0x2000)	/* Clock Invert */
 #define SPMODE_CP	((ushort)0x1000)	/* Clock Phase */
 #define SPMODE_DIV16	((ushort)0x0800)	/* BRG/16 mode */
 #define SPMODE_REV	((ushort)0x0400)	/* Reversed Data */
 #define SPMODE_MSTR	((ushort)0x0200)	/* SPI Master */
 #define SPMODE_EN	((ushort)0x0100)	/* Enable */
 #define SPMODE_LENMSK	((ushort)0x00f0)	/* character length */
 #define SPMODE_PMMSK	((ushort)0x000f)	/* prescale modulus */
 #define SPMODE_LEN(x)	((((x)-1)&0xF)<<4)
 #define SPMODE_PM(x)	((x) &0xF)
 /* HDLC parameter RAM.
 */
 typedef struct hdlc_pram_s {
 	/*
 	 * SCC parameter RAM
 	 */
 	ushort	rbase;		/* Rx Buffer descriptor base address */
 	ushort	tbase;		/* Tx Buffer descriptor base address */
 	uchar	rfcr;		/* Rx function code */
 	uchar	tfcr;		/* Tx function code */
 	ushort	mrblr;		/* Rx buffer length */
 	ulong	rstate;		/* Rx internal state */
 	ulong	rptr;		/* Rx internal data pointer */
 	ushort	rbptr;		/* rb BD Pointer */
 	ushort	rcount;		/* Rx internal byte count */
 	ulong	rtemp;		/* Rx temp */
 	ulong	tstate;		/* Tx internal state */
 	ulong	tptr;		/* Tx internal data pointer */
 	ushort	tbptr;		/* Tx BD pointer */
 	ushort	tcount;		/* Tx byte count */
 	ulong	ttemp;		/* Tx temp */
 	ulong	rcrc;		/* temp receive CRC */
 	ulong	tcrc;		/* temp transmit CRC */
 	/*
 	 * HDLC specific parameter RAM
 	 */
 	uchar	res[4];		/* reserved */
 	ulong	c_mask;		/* CRC constant */
 	ulong	c_pres;		/* CRC preset */
 	ushort	disfc;		/* discarded frame counter */
 	ushort	crcec;		/* CRC error counter */
 	ushort	abtsc;		/* abort sequence counter */
 	ushort	nmarc;		/* nonmatching address rx cnt */
 	ushort	retrc;		/* frame retransmission cnt */
 	ushort	mflr;		/* maximum frame length reg */
 	ushort	max_cnt;	/* maximum length counter */
 	ushort	rfthr;		/* received frames threshold */
 	ushort	rfcnt;		/* received frames count */
 	ushort	hmask;		/* user defined frm addr mask */
 	ushort	haddr1;		/* user defined frm address 1 */
 	ushort	haddr2;		/* user defined frm address 2 */
 	ushort	haddr3;		/* user defined frm address 3 */
 	ushort	haddr4;		/* user defined frm address 4 */
 	ushort	tmp;		/* temp */
 	ushort	tmp_mb;		/* temp */
 } hdlc_pram_t;
 /* CPM interrupts.  There are nearly 32 interrupts generated by CPM
  * channels or devices.  All of these are presented to the PPC core
  * as a single interrupt.  The CPM interrupt handler dispatches its
  * own handlers, in a similar fashion to the PPC core handler.  We
  * use the table as defined in the manuals (i.e. no special high
  * priority and SCC1 == SCCa, etc...).
  */
 #define CPMVEC_NR		32
-#define	CPMVEC_PIO_PC15		((ushort)0x1f)
+#define CPMVEC_OFFSET           0x00010000
-#define	CPMVEC_SCC1		((ushort)0x1e)
+#define CPMVEC_PIO_PC15		((ushort)0x1f | CPMVEC_OFFSET)
-#define	CPMVEC_SCC2		((ushort)0x1d)
+#define CPMVEC_SCC1		((ushort)0x1e | CPMVEC_OFFSET)
-#define	CPMVEC_SCC3		((ushort)0x1c)
+#define CPMVEC_SCC2		((ushort)0x1d | CPMVEC_OFFSET)
-#define	CPMVEC_SCC4		((ushort)0x1b)
+#define CPMVEC_SCC3		((ushort)0x1c | CPMVEC_OFFSET)
-#define	CPMVEC_PIO_PC14		((ushort)0x1a)
+#define CPMVEC_SCC4		((ushort)0x1b | CPMVEC_OFFSET)
-#define	CPMVEC_TIMER1		((ushort)0x19)
+#define CPMVEC_PIO_PC14		((ushort)0x1a | CPMVEC_OFFSET)
-#define	CPMVEC_PIO_PC13		((ushort)0x18)
+#define CPMVEC_TIMER1		((ushort)0x19 | CPMVEC_OFFSET)
-#define	CPMVEC_PIO_PC12		((ushort)0x17)
+#define CPMVEC_PIO_PC13		((ushort)0x18 | CPMVEC_OFFSET)
-#define	CPMVEC_SDMA_CB_ERR	((ushort)0x16)
+#define CPMVEC_PIO_PC12		((ushort)0x17 | CPMVEC_OFFSET)
-#define CPMVEC_IDMA1		((ushort)0x15)
+#define CPMVEC_SDMA_CB_ERR	((ushort)0x16 | CPMVEC_OFFSET)
-#define CPMVEC_IDMA2		((ushort)0x14)
+#define CPMVEC_IDMA1		((ushort)0x15 | CPMVEC_OFFSET)
-#define CPMVEC_TIMER2		((ushort)0x12)
+#define CPMVEC_IDMA2		((ushort)0x14 | CPMVEC_OFFSET)
-#define CPMVEC_RISCTIMER	((ushort)0x11)
+#define CPMVEC_TIMER2		((ushort)0x12 | CPMVEC_OFFSET)
-#define CPMVEC_I2C		((ushort)0x10)
+#define CPMVEC_RISCTIMER	((ushort)0x11 | CPMVEC_OFFSET)
-#define	CPMVEC_PIO_PC11		((ushort)0x0f)
+#define CPMVEC_I2C		((ushort)0x10 | CPMVEC_OFFSET)
-#define	CPMVEC_PIO_PC10		((ushort)0x0e)
+#define CPMVEC_PIO_PC11		((ushort)0x0f | CPMVEC_OFFSET)
-#define CPMVEC_TIMER3		((ushort)0x0c)
+#define CPMVEC_PIO_PC10		((ushort)0x0e | CPMVEC_OFFSET)
-#define	CPMVEC_PIO_PC9		((ushort)0x0b)
+#define CPMVEC_TIMER3		((ushort)0x0c | CPMVEC_OFFSET)
-#define	CPMVEC_PIO_PC8		((ushort)0x0a)
+#define CPMVEC_PIO_PC9		((ushort)0x0b | CPMVEC_OFFSET)
-#define	CPMVEC_PIO_PC7		((ushort)0x09)
+#define CPMVEC_PIO_PC8		((ushort)0x0a | CPMVEC_OFFSET)
-#define CPMVEC_TIMER4		((ushort)0x07)
+#define CPMVEC_PIO_PC7		((ushort)0x09 | CPMVEC_OFFSET)
-#define	CPMVEC_PIO_PC6		((ushort)0x06)
+#define CPMVEC_TIMER4		((ushort)0x07 | CPMVEC_OFFSET)
-#define	CPMVEC_SPI		((ushort)0x05)
+#define CPMVEC_PIO_PC6		((ushort)0x06 | CPMVEC_OFFSET)
-#define	CPMVEC_SMC1		((ushort)0x04)
+#define CPMVEC_SPI		((ushort)0x05 | CPMVEC_OFFSET)
-#define	CPMVEC_SMC2		((ushort)0x03)
+#define CPMVEC_SMC1		((ushort)0x04 | CPMVEC_OFFSET)
-#define	CPMVEC_PIO_PC5		((ushort)0x02)
+#define CPMVEC_SMC2		((ushort)0x03 | CPMVEC_OFFSET)
-#define	CPMVEC_PIO_PC4		((ushort)0x01)
+#define CPMVEC_PIO_PC5		((ushort)0x02 | CPMVEC_OFFSET)
-#define	CPMVEC_ERROR		((ushort)0x00)
+#define CPMVEC_PIO_PC4		((ushort)0x01 | CPMVEC_OFFSET)
+#define CPMVEC_ERROR		((ushort)0x00 | CPMVEC_OFFSET)
 extern void irq_install_handler(int vec, void (*handler)(void *), void *dev_id);
 /* CPM interrupt configuration vector.
 */
 #define	CICR_SCD_SCC4		((uint)0x00c00000)	/* SCC4 @ SCCd */
 #define	CICR_SCC_SCC3		((uint)0x00200000)	/* SCC3 @ SCCc */
 #define	CICR_SCB_SCC2		((uint)0x00040000)	/* SCC2 @ SCCb */
 #define	CICR_SCA_SCC1		((uint)0x00000000)	/* SCC1 @ SCCa */
 #define CICR_IRL_MASK		((uint)0x0000e000)	/* Core interrrupt */
 #define CICR_HP_MASK		((uint)0x00001f00)	/* Hi-pri int. */
 #define CICR_IEN		((uint)0x00000080)	/* Int. enable */
 #define CICR_SPS		((uint)0x00000001)	/* SCC Spread */
 #endif /* __CPM_8XX__ */

include/configs/AmigaOneG3SE.h

Diff comments View file @ 7c7a23b

 /*
  * (C) Copyright 2002
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 /*
  *
  * Configuration settings for the AmigaOneG3SE board.
  *
  */
 /* ------------------------------------------------------------------------- */
 /*
  * board/config.h - configuration options, board specific
  */
 #ifndef __CONFIG_H
 #define __CONFIG_H
 /*
  * High Level Configuration Options
  * (easy to change)
  */
 #define CONFIG_AMIGAONEG3SE	1
 #define CONFIG_BOARD_PRE_INIT	1
 #define CONFIG_MISC_INIT_R	1
 #define CONFIG_VERY_BIG_RAM	1
 #define CONFIG_CONS_INDEX	1
 #define CONFIG_BAUDRATE		9600
 #define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 #undef CONFIG_CLOCKS_IN_MHZ		/* clocks passed to Linux in Hz */
 #define CONFIG_BOOTARGS		"root=/dev/ram rw ramdisk=4096"
 #define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
 				 CONFIG_BOOTP_BOOTFILESIZE)
 #define CONFIG_MAC_PARTITION
 #define CONFIG_DOS_PARTITION
 #define CONFIG_AMIGA_PARTITION
 #define CONFIG_COMMANDS		(CONFIG_CMD_DFL | \
 				 CFG_CMD_ASKENV | \
 				 CFG_CMD_BSP	| \
 				 CFG_CMD_DATE	| \
 				 CFG_CMD_DHCP	| \
 				 CFG_CMD_ELF	| \
 				 CFG_CMD_NET	| \
 				 CFG_CMD_IDE	| \
 				 CFG_CMD_FDC	| \
 				 CFG_CMD_CACHE	| \
 				 CFG_CMD_CONSOLE| \
 				 CFG_CMD_USB	| \
 				 CFG_CMD_BSP	| \
 				 CFG_CMD_PCI	)
 /*				    CFG_CMD_MII	   | \ */
 #define CONFIG_PCI		1
 /* #define CONFIG_PCI_SCAN_SHOW 1 */
 #define CONFIG_PCI_PNP		1	/* PCI plug-and-play */
 /* This must be included AFTER the definition of CONFIG_COMMANDS (if any)
  */
 #include <cmd_confdefs.h>
 /*
  * Miscellaneous configurable options
  */
 #define CFG_LONGHELP			/* undef to save memory		*/
-#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
+#define CFG_PROMPT	"] "		/* Monitor Command Prompt	*/
 #define CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
 /* #undef CFG_HUSH_PARSER */
 #ifdef	CFG_HUSH_PARSER
 #define CFG_PROMPT_HUSH_PS2	"> "
 #endif
 #define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
 /* Print Buffer Size
  */
 #define CFG_PBSIZE	(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
 #define CFG_MAXARGS	64		/* max number of command args	*/
 #define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
 #define CFG_LOAD_ADDR	0x00500000	/* Default load address		*/
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
  * Please note that CFG_SDRAM_BASE _must_ start at 0
  */
 #define CFG_SDRAM_BASE	    0x00000000
 #define CFG_FLASH_BASE	    0xFFF00000
 #define CFG_FLASH_MAX_SIZE  0x00080000
 /* Maximum amount of RAM.
  */
 #define CFG_MAX_RAM_SIZE    0x80000000	/* 2G			*/
 #define CFG_RESET_ADDRESS   0xFFF00100
 #define CFG_MONITOR_BASE    TEXT_BASE
 #define CFG_MONITOR_LEN	    (768 << 10) /* Reserve 512 kB for Monitor	*/
 #define CFG_MALLOC_LEN	    (2500 << 10) /* Reserve 128 kB for malloc() */
 #if CFG_MONITOR_BASE >= CFG_SDRAM_BASE && \
     CFG_MONITOR_BASE < CFG_SDRAM_BASE + CFG_MAX_RAM_SIZE
 #define CFG_RAMBOOT
 #else
 #undef CFG_RAMBOOT
 #endif
 #define CFG_MEMTEST_START	0x00004000	/* memtest works on	*/
 #define CFG_MEMTEST_END		0x02000000	/* 0 ... 32 MB in DRAM	*/
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area
  */
 /* Size in bytes reserved for initial data
  */
-#define CFG_INIT_RAM_ADDR	0x400000
+/* HJF: used to be 0x400000 */
+#define CFG_INIT_RAM_ADDR	0x40000000
 #define CFG_INIT_RAM_END	0x8000
 #define CFG_GBL_DATA_SIZE	128
 #define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 #define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
 #define CFG_INIT_RAM_LOCK
 /*
  * Temporary buffer for serial data until the real serial driver
  * is initialised (memtest will destroy this buffer)
  */
 #define CFG_SCONSOLE_ADDR     CFG_INIT_RAM_ADDR
 #define CFG_SCONSOLE_SIZE     0x0002000
 /* SDRAM 0 - 256MB
  */
-#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
+/*HJF: #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_4M | BATU_VS | BATU_VP)
 #define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
-#define CFG_DBAT0U CFG_IBAT0U
+#define CFG_DBAT0U CFG_IBAT0U*/
-/* SDRAM 1 - 256MB
+#define CFG_DBAT0L	      (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_DBAT0U	      (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_IBAT0L      (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CFG_IBAT0U      (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
+/* PCI Range
  */
-#define CFG_IBAT1L ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR) | BATL_PP_RW) /* | BATL_CACHEINHIBIT) */
+#define CFG_DBAT1L	 (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
+#define CFG_DBAT1U	 (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CFG_IBAT1L	 (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
+#define CFG_IBAT1U	 (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+/* HJF:
+#define CFG_IBAT1L ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR) | BATL_PP_RW)
 #define CFG_IBAT1U ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR) | BATU_BL_256M | BATU_VS | BATU_VP)
-#define CFG_DBAT1L ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR + 0x20000) | BATL_PP_RW ) /* | BATL_CACHEINHIBIT) */
+#define CFG_DBAT1L ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR + 0x20000) | BATL_PP_RW )
 #define CFG_DBAT1U ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR + 0x20000) | BATU_BL_256M | BATU_VS | BATU_VP)
+*/
 /* Init RAM in the CPU DCache (no backing memory)
  */
 #define CFG_DBAT2L	(CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
 #define CFG_DBAT2U	(CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-#define CFG_IBAT2L	0 /* CFG_DBAT2L */
+/* This used to be commented out */
-#define CFG_IBAT2U	0 /* CFG_DBAT2U */
+#define CFG_IBAT2L	  CFG_DBAT2L
+/* This here too */
+#define CFG_IBAT2U	  CFG_DBAT2U
 /* I/O and PCI memory at 0xf0000000
  */
 #define CFG_DBAT3L	(0xf0000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 #define CFG_DBAT3U	(0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 #define CFG_IBAT3L	(0xf0000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
 #define CFG_IBAT3U	(0xf0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 /*
  * Low Level Configuration Settings
  * (address mappings, register initial values, etc.)
  */
 #define CFG_HZ		1000
 #define CFG_BUS_HZ	133000000 /* bus speed - 100 mhz		*/
 #define CFG_CPU_CLK	133000000
 #define CFG_BUS_CLK	133000000
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
 #define CFG_BOOTMAPSZ	(8 << 20) /* Initial Memory map for Linux */
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
 #define CFG_MAX_FLASH_BANKS	1	/* Max number of flash banks		*/
 #define CFG_MAX_FLASH_SECT	8	/* Max number of sectors in one bank	*/
 #define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
 #define CFG_FLASH_WRITE_TOUT	1000	/* Timeout for Flash Write (in ms)	*/
 /*
  * Environment is stored in NVRAM.
  */
 #define CFG_ENV_IS_IN_NVRAM	1
 #define CFG_ENV_ADDR		0xFD0E0000 /* This should be 0xFD0E0000, but we skip bytes to
 					    * protect softex's settings for now.
 					    * Original 768 bytes where not enough.
 					    */
 #define CFG_ENV_SIZE		0x8000	   /* Size of the Environment. See comment above */
 #define CFG_CONSOLE_IS_IN_ENV	1 /* stdin/stdout/stderr are in environment */
 #define CFG_CONSOLE_OVERWRITE_ROUTINE	1
 #define CONFIG_ENV_OVERWRITE 1
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
 #define CFG_CACHELINE_SIZE	32
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 #  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
 #endif
 /*
  * L2 cache
  */
 #define CFG_L2
 #define L2_INIT	  (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
 		   L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
 #define L2_ENABLE (L2_INIT | L2CR_L2E)
 /*
  * Internal Definitions
  *
  * Boot Flags
  */
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH	*/
 #define BOOTFLAG_WARM		0x02	/* Software reboot			*/
 /*-----------------------------------------------------------------------
  * IDE ATAPI Configuration
  */
 #define CONFIG_ATAPI		1
 #define CFG_IDE_MAXBUS		2
 #define CFG_IDE_MAXDEVICE	4
 #define CONFIG_ISO_PARTITION	1
 #define CFG_ATA_BASE_ADDR	0xFE000000  /* was: via_get_base_addr() */
 #define CFG_ATA_IDE0_OFFSET	0x1F0
 #define CFG_ATA_IDE1_OFFSET	0x170
 #define CFG_ATA_REG_OFFSET	0
 #define CFG_ATA_DATA_OFFSET	0
 #define CFG_ATA_ALT_OFFSET	0x0200
 /*-----------------------------------------------------------------------
  * Disk-On-Chip configuration
  */
 #define CFG_MAX_DOC_DEVICE	1	/* Max number of DOC devices		*/
 #define CFG_DOC_SUPPORT_2000
 #undef CFG_DOC_SUPPORT_MILLENNIUM
 /*-----------------------------------------------------------------------
   RTC
 */
 #define CONFIG_RTC_MC146818
 /*-----------------------------------------------------------------------
  * NS16550 Configuration
  */
 #define CFG_NS16550
 #define CFG_NS16550_COM1 0xFE0003F8
 #define CFG_NS16550_COM2 0xFE0002F8
 #define CFG_NS16550_REG_SIZE 1
 /* base address for ISA I/O
  */
 #define CFG_ISA_IO_BASE_ADDRESS 0xFE000000
 /* ISA Interrupt stuff (taken from JWL) */
 #define ISA_INT1_OCW1		0x21
 #define ISA_INT2_OCW1		0xA1
 #define ISA_INT1_OCW2		0x20
 #define ISA_INT2_OCW2		0xA0
 #define ISA_INT1_OCW3		0x20
 #define ISA_INT2_OCW3		0xA0
 #define ISA_INT1_ICW1		0x20
 #define ISA_INT2_ICW1		0xA0
 #define ISA_INT1_ICW2		0x21
 #define ISA_INT2_ICW2		0xA1
 #define ISA_INT1_ICW3		0x21
 #define ISA_INT2_ICW3		0xA1
 #define ISA_INT1_ICW4		0x21
 #define ISA_INT2_ICW4		0xA1
 /*
  * misc
  */
 #define CONFIG_NET_MULTI
 #define CFG_BOARD_ASM_INIT
 #define CONFIG_LAST_STAGE_INIT
 /* #define CONFIG_ETHADDR	00:09:D2:10:00:76 */
 /* #define CONFIG_IPADDR	192.168.0.2 */
 /* #define CONFIG_NETMASK	255.255.255.240 */
 /* #define CONFIG_GATEWAYIP	192.168.0.3 */
 #define CONFIG_3COM
 /* #define CONFIG_BOOTP_RANDOM_DELAY */
 #define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | \
 				 CONFIG_BOOTP_BOOTFILESIZE)
 /*
  * USB configuration
  */
 #define CONFIG_USB_UHCI		1
 #define CONFIG_USB_STORAGE	1
 #define CONFIG_USB_KEYBOARD	1
 #define CFG_DEVICE_DEREGISTER	1 /* needed by CONFIG_USB_KEYBOARD */
 /*
  * Autoboot stuff
  */
 #define CONFIG_BOOTDELAY	5 /* Boot automatically after five seconds */
 #define CONFIG_PREBOOT		""
 #define CONFIG_BOOTCOMMAND	"fdcboot; diskboot"
 #define CONFIG_MENUPROMPT	"Press any key to interrupt autoboot: %2d "
 #define CONFIG_MENUKEY		' '
 #define CONFIG_MENUCOMMAND	"menu"
 /* #define CONFIG_AUTOBOOT_KEYED */
 /*
  * Extra ENV stuff
  */
 #define CONFIG_EXTRA_ENV_SETTINGS		\
 	"stdout=vga\0"				\
 	"stdin=ps2kbd\0"			\
 	"ide_doreset=on\0"			\
 	"ide_maxbus=2\0"			\
 	"ide_cd_timeout=30\0"			\
 	"menucmd=menu\0"			\
 	"pci_irqa=9\0"				\
 	"pci_irqa_select=edge\0"		\
 	"pci_irqb=10\0"				\
 	"pci_irqb_select=edge\0"		\
 	"pci_irqc=11\0"				\
 	"pci_irqc_select=edge\0"		\
-	"pci_irqd=12\0"				\
+	"pci_irqd=7\0"				\
 	"pci_irqd_select=edge\0"
 /* #define CONFIG_MII		1 */
 /* #define CONFIG_BITBANGMII	1 */
 #endif	/* __CONFIG_H */

lib_ppc/board.c

Diff comments View file @ 7c7a23b

 /*
  * (C) Copyright 2000-2002
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
  * published by the Free Software Foundation; either version 2 of
  * the License, or (at your option) any later version.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
 #include <common.h>
 #include <watchdog.h>
 #include <command.h>
 #include <malloc.h>
 #include <devices.h>
 #include <syscall.h>
 #ifdef CONFIG_8xx
 #include <mpc8xx.h>
 #endif
 #if (CONFIG_COMMANDS & CFG_CMD_IDE)
 #include <ide.h>
 #endif
 #if (CONFIG_COMMANDS & CFG_CMD_SCSI)
 #include <scsi.h>
 #endif
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 #include <kgdb.h>
 #endif
 #ifdef CONFIG_STATUS_LED
 #include <status_led.h>
 #endif
 #include <net.h>
 #if (CONFIG_COMMANDS & CFG_CMD_BEDBUG)
 #include <cmd_bedbug.h>
 #endif
 #ifdef CFG_ALLOC_DPRAM
 #include <commproc.h>
 #endif
 #include <version.h>
 #if defined(CONFIG_BAB7xx)
 #include <w83c553f.h>
 #endif
 #include <dtt.h>
 #if defined(CONFIG_POST)
 #include <post.h>
 #endif
 #if defined(CONFIG_LOGBUFFER)
 #include <logbuff.h>
 #endif
 #if (CONFIG_COMMANDS & CFG_CMD_DOC)
 void doc_init (void);
 #endif
 #if defined(CONFIG_HARD_I2C) || \
     defined(CONFIG_SOFT_I2C)
 #include <i2c.h>
 #endif
 static char *failed = "*** failed ***\n";
 #if defined(CONFIG_PCU_E) || defined(CONFIG_OXC)
 extern flash_info_t flash_info[];
 #endif
 #include <environment.h>
 #if ( ((CFG_ENV_ADDR+CFG_ENV_SIZE) < CFG_MONITOR_BASE) || \
       (CFG_ENV_ADDR >= (CFG_MONITOR_BASE + CFG_MONITOR_LEN)) ) || \
     defined(CFG_ENV_IS_IN_NVRAM)
 #define	TOTAL_MALLOC_LEN	(CFG_MALLOC_LEN + CFG_ENV_SIZE)
 #else
 #define	TOTAL_MALLOC_LEN	CFG_MALLOC_LEN
 #endif
 /*
  * Begin and End of memory area for malloc(), and current "brk"
  */
 static	ulong	mem_malloc_start = 0;
 static	ulong	mem_malloc_end	 = 0;
 static	ulong	mem_malloc_brk	 = 0;
 /************************************************************************
  * Utilities								*
  ************************************************************************
  */
 /*
  * The Malloc area is immediately below the monitor copy in DRAM
  */
 static void mem_malloc_init (void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
 	ulong dest_addr = CFG_MONITOR_BASE + gd->reloc_off;
 	mem_malloc_end = dest_addr;
 	mem_malloc_start = dest_addr - TOTAL_MALLOC_LEN;
 	mem_malloc_brk = mem_malloc_start;
 	memset ((void *) mem_malloc_start,
 		0,
 		mem_malloc_end - mem_malloc_start);
 }
 void *sbrk (ptrdiff_t increment)
 {
 	ulong old = mem_malloc_brk;
 	ulong new = old + increment;
 	if ((new < mem_malloc_start) || (new > mem_malloc_end)) {
 		return (NULL);
 	}
 	mem_malloc_brk = new;
 	return ((void *) old);
 }
 char *strmhz (char *buf, long hz)
 {
 	long l, n;
 	long m;
 	n = hz / 1000000L;
 	l = sprintf (buf, "%ld", n);
 	m = (hz % 1000000L) / 1000L;
 	if (m != 0)
 		sprintf (buf + l, ".%03ld", m);
 	return (buf);
 }
 static void syscalls_init (void)
 {
 	ulong *addr;
 	syscall_tbl[SYSCALL_MALLOC] = (void *) malloc;
 	syscall_tbl[SYSCALL_FREE] = (void *) free;
 	syscall_tbl[SYSCALL_INSTALL_HDLR] = (void *) irq_install_handler;
 	syscall_tbl[SYSCALL_FREE_HDLR] = (void *) irq_free_handler;
 	syscall_tbl[SYSCALL_GET_TIMER] = (void *)get_timer;
 	syscall_tbl[SYSCALL_UDELAY] = (void *)udelay;
 	addr = (ulong *) 0xc00;		/* syscall ISR addr */
 	/* patch ISR code */
 	*addr++ |= (ulong) syscall_tbl >> 16;
 	*addr++ |= (ulong) syscall_tbl & 0xFFFF;
 	*addr++ |= NR_SYSCALLS >> 16;
 	*addr++ |= NR_SYSCALLS & 0xFFFF;
 	flush_cache (0x0C00, 0x10);
+	/* Initialize syscalls stack pointer                                 */
+	addr = (ulong *) 0xCFC;
+	*addr = (ulong)addr;
+	flush_cache ((ulong)addr, 0x10);
 }
 /*
  * All attempts to come up with a "common" initialization sequence
  * that works for all boards and architectures failed: some of the
  * requirements are just _too_ different. To get rid of the resulting
  * mess of board dependend #ifdef'ed code we now make the whole
  * initialization sequence configurable to the user.
  *
  * The requirements for any new initalization function is simple: it
  * receives a pointer to the "global data" structure as it's only
  * argument, and returns an integer return code, where 0 means
  * "continue" and != 0 means "fatal error, hang the system".
  */
 typedef int (init_fnc_t) (void);
 /************************************************************************
  * Init Utilities							*
  ************************************************************************
  * Some of this code should be moved into the core functions,
  * but let's get it working (again) first...
  */
 static int init_baudrate (void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
 	uchar tmp[64];	/* long enough for environment variables */
 	int i = getenv_r ("baudrate", tmp, sizeof (tmp));
 	gd->baudrate = (i > 0)
 			? (int) simple_strtoul (tmp, NULL, 10)
 			: CONFIG_BAUDRATE;
 	return (0);
 }
 /***********************************************************************/
 static int init_func_ram (void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
 #ifdef	CONFIG_BOARD_TYPES
 	int board_type = gd->board_type;
 #else
 	int board_type = 0;	/* use dummy arg */
 #endif
 	puts ("DRAM:  ");
 	if ((gd->ram_size = initdram (board_type)) > 0) {
 		print_size (gd->ram_size, "\n");
 		return (0);
 	}
 	puts (failed);
 	return (1);
 }
 /***********************************************************************/
 #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
 static int init_func_i2c (void)
 {
 	puts ("I2C:   ");
 	i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
 	puts ("ready\n");
 	return (0);
 }
 #endif
 /***********************************************************************/
 #if defined(CONFIG_WATCHDOG)
 static int init_func_watchdog_init (void)
 {
 	puts ("       Watchdog enabled\n");
 	WATCHDOG_RESET ();
 	return (0);
 }
 # define INIT_FUNC_WATCHDOG_INIT	init_func_watchdog_init,
 static int init_func_watchdog_reset (void)
 {
 	WATCHDOG_RESET ();
 	return (0);
 }
 # define INIT_FUNC_WATCHDOG_RESET	init_func_watchdog_reset,
 #else
 # define INIT_FUNC_WATCHDOG_INIT	/* undef */
 # define INIT_FUNC_WATCHDOG_RESET	/* undef */
 #endif /* CONFIG_WATCHDOG */
 /************************************************************************
  * Initialization sequence						*
  ************************************************************************
  */
 init_fnc_t *init_sequence[] = {
 #if defined(CONFIG_BOARD_PRE_INIT)
 	board_pre_init,		/* very early board init code (fpga boot, etc.) */
 #endif
 	get_clocks,		/* get CPU and bus clocks (etc.) */
 	init_timebase,
 #ifdef CFG_ALLOC_DPRAM
 	dpram_init,
 #endif
 #if defined(CONFIG_BOARD_POSTCLK_INIT)
 	board_postclk_init,
 #endif
 	env_init,
 	init_baudrate,
 	serial_init,
 	console_init_f,
 	display_options,
 #if defined(CONFIG_8260)
 	prt_8260_rsr,
 	prt_8260_clks,
 #endif /* CONFIG_8260 */
 	checkcpu,
 	checkboard,
 	INIT_FUNC_WATCHDOG_INIT
 #if defined(CONFIG_BMW)		|| \
     defined(CONFIG_COGENT)	|| \
     defined(CONFIG_HYMOD)	|| \
     defined(CONFIG_RSD_PROTO)	|| \
     defined(CONFIG_W7O)
 	misc_init_f,
 #endif
 	INIT_FUNC_WATCHDOG_RESET
 #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
 	init_func_i2c,
 #endif
 #if defined(CONFIG_DTT)		/* Digital Thermometers and Thermostats */
 	dtt_init,
 #endif
 	INIT_FUNC_WATCHDOG_RESET
 	init_func_ram,
 #if defined(CFG_DRAM_TEST)
 	testdram,
 #endif /* CFG_DRAM_TEST */
 	INIT_FUNC_WATCHDOG_RESET
 	NULL,			/* Terminate this list */
 };
 /************************************************************************
  *
  * This is the first part of the initialization sequence that is
  * implemented in C, but still running from ROM.
  *
  * The main purpose is to provide a (serial) console interface as
  * soon as possible (so we can see any error messages), and to
  * initialize the RAM so that we can relocate the monitor code to
  * RAM.
  *
  * Be aware of the restrictions: global data is read-only, BSS is not
  * initialized, and stack space is limited to a few kB.
  *
  ************************************************************************
  */
 void board_init_f (ulong bootflag)
 {
 	DECLARE_GLOBAL_DATA_PTR;
 	bd_t *bd;
 	ulong len, addr, addr_sp;
 	gd_t *id;
 	init_fnc_t **init_fnc_ptr;
 #ifdef CONFIG_PRAM
 	int i;
 	ulong reg;
 	uchar tmp[64];		/* long enough for environment variables */
 #endif
 	/* Pointer is writable since we allocated a register for it */
 	gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
 #ifndef CONFIG_8260
 	/* Clear initial global data */
 	memset ((void *) gd, 0, sizeof (gd_t));
 #endif
 	for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
 		if ((*init_fnc_ptr) () != 0) {
 			hang ();
 		}
 	}
 	/*
 	 * Now that we have DRAM mapped and working, we can
 	 * relocate the code and continue running from DRAM.
 	 *
 	 * Reserve memory at end of RAM for (top down in that order):
 	 *  - protected RAM
 	 *  - LCD framebuffer
 	 *  - monitor code
 	 *  - board info struct
 	 */
 	len = get_endaddr () - CFG_MONITOR_BASE;
 	if (len > CFG_MONITOR_LEN) {
 		printf ("*** U-Boot size %ld > reserved memory (%d)\n",
 				len, CFG_MONITOR_LEN);
 		hang ();
 	}
 	if (CFG_MONITOR_LEN > len)
 		len = CFG_MONITOR_LEN;
 #ifndef	CONFIG_VERY_BIG_RAM
 	addr = CFG_SDRAM_BASE + gd->ram_size;
 #else
 	/* only allow stack below 256M */
 	addr = CFG_SDRAM_BASE +
 	       (gd->ram_size > 256 << 20) ? 256 << 20 : gd->ram_size;
 #endif
 #ifdef CONFIG_PRAM
 	/*
 	 * reserve protected RAM
 	 */
 	i = getenv_r ("pram", tmp, sizeof (tmp));
 	reg = (i > 0) ? simple_strtoul (tmp, NULL, 10) : CONFIG_PRAM;
 	addr -= (reg << 10);		/* size is in kB */
 # ifdef DEBUG
 	printf ("Reserving %ldk for protected RAM at %08lx\n", reg, addr);
 # endif
 #endif /* CONFIG_PRAM */
 	/* round down to next 4 kB limit */
 	addr &= ~(4096 - 1);
 #ifdef DEBUG
 	printf ("Top of RAM usable for U-Boot at: %08lx\n", addr);
 #endif
 #ifdef CONFIG_LCD
 	/* reserve memory for LCD display (always full pages) */
 	addr = lcd_setmem (addr);
 	gd->fb_base = addr;
 #endif /* CONFIG_LCD */
 #if defined(CONFIG_VIDEO) && defined(CONFIG_8xx)
 	/* reserve memory for video display (always full pages) */
 	addr = video_setmem (addr);
 	gd->fb_base = addr;
 #endif /* CONFIG_VIDEO  */
 	/*
 	 * reserve memory for U-Boot code, data & bss
 	 * round down to next 4 kB limit
 	 */
 	addr -= len;
 	addr &= ~(4096 - 1);
 #ifdef DEBUG
 	printf ("Reserving %ldk for U-Boot at: %08lx\n", len >> 10, addr);
 #endif
 #ifdef CONFIG_AMIGAONEG3SE
 	gd->relocaddr = addr;
 #endif
 	/*
 	 * reserve memory for malloc() arena
 	 */
 	addr_sp = addr - TOTAL_MALLOC_LEN;
 #ifdef DEBUG
 	printf ("Reserving %dk for malloc() at: %08lx\n",
 			TOTAL_MALLOC_LEN >> 10, addr_sp);
 #endif
 	/*
 	 * (permanently) allocate a Board Info struct
 	 * and a permanent copy of the "global" data
 	 */
 	addr_sp -= sizeof (bd_t);
 	bd = (bd_t *) addr_sp;
 	gd->bd = bd;
 #ifdef DEBUG
 	printf ("Reserving %d Bytes for Board Info at: %08lx\n",
 			sizeof (bd_t), addr_sp);
 #endif
 	addr_sp -= sizeof (gd_t);
 	id = (gd_t *) addr_sp;
 #ifdef DEBUG
 	printf ("Reserving %d Bytes for Global Data at: %08lx\n",
 			sizeof (gd_t), addr_sp);
 #endif
 	/*
 	 * Finally, we set up a new (bigger) stack.
 	 *
 	 * Leave some safety gap for SP, force alignment on 16 byte boundary
 	 * Clear initial stack frame
 	 */
 	addr_sp -= 16;
 	addr_sp &= ~0xF;
 	*((ulong *) addr_sp)-- = 0;
 	*((ulong *) addr_sp)-- = 0;
 #ifdef DEBUG
 	printf ("Stack Pointer at: %08lx\n", addr_sp);
 #endif
 	/*
 	 * Save local variables to board info struct
 	 */
 	bd->bi_memstart  = CFG_SDRAM_BASE;	/* start of  DRAM memory      */
 	bd->bi_memsize   = gd->ram_size;	/* size  of  DRAM memory in bytes */
 #ifdef CONFIG_IP860
 	bd->bi_sramstart = SRAM_BASE;	/* start of  SRAM memory      */
 	bd->bi_sramsize  = SRAM_SIZE;	/* size  of  SRAM memory      */
 #else
 	bd->bi_sramstart = 0;		/* FIXME */ /* start of  SRAM memory      */
 	bd->bi_sramsize  = 0;		/* FIXME */ /* size  of  SRAM memory      */
 #endif
 #if defined(CONFIG_8xx) || defined(CONFIG_8260)
 	bd->bi_immr_base = CFG_IMMR;	/* base  of IMMR register     */
 #endif
 	bd->bi_bootflags = bootflag;	/* boot / reboot flag (for LynxOS)    */
 	WATCHDOG_RESET ();
 	bd->bi_intfreq = gd->cpu_clk;	/* Internal Freq, in Hz */
 	bd->bi_busfreq = gd->bus_clk;	/* Bus Freq,      in Hz */
 #if defined(CONFIG_8260)
 	bd->bi_cpmfreq = gd->cpm_clk;
 	bd->bi_brgfreq = gd->brg_clk;
 	bd->bi_sccfreq = gd->scc_clk;
 	bd->bi_vco     = gd->vco_out;
 #endif /* CONFIG_8260 */
 	bd->bi_baudrate = gd->baudrate;	/* Console Baudrate     */
 #ifdef CFG_EXTBDINFO
 	strncpy (bd->bi_s_version, "1.2", sizeof (bd->bi_s_version));
 	strncpy (bd->bi_r_version, U_BOOT_VERSION, sizeof (bd->bi_r_version));
 	bd->bi_procfreq = gd->cpu_clk;	/* Processor Speed, In Hz */
 	bd->bi_plb_busfreq = gd->bus_clk;
 #ifdef CONFIG_405GP
 	bd->bi_pci_busfreq = get_PCI_freq ();
 #endif
 #endif
 #ifdef DEBUG
 	printf ("New Stack Pointer is: %08lx\n", addr_sp);
 #endif
 	WATCHDOG_RESET ();
 #ifdef CONFIG_POST
 	post_bootmode_init();
 	post_run (NULL, POST_ROM | post_bootmode_get(0));
 #endif
 	WATCHDOG_RESET();
 	memcpy (id, gd, sizeof (gd_t));
 	relocate_code (addr_sp, id, addr);
 	/* NOTREACHED - relocate_code() does not return */
 }
 /************************************************************************
  *
  * This is the next part if the initialization sequence: we are now
  * running from RAM and have a "normal" C environment, i. e. global
  * data can be written, BSS has been cleared, the stack size in not
  * that critical any more, etc.
  *
  ************************************************************************
  */
 void board_init_r (gd_t *id, ulong dest_addr)
 {
 	DECLARE_GLOBAL_DATA_PTR;
 	cmd_tbl_t *cmdtp;
 	char *s, *e;
 	bd_t *bd;
 	int i;
 	extern void malloc_bin_reloc (void);
 #ifndef CFG_ENV_IS_NOWHERE
 	extern char * env_name_spec;
 #endif
 #ifndef CFG_NO_FLASH
 	ulong flash_size;
 #endif
 	gd = id;		/* initialize RAM version of global data */
 	bd = gd->bd;
 	gd->flags |= GD_FLG_RELOC;	/* tell others: relocation done */
 #ifdef DEBUG
 	printf ("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
 #endif
 	WATCHDOG_RESET ();
 	gd->reloc_off = dest_addr - CFG_MONITOR_BASE;
 	/*
 	 * We have to relocate the command table manually
 	 */
 	for (cmdtp = &cmd_tbl[0]; cmdtp->name; cmdtp++) {
 		ulong addr;
 		addr = (ulong) (cmdtp->cmd) + gd->reloc_off;
 #if 0
 		printf ("Command \"%s\": 0x%08lx => 0x%08lx\n",
 				cmdtp->name, (ulong) (cmdtp->cmd), addr);
 #endif
 		cmdtp->cmd =
 			(int (*)(struct cmd_tbl_s *, int, int, char *[]))addr;
 		addr = (ulong)(cmdtp->name) + gd->reloc_off;
 		cmdtp->name = (char *)addr;
 		if (cmdtp->usage) {
 			addr = (ulong)(cmdtp->usage) + gd->reloc_off;
 			cmdtp->usage = (char *)addr;
 		}
 #ifdef	CFG_LONGHELP
 		if (cmdtp->help) {
 			addr = (ulong)(cmdtp->help) + gd->reloc_off;
 			cmdtp->help = (char *)addr;
 		}
 #endif
 	}
 	/* there are some other pointer constants we must deal with */
 #ifndef CFG_ENV_IS_NOWHERE
 	env_name_spec += gd->reloc_off;
 #endif
 	WATCHDOG_RESET ();
 #ifdef CONFIG_LOGBUFFER
 	logbuff_reset ();
 #endif
 #ifdef CONFIG_POST
 	post_reloc ();
 #endif
 	WATCHDOG_RESET();
 #if defined(CONFIG_IP860) || defined(CONFIG_PCU_E) || defined (CONFIG_FLAGADM)
 	icache_enable ();	/* it's time to enable the instruction cache */
 #endif
 #if defined(CONFIG_BAB7xx)
 	/*
 	 * Do pci configuration on BAB 7xx _before_ the flash
 	 * is initialised, because we need the ISA bridge there.
 	 */
 	pci_init ();
 	/*
 	 * Initialise the ISA bridge
 	 */
 	initialise_w83c553f ();
 #endif
 	asm ("sync ; isync");
 	/*
 	 * Setup trap handlers
 	 */
 	trap_init (dest_addr);
 #if !defined(CFG_NO_FLASH)
 	puts ("FLASH: ");
 	if ((flash_size = flash_init ()) > 0) {
 #ifdef CFG_FLASH_CHECKSUM
 		print_size (flash_size, "");
 		/*
 		 * Compute and print flash CRC if flashchecksum is set to 'y'
 		 *
 		 * NOTE: Maybe we should add some WATCHDOG_RESET()? XXX
 		 */
 		s = getenv ("flashchecksum");
 		if (s && (*s == 'y')) {
 			printf ("  CRC: %08lX",
 					crc32 (0,
 						   (const unsigned char *) CFG_FLASH_BASE,
 						   flash_size)
 					);
 		}
 		putc ('\n');
 #else
 		print_size (flash_size, "\n");
 #endif /* CFG_FLASH_CHECKSUM */
 	} else {
 		puts (failed);
 		hang ();
 	}
 	bd->bi_flashstart = CFG_FLASH_BASE;	/* update start of FLASH memory    */
 	bd->bi_flashsize = flash_size;	/* size of FLASH memory (final value) */
 #if defined(CONFIG_PCU_E) || defined(CONFIG_OXC)
 	bd->bi_flashoffset = 0;
 #elif CFG_MONITOR_BASE == CFG_FLASH_BASE
 	bd->bi_flashoffset = CFG_MONITOR_LEN;	/* reserved area for startup monitor  */
 #else
 	bd->bi_flashoffset = 0;
 #endif
 #else
 	bd->bi_flashsize = 0;
 	bd->bi_flashstart = 0;
 	bd->bi_flashoffset = 0;
 #endif /* !CFG_NO_FLASH */
 	WATCHDOG_RESET ();
 	/* initialize higher level parts of CPU like time base and timers */
 	cpu_init_r ();
 	WATCHDOG_RESET ();
 	/* initialize malloc() area */
 	mem_malloc_init ();
 	malloc_bin_reloc ();
 #ifdef CONFIG_SPI
 # if !defined(CFG_ENV_IS_IN_EEPROM)
 	spi_init_f ();
 # endif
 	spi_init_r ();
 #endif
 	/* relocate environment function pointers etc. */
 	env_relocate ();
 	/*
 	 * Fill in missing fields of bd_info.
          * We do this here, where we have "normal" access to the
          * environment; we used to do this still running from ROM,
          * where had to use getenv_r(), which can be pretty slow when
          * the environment is in EEPROM.
 	 */
 	s = getenv ("ethaddr");
 #if defined (CONFIG_MBX) || defined (CONFIG_RPXCLASSIC) || defined(CONFIG_IAD210)
 	if (s == NULL)
 		board_get_enetaddr (bd->bi_enetaddr);
 	else
 #endif
 		for (i = 0; i < 6; ++i) {
 			bd->bi_enetaddr[i] = s ? simple_strtoul (s, &e, 16) : 0;
 			if (s)
 				s = (*e) ? e + 1 : e;
 		}
 #ifdef	CONFIG_HERMES
 	if ((gd->board_type >> 16) == 2)
 		bd->bi_ethspeed = gd->board_type & 0xFFFF;
 	else
 		bd->bi_ethspeed = 0xFFFF;
 #endif
 #ifdef CONFIG_NX823
 	load_sernum_ethaddr ();
 #endif
 #if defined(CFG_GT_6426x) || defined(CONFIG_PN62)
 	/* handle the 2nd ethernet address */
 	s = getenv ("eth1addr");
 	for (i = 0; i < 6; ++i) {
 		bd->bi_enet1addr[i] = s ? simple_strtoul (s, &e, 16) : 0;
 		if (s)
 			s = (*e) ? e + 1 : e;
 	}
 #endif
 #if defined(CFG_GT_6426x)
 	/* handle the 3rd ethernet address */
 	s = getenv ("eth2addr");
 	for (i = 0; i < 6; ++i) {
 		bd->bi_enet2addr[i] = s ? simple_strtoul (s, &e, 16) : 0;
 		if (s)
 			s = (*e) ? e + 1 : e;
 	}
 #endif
 #if defined(CONFIG_TQM8xxL) || defined(CONFIG_TQM8260) || \
     defined(CONFIG_CCM)
 	load_sernum_ethaddr ();
 #endif
 	/* IP Address */
 	bd->bi_ip_addr = getenv_IPaddr ("ipaddr");
 	WATCHDOG_RESET ();
 #if defined(CONFIG_PCI) && !defined(CONFIG_BAB7xx)
 	/*
 	 * Do pci configuration
 	 */
 	pci_init ();
 #endif
 /** leave this here (after malloc(), environment and PCI are working) **/
 	/* Initialize devices */
 	devices_init ();
 	/* allocate syscalls table (console_init_r will fill it in */
 	syscall_tbl = (void **) malloc (NR_SYSCALLS * sizeof (void *));
 	/* Initialize the console (after the relocation and devices init) */
 	console_init_r ();
 /** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** ** **/
 	syscalls_init ();
 #if defined(CONFIG_CCM)		|| \
     defined(CONFIG_COGENT)	|| \
     defined(CONFIG_CPCI405)	|| \
     defined(CONFIG_EVB64260)	|| \
     defined(CONFIG_HYMOD)	|| \
     defined(CONFIG_KUP4K)	|| \
     defined(CONFIG_LWMON)	|| \
     defined(CONFIG_PCU_E)	|| \
     defined(CONFIG_W7O)		|| \
     defined(CONFIG_MISC_INIT_R)
 	/* miscellaneous platform dependent initialisations */
 	misc_init_r ();
 #endif
 #ifdef	CONFIG_HERMES
 	if (bd->bi_ethspeed != 0xFFFF)
 		hermes_start_lxt980 ((int) bd->bi_ethspeed);
 #endif
 #if (CONFIG_COMMANDS & CFG_CMD_NET) && ( \
     defined(CONFIG_CCM)		|| \
     defined(CONFIG_EP8260)	|| \
     defined(CONFIG_IP860)	|| \
     defined(CONFIG_IVML24)	|| \
     defined(CONFIG_IVMS8)	|| \
     defined(CONFIG_LWMON)	|| \
     defined(CONFIG_MPC8260ADS)	|| \
     defined(CONFIG_PCU_E)	|| \
     defined(CONFIG_RPXSUPER)	|| \
     defined(CONFIG_SPD823TS)	)
 	WATCHDOG_RESET ();
 # ifdef DEBUG
 	puts ("Reset Ethernet PHY\n");
 # endif
 	reset_phy ();
 #endif
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 	WATCHDOG_RESET ();
 	puts ("KGDB:  ");
 	kgdb_init ();
 #endif
 #ifdef DEBUG
 	printf ("U-Boot relocated to %08lx\n", dest_addr);
 #endif
 	/*
 	 * Enable Interrupts
 	 */
 	interrupt_init ();
 	/* Must happen after interrupts are initialized since
 	 * an irq handler gets installed
 	 */
 #ifdef CONFIG_SERIAL_SOFTWARE_FIFO
 	serial_buffered_init();
 #endif
 #ifdef CONFIG_STATUS_LED
 	status_led_set (STATUS_LED_BOOT, STATUS_LED_BLINKING);
 #endif
 	udelay (20);
 	set_timer (0);
 	/* Insert function pointers now that we have relocated the code */
 	/* Initialize from environment */
 	if ((s = getenv ("loadaddr")) != NULL) {
 		load_addr = simple_strtoul (s, NULL, 16);
 	}
 #if (CONFIG_COMMANDS & CFG_CMD_NET)
 	if ((s = getenv ("bootfile")) != NULL) {
 		copy_filename (BootFile, s, sizeof (BootFile));
 	}
 #endif /* CFG_CMD_NET */
 	WATCHDOG_RESET ();
 #if (CONFIG_COMMANDS & CFG_CMD_SCSI)
 	WATCHDOG_RESET ();
 	puts ("SCSI:  ");
 	scsi_init ();
 #endif
 #if (CONFIG_COMMANDS & CFG_CMD_DOC)
 	WATCHDOG_RESET ();
 	puts ("DOC:   ");
 	doc_init ();
 #endif
 #if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI)
 	WATCHDOG_RESET ();
 	puts ("Net:   ");
 	eth_initialize (bd);
 #endif
 #ifdef CONFIG_POST
 	post_run (NULL, POST_RAM | post_bootmode_get(0));
 	if (post_bootmode_get(0) & POST_POWERFAIL) {
 		post_bootmode_clear();
 		board_poweroff();
 	}
 #endif
 #if (CONFIG_COMMANDS & CFG_CMD_PCMCIA) && !(CONFIG_COMMANDS & CFG_CMD_IDE)
 	WATCHDOG_RESET ();
 	puts ("PCMCIA:");
 	pcmcia_init ();
 #endif
 #if (CONFIG_COMMANDS & CFG_CMD_IDE)
 	WATCHDOG_RESET ();
 # ifdef	CONFIG_IDE_8xx_PCCARD
 	puts ("PCMCIA:");
 # else
 	puts ("IDE:   ");
 #endif
 	ide_init ();
 #endif /* CFG_CMD_IDE */
 #ifdef CONFIG_LAST_STAGE_INIT
 	WATCHDOG_RESET ();
 	/*
 	 * Some parts can be only initialized if all others (like
 	 * Interrupts) are up and running (i.e. the PC-style ISA
 	 * keyboard).
 	 */
 	last_stage_init ();
 #endif
 #if (CONFIG_COMMANDS & CFG_CMD_BEDBUG)
 	WATCHDOG_RESET ();
 	bedbug_init ();
 #endif
 #ifdef CONFIG_PRAM
 	/*
 	 * Export available size of memory for Linux,
 	 * taking into account the protected RAM at top of memory
 	 */
 	{
 		ulong pram;
 		char *s;
 		uchar memsz[32];
 		if ((s = getenv ("pram")) != NULL) {
 			pram = simple_strtoul (s, NULL, 10);
 		} else {
 			pram = CONFIG_PRAM;
 		}
 		sprintf (memsz, "%ldk", (bd->bi_memsize / 1024) - pram);
 		setenv ("mem", memsz);
 	}
 #endif
 	/* Initialization complete - start the monitor */
 	/* main_loop() can return to retry autoboot, if so just run it again. */
 	for (;;) {
 		WATCHDOG_RESET ();
 		main_loop ();
 	}
 	/* NOTREACHED - no way out of command loop except booting */
 }
 void hang (void)
 {
 	puts ("### ERROR ### Please RESET the board ###\n");
 	for (;;);
 }
 #if 0 /* We could use plain global data, but the resulting code is bigger */
 /*
  * Pointer to initial global data area
  *
  * Here we initialize it.
  */
 #undef	XTRN_DECLARE_GLOBAL_DATA_PTR
 #define XTRN_DECLARE_GLOBAL_DATA_PTR	/* empty = allocate here */
 DECLARE_GLOBAL_DATA_PTR = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET);
 #endif  /* 0 */
 /************************************************************************/

1	#	1	#
2	# (C) Copyright 2002	2	# (C) Copyright 2002
3	# Wolfgang Denk, DENX Software Engineering, wd@denx.de.	3	# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4	#	4	#
5	# See file CREDITS for list of people who contributed to this	5	# See file CREDITS for list of people who contributed to this
6	# project.	6	# project.
7	#	7	#
8	# This program is free software; you can redistribute it and/or	8	# This program is free software; you can redistribute it and/or
9	# modify it under the terms of the GNU General Public License as	9	# modify it under the terms of the GNU General Public License as
10	# published by the Free Software Foundation; either version 2 of	10	# published by the Free Software Foundation; either version 2 of
11	# the License, or (at your option) any later version.	11	# the License, or (at your option) any later version.
12	#	12	#
13	# This program is distributed in the hope that it will be useful,	13	# This program is distributed in the hope that it will be useful,
14	# but WITHOUT ANY WARRANTY; without even the implied warranty of	14	# but WITHOUT ANY WARRANTY; without even the implied warranty of
15	# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the	15	# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16	# GNU General Public License for more details.	16	# GNU General Public License for more details.
17	#	17	#
18	# You should have received a copy of the GNU General Public License	18	# You should have received a copy of the GNU General Public License
19	# along with this program; if not, write to the Free Software	19	# along with this program; if not, write to the Free Software
20	# Foundation, Inc., 59 Temple Place, Suite 330, Boston,	20	# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21	# MA 02111-1307 USA	21	# MA 02111-1307 USA
22	#	22	#
23		23
24	include $(TOPDIR)/config.mk	24	include $(TOPDIR)/config.mk
25		25
26	LIB = lib$(BOARD).a	26	LIB = lib$(BOARD).a
27		27
28	COBJS = $(BOARD).o articiaS.o flash.o serial.o smbus.o articiaS_pci.o \	28	COBJS = $(BOARD).o articiaS.o flash.o serial.o smbus.o articiaS_pci.o \
29	via686.o i8259.o ../bios_emulator/x86interface.o \	29	via686.o i8259.o ../bios_emulator/x86interface.o \
30	../bios_emulator/bios.o ../bios_emulator/glue.o \	30	../bios_emulator/bios.o ../bios_emulator/glue.o \
31	interrupts.o ps2kbd.o video.o usb_uhci.o enet.o \	31	interrupts.o ps2kbd.o video.o usb_uhci.o enet.o \
32	../menu/cmd_menu.o cmd_boota.o nvram.o	32	../menu/cmd_menu.o cmd_boota.o nvram.o
33		33
34	AOBJS = board_asm_init.o memio.o	34	AOBJS = board_asm_init.o memio.o
35		35
36	OBJS = $(COBJS) $(AOBJS)	36	OBJS = $(COBJS) $(AOBJS)
37		37
38	## FIXME !!!	38	EMUDIR = ../bios_emulator/scitech/src/x86emu/
39	# EMUOBJS = ../bios_emulator/scitech/src/x86emu/*.o	39	EMUOBJ = $(EMUDIR)decode.o $(EMUDIR)ops2.o $(EMUDIR)fpu.o $(EMUDIR)prim_ops.o \
		40	$(EMUDIR)ops.o $(EMUDIR)sys.o
		41	EMUSRC = $(EMUOBJ:.o=.c)
40		42
41		43	$(LIB): .depend $(OBJS) $(EMUSRC)
42	$(LIB): .depend $(OBJS) $(EMUOBJS)	44	make libx86emu.a -C ../bios_emulator/scitech/src/x86emu -f makefile.uboot CROSS_COMPILE=$(CROSS_COMPILE)
43	-rm $(LIB)	45	-rm $(LIB)
44	$(AR) crv $@ $(OBJS) $(EMUOBJS)	46	$(AR) crv $@ $(OBJS) $(EMUOBJ)
		47
45		48
46	#########################################################################	49	#########################################################################
47		50
48	.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c)	51	.depend: Makefile $(AOBJS:.o=.S) $(COBJS:.o=.c)
49	$(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@	52	$(CC) -M $(CFLAGS) $(AOBJS:.o=.S) $(COBJS:.o=.c) > $@
50		53
51	sinclude .depend	54	sinclude .depend
52		55
53	#########################################################################	56	#########################################################################
54		57