Eric Lee / smarc-uboot

Download as
Browse Code »

Commit 7c7a23bd5a0bc149d2edd665ec46381726b24e0c

Authored by wdenk
1 parent 1f53a41603
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

* Patch by Hans-Joerg Frieden, 06 Dec 2002 

Fix misc problems with AmigaOne support

* Patch by Chris Hallinan, 3 Dec 2002:
  minor cleanup to the MPC8245 EPIC driver

* Patch by Pierre Aubert , 28 Nov 2002
  Add support for external (SIU) interrupts on MPC8xx

* Patch by Pierre Aubert , 28 Nov 2002
  Fix nested syscalls bug in standalone applications

* Patch by David Müller, 27 Nov 2002:
  fix output of "pciinfo" command for CardBus bridge devices.

* Fix bug in TQM8260 board detection - boards got stuck when board ID
  was not readable

Showing 30 changed files with 589 additions and 262 deletions Side-by-side Diff

... ... @@ -2,6 +2,24 @@
2 2 Changes since for U-Boot 0.1.0:
3 3 ======================================================================
4 4  
  5 +* Patch by Hans-Joerg Frieden, 06 Dec 2002
  6 + Fix misc problems with AmigaOne support
  7 +
  8 +* Patch by Chris Hallinan, 3 Dec 2002:
  9 + minor cleanup to the MPC8245 EPIC driver
  10 +
  11 +* Patch by Pierre Aubert , 28 Nov 2002
  12 + Add support for external (SIU) interrupts on MPC8xx
  13 +
  14 +* Patch by Pierre Aubert , 28 Nov 2002
  15 + Fix nested syscalls bug in standalone applications
  16 +
  17 +* Patch by David Müller, 27 Nov 2002:
  18 + fix output of "pciinfo" command for CardBus bridge devices.
  19 +
  20 +* Fix bug in TQM8260 board detection - boards got stuck when board ID
  21 + was not readable
  22 +
5 23 * Add LED indication for IDE activity on KUP4K board
6 24  
7 25 * Fix startup problems with VFD display on TRAB
board/MAI/AmigaOneG3SE/AmigaOneG3SE.c
Diff comments   View file @ 7c7a23b
... ... @@ -76,9 +76,8 @@
76 76  
77 77 int checkboard (void)
78 78 {
79   - printf ("AmigaOneG3SE\n");
80   -
81   - return 1;
  79 + printf ("Board: AmigaOneG3SE\n");
  80 + return 0;
82 81 }
83 82  
84 83 long initdram (int board_type)
85 84  
... ... @@ -88,9 +87,9 @@
88 87  
89 88  
90 89  
91   -void after_reloc (ulong dest_addr)
  90 +void after_reloc (ulong dest_addr, gd_t *gd)
92 91 {
93   - DECLARE_GLOBAL_DATA_PTR;
  92 +/* HJF: DECLARE_GLOBAL_DATA_PTR; */
94 93  
95 94 board_init_r (gd, dest_addr);
96 95 }
board/MAI/AmigaOneG3SE/Makefile
Diff comments   View file @ 7c7a23b
... ... @@ -35,13 +35,16 @@
35 35  
36 36 OBJS = $(COBJS) $(AOBJS)
37 37  
38   -## FIXME !!!
39   -# EMUOBJS = ../bios_emulator/scitech/src/x86emu/*.o
  38 +EMUDIR = ../bios_emulator/scitech/src/x86emu/
  39 +EMUOBJ = $(EMUDIR)decode.o $(EMUDIR)ops2.o $(EMUDIR)fpu.o $(EMUDIR)prim_ops.o \
  40 + $(EMUDIR)ops.o $(EMUDIR)sys.o
  41 +EMUSRC = $(EMUOBJ:.o=.c)
40 42  
41   -
42   -$(LIB): .depend $(OBJS) $(EMUOBJS)
  43 +$(LIB): .depend $(OBJS) $(EMUSRC)
  44 + make libx86emu.a -C ../bios_emulator/scitech/src/x86emu -f makefile.uboot CROSS_COMPILE=$(CROSS_COMPILE)
43 45 -rm $(LIB)
44   - $(AR) crv $@ $(OBJS) $(EMUOBJS)
  46 + $(AR) crv $@ $(OBJS) $(EMUOBJ)
  47 +
45 48  
46 49 #########################################################################
47 50  
board/MAI/AmigaOneG3SE/articiaS.c
Diff comments   View file @ 7c7a23b
... ... @@ -82,8 +82,9 @@
82 82  
83 83 long detect_sdram (uint8 * rom, int dimmNum, struct dimm_bank *banks)
84 84 {
  85 + DECLARE_GLOBAL_DATA_PTR;
85 86 int dimm_address = (dimmNum == 0) ? SM_DIMM0_ADDR : SM_DIMM1_ADDR;
86   - uint32 busclock = get_bus_freq (0);
  87 + uint32 busclock = gd->bus_clk;
87 88 uint32 memclock = busclock;
88 89 uint32 tmemclock = 1000000000 / (memclock / 100);
89 90 uint32 datawidth;
... ... @@ -404,7 +405,7 @@
404 405 uint32 total_ram = 0;
405 406  
406 407 struct dimm_bank banks[4]; /* FIXME: Move to initram */
407   - uint32 busclock = get_bus_freq (0);
  408 + uint32 busclock = gd->bus_clk;
408 409 uint32 memclock = busclock;
409 410 uint32 reg32;
410 411 uint32 refresh_clocks;
board/MAI/AmigaOneG3SE/articiaS_pci.c
Diff comments   View file @ 7c7a23b
... ... @@ -26,7 +26,7 @@
26 26 #include "memio.h"
27 27 #include "articiaS.h"
28 28  
29   -//#define ARTICIA_PCI_DEBUG
  29 +#undef ARTICIA_PCI_DEBUG
30 30  
31 31 #ifdef ARTICIA_PCI_DEBUG
32 32 #define PRINTF(fmt,args...) printf (fmt ,##args)
... ... @@ -512,7 +512,11 @@
512 512 PRINTF("Searching for class 0x%x on bus %d\n", classes[classnr], busnr);
513 513 /* Find the first of this class on this bus */
514 514 dev = pci_hose_find_class(&articiaS_hose, busnr, classes[classnr], 0);
515   - if (dev != ~0) break;
  515 + if (dev != ~0)
  516 + {
  517 + PRINTF("Found VGA Card at %02x:%02x:%02x\n", PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
  518 + break;
  519 + }
516 520 busnr++;
517 521 if (busnr > articiaS_hose.last_busno)
518 522 {
... ... @@ -552,7 +556,7 @@
552 556 /*
553 557 * Now try to run the bios
554 558 */
555   -
  559 + PRINTF("Trying to run bios now\n");
556 560 if (execute_bios(dev, gd->relocaddr))
557 561 {
558 562 printf("OK\n");
board/MAI/AmigaOneG3SE/config.mk
Diff comments   View file @ 7c7a23b
... ... @@ -29,5 +29,5 @@
29 29  
30 30 TEXT_BASE = 0xfff00000
31 31  
32   -PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -Wa,-mregnames -DEASTEREGG $(X86EMU) #-DDEBUG
  32 +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -Wa,-mregnames -DEASTEREGG $(X86EMU) -Dprintk=printf #-DDEBUG
board/MAI/AmigaOneG3SE/video.c
Diff comments   View file @ 7c7a23b
... ... @@ -474,13 +474,13 @@
474 474 }
475 475 #endif
476 476  
477   -extern bd_t *bd_global;
478 477 extern block_dev_desc_t * ide_get_dev(int dev);
479 478 extern char version_string[];
480 479  
481 480 void video_banner(void)
482 481 {
483 482 block_dev_desc_t *ide;
  483 + DECLARE_GLOBAL_DATA_PTR;
484 484 int i;
485 485 char *s;
486 486 int maxdev;
... ... @@ -513,8 +513,8 @@
513 513 video_clear();
514 514 printf("%s\n\nCPU: ", version_string);
515 515 checkcpu();
516   - printf("DRAM: %ld MB\n", bd_global->bi_memsize/(1024*1024));
517   - printf("FSB: %ld MHz\n", bd_global->bi_busfreq/1000000);
  516 + printf("DRAM: %ld MB\n", gd->bd->bi_memsize/(1024*1024));
  517 + printf("FSB: %ld MHz\n", gd->bd->bi_busfreq/1000000);
518 518  
519 519 printf("\n---- Disk summary ----\n");
520 520 for (i = 0; i < maxdev; i++)
board/MAI/bios_emulator/glue.c
Diff comments   View file @ 7c7a23b
... ... @@ -271,9 +271,9 @@
271 271 pci_write_config_dword(dev, PCI_ROM_ADDRESS, 0);
272 272 pci_write_config_dword(dev, i, bar_backup);
273 273  
274   - /* FIXME: */
275   - bat_map(2, 0x80000000, 256*1024*1024);
276   - show_bat_mapping();
  274 + /* FIXME: Shouldn't be needed anymore*/
  275 + /* bat_map(2, 0x80000000, 256*1024*1024);
  276 + show_bat_mapping(); */
277 277  
278 278 /*
279 279 * Since most cards can probably only do 16 bit IO addressing, we
... ... @@ -436,7 +436,6 @@
436 436  
437 437 void show_bat_mapping(void)
438 438 {
439   -#ifdef DEBUG
440 439 u32 dbat0u, dbat0l, ibat0u, ibat0l;
441 440 u32 dbat1u, dbat1l, ibat1u, ibat1l;
442 441 u32 dbat2u, dbat2l, ibat2u, ibat2l;
... ... @@ -477,7 +476,6 @@
477 476 dbat3u, dbat3l, ibat3u, ibat3l);
478 477  
479 478 printf("\nMSR: %08x HID0: %08x L2CR: %08x \n", msr,hid0, l2cr_reg);
480   -#endif
481 479 }
482 480  
483 481  
484 482  
485 483  
486 484  
487 485  
488 486  
... ... @@ -485,45 +483,35 @@
485 483 void remove_init_data(void)
486 484 {
487 485 char *s;
488   - u32 batl = ((CFG_SDRAM_BASE+0x100000) | BATL_PP_RW);
489   - u32 batu =((CFG_SDRAM_BASE+0x100000) | BATU_BL_256M | BATU_VS | BATU_VP);
490   -#if 0 /* already done in board_init_r() */
491   - void *data = (void *)(CFG_INIT_RAM_ADDR+CFG_INIT_DATA_OFFSET);
492   - unsigned char data2[CFG_INIT_DATA_SIZE];
493 486  
494   - /* Make a copy of the data */
495   - memcpy(data2, data, CFG_INIT_DATA_SIZE);
496   -#endif /* 0 */
497   -
498 487 /* Invalidate and disable data cache */
499 488 invalidate_l1_data_cache();
500 489 dcache_disable();
501 490  
502   -#if 0
503   - /* Copy to the real RAM address */
504   - memcpy(data, data2, CFG_INIT_DATA_SIZE);
505   -#endif
506   -
507   - /*printf("Before ICache enable\n");
508   - show_bat_mapping();*/
509   -
510   - __asm volatile ("isync \n"
511   - "mtdbatu 2,%2 \n"
512   - "mtdbatl 2,%2 \n"
513   - "mtdbatu 1,%0 \n"
514   - "mtdbatl 1,%1 \n"
515   - "sync \n"
516   - "isync \n"
517   - : : "r" (batu), "r" (batl), "r" (0));
518   -
519   - /* show_bat_mapping(); */
520 491 s = getenv("x86_cache");
521 492  
522   - if (!s || (s && strcmp(s, "on")==0))
  493 + if (!s)
523 494 {
524 495 icache_enable();
525 496 dcache_enable();
526 497 }
  498 + else if (s)
  499 + {
  500 + if (strcmp(s, "dcache")==0)
  501 + {
  502 + dcache_enable();
  503 + }
  504 + else if (strcmp(s, "icache") == 0)
  505 + {
  506 + icache_enable();
  507 + }
  508 + else if (strcmp(s, "on")== 0 || strcmp(s, "both") == 0)
  509 + {
  510 + dcache_enable();
  511 + icache_enable();
  512 + }
  513 + }
527 514  
  515 + /* show_bat_mapping();*/
528 516 }
board/MAI/bios_emulator/scitech/src/x86emu/makefile.uboot
Diff comments   View file @ 7c7a23b
  1 +#############################################################################
  2 +#
  3 +# Realmode X86 Emulator Library
  4 +#
  5 +# Copyright (C) 1996-1999 SciTech Software, Inc.
  6 +#
  7 +# ========================================================================
  8 +#
  9 +# Permission to use, copy, modify, distribute, and sell this software and
  10 +# its documentation for any purpose is hereby granted without fee,
  11 +# provided that the above copyright notice appear in all copies and that
  12 +# both that copyright notice and this permission notice appear in
  13 +# supporting documentation, and that the name of the authors not be used
  14 +# in advertising or publicity pertaining to distribution of the software
  15 +# without specific, written prior permission. The authors makes no
  16 +# representations about the suitability of this software for any purpose.
  17 +# It is provided "as is" without express or implied warranty.
  18 +#
  19 +# THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
  20 +# INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
  21 +# EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
  22 +# CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
  23 +# USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
  24 +# OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  25 +# PERFORMANCE OF THIS SOFTWARE.
  26 +#
  27 +# ========================================================================
  28 +#
  29 +# Descripton: Linux specific makefile for the x86emu library.
  30 +#
  31 +#############################################################################
  32 +CC = $(CROSS_COMPILE)gcc
  33 +AR = $(CROSS_COMPILE)ar
  34 +TARGETLIB = libx86emu.a
  35 +TARGETDEBUGLIB =libx86emud.a
  36 +
  37 +OBJS=\
  38 +decode.o \
  39 +fpu.o \
  40 +ops.o \
  41 +ops2.o \
  42 +prim_ops.o \
  43 +sys.o
  44 +
  45 +DEBUGOBJS=debug.d \
  46 + decode.d \
  47 + fpu.d \
  48 + ops.d \
  49 + ops2.d \
  50 + prim_ops.d \
  51 + sys.d
  52 +
  53 +.SUFFIXES: .d
  54 +
  55 +all: $(TARGETLIB) $(TARGETDEBUGLIB)
  56 +
  57 +$(TARGETLIB): $(OBJS)
  58 + $(AR) rv $(TARGETLIB) $(OBJS)
  59 +
  60 +$(TARGETDEBUGLIB): $(DEBUGOBJS)
  61 + $(AR) rv $(TARGETDEBUGLIB) $(DEBUGOBJS)
  62 +
  63 +INCS = -I. -Ix86emu -I../../include
  64 +CFLAGS = -D__DRIVER__ -DFORCE_POST -D_CEXPORT= -DNO_LONG_LONG -Dprintk=printf -fsigned-char -fomit-frame-pointer -mrelocatable -ffixed-r14 -meabi -mrelocatable -ffixed-r14 -meabi
  65 +CDEBUGFLAGS = -DDEBUG
  66 +
  67 +.c.o:
  68 + $(CC) -g -O2 -Wall -c $(CFLAGS) $(INCS) $*.c
  69 +
  70 +.c.d:
  71 + $(CC) -g -O2 -Wall -c -o$*.d $(CFLAGS) $(CDEBUGFLAGS) $(INCS) $*.c
  72 +
  73 +.cpp.o:
  74 + $(CC) -c $(CFLAGS) $(INCS) $*.cpp
  75 +
  76 +clean:
  77 + rm -f *.a *.o *.d
  78 +
  79 +validate: validate.o libx86emu.a
  80 + $(CC) -o validate validate.o -lx86emu -L.
board/MAI/bios_emulator/x86interface.c
Diff comments   View file @ 7c7a23b
... ... @@ -398,9 +398,7 @@
398 398 u8 cfg;
399 399 int i;
400 400 char c;
401   -#ifdef DEBUG
402 401 char *s;
403   -#endif
404 402 #ifdef EASTEREGG
405 403 int easteregg_active = 0;
406 404 #endif
... ... @@ -409,6 +407,7 @@
409 407 unsigned char *msg;
410 408 unsigned char current_attr;
411 409  
  410 + PRINTF("Trying to remove init data\n");
412 411 remove_init_data();
413 412 PRINTF("Removed init data from cache, now in RAM\n");
414 413  
... ... @@ -438,7 +437,7 @@
438 437 return 0;
439 438 }
440 439  
441   -#ifdef DEBUG
  440 +#if 1 /*def DEBUG*/
442 441 s = getenv("x86_ask_start");
443 442 if (s)
444 443 {
... ... @@ -646,7 +645,7 @@
646 645 if (getenv("x86_do_inout")) do_inout();
647 646 #endif
648 647  
649   - dcache_disable();
  648 +//FIXME: dcache_disable();
650 649 return 1;
651 650 }
652 651  
board/MAI/menu/cmd_menu.c
Diff comments   View file @ 7c7a23b
... ... @@ -2,7 +2,7 @@
2 2 #include <command.h>
3 3 #include <cmd_menu.h>
4 4  
5   -int do_menu( cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[] )
  5 +int do_menu( cmd_tbl_t *cmdtp, /*bd_t *bd,*/ int flag, int argc, char *argv[] )
6 6 {
7 7 // printf("<NOT YET IMPLEMENTED>\n");
8 8 return 0;
board/hermes/u-boot.lds
Diff comments   View file @ 7c7a23b
... ... @@ -56,11 +56,13 @@
56 56 /* WARNING - the following is hand-optimized to fit within */
57 57 /* the sector layout of our flash chips! XXX FIXME XXX */
58 58  
59   - cpu/mpc8xx/start.o (.text)
60   - common/dlmalloc.o (.text)
61   - lib_ppc/ppcstring.o (.text)
62   - cpu/mpc8xx/interrupts.o (.text)
  59 + cpu/mpc8xx/start.o (.text)
  60 + common/dlmalloc.o (.text)
  61 + cpu/mpc8xx/interrupts.o (.text)
63 62 lib_ppc/time.o (.text)
  63 + lib_ppc/ticks.o (.text)
  64 + lib_ppc/cache.o (.text)
  65 + lib_generic/crc32.o (.text)
64 66 . = env_offset;
65 67 common/environment.o(.text)
66 68  
board/tqm8260/tqm8260.c
Diff comments   View file @ 7c7a23b
... ... @@ -202,7 +202,7 @@
202 202  
203 203 if (!i || strncmp (str, "TQM8260", 7)) {
204 204 puts ("### No HW ID - assuming TQM8260\n");
205   - return (1);
  205 + return (0);
206 206 }
207 207  
208 208 puts (str);
... ... @@ -344,7 +344,7 @@
344 344 DECLARE_GLOBAL_DATA_PTR;
345 345  
346 346 if (vfd_init_done != 0)
347   - return;
  347 + return (0);
348 348 vfd_init_done = 1;
349 349  
350 350 vfdbase = gd->fb_base;
... ... @@ -205,9 +205,27 @@
205 205 PRINT (" header type = 0x%.2x\n", byte, PCI_HEADER_TYPE);
206 206 PRINT (" BIST = 0x%.2x\n", byte, PCI_BIST);
207 207 PRINT (" base address 0 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_0);
208   - PRINT (" base address 1 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_1);
209 208  
210   - if (header_type & 0x01) { /* PCI-to-PCI bridge */
  209 + switch (header_type & 0x03) {
  210 + case PCI_HEADER_TYPE_NORMAL: /* "normal" PCI device */
  211 + PRINT (" base address 1 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_1);
  212 + PRINT (" base address 2 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_2);
  213 + PRINT (" base address 3 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_3);
  214 + PRINT (" base address 4 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_4);
  215 + PRINT (" base address 5 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_5);
  216 + PRINT (" cardBus CIS pointer = 0x%.8x\n", dword, PCI_CARDBUS_CIS);
  217 + PRINT (" sub system vendor ID = 0x%.4x\n", word, PCI_SUBSYSTEM_VENDOR_ID);
  218 + PRINT (" sub system ID = 0x%.4x\n", word, PCI_SUBSYSTEM_ID);
  219 + PRINT (" expansion ROM base address = 0x%.8x\n", dword, PCI_ROM_ADDRESS);
  220 + PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
  221 + PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
  222 + PRINT (" min Grant = 0x%.2x\n", byte, PCI_MIN_GNT);
  223 + PRINT (" max Latency = 0x%.2x\n", byte, PCI_MAX_LAT);
  224 + break;
  225 +
  226 + case PCI_HEADER_TYPE_BRIDGE: /* PCI-to-PCI bridge */
  227 +
  228 + PRINT (" base address 1 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_1);
211 229 PRINT (" primary bus number = 0x%.2x\n", byte, PCI_PRIMARY_BUS);
212 230 PRINT (" secondary bus number = 0x%.2x\n", byte, PCI_SECONDARY_BUS);
213 231 PRINT (" subordinate bus number = 0x%.2x\n", byte, PCI_SUBORDINATE_BUS);
... ... @@ -227,19 +245,39 @@
227 245 PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
228 246 PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
229 247 PRINT (" bridge control = 0x%.4x\n", word, PCI_BRIDGE_CONTROL);
230   - } else { /* PCI device */
231   - PRINT(" base address 2 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_2);
232   - PRINT(" base address 3 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_3);
233   - PRINT(" base address 4 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_4);
234   - PRINT(" base address 5 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_5);
235   - PRINT(" cardBus CIS pointer = 0x%.8x\n", dword, PCI_CARDBUS_CIS);
236   - PRINT(" sub system vendor ID = 0x%.4x\n", word, PCI_SUBSYSTEM_VENDOR_ID);
237   - PRINT(" sub system ID = 0x%.4x\n", word, PCI_SUBSYSTEM_ID);
238   - PRINT(" expansion ROM base address = 0x%.8x\n", dword, PCI_ROM_ADDRESS);
239   - PRINT(" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
240   - PRINT(" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
241   - PRINT(" min Grant = 0x%.2x\n", byte, PCI_MIN_GNT);
242   - PRINT(" max Latency = 0x%.2x\n", byte, PCI_MAX_LAT);
  248 + break;
  249 +
  250 + case PCI_HEADER_TYPE_CARDBUS: /* PCI-to-CardBus bridge */
  251 +
  252 + PRINT (" capabilities = 0x%.2x\n", byte, PCI_CB_CAPABILITY_LIST);
  253 + PRINT (" secondary status = 0x%.4x\n", word, PCI_CB_SEC_STATUS);
  254 + PRINT (" primary bus number = 0x%.2x\n", byte, PCI_CB_PRIMARY_BUS);
  255 + PRINT (" CardBus number = 0x%.2x\n", byte, PCI_CB_CARD_BUS);
  256 + PRINT (" subordinate bus number = 0x%.2x\n", byte, PCI_CB_SUBORDINATE_BUS);
  257 + PRINT (" CardBus latency timer = 0x%.2x\n", byte, PCI_CB_LATENCY_TIMER);
  258 + PRINT (" CardBus memory base 0 = 0x%.8x\n", dword, PCI_CB_MEMORY_BASE_0);
  259 + PRINT (" CardBus memory limit 0 = 0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_0);
  260 + PRINT (" CardBus memory base 1 = 0x%.8x\n", dword, PCI_CB_MEMORY_BASE_1);
  261 + PRINT (" CardBus memory limit 1 = 0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_1);
  262 + PRINT (" CardBus IO base 0 = 0x%.4x\n", word, PCI_CB_IO_BASE_0);
  263 + PRINT (" CardBus IO base high 0 = 0x%.4x\n", word, PCI_CB_IO_BASE_0_HI);
  264 + PRINT (" CardBus IO limit 0 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_0);
  265 + PRINT (" CardBus IO limit high 0 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_0_HI);
  266 + PRINT (" CardBus IO base 1 = 0x%.4x\n", word, PCI_CB_IO_BASE_1);
  267 + PRINT (" CardBus IO base high 1 = 0x%.4x\n", word, PCI_CB_IO_BASE_1_HI);
  268 + PRINT (" CardBus IO limit 1 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_1);
  269 + PRINT (" CardBus IO limit high 1 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_1_HI);
  270 + PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
  271 + PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
  272 + PRINT (" bridge control = 0x%.4x\n", word, PCI_CB_BRIDGE_CONTROL);
  273 + PRINT (" subvendor ID = 0x%.4x\n", word, PCI_CB_SUBSYSTEM_VENDOR_ID);
  274 + PRINT (" subdevice ID = 0x%.4x\n", word, PCI_CB_SUBSYSTEM_ID);
  275 + PRINT (" PC Card 16bit base address = 0x%.8x\n", dword, PCI_CB_LEGACY_MODE_BASE);
  276 + break;
  277 +
  278 + default:
  279 + printf("unknown header\n");
  280 + break;
243 281 }
244 282  
245 283 #undef PRINT
... ... @@ -156,9 +156,24 @@
156 156 return (c);
157 157 }
158 158  
  159 +#ifdef CONFIG_AMIGAONEG3SE
159 160 uchar env_get_char_memory (int index)
160 161 {
161 162 DECLARE_GLOBAL_DATA_PTR;
  163 + uchar retval;
  164 + enable_nvram();
  165 + if (gd->env_valid) {
  166 + retval = ( *((uchar *)(gd->env_addr + index)) );
  167 + } else {
  168 + retval = ( default_environment[index] );
  169 + }
  170 + disable_nvram();
  171 + return retval;
  172 +}
  173 +#else
  174 +uchar env_get_char_memory (int index)
  175 +{
  176 + DECLARE_GLOBAL_DATA_PTR;
162 177  
163 178 if (gd->env_valid) {
164 179 return ( *((uchar *)(gd->env_addr + index)) );
... ... @@ -166,6 +181,7 @@
166 181 return ( default_environment[index] );
167 182 }
168 183 }
  184 +#endif
169 185  
170 186 uchar *env_get_addr (int index)
171 187 {
... ... @@ -66,7 +66,25 @@
66 66 extern uchar (*env_get_char)(int);
67 67 extern uchar env_get_char_memory (int index);
68 68  
  69 +#ifdef CONFIG_AMIGAONEG3SE
  70 +uchar env_get_char_spec (int index)
  71 +{
  72 +#ifdef CFG_NVRAM_ACCESS_ROUTINE
  73 + uchar c;
69 74  
  75 + nvram_read(&c, CFG_ENV_ADDR+index, 1);
  76 +
  77 + return c;
  78 +#else
  79 + DECLARE_GLOBAL_DATA_PTR;
  80 + uchar retval;
  81 + enable_nvram();
  82 + retval = *((uchar *)(gd->env_addr + index));
  83 + disable_nvram();
  84 + return retval;
  85 +#endif
  86 +}
  87 +#else
70 88 uchar env_get_char_spec (int index)
71 89 {
72 90 #ifdef CFG_NVRAM_ACCESS_ROUTINE
... ... @@ -81,6 +99,7 @@
81 99 return *((uchar *)(gd->env_addr + index));
82 100 #endif
83 101 }
  102 +#endif
84 103  
85 104 void env_relocate_spec (void)
86 105 {
87 106  
... ... @@ -94,13 +113,19 @@
94 113 int saveenv (void)
95 114 {
96 115 int rcode = 0;
97   -
  116 +#ifdef CONFIG_AMIGAONEG3SE
  117 + enable_nvram();
  118 +#endif
98 119 #ifdef CFG_NVRAM_ACCESS_ROUTINE
99 120 nvram_write(CFG_ENV_ADDR, env_ptr, CFG_ENV_SIZE);
100 121 #else
101 122 if (memcpy ((char *)CFG_ENV_ADDR, env_ptr, CFG_ENV_SIZE) == NULL)
102 123 rcode = 1 ;
103 124 #endif
  125 +#ifdef CONFIG_AMIGAONEG3SE
  126 + udelay(10000);
  127 + disable_nvram();
  128 +#endif
104 129 return rcode;
105 130 }
106 131  
... ... @@ -113,7 +138,9 @@
113 138 int env_init (void)
114 139 {
115 140 DECLARE_GLOBAL_DATA_PTR;
116   -
  141 +#ifdef CONFIG_AMIGAONEG3SE
  142 + enable_nvram();
  143 +#endif
117 144 #if defined(CFG_NVRAM_ACCESS_ROUTINE)
118 145 ulong crc;
119 146 uchar data[ENV_SIZE];
... ... @@ -131,7 +158,9 @@
131 158 gd->env_addr = (ulong)&default_environment[0];
132 159 gd->env_valid = 0;
133 160 }
134   -
  161 +#ifdef CONFIG_AMIGAONEG3SE
  162 + disable_nvram();
  163 +#endif
135 164 return (0);
136 165 }
137 166  
cpu/74xx_7xx/start.S
Diff comments   View file @ 7c7a23b
... ... @@ -177,7 +177,14 @@
177 177 add r11,r11,r0
178 178 lwz r11,0(r11)
179 179  
180   - li r12,0xd00-4*3 /* save LR & SRRx */
  180 + li r20,0xd00-4 /* Get stack pointer */
  181 + lwz r12,0(r20)
  182 + subi r12,r12,12 /* Adjust stack pointer */
  183 + li r0,0xc00+_end_back-SystemCall
  184 + cmplw 0, r0, r12 /* Check stack overflow */
  185 + bgt 1f
  186 + stw r12,0(r20)
  187 +
181 188 mflr r0
182 189 stw r0,0(r12)
183 190 mfspr r0,SRR0
... ... @@ -202,7 +209,9 @@
202 209 mtmsr r11
203 210 SYNC
204 211  
205   - li r12,0xd00-4*3 /* restore regs */
  212 + li r12,0xd00-4 /* restore regs */
  213 + lwz r12,0(r12)
  214 +
206 215 lwz r11,0(r12)
207 216 mtlr r11
208 217 lwz r11,4(r12)
209 218  
... ... @@ -210,8 +219,13 @@
210 219 lwz r11,8(r12)
211 220 mtspr SRR1,r11
212 221  
  222 + addi r12,r12,12 /* Adjust stack pointer */
  223 + li r20,0xd00-4
  224 + stw r12,0(r20)
  225 +
213 226 SYNC
214 227 rfi
  228 +_end_back:
215 229  
216 230 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
217 231  
... ... @@ -716,6 +730,9 @@
716 730 bne 5b
717 731 6:
718 732 mr r3, r10 /* Destination Address */
  733 +#ifdef CONFIG_AMIGAONEG3SE
  734 + mr r4, r9 /* Use RAM copy of the global data */
  735 +#endif
719 736 bl after_reloc
720 737  
721 738 /* not reached - end relocate_code */
cpu/mpc824x/drivers/epic/epic.h
Diff comments   View file @ 7c7a23b
... ... @@ -108,6 +108,9 @@
108 108 #define EPIC_PROC_INT_ACK_REG (EPIC_EUMBBAR + 0x200a0)/* Int. acknowledge */
109 109 #define EPIC_PROC_EOI_REG (EPIC_EUMBBAR + 0x200b0)/* End of interrupt */
110 110  
  111 +#define EPIC_VEC_PRI_MASK 0x80000000 /* Mask Interrupt bit in IVPR */
  112 +#define EPIC_VEC_PRI_DFLT_PRI 8 /* Interrupt Priority in IVPR */
  113 +
111 114 /* Error code */
112 115  
113 116 #define OK 0
cpu/mpc824x/drivers/epic/epic1.c
Diff comments   View file @ 7c7a23b
... ... @@ -70,6 +70,10 @@
70 70 tmp = sysEUMBBARRead(EPIC_GLOBAL_REG);
71 71 tmp |= 0xa0000000; /* Set the Global Conf. register */
72 72 sysEUMBBARWrite(EPIC_GLOBAL_REG, tmp);
  73 + /*
  74 + * Wait for EPIC to reset - CLH
  75 + */
  76 + while( (sysEUMBBARRead(EPIC_GLOBAL_REG) & 0x80000000) == 1);
73 77 sysEUMBBARWrite(EPIC_GLOBAL_REG, 0x20000000);
74 78 tmp = sysEUMBBARRead(EPIC_INT_CONF_REG); /* Read interrupt conf. reg */
75 79  
... ... @@ -81,7 +85,8 @@
81 85 sysEUMBBARWrite(EPIC_INT_CONF_REG, tmp);
82 86 }
83 87  
84   - while (epicIntAck() != 0xff); /* Clear all pending interrupts */
  88 + while (epicIntAck() != 0xff) /* Clear all pending interrupts */
  89 + epicEOI();
85 90 }
86 91  
87 92 /****************************************************************************
88 93  
89 94  
... ... @@ -92,18 +97,18 @@
92 97 *
93 98 * RETURNS: None
94 99 */
95   -void epicIntEnable
96   - (
97   - int intVec /* Interrupt Vector Number */
98   - )
99   - {
  100 +void epicIntEnable(int intVec)
  101 +{
100 102 ULONG tmp;
101 103 ULONG srAddr;
102 104  
103 105 srAddr = SrcVecTable[intVec].srcAddr; /* Retrieve src Vec/Prio register */
104 106 tmp = sysEUMBBARRead(srAddr);
105   - tmp &= 0x7fffffff; /* Clear the mask bit */
  107 + tmp &= ~EPIC_VEC_PRI_MASK; /* Clear the mask bit */
  108 + tmp |= (EPIC_VEC_PRI_DFLT_PRI << 16); /* Set priority to Default - CLH */
  109 + tmp |= intVec; /* Set Vector number */
106 110 sysEUMBBARWrite(srAddr, tmp);
  111 +
107 112 return;
108 113 }
109 114  
cpu/mpc824x/interrupts.c
Diff comments   View file @ 7c7a23b
... ... @@ -92,6 +92,8 @@
92 92 */
93 93  
94 94 epicInit (EPIC_DIRECT_IRQ, 0);
  95 + /* EPIC won't generate INT unless Current Task Pri < 15 */
  96 + epicCurTaskPrioSet(0);
95 97  
96 98 set_dec (decrementer_count);
97 99  
... ... @@ -278,7 +278,14 @@
278 278 add r11,r11,r0
279 279 lwz r11,0(r11)
280 280  
281   - li r12,0xd00-4*3 /* save LR & SRRx */
  281 + li r20,0xd00-4 /* Get stack pointer */
  282 + lwz r12,0(r20)
  283 + subi r12,r12,12 /* Adjust stack pointer */
  284 + li r0,0xc00+_end_back-SystemCall
  285 + cmplw 0, r0, r12 /* Check stack overflow */
  286 + bgt 1f
  287 + stw r12,0(r20)
  288 +
282 289 mflr r0
283 290 stw r0,0(r12)
284 291 mfspr r0,SRR0
... ... @@ -303,7 +310,9 @@
303 310 mtmsr r11
304 311 SYNC
305 312  
306   - li r12,0xd00-4*3 /* restore regs */
  313 + li r12,0xd00-4 /* restore regs */
  314 + lwz r12,0(r12)
  315 +
307 316 lwz r11,0(r12)
308 317 mtlr r11
309 318 lwz r11,4(r12)
310 319  
... ... @@ -311,8 +320,13 @@
311 320 lwz r11,8(r12)
312 321 mtspr SRR1,r11
313 322  
  323 + addi r12,r12,12 /* Adjust stack pointer */
  324 + li r20,0xd00-4
  325 + stw r12,0(r20)
  326 +
314 327 SYNC
315 328 rfi
  329 +_end_back:
316 330  
317 331 STD_EXCEPTION(EXC_OFF_TRACE, SingleStep, UnknownException)
318 332  
... ... @@ -324,7 +324,14 @@
324 324 add r11,r11,r0
325 325 lwz r11,0(r11)
326 326  
327   - li r12,0xd00-4*3 /* save LR & SRRx */
  327 + li r20,0xd00-4 /* Get stack pointer */
  328 + lwz r12,0(r20)
  329 + subi r12,r12,12 /* Adjust stack pointer */
  330 + li r0,0xc00+_end_back-SystemCall
  331 + cmplw 0, r0, r12 /* Check stack overflow */
  332 + bgt 1f
  333 + stw r12,0(r20)
  334 +
328 335 mflr r0
329 336 stw r0,0(r12)
330 337 mfspr r0,SRR0
... ... @@ -349,7 +356,9 @@
349 356 mtmsr r11
350 357 SYNC
351 358  
352   - li r12,0xd00-4*3 /* restore regs */
  359 + li r12,0xd00-4 /* restore regs */
  360 + lwz r12,0(r12)
  361 +
353 362 lwz r11,0(r12)
354 363 mtlr r11
355 364 lwz r11,4(r12)
356 365  
... ... @@ -357,8 +366,13 @@
357 366 lwz r11,8(r12)
358 367 mtspr SRR1,r11
359 368  
  369 + addi r12,r12,12 /* Adjust stack pointer */
  370 + li r20,0xd00-4
  371 + stw r12,0(r20)
  372 +
360 373 SYNC
361 374 rfi
  375 +_end_back:
362 376  
363 377 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
364 378  
cpu/mpc8xx/interrupts.c
Diff comments   View file @ 7c7a23b
... ... @@ -28,99 +28,104 @@
28 28 #include <asm/processor.h>
29 29 #include <commproc.h>
30 30  
31   -/****************************************************************************/
  31 +/************************************************************************/
32 32  
33   -unsigned decrementer_count; /* count value for 1e6/HZ microseconds */
  33 +unsigned decrementer_count; /* count value for 1e6/HZ microseconds */
34 34  
35   -/****************************************************************************/
  35 +/************************************************************************/
36 36  
37 37 /*
38 38 * CPM interrupt vector functions.
39 39 */
40   -struct cpm_action {
41   - interrupt_handler_t *handler;
42   - void *arg;
  40 +struct interrupt_action {
  41 + interrupt_handler_t *handler;
  42 + void *arg;
43 43 };
44 44  
45   -static struct cpm_action cpm_vecs[CPMVEC_NR];
  45 +static struct interrupt_action cpm_vecs[CPMVEC_NR];
  46 +static struct interrupt_action irq_vecs[NR_IRQS];
46 47  
47 48 static void cpm_interrupt_init (void);
48   -static void cpm_interrupt(int irq, struct pt_regs * regs);
  49 +static void cpm_interrupt (void *regs);
49 50  
50   -/****************************************************************************/
  51 +/************************************************************************/
51 52  
52   -static __inline__ unsigned long get_msr(void)
  53 +static __inline__ unsigned long get_msr (void)
53 54 {
54   - unsigned long msr;
  55 + unsigned long msr;
55 56  
56   - asm volatile("mfmsr %0" : "=r" (msr) :);
57   - return msr;
  57 + asm volatile ("mfmsr %0":"=r" (msr):);
  58 +
  59 + return msr;
58 60 }
59 61  
60   -static __inline__ void set_msr(unsigned long msr)
  62 +static __inline__ void set_msr (unsigned long msr)
61 63 {
62   - asm volatile("mtmsr %0" : : "r" (msr));
  64 + asm volatile ("mtmsr %0"::"r" (msr));
63 65 }
64 66  
65   -static __inline__ unsigned long get_dec(void)
  67 +static __inline__ unsigned long get_dec (void)
66 68 {
67   - unsigned long val;
  69 + unsigned long val;
68 70  
69   - asm volatile("mfdec %0" : "=r" (val) :);
70   - return val;
  71 + asm volatile ("mfdec %0":"=r" (val):);
  72 +
  73 + return val;
71 74 }
72 75  
73 76  
74   -static __inline__ void set_dec(unsigned long val)
  77 +static __inline__ void set_dec (unsigned long val)
75 78 {
76   - asm volatile("mtdec %0" : : "r" (val));
  79 + asm volatile ("mtdec %0"::"r" (val));
77 80 }
78 81  
79 82  
80 83 void enable_interrupts (void)
81 84 {
82   - set_msr (get_msr() | MSR_EE);
  85 + set_msr (get_msr () | MSR_EE);
83 86 }
84 87  
85 88 /* returns flag if MSR_EE was set before */
86 89 int disable_interrupts (void)
87 90 {
88   - ulong msr = get_msr();
  91 + ulong msr = get_msr ();
  92 +
89 93 set_msr (msr & ~MSR_EE);
90 94 return ((msr & MSR_EE) != 0);
91 95 }
92 96  
93   -/****************************************************************************/
  97 +/************************************************************************/
94 98  
95   -int interrupt_init(void)
  99 +int interrupt_init (void)
96 100 {
97   - volatile immap_t *immr = (immap_t *)CFG_IMMR;
  101 + volatile immap_t *immr = (immap_t *) CFG_IMMR;
98 102  
99   - decrementer_count = get_tbclk() / CFG_HZ;
  103 + decrementer_count = get_tbclk () / CFG_HZ;
100 104  
101   - cpm_interrupt_init();
  105 + /* disable all interrupts */
  106 + immr->im_siu_conf.sc_simask = 0;
102 107  
103   - /* disable all interrupts except for the CPM interrupt */
104   - immr->im_siu_conf.sc_simask = 1 << (31-CPM_INTERRUPT);
  108 + /* Configure CPM interrupts */
  109 + cpm_interrupt_init ();
105 110  
106 111 set_dec (decrementer_count);
107 112  
108   - set_msr (get_msr() | MSR_EE);
  113 + set_msr (get_msr () | MSR_EE);
109 114  
110 115 return (0);
111 116 }
112 117  
113   -/****************************************************************************/
  118 +/************************************************************************/
114 119  
115 120 /*
116 121 * Handle external interrupts
117 122 */
118   -void external_interrupt(struct pt_regs *regs)
  123 +void external_interrupt (struct pt_regs *regs)
119 124 {
120   - volatile immap_t *immr = (immap_t *)CFG_IMMR;
121   - int irq;
122   - ulong simask, newmask;
123   - ulong vec, v_bit;
  125 + volatile immap_t *immr = (immap_t *) CFG_IMMR;
  126 + int irq;
  127 + ulong simask, newmask;
  128 + ulong vec, v_bit;
124 129  
125 130 /*
126 131 * read the SIVEC register and shift the bits down
127 132  
128 133  
... ... @@ -137,14 +142,15 @@
137 142 newmask = simask & (~(0xFFFF0000 >> irq));
138 143 immr->im_siu_conf.sc_simask = newmask;
139 144  
140   - if (!(irq & 0x1)) { /* External Interrupt ? */
  145 + if (!(irq & 0x1)) { /* External Interrupt ? */
141 146 ulong siel;
  147 +
142 148 /*
143 149 * Read Interrupt Edge/Level Register
144 150 */
145 151 siel = immr->im_siu_conf.sc_siel;
146 152  
147   - if (siel & v_bit) { /* edge triggered interrupt ? */
  153 + if (siel & v_bit) { /* edge triggered interrupt ? */
148 154 /*
149 155 * Rewrite SIPEND Register to clear interrupt
150 156 */
151 157  
152 158  
153 159  
154 160  
155 161  
156 162  
... ... @@ -152,34 +158,29 @@
152 158 }
153 159 }
154 160  
155   - switch (irq) {
156   - case CPM_INTERRUPT:
157   - cpm_interrupt (irq, regs);
158   - break;
159   - default:
  161 + if (irq_vecs[irq].handler != NULL) {
  162 + irq_vecs[irq].handler (irq_vecs[irq].arg);
  163 + } else {
160 164 printf ("\nBogus External Interrupt IRQ %d Vector %ld\n",
161   - irq, vec);
  165 + irq, vec);
162 166 /* turn off the bogus interrupt to avoid it from now */
163 167 simask &= ~v_bit;
164   - break;
165 168 }
166   -
167 169 /*
168 170 * Re-Enable old Interrupt Mask
169 171 */
170 172 immr->im_siu_conf.sc_simask = simask;
171 173 }
172 174  
173   -/****************************************************************************/
  175 +/************************************************************************/
174 176  
175 177 /*
176 178 * CPM interrupt handler
177 179 */
178   -static void
179   -cpm_interrupt(int irq, struct pt_regs * regs)
  180 +static void cpm_interrupt (void *regs)
180 181 {
181   - volatile immap_t *immr = (immap_t *)CFG_IMMR;
182   - uint vec;
  182 + volatile immap_t *immr = (immap_t *) CFG_IMMR;
  183 + uint vec;
183 184  
184 185 /*
185 186 * Get the vector by setting the ACK bit
186 187  
... ... @@ -190,13 +191,14 @@
190 191 vec >>= 11;
191 192  
192 193 if (cpm_vecs[vec].handler != NULL) {
193   - (*cpm_vecs[vec].handler)(cpm_vecs[vec].arg);
  194 + (*cpm_vecs[vec].handler) (cpm_vecs[vec].arg);
194 195 } else {
195 196 immr->im_cpic.cpic_cimr &= ~(1 << vec);
196 197 printf ("Masking bogus CPM interrupt vector 0x%x\n", vec);
197 198 }
198 199 /*
199   - * After servicing the interrupt, we have to remove the status indicator.
  200 + * After servicing the interrupt,
  201 + * we have to remove the status indicator.
200 202 */
201 203 immr->im_cpic.cpic_cisr |= (1 << vec);
202 204 }
203 205  
204 206  
205 207  
206 208  
207 209  
208 210  
209 211  
210 212  
211 213  
212 214  
213 215  
214 216  
215 217  
216 218  
217 219  
218 220  
219 221  
220 222  
... ... @@ -207,75 +209,110 @@
207 209 * to do is ACK it and return. This is a no-op function so we don't
208 210 * need any special tests in the interrupt handler.
209 211 */
210   -static void
211   -cpm_error_interrupt (void *dummy)
  212 +static void cpm_error_interrupt (void *dummy)
212 213 {
213 214 }
214 215  
215   -/****************************************************************************/
216   -
  216 +/************************************************************************/
217 217 /*
218   - * Install and free a CPM interrupt handler.
  218 + * Install and free an interrupt handler
219 219 */
220   -
221   -void
222   -irq_install_handler(int vec, interrupt_handler_t *handler, void *arg)
  220 +void irq_install_handler (int vec, interrupt_handler_t * handler,
  221 + void *arg)
223 222 {
224   - volatile immap_t *immr = (immap_t *)CFG_IMMR;
  223 + volatile immap_t *immr = (immap_t *) CFG_IMMR;
225 224  
226   - if (cpm_vecs[vec].handler != NULL) {
227   - printf ("CPM interrupt 0x%x replacing 0x%x\n",
228   - (uint)handler, (uint)cpm_vecs[vec].handler);
229   - }
230   - cpm_vecs[vec].handler = handler;
231   - cpm_vecs[vec].arg = arg;
232   - immr->im_cpic.cpic_cimr |= (1 << vec);
  225 + if ((vec & CPMVEC_OFFSET) != 0) {
  226 + /* CPM interrupt */
  227 + vec &= 0xffff;
  228 + if (cpm_vecs[vec].handler != NULL) {
  229 + printf ("CPM interrupt 0x%x replacing 0x%x\n",
  230 + (uint) handler,
  231 + (uint) cpm_vecs[vec].handler);
  232 + }
  233 + cpm_vecs[vec].handler = handler;
  234 + cpm_vecs[vec].arg = arg;
  235 + immr->im_cpic.cpic_cimr |= (1 << vec);
233 236 #if 0
234   - printf ("Install CPM interrupt for vector %d ==> %p\n", vec, handler);
  237 + printf ("Install CPM interrupt for vector %d ==> %p\n",
  238 + vec, handler);
235 239 #endif
  240 + } else {
  241 + /* SIU interrupt */
  242 + if (irq_vecs[vec].handler != NULL) {
  243 + printf ("SIU interrupt %d 0x%x replacing 0x%x\n",
  244 + vec,
  245 + (uint) handler,
  246 + (uint) cpm_vecs[vec].handler);
  247 + }
  248 + irq_vecs[vec].handler = handler;
  249 + irq_vecs[vec].arg = arg;
  250 + immr->im_siu_conf.sc_simask |= 1 << (31 - vec);
  251 +#if 0
  252 + printf ("Install SIU interrupt for vector %d ==> %p\n",
  253 + vec, handler);
  254 +#endif
  255 + }
236 256 }
237 257  
238   -void
239   -irq_free_handler(int vec)
  258 +void irq_free_handler (int vec)
240 259 {
241   - volatile immap_t *immr = (immap_t *)CFG_IMMR;
  260 + volatile immap_t *immr = (immap_t *) CFG_IMMR;
  261 +
  262 + if ((vec & CPMVEC_OFFSET) != 0) {
  263 + /* CPM interrupt */
  264 + vec &= 0xffff;
242 265 #if 0
243   - printf ("Free CPM interrupt for vector %d ==> %p\n",
244   - vec, cpm_vecs[vec].handler);
  266 + printf ("Free CPM interrupt for vector %d ==> %p\n",
  267 + vec, cpm_vecs[vec].handler);
245 268 #endif
246   - immr->im_cpic.cpic_cimr &= ~(1 << vec);
247   - cpm_vecs[vec].handler = NULL;
248   - cpm_vecs[vec].arg = NULL;
  269 + immr->im_cpic.cpic_cimr &= ~(1 << vec);
  270 + cpm_vecs[vec].handler = NULL;
  271 + cpm_vecs[vec].arg = NULL;
  272 + } else {
  273 + /* SIU interrupt */
  274 +#if 0
  275 + printf ("Free CPM interrupt for vector %d ==> %p\n",
  276 + vec, cpm_vecs[vec].handler);
  277 +#endif
  278 + immr->im_siu_conf.sc_simask &= ~(1 << (31 - vec));
  279 + irq_vecs[vec].handler = NULL;
  280 + irq_vecs[vec].arg = NULL;
  281 + }
249 282 }
250 283  
251   -/****************************************************************************/
  284 +/************************************************************************/
252 285  
253   -static void
254   -cpm_interrupt_init (void)
  286 +static void cpm_interrupt_init (void)
255 287 {
256   - volatile immap_t *immr = (immap_t *)CFG_IMMR;
  288 + volatile immap_t *immr = (immap_t *) CFG_IMMR;
257 289  
258 290 /*
259 291 * Initialize the CPM interrupt controller.
260 292 */
261 293  
262 294 immr->im_cpic.cpic_cicr =
263   - ( CICR_SCD_SCC4 |
264   - CICR_SCC_SCC3 |
265   - CICR_SCB_SCC2 |
266   - CICR_SCA_SCC1 ) | ((CPM_INTERRUPT/2) << 13) | CICR_HP_MASK;
  295 + (CICR_SCD_SCC4 |
  296 + CICR_SCC_SCC3 |
  297 + CICR_SCB_SCC2 |
  298 + CICR_SCA_SCC1) | ((CPM_INTERRUPT / 2) << 13) | CICR_HP_MASK;
267 299  
268 300 immr->im_cpic.cpic_cimr = 0;
269 301  
270 302 /*
271 303 * Install the error handler.
272 304 */
273   - irq_install_handler(CPMVEC_ERROR, cpm_error_interrupt, NULL);
  305 + irq_install_handler (CPMVEC_ERROR, cpm_error_interrupt, NULL);
274 306  
275 307 immr->im_cpic.cpic_cicr |= CICR_IEN;
  308 +
  309 + /*
  310 + * Install the cpm interrupt handler
  311 + */
  312 + irq_install_handler (CPM_INTERRUPT, cpm_interrupt, NULL);
276 313 }
277 314  
278   -/****************************************************************************/
  315 +/************************************************************************/
279 316  
280 317 volatile ulong timestamp = 0;
281 318  
282 319  
283 320  
284 321  
... ... @@ -284,18 +321,19 @@
284 321 * with interrupts disabled.
285 322 * Trivial implementation - no need to be really accurate.
286 323 */
287   -void timer_interrupt(struct pt_regs *regs)
  324 +void timer_interrupt (struct pt_regs *regs)
288 325 {
289   - volatile immap_t *immr = (immap_t *)CFG_IMMR;
  326 + volatile immap_t *immr = (immap_t *) CFG_IMMR;
  327 +
290 328 #ifdef CONFIG_STATUS_LED
291   - extern void status_led_tick (ulong);
  329 + extern void status_led_tick (ulong);
292 330 #endif
293 331 #if 0
294 332 printf ("*** Timer Interrupt *** ");
295 333 #endif
296 334 /* Reset Timer Expired and Timers Interrupt Status */
297 335 immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
298   - __asm__("nop");
  336 + __asm__ ("nop");
299 337 immr->im_clkrst.car_plprcr |= PLPRCR_TEXPS | PLPRCR_TMIST;
300 338 /* Restore Decrementer Count */
301 339 set_dec (decrementer_count);
302 340  
... ... @@ -304,11 +342,10 @@
304 342  
305 343 #ifdef CONFIG_STATUS_LED
306 344 status_led_tick (timestamp);
307   -#endif /* CONFIG_STATUS_LED */
  345 +#endif /* CONFIG_STATUS_LED */
308 346  
309 347 #if defined(CONFIG_WATCHDOG) || defined(CFG_CMA_LCD_HEARTBEAT)
310 348  
311   -
312 349 /*
313 350 * The shortest watchdog period of all boards (except LWMON)
314 351 * is approx. 1 sec, thus re-trigger watchdog at least
315 352  
316 353  
317 354  
... ... @@ -321,20 +358,20 @@
321 358 #endif
322 359  
323 360 #if defined(CFG_CMA_LCD_HEARTBEAT)
324   - extern void lcd_heartbeat(void);
325   - lcd_heartbeat();
  361 + extern void lcd_heartbeat (void);
  362 +
  363 + lcd_heartbeat ();
326 364 #endif /* CFG_CMA_LCD_HEARTBEAT */
327 365  
328 366 #if defined(CONFIG_WATCHDOG)
329   - reset_8xx_watchdog(immr);
  367 + reset_8xx_watchdog (immr);
330 368 #endif /* CONFIG_WATCHDOG */
331 369  
332 370 }
333   -
334 371 #endif /* CONFIG_WATCHDOG || CFG_CMA_LCD_HEARTBEAT */
335 372 }
336 373  
337   -/****************************************************************************/
  374 +/************************************************************************/
338 375  
339 376 void reset_timer (void)
340 377 {
... ... @@ -351,5 +388,5 @@
351 388 timestamp = t;
352 389 }
353 390  
354   -/****************************************************************************/
  391 +/************************************************************************/
... ... @@ -285,7 +285,14 @@
285 285 add r11,r11,r0
286 286 lwz r11,0(r11)
287 287  
288   - li r12,0xd00-4*3 /* save LR & SRRx */
  288 + li r20,0xd00-4 /* Get stack pointer */
  289 + lwz r12,0(r20)
  290 + subi r12,r12,12 /* Adjust stack pointer */
  291 + li r0,0xc00+_end_back-SystemCall
  292 + cmplw 0, r0, r12 /* Check stack overflow */
  293 + bgt 1f
  294 + stw r12,0(r20)
  295 +
289 296 mflr r0
290 297 stw r0,0(r12)
291 298 mfspr r0,SRR0
... ... @@ -310,7 +317,9 @@
310 317 mtmsr r11
311 318 SYNC
312 319  
313   - li r12,0xd00-4*3 /* restore regs */
  320 + li r12,0xd00-4 /* restore regs */
  321 + lwz r12,0(r12)
  322 +
314 323 lwz r11,0(r12)
315 324 mtlr r11
316 325 lwz r11,4(r12)
317 326  
... ... @@ -318,8 +327,13 @@
318 327 lwz r11,8(r12)
319 328 mtspr SRR1,r11
320 329  
  330 + addi r12,r12,12 /* Adjust stack pointer */
  331 + li r20,0xd00-4
  332 + stw r12,0(r20)
  333 +
321 334 SYNC
322 335 rfi
  336 +_end_back:
323 337  
324 338 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
325 339  
... ... @@ -775,7 +775,14 @@
775 775 add r11,r11,r0
776 776 lwz r11,0(r11)
777 777  
778   - li r12,0xd00-4*3 /* save LR & SRRx */
  778 + li r20,0xd00-4 /* Get stack pointer */
  779 + lwz r12,0(r20)
  780 + subi r12,r12,12 /* Adjust stack pointer */
  781 + li r0,0xc00+_end_back-SystemCall
  782 + cmplw 0, r0, r12 /* Check stack overflow */
  783 + bgt 1f
  784 + stw r12,0(r20)
  785 +
779 786 mflr r0
780 787 stw r0,0(r12)
781 788 mfspr r0,SRR0
... ... @@ -800,7 +807,9 @@
800 807 mtmsr r11
801 808 SYNC
802 809  
803   - li r12,0xd00-4*3 /* restore regs */
  810 + li r12,0xd00-4 /* restore regs */
  811 + lwz r12,0(r12)
  812 +
804 813 lwz r11,0(r12)
805 814 mtlr r11
806 815 lwz r11,4(r12)
807 816  
... ... @@ -808,8 +817,13 @@
808 817 lwz r11,8(r12)
809 818 mtspr SRR1,r11
810 819  
  820 + addi r12,r12,12 /* Adjust stack pointer */
  821 + li r20,0xd00-4
  822 + stw r12,0(r20)
  823 +
811 824 SYNC
812 825 rfi
  826 +_end_back:
813 827  
814 828 STD_EXCEPTION(0xd00, SingleStep, UnknownException)
815 829  
... ... @@ -122,6 +122,7 @@
122 122 tid_8xx_cpmtimer_t hw;
123 123 tid_8xx_cpmtimer_t *hwp = &hw;
124 124 int c;
  125 + int running;
125 126  
126 127 /* Pointer to CPM Timer structure */
127 128 cpmtimerp = &((immap_t *) gd->bd->bi_immr_base)->im_cpmtimer;
... ... @@ -185,6 +186,7 @@
185 186 *hwp->terp = (CPMT_EVENT_CAP | CPMT_EVENT_REF);
186 187  
187 188 mon_printf (usage);
  189 + running = 0;
188 190 while ((c = mon_getc()) != 'q') {
189 191 if (c == 'b') {
190 192  
... ... @@ -197,6 +199,7 @@
197 199  
198 200 /* enable timer */
199 201 *hwp->tgcrp |= (CPMT_GCR_RST << TID_TIMER_ID);
  202 + running = 1;
200 203  
201 204 #ifdef DEBUG
202 205 mon_printf ("tgcr=0x%x, tmr=0x%x, trr=0x%x,"
... ... @@ -210,6 +213,7 @@
210 213 mon_printf ("Stopping timer\n");
211 214  
212 215 *hwp->tgcrp &= ~(CPMT_GCR_MASK << TID_TIMER_ID);
  216 + running = 0;
213 217  
214 218 #ifdef DEBUG
215 219 mon_printf ("tgcr=0x%x, tmr=0x%x, trr=0x%x,"
... ... @@ -252,6 +256,12 @@
252 256 }
253 257 mon_printf (usage);
254 258 }
  259 + if (running) {
  260 + mon_printf ("Stopping timer\n");
  261 + *hwp->tgcrp &= ~(CPMT_GCR_MASK << TID_TIMER_ID);
  262 + mon_free_hdlr (hwp->cpm_vec);
  263 + }
  264 +
255 265 return (0);
256 266 }
257 267  
... ... @@ -22,10 +22,10 @@
22 22  
23 23 /* CPM Command register.
24 24 */
25   -#define CPM_CR_RST ((ushort)0x8000)
26   -#define CPM_CR_OPCODE ((ushort)0x0f00)
27   -#define CPM_CR_CHAN ((ushort)0x00f0)
28   -#define CPM_CR_FLG ((ushort)0x0001)
  25 +#define CPM_CR_RST ((ushort)0x8000)
  26 +#define CPM_CR_OPCODE ((ushort)0x0f00)
  27 +#define CPM_CR_CHAN ((ushort)0x00f0)
  28 +#define CPM_CR_FLG ((ushort)0x0001)
29 29  
30 30 /* Some commands (there are more...later)
31 31 */
... ... @@ -39,14 +39,14 @@
39 39  
40 40 /* Channel numbers.
41 41 */
42   -#define CPM_CR_CH_SCC1 ((ushort)0x0000)
43   -#define CPM_CR_CH_I2C ((ushort)0x0001) /* I2C and IDMA1 */
44   -#define CPM_CR_CH_SCC2 ((ushort)0x0004)
45   -#define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI / IDMA2 / Timers */
46   -#define CPM_CR_CH_SCC3 ((ushort)0x0008)
47   -#define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / DSP1 */
48   -#define CPM_CR_CH_SCC4 ((ushort)0x000c)
49   -#define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / DSP2 */
  42 +#define CPM_CR_CH_SCC1 ((ushort)0x0000)
  43 +#define CPM_CR_CH_I2C ((ushort)0x0001) /* I2C and IDMA1 */
  44 +#define CPM_CR_CH_SCC2 ((ushort)0x0004)
  45 +#define CPM_CR_CH_SPI ((ushort)0x0005) /* SPI/IDMA2/Timers */
  46 +#define CPM_CR_CH_SCC3 ((ushort)0x0008)
  47 +#define CPM_CR_CH_SMC1 ((ushort)0x0009) /* SMC1 / DSP1 */
  48 +#define CPM_CR_CH_SCC4 ((ushort)0x000c)
  49 +#define CPM_CR_CH_SMC2 ((ushort)0x000d) /* SMC2 / DSP2 */
50 50  
51 51 #define mk_cr_cmd(CH, CMD) ((CMD << 8) | (CH << 4))
52 52  
... ... @@ -523,8 +523,8 @@
523 523 #define PROFF_ENET PROFF_SCC2
524 524 #define CPM_CR_ENET CPM_CR_CH_SCC2
525 525 #define SCC_ENET 1
526   -#define PA_ENET_RXD ((ushort)0x0004)
527   -#define PA_ENET_TXD ((ushort)0x0008)
  526 +#define PA_ENET_RXD ((ushort)0x0004)
  527 +#define PA_ENET_TXD ((ushort)0x0008)
528 528 #define PA_ENET_TCLK ((ushort)0x0100)
529 529 #define PA_ENET_RCLK ((ushort)0x0400)
530 530 #define PB_ENET_TENA ((uint)0x00002000)
531 531  
532 532  
533 533  
... ... @@ -1034,21 +1034,21 @@
1034 1034 #define PROFF_ENET PROFF_SCC2
1035 1035 #define CPM_CR_ENET CPM_CR_CH_SCC2
1036 1036 #define SCC_ENET 1
1037   -#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
1038   -#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
1039   -#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
1040   -#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */
  1037 +#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */
  1038 +#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */
  1039 +#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */
  1040 +#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */
1041 1041  
1042   -#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
  1042 +#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */
1043 1043  
1044   -#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
1045   -#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
  1044 +#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */
  1045 +#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */
1046 1046  
1047 1047 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
1048 1048 * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
1049 1049 */
1050   -#define SICR_ENET_MASK ((uint)0x0000ff00)
1051   -#define SICR_ENET_CLKRT ((uint)0x00002f00)
  1050 +#define SICR_ENET_MASK ((uint)0x0000ff00)
  1051 +#define SICR_ENET_CLKRT ((uint)0x00002f00)
1052 1052  
1053 1053 #endif /* CONFIG_NX823 */
1054 1054  
... ... @@ -1583,35 +1583,36 @@
1583 1583 * priority and SCC1 == SCCa, etc...).
1584 1584 */
1585 1585 #define CPMVEC_NR 32
1586   -#define CPMVEC_PIO_PC15 ((ushort)0x1f)
1587   -#define CPMVEC_SCC1 ((ushort)0x1e)
1588   -#define CPMVEC_SCC2 ((ushort)0x1d)
1589   -#define CPMVEC_SCC3 ((ushort)0x1c)
1590   -#define CPMVEC_SCC4 ((ushort)0x1b)
1591   -#define CPMVEC_PIO_PC14 ((ushort)0x1a)
1592   -#define CPMVEC_TIMER1 ((ushort)0x19)
1593   -#define CPMVEC_PIO_PC13 ((ushort)0x18)
1594   -#define CPMVEC_PIO_PC12 ((ushort)0x17)
1595   -#define CPMVEC_SDMA_CB_ERR ((ushort)0x16)
1596   -#define CPMVEC_IDMA1 ((ushort)0x15)
1597   -#define CPMVEC_IDMA2 ((ushort)0x14)
1598   -#define CPMVEC_TIMER2 ((ushort)0x12)
1599   -#define CPMVEC_RISCTIMER ((ushort)0x11)
1600   -#define CPMVEC_I2C ((ushort)0x10)
1601   -#define CPMVEC_PIO_PC11 ((ushort)0x0f)
1602   -#define CPMVEC_PIO_PC10 ((ushort)0x0e)
1603   -#define CPMVEC_TIMER3 ((ushort)0x0c)
1604   -#define CPMVEC_PIO_PC9 ((ushort)0x0b)
1605   -#define CPMVEC_PIO_PC8 ((ushort)0x0a)
1606   -#define CPMVEC_PIO_PC7 ((ushort)0x09)
1607   -#define CPMVEC_TIMER4 ((ushort)0x07)
1608   -#define CPMVEC_PIO_PC6 ((ushort)0x06)
1609   -#define CPMVEC_SPI ((ushort)0x05)
1610   -#define CPMVEC_SMC1 ((ushort)0x04)
1611   -#define CPMVEC_SMC2 ((ushort)0x03)
1612   -#define CPMVEC_PIO_PC5 ((ushort)0x02)
1613   -#define CPMVEC_PIO_PC4 ((ushort)0x01)
1614   -#define CPMVEC_ERROR ((ushort)0x00)
  1586 +#define CPMVEC_OFFSET 0x00010000
  1587 +#define CPMVEC_PIO_PC15 ((ushort)0x1f | CPMVEC_OFFSET)
  1588 +#define CPMVEC_SCC1 ((ushort)0x1e | CPMVEC_OFFSET)
  1589 +#define CPMVEC_SCC2 ((ushort)0x1d | CPMVEC_OFFSET)
  1590 +#define CPMVEC_SCC3 ((ushort)0x1c | CPMVEC_OFFSET)
  1591 +#define CPMVEC_SCC4 ((ushort)0x1b | CPMVEC_OFFSET)
  1592 +#define CPMVEC_PIO_PC14 ((ushort)0x1a | CPMVEC_OFFSET)
  1593 +#define CPMVEC_TIMER1 ((ushort)0x19 | CPMVEC_OFFSET)
  1594 +#define CPMVEC_PIO_PC13 ((ushort)0x18 | CPMVEC_OFFSET)
  1595 +#define CPMVEC_PIO_PC12 ((ushort)0x17 | CPMVEC_OFFSET)
  1596 +#define CPMVEC_SDMA_CB_ERR ((ushort)0x16 | CPMVEC_OFFSET)
  1597 +#define CPMVEC_IDMA1 ((ushort)0x15 | CPMVEC_OFFSET)
  1598 +#define CPMVEC_IDMA2 ((ushort)0x14 | CPMVEC_OFFSET)
  1599 +#define CPMVEC_TIMER2 ((ushort)0x12 | CPMVEC_OFFSET)
  1600 +#define CPMVEC_RISCTIMER ((ushort)0x11 | CPMVEC_OFFSET)
  1601 +#define CPMVEC_I2C ((ushort)0x10 | CPMVEC_OFFSET)
  1602 +#define CPMVEC_PIO_PC11 ((ushort)0x0f | CPMVEC_OFFSET)
  1603 +#define CPMVEC_PIO_PC10 ((ushort)0x0e | CPMVEC_OFFSET)
  1604 +#define CPMVEC_TIMER3 ((ushort)0x0c | CPMVEC_OFFSET)
  1605 +#define CPMVEC_PIO_PC9 ((ushort)0x0b | CPMVEC_OFFSET)
  1606 +#define CPMVEC_PIO_PC8 ((ushort)0x0a | CPMVEC_OFFSET)
  1607 +#define CPMVEC_PIO_PC7 ((ushort)0x09 | CPMVEC_OFFSET)
  1608 +#define CPMVEC_TIMER4 ((ushort)0x07 | CPMVEC_OFFSET)
  1609 +#define CPMVEC_PIO_PC6 ((ushort)0x06 | CPMVEC_OFFSET)
  1610 +#define CPMVEC_SPI ((ushort)0x05 | CPMVEC_OFFSET)
  1611 +#define CPMVEC_SMC1 ((ushort)0x04 | CPMVEC_OFFSET)
  1612 +#define CPMVEC_SMC2 ((ushort)0x03 | CPMVEC_OFFSET)
  1613 +#define CPMVEC_PIO_PC5 ((ushort)0x02 | CPMVEC_OFFSET)
  1614 +#define CPMVEC_PIO_PC4 ((ushort)0x01 | CPMVEC_OFFSET)
  1615 +#define CPMVEC_ERROR ((ushort)0x00 | CPMVEC_OFFSET)
1615 1616  
1616 1617 extern void irq_install_handler(int vec, void (*handler)(void *), void *dev_id);
1617 1618  
include/configs/AmigaOneG3SE.h
Diff comments   View file @ 7c7a23b
... ... @@ -93,7 +93,7 @@
93 93 * Miscellaneous configurable options
94 94 */
95 95 #define CFG_LONGHELP /* undef to save memory */
96   -#define CFG_PROMPT "=> " /* Monitor Command Prompt */
  96 +#define CFG_PROMPT "] " /* Monitor Command Prompt */
97 97  
98 98 #define CFG_HUSH_PARSER 1 /* use "hush" command parser */
99 99 /* #undef CFG_HUSH_PARSER */
... ... @@ -145,7 +145,8 @@
145 145  
146 146 /* Size in bytes reserved for initial data
147 147 */
148   -#define CFG_INIT_RAM_ADDR 0x400000
  148 +/* HJF: used to be 0x400000 */
  149 +#define CFG_INIT_RAM_ADDR 0x40000000
149 150 #define CFG_INIT_RAM_END 0x8000
150 151 #define CFG_GBL_DATA_SIZE 128
151 152 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
152 153  
153 154  
154 155  
155 156  
156 157  
157 158  
158 159  
... ... @@ -163,25 +164,38 @@
163 164 /* SDRAM 0 - 256MB
164 165 */
165 166  
166   -#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
  167 +/*HJF: #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
167 168 #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_4M | BATU_VS | BATU_VP)
168 169 #define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
169   -#define CFG_DBAT0U CFG_IBAT0U
  170 +#define CFG_DBAT0U CFG_IBAT0U*/
170 171  
171   -/* SDRAM 1 - 256MB
  172 +#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
  173 +#define CFG_DBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
  174 +#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
  175 +#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
  176 +/* PCI Range
172 177 */
173   -#define CFG_IBAT1L ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR) | BATL_PP_RW) /* | BATL_CACHEINHIBIT) */
  178 +#define CFG_DBAT1L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
  179 +#define CFG_DBAT1U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
  180 +#define CFG_IBAT1L (0x80000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
  181 +#define CFG_IBAT1U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
  182 +/* HJF:
  183 +#define CFG_IBAT1L ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR) | BATL_PP_RW)
174 184 #define CFG_IBAT1U ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR) | BATU_BL_256M | BATU_VS | BATU_VP)
175   -#define CFG_DBAT1L ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR + 0x20000) | BATL_PP_RW ) /* | BATL_CACHEINHIBIT) */
  185 +#define CFG_DBAT1L ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR + 0x20000) | BATL_PP_RW )
176 186 #define CFG_DBAT1U ((CFG_SDRAM_BASE+CFG_INIT_RAM_ADDR + 0x20000) | BATU_BL_256M | BATU_VS | BATU_VP)
  187 +*/
177 188  
178 189 /* Init RAM in the CPU DCache (no backing memory)
179 190 */
180 191 #define CFG_DBAT2L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
181 192 #define CFG_DBAT2U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
182   -#define CFG_IBAT2L 0 /* CFG_DBAT2L */
183   -#define CFG_IBAT2U 0 /* CFG_DBAT2U */
  193 +/* This used to be commented out */
  194 +#define CFG_IBAT2L CFG_DBAT2L
  195 +/* This here too */
  196 +#define CFG_IBAT2U CFG_DBAT2U
184 197  
  198 +
185 199 /* I/O and PCI memory at 0xf0000000
186 200 */
187 201 #define CFG_DBAT3L (0xf0000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
... ... @@ -372,7 +386,7 @@
372 386 "pci_irqb_select=edge\0" \
373 387 "pci_irqc=11\0" \
374 388 "pci_irqc_select=edge\0" \
375   - "pci_irqd=12\0" \" \
  389 + "pci_irqd=7\0" \" \
376 390 "pci_irqd_select=edge\0"
377 391  
378 392  
... ... @@ -161,6 +161,11 @@
161 161 *addr++ |= NR_SYSCALLS & 0xFFFF;
162 162  
163 163 flush_cache (0x0C00, 0x10);
  164 +
  165 + /* Initialize syscalls stack pointer */
  166 + addr = (ulong *) 0xCFC;
  167 + *addr = (ulong)addr;
  168 + flush_cache ((ulong)addr, 0x10);
164 169 }
165 170  
166 171 /*