Eric Lee / smarc-uboot

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Commit 7d2a0534a6a4a4b92a58098f484f9e172149b784

Authored by Stefan Roese
Committed by Bin Meng
1 parent 24a72511e7
Exists in smarc_8mq_lf_v2020.04 and in 12 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, emb_lf_v2023.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

x86: BayTrail: southcluster.asl: Change PCI 64 bit address range / region 

To allow bigger 64 bit prefetchable PCI regions in Linux, this patch
changes the base address and range of the ACPI area passed to Linux.
BayTrail can only physically access 36 bit of PCI address space. So
just chaning the range without changing the base address won't work
here, as 0xf.ffff.ffff is already the maximum address.

With this patch, a maximum of 16 GiB of local DDR is supported. This
should be enough for all BayTrail boards though.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Showing 1 changed file with 3 additions and 3 deletions Side-by-side Diff

arch/x86/include/asm/arch-baytrail/acpi/southcluster.asl
Diff comments   View file @ 7d2a053
... ... @@ -150,9 +150,9 @@
150 150 CreateQwordField(MCRS, ^UMEM._MAX, UMAX)
151 151 CreateQwordField(MCRS, ^UMEM._LEN, ULEN)
152 152  
153   - /* Set base address to 48GB and allocate 16GB for PCI space */
154   - Store(0xc00000000, UMIN)
155   - Store(0x400000000, ULEN)
  153 + /* Set base address to 16GB and allocate 48GB for PCI space */
  154 + Store(0x400000000, UMIN)
  155 + Store(0xc00000000, ULEN)
156 156 Add(UMIN, Subtract(ULEN, 1), UMAX)
157 157  
158 158 Return (MCRS)