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Commit 7d30793685efcada183891c78fc892e6c9ba50c7

Authored by Feng Kan
Committed by Stefan Roese
1 parent 9b55a25369
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

ppc4xx: Add initial 460SX defines for the cpu/ppc4xx directory. 

Signed-off-by: Feng Kan <fkan@amcc.com>
Signed-off-by: Stefan Roese <sr@denx.de>

Showing 4 changed files with 54 additions and 4 deletions Side-by-side Diff

cpu/ppc4xx/44x_spd_ddr2.c
Diff comments   View file @ 7d30793
... ... @@ -52,7 +52,8 @@
52 52  
53 53 #if defined(CONFIG_SPD_EEPROM) && \
54 54 (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
55   - defined(CONFIG_460EX) || defined(CONFIG_460GT))
  55 + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
  56 + defined(CONFIG_460SX))
56 57  
57 58 /*-----------------------------------------------------------------------------+
58 59 * Defines
... ... @@ -184,6 +184,19 @@
184 184 static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G', 'F', 'H' };
185 185 #endif
186 186  
  187 +#if defined(CONFIG_460SX)
  188 +#define SDR0_PINSTP_SHIFT 29
  189 +static char *bootstrap_str[] = {
  190 + "EBC (8 bits)",
  191 + "EBC (16 bits)",
  192 + "EBC (32 bits)",
  193 + "NAND (8 bits)",
  194 + "I2C (Addr 0x54)", /* A8 */
  195 + "I2C (Addr 0x52)", /* A4 */
  196 +};
  197 +static char bootstrap_char[] = { 'A', 'B', 'C', 'D', 'E', 'G' };
  198 +#endif
  199 +
187 200 #if defined(CONFIG_405EZ)
188 201 #define SDR0_PINSTP_SHIFT 28
189 202 static char *bootstrap_str[] = {
... ... @@ -507,6 +520,26 @@
507 520 case PVR_460GT_SE_RA:
508 521 puts("GT Rev. A");
509 522 strcpy(addstr, "Security/Kasumi support");
  523 + break;
  524 +
  525 + case PVR_460SX_RA:
  526 + puts("SX Rev. A");
  527 + strcpy(addstr, "Security support");
  528 + break;
  529 +
  530 + case PVR_460SX_RA_V1:
  531 + puts("SX Rev. A");
  532 + strcpy(addstr, "No Security support");
  533 + break;
  534 +
  535 + case PVR_460GX_RA:
  536 + puts("GX Rev. A");
  537 + strcpy(addstr, "Security support");
  538 + break;
  539 +
  540 + case PVR_460GX_RA_V1:
  541 + puts("GX Rev. A");
  542 + strcpy(addstr, "No Security support");
510 543 break;
511 544  
512 545 default:
... ... @@ -205,7 +205,8 @@
205 205  
206 206 #elif defined(CONFIG_440)
207 207  
208   -#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
  208 +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
  209 + defined(CONFIG_460SX)
209 210 static u8 pll_fwdv_multi_bits[] = {
210 211 /* values for: 1 - 16 */
211 212 0x00, 0x01, 0x0f, 0x04, 0x09, 0x0a, 0x0d, 0x0e, 0x03, 0x0c,
... ... @@ -677,7 +677,8 @@
677 677 /* not all PPC's have internal SRAM usable as L2-cache */
678 678 #if defined(CONFIG_440GX) || \
679 679 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
680   - defined(CONFIG_460EX) || defined(CONFIG_460GT)
  680 + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
  681 + defined(CONFIG_460SX)
681 682 mtdcr l2_cache_cfg,r0 /* Ensure L2 Cache is off */
682 683 #endif
683 684  
... ... @@ -720,6 +721,19 @@
720 721 lis r1,0x4000 /* BAS = 8000_0000 */
721 722 ori r1,r1,0x4580 /* 16k */
722 723 mtdcr isram0_sb0cr,r1
  724 +#elif defined(CONFIG_460SX)
  725 + lis r1,0x0000 /* BAS = 0000_0000 */
  726 + ori r1,r1,0x0B84 /* first 128k */
  727 + mtdcr isram0_sb0cr,r1
  728 + lis r1,0x0001
  729 + ori r1,r1,0x0B84 /* second 128k */
  730 + mtdcr isram0_sb1cr,r1
  731 + lis r1, 0x0002
  732 + ori r1,r1, 0x0B84 /* third 128k */
  733 + mtdcr isram0_sb2cr,r1
  734 + lis r1, 0x0003
  735 + ori r1,r1, 0x0B84 /* fourth 128k */
  736 + mtdcr isram0_sb3cr,r1
723 737 #elif defined(CONFIG_440GP)
724 738 ori r1,r1,0x0380 /* 8k rw */
725 739 mtdcr isram0_sb0cr,r1
... ... @@ -1415,7 +1429,8 @@
1415 1429 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
1416 1430 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1417 1431 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
1418   - defined(CONFIG_460EX) || defined(CONFIG_460GT)
  1432 + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
  1433 + defined(CONFIG_460SX)
1419 1434 /*
1420 1435 * On some 440er platforms the cache is enabled in the first TLB (Boot-CS)
1421 1436 * to speed up the boot process. Now this cache needs to be disabled.