ARM: Tegra: USB: EHCI: Add support for Tegra30/Tegra114

Tegra30 and Tegra114 are compatible except PLL parameters. Tested on Tegra30 Cardhu, and Tegra114 Dalmore platforms. All works well. Signed-off-by: Jim Lin <jilin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>

ARM: Tegra: USB: EHCI: Add support for Tegra30/Tegra114
Tegra30 and Tegra114 are compatible except PLL parameters. Tested on Tegra30 Cardhu, and Tegra114 Dalmore platforms. All works well. Signed-off-by: Jim Lin <jilin@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Jim Lin · Tom Warren · Eric Lee · Eric Lee · Eric Lee · Eric Lee
1 parent 56867d88c4
Showing 9 changed files with 805 additions and 175 deletions Side-by-side Diff
arch/arm/include/asm/arch-tegra/clk_rst.h
arch/arm/include/asm/arch-tegra/usb.h
arch/arm/include/asm/arch-tegra114/usb.h
arch/arm/include/asm/arch-tegra20/usb.h
arch/arm/include/asm/arch-tegra30/usb.h
board/nvidia/common/board.c
drivers/usb/host/ehci-tegra.c
include/fdtdec.h
lib/fdtdec.c
@@ -225,6 +225,16 @@
 	IN_408_OUT_9_6_DIVISOR = 83,
 };
  
+/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0 */
+#define PLLU_POWERDOWN		(1 << 16)
+#define PLL_ENABLE_POWERDOWN	(1 << 14)
+#define PLL_ACTIVE_POWERDOWN	(1 << 12)
+
+/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0 */
+#define UTMIP_FORCE_PD_SAMP_C_POWERDOWN		(1 << 4)
+#define UTMIP_FORCE_PD_SAMP_B_POWERDOWN		(1 << 2)
+#define UTMIP_FORCE_PD_SAMP_A_POWERDOWN		(1 << 0)
+
 /* CLK_RST_CONTROLLER_OSC_CTRL_0 */
 #define OSC_XOBP_SHIFT		1
 #define OSC_XOBP_MASK		(1U << OSC_XOBP_SHIFT)
 /*
  * Copyright (c) 2011 The Chromium OS Authors.
+ * Copyright (c) 2013 NVIDIA Corporation
  * See file CREDITS for list of people who contributed to this
  * project.
  *
@@ -22,120 +23,6 @@
 #ifndef _TEGRA_USB_H_
 #define _TEGRA_USB_H_
  
-
-/* USB Controller (USBx_CONTROLLER_) regs */
-struct usb_ctlr {
-	/* 0x000 */
-	uint id;
-	uint reserved0;
-	uint host;
-	uint device;
-
-	/* 0x010 */
-	uint txbuf;
-	uint rxbuf;
-	uint reserved1[2];
-
-	/* 0x020 */
-	uint reserved2[56];
-
-	/* 0x100 */
-	u16 cap_length;
-	u16 hci_version;
-	uint hcs_params;
-	uint hcc_params;
-	uint reserved3[5];
-
-	/* 0x120 */
-	uint dci_version;
-	uint dcc_params;
-	uint reserved4[6];
-
-	/* 0x140 */
-	uint usb_cmd;
-	uint usb_sts;
-	uint usb_intr;
-	uint frindex;
-
-	/* 0x150 */
-	uint reserved5;
-	uint periodic_list_base;
-	uint async_list_addr;
-	uint async_tt_sts;
-
-	/* 0x160 */
-	uint burst_size;
-	uint tx_fill_tuning;
-	uint reserved6;   /* is this port_sc1 on some controllers? */
-	uint icusb_ctrl;
-
-	/* 0x170 */
-	uint ulpi_viewport;
-	uint reserved7;
-	uint endpt_nak;
-	uint endpt_nak_enable;
-
-	/* 0x180 */
-	uint reserved;
-	uint port_sc1;
-	uint reserved8[6];
-
-	/* 0x1a0 */
-	uint reserved9;
-	uint otgsc;
-	uint usb_mode;
-	uint endpt_setup_stat;
-
-	/* 0x1b0 */
-	uint reserved10[20];
-
-	/* 0x200 */
-	uint reserved11[0x80];
-
-	/* 0x400 */
-	uint susp_ctrl;
-	uint phy_vbus_sensors;
-	uint phy_vbus_wakeup_id;
-	uint phy_alt_vbus_sys;
-
-	/* 0x410 */
-	uint usb1_legacy_ctrl;
-	uint reserved12[4];
-
-	/* 0x424 */
-	uint ulpi_timing_ctrl_0;
-	uint ulpi_timing_ctrl_1;
-	uint reserved13[53];
-
-	/* 0x500 */
-	uint reserved14[64 * 3];
-
-	/* 0x800 */
-	uint utmip_pll_cfg0;
-	uint utmip_pll_cfg1;
-	uint utmip_xcvr_cfg0;
-	uint utmip_bias_cfg0;
-
-	/* 0x810 */
-	uint utmip_hsrx_cfg0;
-	uint utmip_hsrx_cfg1;
-	uint utmip_fslsrx_cfg0;
-	uint utmip_fslsrx_cfg1;
-
-	/* 0x820 */
-	uint utmip_tx_cfg0;
-	uint utmip_misc_cfg0;
-	uint utmip_misc_cfg1;
-	uint utmip_debounce_cfg0;
-
-	/* 0x830 */
-	uint utmip_bat_chrg_cfg0;
-	uint utmip_spare_cfg0;
-	uint utmip_xcvr_cfg1;
-	uint utmip_bias_cfg1;
-};
-
-
 /* USB1_LEGACY_CTRL */
 #define USB1_NO_LEGACY_MODE		1
  
  
  
@@ -146,25 +33,18 @@
 #define VBUS_SENSE_CTL_AB_SESS_VLD		2
 #define VBUS_SENSE_CTL_A_SESS_VLD		3
  
-/* USB2_IF_ULPI_TIMING_CTRL_0 */
-#define ULPI_OUTPUT_PINMUX_BYP			(1 << 10)
-#define ULPI_CLKOUT_PINMUX_BYP			(1 << 11)
-
-/* USB2_IF_ULPI_TIMING_CTRL_1 */
-#define ULPI_DATA_TRIMMER_LOAD			(1 << 0)
-#define ULPI_DATA_TRIMMER_SEL(x)		(((x) & 0x7) << 1)
-#define ULPI_STPDIRNXT_TRIMMER_LOAD		(1 << 16)
-#define ULPI_STPDIRNXT_TRIMMER_SEL(x)	(((x) & 0x7) << 17)
-#define ULPI_DIR_TRIMMER_LOAD			(1 << 24)
-#define ULPI_DIR_TRIMMER_SEL(x)			(((x) & 0x7) << 25)
-
 /* USBx_IF_USB_SUSP_CTRL_0 */
-#define ULPI_PHY_ENB				(1 << 13)
 #define UTMIP_PHY_ENB			        (1 << 12)
 #define UTMIP_RESET			        (1 << 11)
 #define USB_PHY_CLK_VALID			(1 << 7)
 #define USB_SUSP_CLR				(1 << 5)
  
+/* USB2_IF_USB_SUSP_CTRL_0 */
+#define ULPI_PHY_ENB				(1 << 13)
+
+/* USBx_UTMIP_MISC_CFG0 */
+#define UTMIP_SUSPEND_EXIT_ON_EDGE		(1 << 22)
+
 /* USBx_UTMIP_MISC_CFG1 */
 #define UTMIP_PLLU_STABLE_COUNT_SHIFT		6
 #define UTMIP_PLLU_STABLE_COUNT_MASK		\
  
  
  
@@ -177,15 +57,28 @@
 /* USBx_UTMIP_PLL_CFG1_0 */
 #define UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT	27
 #define UTMIP_PLLU_ENABLE_DLY_COUNT_MASK	\
-				(0xf << UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT)
+				(0x1f << UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT)
 #define UTMIP_XTAL_FREQ_COUNT_SHIFT		0
 #define UTMIP_XTAL_FREQ_COUNT_MASK		0xfff
  
+/* USBx_UTMIP_BIAS_CFG0_0 */
+#define UTMIP_HSDISCON_LEVEL_MSB		(1 << 24)
+#define UTMIP_OTGPD				(1 << 11)
+#define UTMIP_BIASPD				(1 << 10)
+#define UTMIP_HSDISCON_LEVEL_SHIFT		2
+#define UTMIP_HSDISCON_LEVEL_MASK		\
+				(0x3 << UTMIP_HSDISCON_LEVEL_SHIFT)
+#define UTMIP_HSSQUELCH_LEVEL_SHIFT		0
+#define UTMIP_HSSQUELCH_LEVEL_MASK		\
+				(0x3 << UTMIP_HSSQUELCH_LEVEL_SHIFT)
+
 /* USBx_UTMIP_BIAS_CFG1_0 */
+#define UTMIP_FORCE_PDTRK_POWERDOWN		1
 #define UTMIP_BIAS_PDTRK_COUNT_SHIFT		3
 #define UTMIP_BIAS_PDTRK_COUNT_MASK		\
 				(0x1f << UTMIP_BIAS_PDTRK_COUNT_SHIFT)
  
+/* USBx_UTMIP_DEBOUNCE_CFG0_0 */
 #define UTMIP_DEBOUNCE_CFG0_SHIFT		0
 #define UTMIP_DEBOUNCE_CFG0_MASK		0xffff
  
@@ -195,9 +88,6 @@
 /* USBx_UTMIP_BAT_CHRG_CFG0_0 */
 #define UTMIP_PD_CHRG				1
  
-/* USBx_UTMIP_XCVR_CFG0_0 */
-#define UTMIP_XCVR_LSBIAS_SE			(1 << 21)
-
 /* USBx_UTMIP_SPARE_CFG0_0 */
 #define FUSE_SETUP_SEL				(1 << 3)
  
  
  
  
  
  
@@ -208,23 +98,26 @@
 #define UTMIP_ELASTIC_LIMIT_MASK		\
 				(0x1f << UTMIP_ELASTIC_LIMIT_SHIFT)
  
-/* USBx_UTMIP_HSRX_CFG0_1 */
+/* USBx_UTMIP_HSRX_CFG1_0 */
 #define UTMIP_HS_SYNC_START_DLY_SHIFT		1
 #define UTMIP_HS_SYNC_START_DLY_MASK		\
-				(0xf << UTMIP_HS_SYNC_START_DLY_SHIFT)
+				(0x1f << UTMIP_HS_SYNC_START_DLY_SHIFT)
  
 /* USBx_CONTROLLER_2_USB2D_ICUSB_CTRL_0 */
 #define IC_ENB1					(1 << 3)
  
-/* SB2_CONTROLLER_2_USB2D_PORTSC1_0 */
-#define PTS_SHIFT				30
-#define PTS_MASK				(3U << PTS_SHIFT)
-#define PTS_UTMI		0
+/* PORTSC1, USB1, defined for Tegra20 */
+#define PTS1_SHIFT				31
+#define PTS1_MASK				(1 << PTS1_SHIFT)
+#define STS1					(1 << 30)
+
+#define PTS_UTMI	0
 #define PTS_RESERVED	1
-#define PTS_ULPI		2
+#define PTS_ULPI	2
 #define PTS_ICUSB_SER	3
+#define PTS_HSIC	4
  
-#define STS					(1 << 29)
+/* SB2_CONTROLLER_2_USB2D_PORTSC1_0 */
 #define WKOC				(1 << 22)
 #define WKDS				(1 << 21)
 #define WKCN				(1 << 20)
  
@@ -233,8 +126,19 @@
 #define UTMIP_FORCE_PD_POWERDOWN		(1 << 14)
 #define UTMIP_FORCE_PD2_POWERDOWN		(1 << 16)
 #define UTMIP_FORCE_PDZI_POWERDOWN		(1 << 18)
+#define UTMIP_XCVR_LSBIAS_SE			(1 << 21)
+#define UTMIP_XCVR_HSSLEW_MSB_SHIFT		25
+#define UTMIP_XCVR_HSSLEW_MSB_MASK		\
+			(0x7f << UTMIP_XCVR_HSSLEW_MSB_SHIFT)
+#define UTMIP_XCVR_SETUP_MSB_SHIFT	22
+#define UTMIP_XCVR_SETUP_MSB_MASK	(0x7 << UTMIP_XCVR_SETUP_MSB_SHIFT)
+#define UTMIP_XCVR_SETUP_SHIFT		0
+#define UTMIP_XCVR_SETUP_MASK		(0xf << UTMIP_XCVR_SETUP_SHIFT)
  
 /* USBx_UTMIP_XCVR_CFG1_0 */
+#define UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT		18
+#define UTMIP_XCVR_TERM_RANGE_ADJ_MASK		\
+			(0xf << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT)
 #define UTMIP_FORCE_PDDISC_POWERDOWN		(1 << 0)
 #define UTMIP_FORCE_PDCHRP_POWERDOWN		(1 << 2)
 #define UTMIP_FORCE_PDDR_POWERDOWN		(1 << 4)
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * Copyright (c) 2013 NVIDIA Corporation
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _TEGRA114_USB_H_
+#define _TEGRA114_USB_H_
+
+/* USB Controller (USBx_CONTROLLER_) regs */
+struct usb_ctlr {
+	/* 0x000 */
+	uint id;
+	uint reserved0;
+	uint host;
+	uint device;
+
+	/* 0x010 */
+	uint txbuf;
+	uint rxbuf;
+	uint reserved1[2];
+
+	/* 0x020 */
+	uint reserved2[56];
+
+	/* 0x100 */
+	u16 cap_length;
+	u16 hci_version;
+	uint hcs_params;
+	uint hcc_params;
+	uint reserved3[5];
+
+	/* 0x120 */
+	uint dci_version;
+	uint dcc_params;
+	uint reserved4[2];
+
+	/* 0x130 */
+	uint usb_cmd;
+	uint usb_sts;
+	uint usb_intr;
+	uint frindex;
+
+	/* 0x140 */
+	uint reserved5;
+	uint periodic_list_base;
+	uint async_list_addr;
+	uint reserved5_1;
+
+	/* 0x150 */
+	uint burst_size;
+	uint tx_fill_tuning;
+	uint reserved6;
+	uint icusb_ctrl;
+
+	/* 0x160 */
+	uint ulpi_viewport;
+	uint reserved7[3];
+
+	/* 0x170 */
+	uint reserved;
+	uint port_sc1;
+	uint reserved8[6];
+
+	/* 0x190 */
+	uint reserved9[8];
+
+	/* 0x1b0 */
+	uint reserved10;
+	uint hostpc1_devlc;
+	uint reserved10_1[2];
+
+	/* 0x1c0 */
+	uint reserved10_2[4];
+
+	/* 0x1d0 */
+	uint reserved10_3[4];
+
+	/* 0x1e0 */
+	uint reserved10_4[4];
+
+	/* 0x1f0 */
+	uint reserved10_5;
+	uint otgsc;
+	uint usb_mode;
+	uint reserved10_6;
+
+	/* 0x200 */
+	uint endpt_nak;
+	uint endpt_nak_enable;
+	uint endpt_setup_stat;
+	uint reserved11_1[0x7D];
+
+	/* 0x400 */
+	uint susp_ctrl;
+	uint phy_vbus_sensors;
+	uint phy_vbus_wakeup_id;
+	uint phy_alt_vbus_sys;
+
+	/* 0x410 */
+	uint usb1_legacy_ctrl;
+	uint reserved12[3];
+
+	/* 0x420 */
+	uint reserved13[56];
+
+	/* 0x500 */
+	uint reserved14[64 * 3];
+
+	/* 0x800 */
+	uint utmip_pll_cfg0;
+	uint utmip_pll_cfg1;
+	uint utmip_xcvr_cfg0;
+	uint utmip_bias_cfg0;
+
+	/* 0x810 */
+	uint utmip_hsrx_cfg0;
+	uint utmip_hsrx_cfg1;
+	uint utmip_fslsrx_cfg0;
+	uint utmip_fslsrx_cfg1;
+
+	/* 0x820 */
+	uint utmip_tx_cfg0;
+	uint utmip_misc_cfg0;
+	uint utmip_misc_cfg1;
+	uint utmip_debounce_cfg0;
+
+	/* 0x830 */
+	uint utmip_bat_chrg_cfg0;
+	uint utmip_spare_cfg0;
+	uint utmip_xcvr_cfg1;
+	uint utmip_bias_cfg1;
+};
+
+/* USB2D_HOSTPC1_DEVLC_0 */
+#define PTS_SHIFT				29
+#define PTS_MASK				(0x7U << PTS_SHIFT)
+
+#define STS					(1 << 28)
+#endif /* _TEGRA114_USB_H_ */
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * Copyright (c) 2013 NVIDIA Corporation
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _TEGRA20_USB_H_
+#define _TEGRA20_USB_H_
+
+/* USB Controller (USBx_CONTROLLER_) regs */
+struct usb_ctlr {
+	/* 0x000 */
+	uint id;
+	uint reserved0;
+	uint host;
+	uint device;
+
+	/* 0x010 */
+	uint txbuf;
+	uint rxbuf;
+	uint reserved1[2];
+
+	/* 0x020 */
+	uint reserved2[56];
+
+	/* 0x100 */
+	u16 cap_length;
+	u16 hci_version;
+	uint hcs_params;
+	uint hcc_params;
+	uint reserved3[5];
+
+	/* 0x120 */
+	uint dci_version;
+	uint dcc_params;
+	uint reserved4[6];
+
+	/* 0x140 */
+	uint usb_cmd;
+	uint usb_sts;
+	uint usb_intr;
+	uint frindex;
+
+	/* 0x150 */
+	uint reserved5;
+	uint periodic_list_base;
+	uint async_list_addr;
+	uint async_tt_sts;
+
+	/* 0x160 */
+	uint burst_size;
+	uint tx_fill_tuning;
+	uint reserved6;   /* is this port_sc1 on some controllers? */
+	uint icusb_ctrl;
+
+	/* 0x170 */
+	uint ulpi_viewport;
+	uint reserved7;
+	uint endpt_nak;
+	uint endpt_nak_enable;
+
+	/* 0x180 */
+	uint reserved;
+	uint port_sc1;
+	uint reserved8[6];
+
+	/* 0x1a0 */
+	uint reserved9;
+	uint otgsc;
+	uint usb_mode;
+	uint endpt_setup_stat;
+
+	/* 0x1b0 */
+	uint reserved10[20];
+
+	/* 0x200 */
+	uint reserved11[0x80];
+
+	/* 0x400 */
+	uint susp_ctrl;
+	uint phy_vbus_sensors;
+	uint phy_vbus_wakeup_id;
+	uint phy_alt_vbus_sys;
+
+	/* 0x410 */
+	uint usb1_legacy_ctrl;
+	uint reserved12[4];
+
+	/* 0x424 */
+	uint ulpi_timing_ctrl_0;
+	uint ulpi_timing_ctrl_1;
+	uint reserved13[53];
+
+	/* 0x500 */
+	uint reserved14[64 * 3];
+
+	/* 0x800 */
+	uint utmip_pll_cfg0;
+	uint utmip_pll_cfg1;
+	uint utmip_xcvr_cfg0;
+	uint utmip_bias_cfg0;
+
+	/* 0x810 */
+	uint utmip_hsrx_cfg0;
+	uint utmip_hsrx_cfg1;
+	uint utmip_fslsrx_cfg0;
+	uint utmip_fslsrx_cfg1;
+
+	/* 0x820 */
+	uint utmip_tx_cfg0;
+	uint utmip_misc_cfg0;
+	uint utmip_misc_cfg1;
+	uint utmip_debounce_cfg0;
+
+	/* 0x830 */
+	uint utmip_bat_chrg_cfg0;
+	uint utmip_spare_cfg0;
+	uint utmip_xcvr_cfg1;
+	uint utmip_bias_cfg1;
+};
+
+/* USB2_IF_ULPI_TIMING_CTRL_0 */
+#define ULPI_OUTPUT_PINMUX_BYP			(1 << 10)
+#define ULPI_CLKOUT_PINMUX_BYP			(1 << 11)
+
+/* USB2_IF_ULPI_TIMING_CTRL_1 */
+#define ULPI_DATA_TRIMMER_LOAD			(1 << 0)
+#define ULPI_DATA_TRIMMER_SEL(x)		(((x) & 0x7) << 1)
+#define ULPI_STPDIRNXT_TRIMMER_LOAD		(1 << 16)
+#define ULPI_STPDIRNXT_TRIMMER_SEL(x)	(((x) & 0x7) << 17)
+#define ULPI_DIR_TRIMMER_LOAD			(1 << 24)
+#define ULPI_DIR_TRIMMER_SEL(x)			(((x) & 0x7) << 25)
+
+/* PORTSC, USB2, USB3 */
+#define PTS_SHIFT		30
+#define PTS_MASK		(3U << PTS_SHIFT)
+
+#define STS			(1 << 29)
+#endif /* _TEGRA20_USB_H_ */
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * Copyright (c) 2013 NVIDIA Corporation
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _TEGRA30_USB_H_
+#define _TEGRA30_USB_H_
+
+/* USB Controller (USBx_CONTROLLER_) regs */
+struct usb_ctlr {
+	/* 0x000 */
+	uint id;
+	uint reserved0;
+	uint host;
+	uint device;
+
+	/* 0x010 */
+	uint txbuf;
+	uint rxbuf;
+	uint reserved1[2];
+
+	/* 0x020 */
+	uint reserved2[56];
+
+	/* 0x100 */
+	u16 cap_length;
+	u16 hci_version;
+	uint hcs_params;
+	uint hcc_params;
+	uint reserved3[5];
+
+	/* 0x120 */
+	uint dci_version;
+	uint dcc_params;
+	uint reserved4[2];
+
+	/* 0x130 */
+	uint usb_cmd;
+	uint usb_sts;
+	uint usb_intr;
+	uint frindex;
+
+	/* 0x140 */
+	uint reserved5;
+	uint periodic_list_base;
+	uint async_list_addr;
+	uint reserved5_1;
+
+	/* 0x150 */
+	uint burst_size;
+	uint tx_fill_tuning;
+	uint reserved6;
+	uint icusb_ctrl;
+
+	/* 0x160 */
+	uint ulpi_viewport;
+	uint reserved7[3];
+
+	/* 0x170 */
+	uint reserved;
+	uint port_sc1;
+	uint reserved8[6];
+
+	/* 0x190 */
+	uint reserved9[8];
+
+	/* 0x1b0 */
+	uint reserved10;
+	uint hostpc1_devlc;
+	uint reserved10_1[2];
+
+	/* 0x1c0 */
+	uint reserved10_2[4];
+
+	/* 0x1d0 */
+	uint reserved10_3[4];
+
+	/* 0x1e0 */
+	uint reserved10_4[4];
+
+	/* 0x1f0 */
+	uint reserved10_5;
+	uint otgsc;
+	uint usb_mode;
+	uint reserved10_6;
+
+	/* 0x200 */
+	uint endpt_nak;
+	uint endpt_nak_enable;
+	uint endpt_setup_stat;
+	uint reserved11_1[0x7D];
+
+	/* 0x400 */
+	uint susp_ctrl;
+	uint phy_vbus_sensors;
+	uint phy_vbus_wakeup_id;
+	uint phy_alt_vbus_sys;
+
+	/* 0x410 */
+	uint usb1_legacy_ctrl;
+	uint reserved12[3];
+
+	/* 0x420 */
+	uint reserved13[56];
+
+	/* 0x500 */
+	uint reserved14[64 * 3];
+
+	/* 0x800 */
+	uint utmip_pll_cfg0;
+	uint utmip_pll_cfg1;
+	uint utmip_xcvr_cfg0;
+	uint utmip_bias_cfg0;
+
+	/* 0x810 */
+	uint utmip_hsrx_cfg0;
+	uint utmip_hsrx_cfg1;
+	uint utmip_fslsrx_cfg0;
+	uint utmip_fslsrx_cfg1;
+
+	/* 0x820 */
+	uint utmip_tx_cfg0;
+	uint utmip_misc_cfg0;
+	uint utmip_misc_cfg1;
+	uint utmip_debounce_cfg0;
+
+	/* 0x830 */
+	uint utmip_bat_chrg_cfg0;
+	uint utmip_spare_cfg0;
+	uint utmip_xcvr_cfg1;
+	uint utmip_bias_cfg1;
+};
+
+/* USB2_IF_ULPI_TIMING_CTRL_0 */
+#define ULPI_OUTPUT_PINMUX_BYP			(1 << 10)
+#define ULPI_CLKOUT_PINMUX_BYP			(1 << 11)
+
+/* USB2_IF_ULPI_TIMING_CTRL_1 */
+#define ULPI_DATA_TRIMMER_LOAD			(1 << 0)
+#define ULPI_DATA_TRIMMER_SEL(x)		(((x) & 0x7) << 1)
+#define ULPI_STPDIRNXT_TRIMMER_LOAD		(1 << 16)
+#define ULPI_STPDIRNXT_TRIMMER_SEL(x)	(((x) & 0x7) << 17)
+#define ULPI_DIR_TRIMMER_LOAD			(1 << 24)
+#define ULPI_DIR_TRIMMER_SEL(x)			(((x) & 0x7) << 25)
+
+/* USB2D_HOSTPC1_DEVLC_0 */
+#define PTS_SHIFT				29
+#define PTS_MASK				(0x7U << PTS_SHIFT)
+
+#define STS					(1 << 28)
+#endif /* _TEGRA30_USB_H_ */
@@ -47,6 +47,7 @@
 #endif
 #ifdef CONFIG_USB_EHCI_TEGRA
 #include <asm/arch-tegra/usb.h>
+#include <asm/arch/usb.h>
 #endif
 #ifdef CONFIG_TEGRA_MMC
 #include <asm/arch-tegra/tegra_mmc.h>
 /*
  * Copyright (c) 2011 The Chromium OS Authors.
- * Copyright (c) 2009-2012 NVIDIA Corporation
+ * Copyright (c) 2009-2013 NVIDIA Corporation
  * Copyright (c) 2013 Lucas Stach
  *
  * See file CREDITS for list of people who contributed to this
@@ -28,6 +28,8 @@
 #include <asm-generic/gpio.h>
 #include <asm/arch/clock.h>
 #include <asm/arch-tegra/usb.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch/usb.h>
 #include <usb.h>
 #include <usb/ulpi.h>
 #include <libfdt.h>
@@ -35,6 +37,11 @@
  
 #include "ehci.h"
  
+#define USB1_ADDR_MASK	0xFFFF0000
+
+#define HOSTPC1_DEVLC	0x84
+#define HOSTPC1_PSPD(x)		(((x) >> 25) & 0x3)
+
 #ifdef CONFIG_USB_ULPI
 	#ifndef CONFIG_USB_ULPI_VIEWPORT
 	#error	"To use CONFIG_USB_ULPI on Tegra Boards you have to also \
@@ -87,6 +94,8 @@
  
 static struct fdt_usb port[USB_PORTS_MAX];	/* List of valid USB ports */
 static unsigned port_count;			/* Number of available ports */
+/* Port that needs to clear CSC after Port Reset */
+static u32 port_addr_clear_csc;
  
 /*
  * This table has USB timing parameters for each Oscillator frequency we
@@ -129,7 +138,7 @@
  *
  * 4. The 20 microsecond delay after bias cell operation.
  */
-static const unsigned usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = {
+static const unsigned T20_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = {
 	/* DivN, DivM, DivP, CPCON, LFCON, Delays             Debounce, Bias */
 	{ 0x3C0, 0x0D, 0x00, 0xC,   0,  0x02, 0x33, 0x05, 0x7F, 0x7EF4, 5 },
 	{ 0x0C8, 0x04, 0x00, 0x3,   0,  0x03, 0x4B, 0x06, 0xBB, 0xBB80, 7 },
@@ -137,6 +146,22 @@
 	{ 0x3C0, 0x1A, 0x00, 0xC,   0,  0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 }
 };
  
+static const unsigned T30_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = {
+	/* DivN, DivM, DivP, CPCON, LFCON, Delays             Debounce, Bias */
+	{ 0x3C0, 0x0D, 0x00, 0xC,   1,  0x02, 0x33, 0x09, 0x7F, 0x7EF4, 5 },
+	{ 0x0C8, 0x04, 0x00, 0x3,   0,  0x03, 0x4B, 0x0C, 0xBB, 0xBB80, 7 },
+	{ 0x3C0, 0x0C, 0x00, 0xC,   1,  0x02, 0x2F, 0x08, 0x76, 0x7530, 5 },
+	{ 0x3C0, 0x1A, 0x00, 0xC,   1,  0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 }
+};
+
+static const unsigned T114_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = {
+	/* DivN, DivM, DivP, CPCON, LFCON, Delays             Debounce, Bias */
+	{ 0x3C0, 0x0D, 0x00, 0xC,   2,  0x02, 0x33, 0x09, 0x7F, 0x7EF4, 6 },
+	{ 0x0C8, 0x04, 0x00, 0x3,   2,  0x03, 0x4B, 0x0C, 0xBB, 0xBB80, 8 },
+	{ 0x3C0, 0x0C, 0x00, 0xC,   2,  0x02, 0x2F, 0x08, 0x76, 0x7530, 5 },
+	{ 0x3C0, 0x1A, 0x00, 0xC,   2,  0x04, 0x66, 0x09, 0xFE, 0xFDE8, 0xB }
+};
+
 /* UTMIP Idle Wait Delay */
 static const u8 utmip_idle_wait_delay = 17;
  
@@ -146,6 +171,33 @@
 /* UTMIP High Speed Sync Start Delay */
 static const u8 utmip_hs_sync_start_delay = 9;
  
+struct fdt_usb_controller {
+	int compat;
+	/* flag to determine whether controller supports hostpc register */
+	u32 has_hostpc:1;
+	const unsigned *pll_parameter;
+};
+
+static struct fdt_usb_controller fdt_usb_controllers[] = {
+	{
+		.compat		= COMPAT_NVIDIA_TEGRA20_USB,
+		.has_hostpc	= 0,
+		.pll_parameter	= (const unsigned *)T20_usb_pll,
+	},
+	{
+		.compat		= COMPAT_NVIDIA_TEGRA30_USB,
+		.has_hostpc	= 1,
+		.pll_parameter	= (const unsigned *)T30_usb_pll,
+	},
+	{
+		.compat		= COMPAT_NVIDIA_TEGRA114_USB,
+		.has_hostpc	= 1,
+		.pll_parameter	= (const unsigned *)T114_usb_pll,
+	},
+};
+
+static struct fdt_usb_controller *controller;
+
 /*
  * A known hardware issue where Connect Status Change bit of PORTSC register
  * of USB1 controller will be set after Port Reset.
  
@@ -156,13 +208,52 @@
 void ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg)
 {
 	mdelay(50);
-	if (((u32) status_reg & TEGRA_USB_ADDR_MASK) != TEGRA_USB1_BASE)
+	/* This is to avoid PORT_ENABLE bit to be cleared in "ehci-hcd.c". */
+	if (controller->has_hostpc)
+		*reg |= EHCI_PS_PE;
+
+	if (((u32)status_reg & TEGRA_USB_ADDR_MASK) != port_addr_clear_csc)
 		return;
 	/* For EHCI_PS_CSC to be cleared in ehci_hcd.c */
 	if (ehci_readl(status_reg) & EHCI_PS_CSC)
 		*reg |= EHCI_PS_CSC;
 }
  
+/*
+ * This ehci_set_usbmode overrides the weak function ehci_set_usbmode
+ * in "ehci-hcd.c".
+ */
+void ehci_set_usbmode(int index)
+{
+	struct fdt_usb *config;
+	struct usb_ctlr *usbctlr;
+	uint32_t tmp;
+
+	config = &port[index];
+	usbctlr = config->reg;
+
+	tmp = ehci_readl(&usbctlr->usb_mode);
+	tmp |= USBMODE_CM_HC;
+	ehci_writel(&usbctlr->usb_mode, tmp);
+}
+
+/*
+ * This ehci_get_port_speed overrides the weak function ehci_get_port_speed
+ * in "ehci-hcd.c".
+ */
+int ehci_get_port_speed(struct ehci_hcor *hcor, uint32_t reg)
+{
+	uint32_t tmp;
+	uint32_t *reg_ptr;
+
+	if (controller->has_hostpc) {
+		reg_ptr = (uint32_t *)((u8 *)&hcor->or_usbcmd + HOSTPC1_DEVLC);
+		tmp = ehci_readl(reg_ptr);
+		return HOSTPC1_PSPD(tmp);
+	} else
+		return PORTSC_PSPD(reg);
+}
+
 /* Put the port into host mode */
 static void set_host_mode(struct fdt_usb *config)
 {
@@ -209,6 +300,16 @@
 		setbits_le32(&usbctlr->susp_ctrl, UTMIP_PHY_ENB);
 }
  
+static const unsigned *get_pll_timing(void)
+{
+	const unsigned *timing;
+
+	timing = controller->pll_parameter +
+		clock_get_osc_freq() * PARAM_COUNT;
+
+	return timing;
+}
+
 /* set up the UTMI USB controller with the parameters provided */
 static int init_utmi_usb_controller(struct fdt_usb *config)
 {
@@ -216,6 +317,8 @@
 	int loop_count;
 	const unsigned *timing;
 	struct usb_ctlr *usbctlr = config->reg;
+	struct clk_rst_ctlr *clkrst;
+	struct usb_ctlr *usb1ctlr;
  
 	clock_enable(config->periph_id);
  
  
  
  
  
  
@@ -232,36 +335,98 @@
 	 * To Use the A Session Valid for cable detection logic, VBUS_WAKEUP
 	 * mux must be switched to actually use a_sess_vld threshold.
 	 */
-	if (fdt_gpio_isvalid(&config->vbus_gpio)) {
+	if (config->dr_mode == DR_MODE_OTG &&
+	    fdt_gpio_isvalid(&config->vbus_gpio))
 		clrsetbits_le32(&usbctlr->usb1_legacy_ctrl,
 			VBUS_SENSE_CTL_MASK,
 			VBUS_SENSE_CTL_A_SESS_VLD << VBUS_SENSE_CTL_SHIFT);
-	}
  
 	/*
 	 * PLL Delay CONFIGURATION settings. The following parameters control
 	 * the bring up of the plls.
 	 */
-	timing = usb_pll[clock_get_osc_freq()];
+	timing = get_pll_timing();
  
-	val = readl(&usbctlr->utmip_misc_cfg1);
-	clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK,
-		timing[PARAM_STABLE_COUNT] << UTMIP_PLLU_STABLE_COUNT_SHIFT);
-	clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK,
-		timing[PARAM_ACTIVE_DELAY_COUNT] <<
-			UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT);
-	writel(val, &usbctlr->utmip_misc_cfg1);
+	if (!controller->has_hostpc) {
+		val = readl(&usbctlr->utmip_misc_cfg1);
+		clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK,
+				timing[PARAM_STABLE_COUNT] <<
+				UTMIP_PLLU_STABLE_COUNT_SHIFT);
+		clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK,
+				timing[PARAM_ACTIVE_DELAY_COUNT] <<
+				UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT);
+		writel(val, &usbctlr->utmip_misc_cfg1);
  
-	/* Set PLL enable delay count and crystal frequency count */
-	val = readl(&usbctlr->utmip_pll_cfg1);
-	clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK,
-		timing[PARAM_ENABLE_DELAY_COUNT] <<
-			UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT);
-	clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK,
-		timing[PARAM_XTAL_FREQ_COUNT] <<
-			UTMIP_XTAL_FREQ_COUNT_SHIFT);
-	writel(val, &usbctlr->utmip_pll_cfg1);
+		/* Set PLL enable delay count and crystal frequency count */
+		val = readl(&usbctlr->utmip_pll_cfg1);
+		clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK,
+				timing[PARAM_ENABLE_DELAY_COUNT] <<
+				UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT);
+		clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK,
+				timing[PARAM_XTAL_FREQ_COUNT] <<
+				UTMIP_XTAL_FREQ_COUNT_SHIFT);
+		writel(val, &usbctlr->utmip_pll_cfg1);
+	} else {
+		clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
  
+		val = readl(&clkrst->crc_utmip_pll_cfg2);
+		clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK,
+				timing[PARAM_STABLE_COUNT] <<
+				UTMIP_PLLU_STABLE_COUNT_SHIFT);
+		clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK,
+				timing[PARAM_ACTIVE_DELAY_COUNT] <<
+				UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT);
+		writel(val, &clkrst->crc_utmip_pll_cfg2);
+
+		/* Set PLL enable delay count and crystal frequency count */
+		val = readl(&clkrst->crc_utmip_pll_cfg1);
+		clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK,
+				timing[PARAM_ENABLE_DELAY_COUNT] <<
+				UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT);
+		clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK,
+				timing[PARAM_XTAL_FREQ_COUNT] <<
+				UTMIP_XTAL_FREQ_COUNT_SHIFT);
+		writel(val, &clkrst->crc_utmip_pll_cfg1);
+
+		/* Disable Power Down state for PLL */
+		clrbits_le32(&clkrst->crc_utmip_pll_cfg1,
+			     PLLU_POWERDOWN | PLL_ENABLE_POWERDOWN |
+			     PLL_ACTIVE_POWERDOWN);
+
+		/* Recommended PHY settings for EYE diagram */
+		val = readl(&usbctlr->utmip_xcvr_cfg0);
+		clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MASK,
+				0x4 << UTMIP_XCVR_SETUP_SHIFT);
+		clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MSB_MASK,
+				0x3 << UTMIP_XCVR_SETUP_MSB_SHIFT);
+		clrsetbits_le32(&val, UTMIP_XCVR_HSSLEW_MSB_MASK,
+				0x8 << UTMIP_XCVR_HSSLEW_MSB_SHIFT);
+		writel(val, &usbctlr->utmip_xcvr_cfg0);
+		clrsetbits_le32(&usbctlr->utmip_xcvr_cfg1,
+				UTMIP_XCVR_TERM_RANGE_ADJ_MASK,
+				0x7 << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT);
+
+		/* Some registers can be controlled from USB1 only. */
+		if (config->periph_id != PERIPH_ID_USBD) {
+			clock_enable(PERIPH_ID_USBD);
+			/* Disable Reset if in Reset state */
+			reset_set_enable(PERIPH_ID_USBD, 0);
+		}
+		usb1ctlr = (struct usb_ctlr *)
+			((u32)config->reg & USB1_ADDR_MASK);
+		val = readl(&usb1ctlr->utmip_bias_cfg0);
+		setbits_le32(&val, UTMIP_HSDISCON_LEVEL_MSB);
+		clrsetbits_le32(&val, UTMIP_HSDISCON_LEVEL_MASK,
+				0x1 << UTMIP_HSDISCON_LEVEL_SHIFT);
+		clrsetbits_le32(&val, UTMIP_HSSQUELCH_LEVEL_MASK,
+				0x2 << UTMIP_HSSQUELCH_LEVEL_SHIFT);
+		writel(val, &usb1ctlr->utmip_bias_cfg0);
+
+		/* Miscellaneous setting mentioned in Programming Guide */
+		clrbits_le32(&usbctlr->utmip_misc_cfg0,
+			     UTMIP_SUSPEND_EXIT_ON_EDGE);
+	}
+
 	/* Setting the tracking length time */
 	clrsetbits_le32(&usbctlr->utmip_bias_cfg1,
 		UTMIP_BIAS_PDTRK_COUNT_MASK,
@@ -308,6 +473,14 @@
 	/* Resuscitate crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN */
 	setbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN);
  
+	if (controller->has_hostpc) {
+		if (config->periph_id == PERIPH_ID_USBD)
+			clrbits_le32(&clkrst->crc_utmip_pll_cfg2,
+				     UTMIP_FORCE_PD_SAMP_A_POWERDOWN);
+		if (config->periph_id == PERIPH_ID_USB3)
+			clrbits_le32(&clkrst->crc_utmip_pll_cfg2,
+				     UTMIP_FORCE_PD_SAMP_C_POWERDOWN);
+	}
 	/* Finished the per-controller init. */
  
 	/* De-assert UTMIP_RESET to bring out of reset. */
@@ -336,6 +509,18 @@
 	clrbits_le32(&usbctlr->utmip_xcvr_cfg1, UTMIP_FORCE_PDDISC_POWERDOWN |
 		UTMIP_FORCE_PDCHRP_POWERDOWN | UTMIP_FORCE_PDDR_POWERDOWN);
  
+	if (controller->has_hostpc) {
+		/*
+		 * BIAS Pad Power Down is common among all 3 USB
+		 * controllers and can be controlled from USB1 only.
+		 */
+		usb1ctlr = (struct usb_ctlr *)
+			((u32)config->reg & USB1_ADDR_MASK);
+		clrbits_le32(&usb1ctlr->utmip_bias_cfg0, UTMIP_BIASPD);
+		udelay(25);
+		clrbits_le32(&usb1ctlr->utmip_bias_cfg1,
+			     UTMIP_FORCE_PDTRK_POWERDOWN);
+	}
 	return 0;
 }
  
@@ -438,7 +623,7 @@
 		timing[PARAM_CPCON], timing[PARAM_LFCON]);
 }
  
-int fdt_decode_usb(const void *blob, int node, struct fdt_usb *config)
+static int fdt_decode_usb(const void *blob, int node, struct fdt_usb *config)
 {
 	const char *phy, *mode;
  
@@ -466,6 +651,8 @@
 	config->enabled = fdtdec_get_is_enabled(blob, node);
 	config->has_legacy_mode = fdtdec_get_bool(blob, node,
 						  "nvidia,has-legacy-mode");
+	if (config->has_legacy_mode)
+		port_addr_clear_csc = (u32) config->reg;
 	config->periph_id = clock_decode_periph_id(blob, node);
 	if (config->periph_id == PERIPH_ID_NONE) {
 		debug("%s: Missing/invalid peripheral ID\n", __func__);
  
  
@@ -483,20 +670,22 @@
 	return 0;
 }
  
-int board_usb_init(const void *blob)
+/*
+ * process_usb_nodes() - Process a list of USB nodes, adding them to our list
+ *			of USB ports.
+ * @blob:	fdt blob
+ * @node_list:	list of nodes to process (any <=0 are ignored)
+ * @count:	number of nodes to process
+ *
+ * Return:	0 - ok, -1 - error
+ */
+static int process_usb_nodes(const void *blob, int node_list[], int count)
 {
 	struct fdt_usb config;
-	enum clock_osc_freq freq;
-	int node_list[USB_PORTS_MAX];
-	int node, count, i;
+	int node, i;
+	int clk_done = 0;
  
-	/* Set up the USB clocks correctly based on our oscillator frequency */
-	freq = clock_get_osc_freq();
-	config_clock(usb_pll[freq]);
-
-	/* count may return <0 on error */
-	count = fdtdec_find_aliases_for_id(blob, "usb",
-			COMPAT_NVIDIA_TEGRA20_USB, node_list, USB_PORTS_MAX);
+	port_count = 0;
 	for (i = 0; i < count; i++) {
 		if (port_count == USB_PORTS_MAX) {
 			printf("tegrausb: Cannot register more than %d ports\n",
@@ -513,6 +702,10 @@
 			      fdt_get_name(blob, node, NULL));
 			return -1;
 		}
+		if (!clk_done) {
+			config_clock(get_pll_timing());
+			clk_done = 1;
+		}
 		config.initialized = 0;
  
 		/* add new USB port to the list of available ports */
@@ -522,6 +715,31 @@
 	return 0;
 }
  
+int board_usb_init(const void *blob)
+{
+	int node_list[USB_PORTS_MAX];
+	int count, err = 0;
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(fdt_usb_controllers); i++) {
+		controller = &fdt_usb_controllers[i];
+
+		count = fdtdec_find_aliases_for_id(blob, "usb",
+			controller->compat, node_list, USB_PORTS_MAX);
+		if (count) {
+			err = process_usb_nodes(blob, node_list, count);
+			if (err)
+				printf("%s: Error processing USB node!\n",
+				       __func__);
+			return err;
+		}
+	}
+	if (i == ARRAY_SIZE(fdt_usb_controllers))
+		controller = NULL;
+
+	return err;
+}
+
 /**
  * Start up the given port number (ports are numbered from 0 on each board).
  * This returns values for the appropriate hccr and hcor addresses to use for
@@ -564,6 +782,20 @@
 	usbctlr = config->reg;
 	*hccr = (struct ehci_hccr *)&usbctlr->cap_length;
 	*hcor = (struct ehci_hcor *)&usbctlr->usb_cmd;
+
+	if (controller->has_hostpc) {
+		/* Set to Host mode after Controller Reset was done */
+		clrsetbits_le32(&usbctlr->usb_mode, USBMODE_CM_HC,
+				USBMODE_CM_HC);
+		/* Select UTMI parallel interface after setting host mode */
+		if (config->utmi) {
+			clrsetbits_le32((char *)&usbctlr->usb_cmd +
+					HOSTPC1_DEVLC, PTS_MASK,
+					PTS_UTMI << PTS_SHIFT);
+			clrbits_le32((char *)&usbctlr->usb_cmd +
+				     HOSTPC1_DEVLC, STS);
+		}
+	}
 	return 0;
 }
  
@@ -64,6 +64,8 @@
 enum fdt_compat_id {
 	COMPAT_UNKNOWN,
 	COMPAT_NVIDIA_TEGRA20_USB,	/* Tegra20 USB port */
+	COMPAT_NVIDIA_TEGRA30_USB,	/* Tegra30 USB port */
+	COMPAT_NVIDIA_TEGRA114_USB,	/* Tegra114 USB port */
 	COMPAT_NVIDIA_TEGRA114_I2C,	/* Tegra114 I2C w/single clock source */
 	COMPAT_NVIDIA_TEGRA20_I2C,	/* Tegra20 i2c */
 	COMPAT_NVIDIA_TEGRA20_DVC,	/* Tegra20 dvc (really just i2c) */
@@ -37,6 +37,8 @@
 static const char * const compat_names[COMPAT_COUNT] = {
 	COMPAT(UNKNOWN, "<none>"),
 	COMPAT(NVIDIA_TEGRA20_USB, "nvidia,tegra20-ehci"),
+	COMPAT(NVIDIA_TEGRA30_USB, "nvidia,tegra30-ehci"),
+	COMPAT(NVIDIA_TEGRA114_USB, "nvidia,tegra114-ehci"),
 	COMPAT(NVIDIA_TEGRA114_I2C, "nvidia,tegra114-i2c"),
 	COMPAT(NVIDIA_TEGRA20_I2C, "nvidia,tegra20-i2c"),
 	COMPAT(NVIDIA_TEGRA20_DVC, "nvidia,tegra20-i2c-dvc"),
...	...	@@ -225,6 +225,16 @@
225	225	IN_408_OUT_9_6_DIVISOR = 83,
226	226	};
227	227
	228	+/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG1_0 */
	229	+#define PLLU_POWERDOWN (1 << 16)
	230	+#define PLL_ENABLE_POWERDOWN (1 << 14)
	231	+#define PLL_ACTIVE_POWERDOWN (1 << 12)
	232	+
	233	+/* CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0 */
	234	+#define UTMIP_FORCE_PD_SAMP_C_POWERDOWN (1 << 4)
	235	+#define UTMIP_FORCE_PD_SAMP_B_POWERDOWN (1 << 2)
	236	+#define UTMIP_FORCE_PD_SAMP_A_POWERDOWN (1 << 0)
	237	+
228	238	/* CLK_RST_CONTROLLER_OSC_CTRL_0 */
229	239	#define OSC_XOBP_SHIFT 1
230	240	#define OSC_XOBP_MASK (1U << OSC_XOBP_SHIFT)
1	1	/*
2	2	* Copyright (c) 2011 The Chromium OS Authors.
	3	+ * Copyright (c) 2013 NVIDIA Corporation
3	4	* See file CREDITS for list of people who contributed to this
4	5	* project.
5	6	*
...	...	@@ -22,120 +23,6 @@
22	23	#ifndef _TEGRA_USB_H_
23	24	#define _TEGRA_USB_H_
24	25
25		-
26		-/* USB Controller (USBx_CONTROLLER_) regs */
27		-struct usb_ctlr {
28		- /* 0x000 */
29		- uint id;
30		- uint reserved0;
31		- uint host;
32		- uint device;
33		-
34		- /* 0x010 */
35		- uint txbuf;
36		- uint rxbuf;
37		- uint reserved1[2];
38		-
39		- /* 0x020 */
40		- uint reserved2[56];
41		-
42		- /* 0x100 */
43		- u16 cap_length;
44		- u16 hci_version;
45		- uint hcs_params;
46		- uint hcc_params;
47		- uint reserved3[5];
48		-
49		- /* 0x120 */
50		- uint dci_version;
51		- uint dcc_params;
52		- uint reserved4[6];
53		-
54		- /* 0x140 */
55		- uint usb_cmd;
56		- uint usb_sts;
57		- uint usb_intr;
58		- uint frindex;
59		-
60		- /* 0x150 */
61		- uint reserved5;
62		- uint periodic_list_base;
63		- uint async_list_addr;
64		- uint async_tt_sts;
65		-
66		- /* 0x160 */
67		- uint burst_size;
68		- uint tx_fill_tuning;
69		- uint reserved6; /* is this port_sc1 on some controllers? */
70		- uint icusb_ctrl;
71		-
72		- /* 0x170 */
73		- uint ulpi_viewport;
74		- uint reserved7;
75		- uint endpt_nak;
76		- uint endpt_nak_enable;
77		-
78		- /* 0x180 */
79		- uint reserved;
80		- uint port_sc1;
81		- uint reserved8[6];
82		-
83		- /* 0x1a0 */
84		- uint reserved9;
85		- uint otgsc;
86		- uint usb_mode;
87		- uint endpt_setup_stat;
88		-
89		- /* 0x1b0 */
90		- uint reserved10[20];
91		-
92		- /* 0x200 */
93		- uint reserved11[0x80];
94		-
95		- /* 0x400 */
96		- uint susp_ctrl;
97		- uint phy_vbus_sensors;
98		- uint phy_vbus_wakeup_id;
99		- uint phy_alt_vbus_sys;
100		-
101		- /* 0x410 */
102		- uint usb1_legacy_ctrl;
103		- uint reserved12[4];
104		-
105		- /* 0x424 */
106		- uint ulpi_timing_ctrl_0;
107		- uint ulpi_timing_ctrl_1;
108		- uint reserved13[53];
109		-
110		- /* 0x500 */
111		- uint reserved14[64 * 3];
112		-
113		- /* 0x800 */
114		- uint utmip_pll_cfg0;
115		- uint utmip_pll_cfg1;
116		- uint utmip_xcvr_cfg0;
117		- uint utmip_bias_cfg0;
118		-
119		- /* 0x810 */
120		- uint utmip_hsrx_cfg0;
121		- uint utmip_hsrx_cfg1;
122		- uint utmip_fslsrx_cfg0;
123		- uint utmip_fslsrx_cfg1;
124		-
125		- /* 0x820 */
126		- uint utmip_tx_cfg0;
127		- uint utmip_misc_cfg0;
128		- uint utmip_misc_cfg1;
129		- uint utmip_debounce_cfg0;
130		-
131		- /* 0x830 */
132		- uint utmip_bat_chrg_cfg0;
133		- uint utmip_spare_cfg0;
134		- uint utmip_xcvr_cfg1;
135		- uint utmip_bias_cfg1;
136		-};
137		-
138		-
139	26	/* USB1_LEGACY_CTRL */
140	27	#define USB1_NO_LEGACY_MODE 1
141	28
142	29
143	30
...	...	@@ -146,25 +33,18 @@
146	33	#define VBUS_SENSE_CTL_AB_SESS_VLD 2
147	34	#define VBUS_SENSE_CTL_A_SESS_VLD 3
148	35
149		-/* USB2_IF_ULPI_TIMING_CTRL_0 */
150		-#define ULPI_OUTPUT_PINMUX_BYP (1 << 10)
151		-#define ULPI_CLKOUT_PINMUX_BYP (1 << 11)
152		-
153		-/* USB2_IF_ULPI_TIMING_CTRL_1 */
154		-#define ULPI_DATA_TRIMMER_LOAD (1 << 0)
155		-#define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1)
156		-#define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16)
157		-#define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
158		-#define ULPI_DIR_TRIMMER_LOAD (1 << 24)
159		-#define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25)
160		-
161	36	/* USBx_IF_USB_SUSP_CTRL_0 */
162		-#define ULPI_PHY_ENB (1 << 13)
163	37	#define UTMIP_PHY_ENB (1 << 12)
164	38	#define UTMIP_RESET (1 << 11)
165	39	#define USB_PHY_CLK_VALID (1 << 7)
166	40	#define USB_SUSP_CLR (1 << 5)
167	41
	42	+/* USB2_IF_USB_SUSP_CTRL_0 */
	43	+#define ULPI_PHY_ENB (1 << 13)
	44	+
	45	+/* USBx_UTMIP_MISC_CFG0 */
	46	+#define UTMIP_SUSPEND_EXIT_ON_EDGE (1 << 22)
	47	+
168	48	/* USBx_UTMIP_MISC_CFG1 */
169	49	#define UTMIP_PLLU_STABLE_COUNT_SHIFT 6
170	50	#define UTMIP_PLLU_STABLE_COUNT_MASK \
171	51
172	52
173	53
...	...	@@ -177,15 +57,28 @@
177	57	/* USBx_UTMIP_PLL_CFG1_0 */
178	58	#define UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT 27
179	59	#define UTMIP_PLLU_ENABLE_DLY_COUNT_MASK \
180		- (0xf << UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT)
	60	+ (0x1f << UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT)
181	61	#define UTMIP_XTAL_FREQ_COUNT_SHIFT 0
182	62	#define UTMIP_XTAL_FREQ_COUNT_MASK 0xfff
183	63
	64	+/* USBx_UTMIP_BIAS_CFG0_0 */
	65	+#define UTMIP_HSDISCON_LEVEL_MSB (1 << 24)
	66	+#define UTMIP_OTGPD (1 << 11)
	67	+#define UTMIP_BIASPD (1 << 10)
	68	+#define UTMIP_HSDISCON_LEVEL_SHIFT 2
	69	+#define UTMIP_HSDISCON_LEVEL_MASK \
	70	+ (0x3 << UTMIP_HSDISCON_LEVEL_SHIFT)
	71	+#define UTMIP_HSSQUELCH_LEVEL_SHIFT 0
	72	+#define UTMIP_HSSQUELCH_LEVEL_MASK \
	73	+ (0x3 << UTMIP_HSSQUELCH_LEVEL_SHIFT)
	74	+
184	75	/* USBx_UTMIP_BIAS_CFG1_0 */
	76	+#define UTMIP_FORCE_PDTRK_POWERDOWN 1
185	77	#define UTMIP_BIAS_PDTRK_COUNT_SHIFT 3
186	78	#define UTMIP_BIAS_PDTRK_COUNT_MASK \
187	79	(0x1f << UTMIP_BIAS_PDTRK_COUNT_SHIFT)
188	80
	81	+/* USBx_UTMIP_DEBOUNCE_CFG0_0 */
189	82	#define UTMIP_DEBOUNCE_CFG0_SHIFT 0
190	83	#define UTMIP_DEBOUNCE_CFG0_MASK 0xffff
191	84
...	...	@@ -195,9 +88,6 @@
195	88	/* USBx_UTMIP_BAT_CHRG_CFG0_0 */
196	89	#define UTMIP_PD_CHRG 1
197	90
198		-/* USBx_UTMIP_XCVR_CFG0_0 */
199		-#define UTMIP_XCVR_LSBIAS_SE (1 << 21)
200		-
201	91	/* USBx_UTMIP_SPARE_CFG0_0 */
202	92	#define FUSE_SETUP_SEL (1 << 3)
203	93
204	94
205	95
206	96
207	97
208	98
...	...	@@ -208,23 +98,26 @@
208	98	#define UTMIP_ELASTIC_LIMIT_MASK \
209	99	(0x1f << UTMIP_ELASTIC_LIMIT_SHIFT)
210	100
211		-/* USBx_UTMIP_HSRX_CFG0_1 */
	101	+/* USBx_UTMIP_HSRX_CFG1_0 */
212	102	#define UTMIP_HS_SYNC_START_DLY_SHIFT 1
213	103	#define UTMIP_HS_SYNC_START_DLY_MASK \
214		- (0xf << UTMIP_HS_SYNC_START_DLY_SHIFT)
	104	+ (0x1f << UTMIP_HS_SYNC_START_DLY_SHIFT)
215	105
216	106	/* USBx_CONTROLLER_2_USB2D_ICUSB_CTRL_0 */
217	107	#define IC_ENB1 (1 << 3)
218	108
219		-/* SB2_CONTROLLER_2_USB2D_PORTSC1_0 */
220		-#define PTS_SHIFT 30
221		-#define PTS_MASK (3U << PTS_SHIFT)
222		-#define PTS_UTMI 0
	109	+/* PORTSC1, USB1, defined for Tegra20 */
	110	+#define PTS1_SHIFT 31
	111	+#define PTS1_MASK (1 << PTS1_SHIFT)
	112	+#define STS1 (1 << 30)
	113	+
	114	+#define PTS_UTMI 0
223	115	#define PTS_RESERVED 1
224		-#define PTS_ULPI 2
	116	+#define PTS_ULPI 2
225	117	#define PTS_ICUSB_SER 3
	118	+#define PTS_HSIC 4
226	119
227		-#define STS (1 << 29)
	120	+/* SB2_CONTROLLER_2_USB2D_PORTSC1_0 */
228	121	#define WKOC (1 << 22)
229	122	#define WKDS (1 << 21)
230	123	#define WKCN (1 << 20)
231	124
...	...	@@ -233,8 +126,19 @@
233	126	#define UTMIP_FORCE_PD_POWERDOWN (1 << 14)
234	127	#define UTMIP_FORCE_PD2_POWERDOWN (1 << 16)
235	128	#define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18)
	129	+#define UTMIP_XCVR_LSBIAS_SE (1 << 21)
	130	+#define UTMIP_XCVR_HSSLEW_MSB_SHIFT 25
	131	+#define UTMIP_XCVR_HSSLEW_MSB_MASK \
	132	+ (0x7f << UTMIP_XCVR_HSSLEW_MSB_SHIFT)
	133	+#define UTMIP_XCVR_SETUP_MSB_SHIFT 22
	134	+#define UTMIP_XCVR_SETUP_MSB_MASK (0x7 << UTMIP_XCVR_SETUP_MSB_SHIFT)
	135	+#define UTMIP_XCVR_SETUP_SHIFT 0
	136	+#define UTMIP_XCVR_SETUP_MASK (0xf << UTMIP_XCVR_SETUP_SHIFT)
236	137
237	138	/* USBx_UTMIP_XCVR_CFG1_0 */
	139	+#define UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT 18
	140	+#define UTMIP_XCVR_TERM_RANGE_ADJ_MASK \
	141	+ (0xf << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT)
238	142	#define UTMIP_FORCE_PDDISC_POWERDOWN (1 << 0)
239	143	#define UTMIP_FORCE_PDCHRP_POWERDOWN (1 << 2)
240	144	#define UTMIP_FORCE_PDDR_POWERDOWN (1 << 4)
	1	+/*
	2	+ * Copyright (c) 2011 The Chromium OS Authors.
	3	+ * Copyright (c) 2013 NVIDIA Corporation
	4	+ * See file CREDITS for list of people who contributed to this
	5	+ * project.
	6	+ *
	7	+ * This program is free software; you can redistribute it and/or
	8	+ * modify it under the terms of the GNU General Public License as
	9	+ * published by the Free Software Foundation; either version 2 of
	10	+ * the License, or (at your option) any later version.
	11	+ *
	12	+ * This program is distributed in the hope that it will be useful,
	13	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	+ * GNU General Public License for more details.
	16	+ *
	17	+ * You should have received a copy of the GNU General Public License
	18	+ * along with this program; if not, write to the Free Software
	19	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	+ * MA 02111-1307 USA
	21	+ */
	22	+
	23	+#ifndef _TEGRA114_USB_H_
	24	+#define _TEGRA114_USB_H_
	25	+
	26	+/* USB Controller (USBx_CONTROLLER_) regs */
	27	+struct usb_ctlr {
	28	+ /* 0x000 */
	29	+ uint id;
	30	+ uint reserved0;
	31	+ uint host;
	32	+ uint device;
	33	+
	34	+ /* 0x010 */
	35	+ uint txbuf;
	36	+ uint rxbuf;
	37	+ uint reserved1[2];
	38	+
	39	+ /* 0x020 */
	40	+ uint reserved2[56];
	41	+
	42	+ /* 0x100 */
	43	+ u16 cap_length;
	44	+ u16 hci_version;
	45	+ uint hcs_params;
	46	+ uint hcc_params;
	47	+ uint reserved3[5];
	48	+
	49	+ /* 0x120 */
	50	+ uint dci_version;
	51	+ uint dcc_params;
	52	+ uint reserved4[2];
	53	+
	54	+ /* 0x130 */
	55	+ uint usb_cmd;
	56	+ uint usb_sts;
	57	+ uint usb_intr;
	58	+ uint frindex;
	59	+
	60	+ /* 0x140 */
	61	+ uint reserved5;
	62	+ uint periodic_list_base;
	63	+ uint async_list_addr;
	64	+ uint reserved5_1;
	65	+
	66	+ /* 0x150 */
	67	+ uint burst_size;
	68	+ uint tx_fill_tuning;
	69	+ uint reserved6;
	70	+ uint icusb_ctrl;
	71	+
	72	+ /* 0x160 */
	73	+ uint ulpi_viewport;
	74	+ uint reserved7[3];
	75	+
	76	+ /* 0x170 */
	77	+ uint reserved;
	78	+ uint port_sc1;
	79	+ uint reserved8[6];
	80	+
	81	+ /* 0x190 */
	82	+ uint reserved9[8];
	83	+
	84	+ /* 0x1b0 */
	85	+ uint reserved10;
	86	+ uint hostpc1_devlc;
	87	+ uint reserved10_1[2];
	88	+
	89	+ /* 0x1c0 */
	90	+ uint reserved10_2[4];
	91	+
	92	+ /* 0x1d0 */
	93	+ uint reserved10_3[4];
	94	+
	95	+ /* 0x1e0 */
	96	+ uint reserved10_4[4];
	97	+
	98	+ /* 0x1f0 */
	99	+ uint reserved10_5;
	100	+ uint otgsc;
	101	+ uint usb_mode;
	102	+ uint reserved10_6;
	103	+
	104	+ /* 0x200 */
	105	+ uint endpt_nak;
	106	+ uint endpt_nak_enable;
	107	+ uint endpt_setup_stat;
	108	+ uint reserved11_1[0x7D];
	109	+
	110	+ /* 0x400 */
	111	+ uint susp_ctrl;
	112	+ uint phy_vbus_sensors;
	113	+ uint phy_vbus_wakeup_id;
	114	+ uint phy_alt_vbus_sys;
	115	+
	116	+ /* 0x410 */
	117	+ uint usb1_legacy_ctrl;
	118	+ uint reserved12[3];
	119	+
	120	+ /* 0x420 */
	121	+ uint reserved13[56];
	122	+
	123	+ /* 0x500 */
	124	+ uint reserved14[64 * 3];
	125	+
	126	+ /* 0x800 */
	127	+ uint utmip_pll_cfg0;
	128	+ uint utmip_pll_cfg1;
	129	+ uint utmip_xcvr_cfg0;
	130	+ uint utmip_bias_cfg0;
	131	+
	132	+ /* 0x810 */
	133	+ uint utmip_hsrx_cfg0;
	134	+ uint utmip_hsrx_cfg1;
	135	+ uint utmip_fslsrx_cfg0;
	136	+ uint utmip_fslsrx_cfg1;
	137	+
	138	+ /* 0x820 */
	139	+ uint utmip_tx_cfg0;
	140	+ uint utmip_misc_cfg0;
	141	+ uint utmip_misc_cfg1;
	142	+ uint utmip_debounce_cfg0;
	143	+
	144	+ /* 0x830 */
	145	+ uint utmip_bat_chrg_cfg0;
	146	+ uint utmip_spare_cfg0;
	147	+ uint utmip_xcvr_cfg1;
	148	+ uint utmip_bias_cfg1;
	149	+};
	150	+
	151	+/* USB2D_HOSTPC1_DEVLC_0 */
	152	+#define PTS_SHIFT 29
	153	+#define PTS_MASK (0x7U << PTS_SHIFT)
	154	+
	155	+#define STS (1 << 28)
	156	+#endif /* _TEGRA114_USB_H_ */
...	...	@@ -47,6 +47,7 @@
47	47	#endif
48	48	#ifdef CONFIG_USB_EHCI_TEGRA
49	49	#include <asm/arch-tegra/usb.h>
	50	+#include <asm/arch/usb.h>
50	51	#endif
51	52	#ifdef CONFIG_TEGRA_MMC
52	53	#include <asm/arch-tegra/tegra_mmc.h>
1	1	/*
2	2	* Copyright (c) 2011 The Chromium OS Authors.
3		- * Copyright (c) 2009-2012 NVIDIA Corporation
	3	+ * Copyright (c) 2009-2013 NVIDIA Corporation
4	4	* Copyright (c) 2013 Lucas Stach
5	5	*
6	6	* See file CREDITS for list of people who contributed to this
...	...	@@ -28,6 +28,8 @@
28	28	#include <asm-generic/gpio.h>
29	29	#include <asm/arch/clock.h>
30	30	#include <asm/arch-tegra/usb.h>
	31	+#include <asm/arch-tegra/clk_rst.h>
	32	+#include <asm/arch/usb.h>
31	33	#include <usb.h>
32	34	#include <usb/ulpi.h>
33	35	#include <libfdt.h>
...	...	@@ -35,6 +37,11 @@
35	37
36	38	#include "ehci.h"
37	39
	40	+#define USB1_ADDR_MASK 0xFFFF0000
	41	+
	42	+#define HOSTPC1_DEVLC 0x84
	43	+#define HOSTPC1_PSPD(x) (((x) >> 25) & 0x3)
	44	+
38	45	#ifdef CONFIG_USB_ULPI
39	46	#ifndef CONFIG_USB_ULPI_VIEWPORT
40	47	#error "To use CONFIG_USB_ULPI on Tegra Boards you have to also \
...	...	@@ -87,6 +94,8 @@
87	94
88	95	static struct fdt_usb port[USB_PORTS_MAX]; /* List of valid USB ports */
89	96	static unsigned port_count; /* Number of available ports */
	97	+/* Port that needs to clear CSC after Port Reset */
	98	+static u32 port_addr_clear_csc;
90	99
91	100	/*
92	101	* This table has USB timing parameters for each Oscillator frequency we
...	...	@@ -129,7 +138,7 @@
129	138	*
130	139	* 4. The 20 microsecond delay after bias cell operation.
131	140	*/
132		-static const unsigned usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = {
	141	+static const unsigned T20_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = {
133	142	/* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */
134	143	{ 0x3C0, 0x0D, 0x00, 0xC, 0, 0x02, 0x33, 0x05, 0x7F, 0x7EF4, 5 },
135	144	{ 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x06, 0xBB, 0xBB80, 7 },
...	...	@@ -137,6 +146,22 @@
137	146	{ 0x3C0, 0x1A, 0x00, 0xC, 0, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 }
138	147	};
139	148
	149	+static const unsigned T30_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = {
	150	+ /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */
	151	+ { 0x3C0, 0x0D, 0x00, 0xC, 1, 0x02, 0x33, 0x09, 0x7F, 0x7EF4, 5 },
	152	+ { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x0C, 0xBB, 0xBB80, 7 },
	153	+ { 0x3C0, 0x0C, 0x00, 0xC, 1, 0x02, 0x2F, 0x08, 0x76, 0x7530, 5 },
	154	+ { 0x3C0, 0x1A, 0x00, 0xC, 1, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 }
	155	+};
	156	+
	157	+static const unsigned T114_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = {
	158	+ /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */
	159	+ { 0x3C0, 0x0D, 0x00, 0xC, 2, 0x02, 0x33, 0x09, 0x7F, 0x7EF4, 6 },
	160	+ { 0x0C8, 0x04, 0x00, 0x3, 2, 0x03, 0x4B, 0x0C, 0xBB, 0xBB80, 8 },
	161	+ { 0x3C0, 0x0C, 0x00, 0xC, 2, 0x02, 0x2F, 0x08, 0x76, 0x7530, 5 },
	162	+ { 0x3C0, 0x1A, 0x00, 0xC, 2, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 0xB }
	163	+};
	164	+
140	165	/* UTMIP Idle Wait Delay */
141	166	static const u8 utmip_idle_wait_delay = 17;
142	167
...	...	@@ -146,6 +171,33 @@
146	171	/* UTMIP High Speed Sync Start Delay */
147	172	static const u8 utmip_hs_sync_start_delay = 9;
148	173
	174	+struct fdt_usb_controller {
	175	+ int compat;
	176	+ /* flag to determine whether controller supports hostpc register */
	177	+ u32 has_hostpc:1;
	178	+ const unsigned *pll_parameter;
	179	+};
	180	+
	181	+static struct fdt_usb_controller fdt_usb_controllers[] = {
	182	+ {
	183	+ .compat = COMPAT_NVIDIA_TEGRA20_USB,
	184	+ .has_hostpc = 0,
	185	+ .pll_parameter = (const unsigned *)T20_usb_pll,
	186	+ },
	187	+ {
	188	+ .compat = COMPAT_NVIDIA_TEGRA30_USB,
	189	+ .has_hostpc = 1,
	190	+ .pll_parameter = (const unsigned *)T30_usb_pll,
	191	+ },
	192	+ {
	193	+ .compat = COMPAT_NVIDIA_TEGRA114_USB,
	194	+ .has_hostpc = 1,
	195	+ .pll_parameter = (const unsigned *)T114_usb_pll,
	196	+ },
	197	+};
	198	+
	199	+static struct fdt_usb_controller *controller;
	200	+
149	201	/*
150	202	* A known hardware issue where Connect Status Change bit of PORTSC register
151	203	* of USB1 controller will be set after Port Reset.
152	204
...	...	@@ -156,13 +208,52 @@
156	208	void ehci_powerup_fixup(uint32_t status_reg, uint32_t reg)
157	209	{
158	210	mdelay(50);
159		- if (((u32) status_reg & TEGRA_USB_ADDR_MASK) != TEGRA_USB1_BASE)
	211	+ /* This is to avoid PORT_ENABLE bit to be cleared in "ehci-hcd.c". */
	212	+ if (controller->has_hostpc)
	213	+ *reg \|= EHCI_PS_PE;
	214	+
	215	+ if (((u32)status_reg & TEGRA_USB_ADDR_MASK) != port_addr_clear_csc)
160	216	return;
161	217	/* For EHCI_PS_CSC to be cleared in ehci_hcd.c */
162	218	if (ehci_readl(status_reg) & EHCI_PS_CSC)
163	219	*reg \|= EHCI_PS_CSC;
164	220	}
165	221
	222	+/*
	223	+ * This ehci_set_usbmode overrides the weak function ehci_set_usbmode
	224	+ * in "ehci-hcd.c".
	225	+ */
	226	+void ehci_set_usbmode(int index)
	227	+{
	228	+ struct fdt_usb *config;
	229	+ struct usb_ctlr *usbctlr;
	230	+ uint32_t tmp;
	231	+
	232	+ config = &port[index];
	233	+ usbctlr = config->reg;
	234	+
	235	+ tmp = ehci_readl(&usbctlr->usb_mode);
	236	+ tmp \|= USBMODE_CM_HC;
	237	+ ehci_writel(&usbctlr->usb_mode, tmp);
	238	+}
	239	+
	240	+/*
	241	+ * This ehci_get_port_speed overrides the weak function ehci_get_port_speed
	242	+ * in "ehci-hcd.c".
	243	+ */
	244	+int ehci_get_port_speed(struct ehci_hcor *hcor, uint32_t reg)
	245	+{
	246	+ uint32_t tmp;
	247	+ uint32_t *reg_ptr;
	248	+
	249	+ if (controller->has_hostpc) {
	250	+ reg_ptr = (uint32_t )((u8 )&hcor->or_usbcmd + HOSTPC1_DEVLC);
	251	+ tmp = ehci_readl(reg_ptr);
	252	+ return HOSTPC1_PSPD(tmp);
	253	+ } else
	254	+ return PORTSC_PSPD(reg);
	255	+}
	256	+
166	257	/* Put the port into host mode */
167	258	static void set_host_mode(struct fdt_usb *config)
168	259	{
...	...	@@ -209,6 +300,16 @@
209	300	setbits_le32(&usbctlr->susp_ctrl, UTMIP_PHY_ENB);
210	301	}
211	302
	303	+static const unsigned *get_pll_timing(void)
	304	+{
	305	+ const unsigned *timing;
	306	+
	307	+ timing = controller->pll_parameter +
	308	+ clock_get_osc_freq() * PARAM_COUNT;
	309	+
	310	+ return timing;
	311	+}
	312	+
212	313	/* set up the UTMI USB controller with the parameters provided */
213	314	static int init_utmi_usb_controller(struct fdt_usb *config)
214	315	{
...	...	@@ -216,6 +317,8 @@
216	317	int loop_count;
217	318	const unsigned *timing;
218	319	struct usb_ctlr *usbctlr = config->reg;
	320	+ struct clk_rst_ctlr *clkrst;
	321	+ struct usb_ctlr *usb1ctlr;
219	322
220	323	clock_enable(config->periph_id);
221	324
222	325
223	326
224	327
225	328
226	329
...	...	@@ -232,36 +335,98 @@
232	335	* To Use the A Session Valid for cable detection logic, VBUS_WAKEUP
233	336	* mux must be switched to actually use a_sess_vld threshold.
234	337	*/
235		- if (fdt_gpio_isvalid(&config->vbus_gpio)) {
	338	+ if (config->dr_mode == DR_MODE_OTG &&
	339	+ fdt_gpio_isvalid(&config->vbus_gpio))
236	340	clrsetbits_le32(&usbctlr->usb1_legacy_ctrl,
237	341	VBUS_SENSE_CTL_MASK,
238	342	VBUS_SENSE_CTL_A_SESS_VLD << VBUS_SENSE_CTL_SHIFT);
239		- }
240	343
241	344	/*
242	345	* PLL Delay CONFIGURATION settings. The following parameters control
243	346	* the bring up of the plls.
244	347	*/
245		- timing = usb_pll[clock_get_osc_freq()];
	348	+ timing = get_pll_timing();
246	349
247		- val = readl(&usbctlr->utmip_misc_cfg1);
248		- clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK,
249		- timing[PARAM_STABLE_COUNT] << UTMIP_PLLU_STABLE_COUNT_SHIFT);
250		- clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK,
251		- timing[PARAM_ACTIVE_DELAY_COUNT] <<
252		- UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT);
253		- writel(val, &usbctlr->utmip_misc_cfg1);
	350	+ if (!controller->has_hostpc) {
	351	+ val = readl(&usbctlr->utmip_misc_cfg1);
	352	+ clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK,
	353	+ timing[PARAM_STABLE_COUNT] <<
	354	+ UTMIP_PLLU_STABLE_COUNT_SHIFT);
	355	+ clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK,
	356	+ timing[PARAM_ACTIVE_DELAY_COUNT] <<
	357	+ UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT);
	358	+ writel(val, &usbctlr->utmip_misc_cfg1);
254	359
255		- /* Set PLL enable delay count and crystal frequency count */
256		- val = readl(&usbctlr->utmip_pll_cfg1);
257		- clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK,
258		- timing[PARAM_ENABLE_DELAY_COUNT] <<
259		- UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT);
260		- clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK,
261		- timing[PARAM_XTAL_FREQ_COUNT] <<
262		- UTMIP_XTAL_FREQ_COUNT_SHIFT);
263		- writel(val, &usbctlr->utmip_pll_cfg1);
	360	+ /* Set PLL enable delay count and crystal frequency count */
	361	+ val = readl(&usbctlr->utmip_pll_cfg1);
	362	+ clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK,
	363	+ timing[PARAM_ENABLE_DELAY_COUNT] <<
	364	+ UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT);
	365	+ clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK,
	366	+ timing[PARAM_XTAL_FREQ_COUNT] <<
	367	+ UTMIP_XTAL_FREQ_COUNT_SHIFT);
	368	+ writel(val, &usbctlr->utmip_pll_cfg1);
	369	+ } else {
	370	+ clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
264	371
	372	+ val = readl(&clkrst->crc_utmip_pll_cfg2);
	373	+ clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK,
	374	+ timing[PARAM_STABLE_COUNT] <<
	375	+ UTMIP_PLLU_STABLE_COUNT_SHIFT);
	376	+ clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK,
	377	+ timing[PARAM_ACTIVE_DELAY_COUNT] <<
	378	+ UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT);
	379	+ writel(val, &clkrst->crc_utmip_pll_cfg2);
	380	+
	381	+ /* Set PLL enable delay count and crystal frequency count */
	382	+ val = readl(&clkrst->crc_utmip_pll_cfg1);
	383	+ clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK,
	384	+ timing[PARAM_ENABLE_DELAY_COUNT] <<
	385	+ UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT);
	386	+ clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK,
	387	+ timing[PARAM_XTAL_FREQ_COUNT] <<
	388	+ UTMIP_XTAL_FREQ_COUNT_SHIFT);
	389	+ writel(val, &clkrst->crc_utmip_pll_cfg1);
	390	+
	391	+ /* Disable Power Down state for PLL */
	392	+ clrbits_le32(&clkrst->crc_utmip_pll_cfg1,
	393	+ PLLU_POWERDOWN \| PLL_ENABLE_POWERDOWN \|
	394	+ PLL_ACTIVE_POWERDOWN);
	395	+
	396	+ /* Recommended PHY settings for EYE diagram */
	397	+ val = readl(&usbctlr->utmip_xcvr_cfg0);
	398	+ clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MASK,
	399	+ 0x4 << UTMIP_XCVR_SETUP_SHIFT);
	400	+ clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MSB_MASK,
	401	+ 0x3 << UTMIP_XCVR_SETUP_MSB_SHIFT);
	402	+ clrsetbits_le32(&val, UTMIP_XCVR_HSSLEW_MSB_MASK,
	403	+ 0x8 << UTMIP_XCVR_HSSLEW_MSB_SHIFT);
	404	+ writel(val, &usbctlr->utmip_xcvr_cfg0);
	405	+ clrsetbits_le32(&usbctlr->utmip_xcvr_cfg1,
	406	+ UTMIP_XCVR_TERM_RANGE_ADJ_MASK,
	407	+ 0x7 << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT);
	408	+
	409	+ /* Some registers can be controlled from USB1 only. */
	410	+ if (config->periph_id != PERIPH_ID_USBD) {
	411	+ clock_enable(PERIPH_ID_USBD);
	412	+ /* Disable Reset if in Reset state */
	413	+ reset_set_enable(PERIPH_ID_USBD, 0);
	414	+ }
	415	+ usb1ctlr = (struct usb_ctlr *)
	416	+ ((u32)config->reg & USB1_ADDR_MASK);
	417	+ val = readl(&usb1ctlr->utmip_bias_cfg0);
	418	+ setbits_le32(&val, UTMIP_HSDISCON_LEVEL_MSB);
	419	+ clrsetbits_le32(&val, UTMIP_HSDISCON_LEVEL_MASK,
	420	+ 0x1 << UTMIP_HSDISCON_LEVEL_SHIFT);
	421	+ clrsetbits_le32(&val, UTMIP_HSSQUELCH_LEVEL_MASK,
	422	+ 0x2 << UTMIP_HSSQUELCH_LEVEL_SHIFT);
	423	+ writel(val, &usb1ctlr->utmip_bias_cfg0);
	424	+
	425	+ /* Miscellaneous setting mentioned in Programming Guide */
	426	+ clrbits_le32(&usbctlr->utmip_misc_cfg0,
	427	+ UTMIP_SUSPEND_EXIT_ON_EDGE);
	428	+ }
	429	+
265	430	/* Setting the tracking length time */
266	431	clrsetbits_le32(&usbctlr->utmip_bias_cfg1,
267	432	UTMIP_BIAS_PDTRK_COUNT_MASK,
...	...	@@ -308,6 +473,14 @@
308	473	/* Resuscitate crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN */
309	474	setbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN);
310	475
	476	+ if (controller->has_hostpc) {
	477	+ if (config->periph_id == PERIPH_ID_USBD)
	478	+ clrbits_le32(&clkrst->crc_utmip_pll_cfg2,
	479	+ UTMIP_FORCE_PD_SAMP_A_POWERDOWN);
	480	+ if (config->periph_id == PERIPH_ID_USB3)
	481	+ clrbits_le32(&clkrst->crc_utmip_pll_cfg2,
	482	+ UTMIP_FORCE_PD_SAMP_C_POWERDOWN);
	483	+ }
311	484	/* Finished the per-controller init. */
312	485
313	486	/* De-assert UTMIP_RESET to bring out of reset. */
...	...	@@ -336,6 +509,18 @@
336	509	clrbits_le32(&usbctlr->utmip_xcvr_cfg1, UTMIP_FORCE_PDDISC_POWERDOWN \|
337	510	UTMIP_FORCE_PDCHRP_POWERDOWN \| UTMIP_FORCE_PDDR_POWERDOWN);
338	511
	512	+ if (controller->has_hostpc) {
	513	+ /*
	514	+ * BIAS Pad Power Down is common among all 3 USB
	515	+ * controllers and can be controlled from USB1 only.
	516	+ */
	517	+ usb1ctlr = (struct usb_ctlr *)
	518	+ ((u32)config->reg & USB1_ADDR_MASK);
	519	+ clrbits_le32(&usb1ctlr->utmip_bias_cfg0, UTMIP_BIASPD);
	520	+ udelay(25);
	521	+ clrbits_le32(&usb1ctlr->utmip_bias_cfg1,
	522	+ UTMIP_FORCE_PDTRK_POWERDOWN);
	523	+ }
339	524	return 0;
340	525	}
341	526
...	...	@@ -438,7 +623,7 @@
438	623	timing[PARAM_CPCON], timing[PARAM_LFCON]);
439	624	}
440	625
441		-int fdt_decode_usb(const void blob, int node, struct fdt_usb config)
	626	+static int fdt_decode_usb(const void blob, int node, struct fdt_usb config)
442	627	{
443	628	const char phy, mode;
444	629
...	...	@@ -466,6 +651,8 @@
466	651	config->enabled = fdtdec_get_is_enabled(blob, node);
467	652	config->has_legacy_mode = fdtdec_get_bool(blob, node,
468	653	"nvidia,has-legacy-mode");
	654	+ if (config->has_legacy_mode)
	655	+ port_addr_clear_csc = (u32) config->reg;
469	656	config->periph_id = clock_decode_periph_id(blob, node);
470	657	if (config->periph_id == PERIPH_ID_NONE) {
471	658	debug("%s: Missing/invalid peripheral ID\n", __func__);
472	659
473	660
...	...	@@ -483,20 +670,22 @@
483	670	return 0;
484	671	}
485	672
486		-int board_usb_init(const void *blob)
	673	+/*
	674	+ * process_usb_nodes() - Process a list of USB nodes, adding them to our list
	675	+ * of USB ports.
	676	+ * @blob: fdt blob
	677	+ * @node_list: list of nodes to process (any <=0 are ignored)
	678	+ * @count: number of nodes to process
	679	+ *
	680	+ * Return: 0 - ok, -1 - error
	681	+ */
	682	+static int process_usb_nodes(const void *blob, int node_list[], int count)
487	683	{
488	684	struct fdt_usb config;
489		- enum clock_osc_freq freq;
490		- int node_list[USB_PORTS_MAX];
491		- int node, count, i;
	685	+ int node, i;
	686	+ int clk_done = 0;
492	687
493		- /* Set up the USB clocks correctly based on our oscillator frequency */
494		- freq = clock_get_osc_freq();
495		- config_clock(usb_pll[freq]);
496		-
497		- /* count may return <0 on error */
498		- count = fdtdec_find_aliases_for_id(blob, "usb",
499		- COMPAT_NVIDIA_TEGRA20_USB, node_list, USB_PORTS_MAX);
	688	+ port_count = 0;
500	689	for (i = 0; i < count; i++) {
501	690	if (port_count == USB_PORTS_MAX) {
502	691	printf("tegrausb: Cannot register more than %d ports\n",
...	...	@@ -513,6 +702,10 @@
513	702	fdt_get_name(blob, node, NULL));
514	703	return -1;
515	704	}
	705	+ if (!clk_done) {
	706	+ config_clock(get_pll_timing());
	707	+ clk_done = 1;
	708	+ }
516	709	config.initialized = 0;
517	710
518	711	/* add new USB port to the list of available ports */
...	...	@@ -522,6 +715,31 @@
522	715	return 0;
523	716	}
524	717
	718	+int board_usb_init(const void *blob)
	719	+{
	720	+ int node_list[USB_PORTS_MAX];
	721	+ int count, err = 0;
	722	+ int i;
	723	+
	724	+ for (i = 0; i < ARRAY_SIZE(fdt_usb_controllers); i++) {
	725	+ controller = &fdt_usb_controllers[i];
	726	+
	727	+ count = fdtdec_find_aliases_for_id(blob, "usb",
	728	+ controller->compat, node_list, USB_PORTS_MAX);
	729	+ if (count) {
	730	+ err = process_usb_nodes(blob, node_list, count);
	731	+ if (err)
	732	+ printf("%s: Error processing USB node!\n",
	733	+ __func__);
	734	+ return err;
	735	+ }
	736	+ }
	737	+ if (i == ARRAY_SIZE(fdt_usb_controllers))
	738	+ controller = NULL;
	739	+
	740	+ return err;
	741	+}
	742	+
525	743	/**
526	744	* Start up the given port number (ports are numbered from 0 on each board).
527	745	* This returns values for the appropriate hccr and hcor addresses to use for
...	...	@@ -564,6 +782,20 @@
564	782	usbctlr = config->reg;
565	783	hccr = (struct ehci_hccr )&usbctlr->cap_length;
566	784	hcor = (struct ehci_hcor )&usbctlr->usb_cmd;
	785	+
	786	+ if (controller->has_hostpc) {
	787	+ /* Set to Host mode after Controller Reset was done */
	788	+ clrsetbits_le32(&usbctlr->usb_mode, USBMODE_CM_HC,
	789	+ USBMODE_CM_HC);
	790	+ /* Select UTMI parallel interface after setting host mode */
	791	+ if (config->utmi) {
	792	+ clrsetbits_le32((char *)&usbctlr->usb_cmd +
	793	+ HOSTPC1_DEVLC, PTS_MASK,
	794	+ PTS_UTMI << PTS_SHIFT);
	795	+ clrbits_le32((char *)&usbctlr->usb_cmd +
	796	+ HOSTPC1_DEVLC, STS);
	797	+ }
	798	+ }
567	799	return 0;
568	800	}
569	801
...	...	@@ -64,6 +64,8 @@
64	64	enum fdt_compat_id {
65	65	COMPAT_UNKNOWN,
66	66	COMPAT_NVIDIA_TEGRA20_USB, /* Tegra20 USB port */
	67	+ COMPAT_NVIDIA_TEGRA30_USB, /* Tegra30 USB port */
	68	+ COMPAT_NVIDIA_TEGRA114_USB, /* Tegra114 USB port */
67	69	COMPAT_NVIDIA_TEGRA114_I2C, /* Tegra114 I2C w/single clock source */
68	70	COMPAT_NVIDIA_TEGRA20_I2C, /* Tegra20 i2c */
69	71	COMPAT_NVIDIA_TEGRA20_DVC, /* Tegra20 dvc (really just i2c) */
...	...	@@ -37,6 +37,8 @@
37	37	static const char * const compat_names[COMPAT_COUNT] = {
38	38	COMPAT(UNKNOWN, "<none>"),
39	39	COMPAT(NVIDIA_TEGRA20_USB, "nvidia,tegra20-ehci"),
	40	+ COMPAT(NVIDIA_TEGRA30_USB, "nvidia,tegra30-ehci"),
	41	+ COMPAT(NVIDIA_TEGRA114_USB, "nvidia,tegra114-ehci"),
40	42	COMPAT(NVIDIA_TEGRA114_I2C, "nvidia,tegra114-i2c"),
41	43	COMPAT(NVIDIA_TEGRA20_I2C, "nvidia,tegra20-i2c"),
42	44	COMPAT(NVIDIA_TEGRA20_DVC, "nvidia,tegra20-i2c-dvc"),