Eric Lee / smarc-uboot

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Commit 7e4902d47933eeeadb2eb5505683ffafa96691b7

Authored by Peter Griffin
Committed by Tom Rini
1 parent 9261f8b180
Exists in v2017.01-smarct4x and in 29 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

ARM: hisilicon: hikey: dts: Add pl011 additional clock binding. 

This is a binding which only exists in U-Boot, but is
required to get working serial in U-Boot.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Reviewed-by: Tom Rini <trini@konsulko.com>

Showing 1 changed file with 5 additions and 0 deletions Side-by-side Diff

arch/arm/dts/hi6220.dtsi
Diff comments   View file @ 7e4902d
... ... @@ -166,6 +166,7 @@
166 166 compatible = "arm,pl011", "arm,primecell";
167 167 reg = <0x0 0xf8015000 0x0 0x1000>;
168 168 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
  169 + clock = <19200000>;
169 170 clocks = <&ao_ctrl HI6220_UART0_PCLK>,
170 171 <&ao_ctrl HI6220_UART0_PCLK>;
171 172 clock-names = "uartclk", "apb_pclk";
... ... @@ -175,6 +176,7 @@
175 176 compatible = "arm,pl011", "arm,primecell";
176 177 reg = <0x0 0xf7111000 0x0 0x1000>;
177 178 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
  179 + clock = <19200000>;
178 180 clocks = <&sys_ctrl HI6220_UART1_PCLK>,
179 181 <&sys_ctrl HI6220_UART1_PCLK>;
180 182 clock-names = "uartclk", "apb_pclk";
... ... @@ -185,6 +187,7 @@
185 187 compatible = "arm,pl011", "arm,primecell";
186 188 reg = <0x0 0xf7112000 0x0 0x1000>;
187 189 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
  190 + clock = <19200000>;
188 191 clocks = <&sys_ctrl HI6220_UART2_PCLK>,
189 192 <&sys_ctrl HI6220_UART2_PCLK>;
190 193 clock-names = "uartclk", "apb_pclk";
... ... @@ -195,6 +198,7 @@
195 198 compatible = "arm,pl011", "arm,primecell";
196 199 reg = <0x0 0xf7113000 0x0 0x1000>;
197 200 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
  201 + clock = <19200000>;
198 202 clocks = <&sys_ctrl HI6220_UART3_PCLK>,
199 203 <&sys_ctrl HI6220_UART3_PCLK>;
200 204 clock-names = "uartclk", "apb_pclk";
... ... @@ -204,6 +208,7 @@
204 208 compatible = "arm,pl011", "arm,primecell";
205 209 reg = <0x0 0xf7114000 0x0 0x1000>;
206 210 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
  211 + clock = <19200000>;
207 212 clocks = <&sys_ctrl HI6220_UART4_PCLK>,
208 213 <&sys_ctrl HI6220_UART4_PCLK>;
209 214 clock-names = "uartclk", "apb_pclk";