mpc83xx: MPC837XERDB: Add PCIe support

On MPC8377E-RDB and MPC8378E-RDB boards we have PCIe and mini-PCIe slots. Let's support them. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>

mpc83xx: MPC837XERDB: Add PCIe support
On MPC8377E-RDB and MPC8378E-RDB boards we have PCIe and mini-PCIe slots. Let's support them. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Anton Vorontsov · Kim Phillips
1 parent 50a4d08e8f
Showing 2 changed files with 78 additions and 0 deletions Side-by-side Diff
board/freescale/mpc837xerdb/pci.c
include/configs/MPC837XERDB.h
@@ -13,6 +13,7 @@
 #include <common.h>
 #include <mpc83xx.h>
 #include <pci.h>
+#include <asm/io.h>
  
 #if defined(CONFIG_PCI)
 static struct pci_region pci_regions[] = {
  
  
  
@@ -36,12 +37,46 @@
 	}
 };
  
+static struct pci_region pcie_regions_0[] = {
+	{
+		.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
+		.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
+		.size = CONFIG_SYS_PCIE1_MEM_SIZE,
+		.flags = PCI_REGION_MEM,
+	},
+	{
+		.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
+		.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
+		.size = CONFIG_SYS_PCIE1_IO_SIZE,
+		.flags = PCI_REGION_IO,
+	},
+};
+
+static struct pci_region pcie_regions_1[] = {
+	{
+		.bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
+		.phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
+		.size = CONFIG_SYS_PCIE2_MEM_SIZE,
+		.flags = PCI_REGION_MEM,
+	},
+	{
+		.bus_start = CONFIG_SYS_PCIE2_IO_BASE,
+		.phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
+		.size = CONFIG_SYS_PCIE2_IO_SIZE,
+		.flags = PCI_REGION_IO,
+	},
+};
+
 void pci_init_board(void)
 {
 	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
+	volatile sysconf83xx_t *sysconf = &immr->sysconf;
 	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
 	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
+	volatile law83xx_t *pcie_law = sysconf->pcielaw;
 	struct pci_region *reg[] = { pci_regions };
+	struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
+	u32 spridr = in_be32(&immr->sysconf.spridr);
  
 	/* Enable all 5 PCI_CLK_OUTPUTS */
 	clk->occr |= 0xf8000000;
@@ -55,6 +90,28 @@
 	pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
  
 	mpc83xx_pci_init(1, reg, 0);
+
+	/* There is no PEX in MPC8379 parts. */
+	if (PARTID_NO_E(spridr) == SPR_8379)
+		return;
+
+	/* Configure the clock for PCIE controller */
+	clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
+				    SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
+
+	/* Deassert the resets in the control register */
+	out_be32(&sysconf->pecr1, 0xE0008000);
+	out_be32(&sysconf->pecr2, 0xE0008000);
+	udelay(2000);
+
+	/* Configure PCI Express Local Access Windows */
+	out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
+	out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
+
+	out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
+	out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
+
+	mpc83xx_pcie_init(2, pcie_reg, 0);
 }
 #endif	/* CONFIG_PCI */
@@ -49,6 +49,7 @@
 #else
 #define CONFIG_83XX_CLKIN	66666667 /* in Hz */
 #define CONFIG_83XX_GENERIC_PCI	1
+#define CONFIG_83XX_GENERIC_PCIE	1
 #endif
  
 #ifndef CONFIG_SYS_CLK_FREQ
@@ -374,6 +375,26 @@
 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL	CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_PCI_SLV_MEM_BUS	0x00000000
 #define CONFIG_SYS_PCI_SLV_MEM_SIZE	0x80000000
+
+#define CONFIG_SYS_PCIE1_BASE		0xA0000000
+#define CONFIG_SYS_PCIE1_CFG_BASE	0xA0000000
+#define CONFIG_SYS_PCIE1_CFG_SIZE	0x08000000
+#define CONFIG_SYS_PCIE1_MEM_BASE	0xA8000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xA8000000
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000
+#define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xB8000000
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000
+
+#define CONFIG_SYS_PCIE2_BASE		0xC0000000
+#define CONFIG_SYS_PCIE2_CFG_BASE	0xC0000000
+#define CONFIG_SYS_PCIE2_CFG_SIZE	0x08000000
+#define CONFIG_SYS_PCIE2_MEM_BASE	0xC8000000
+#define CONFIG_SYS_PCIE2_MEM_PHYS	0xC8000000
+#define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000
+#define CONFIG_SYS_PCIE2_IO_BASE	0x00000000
+#define CONFIG_SYS_PCIE2_IO_PHYS	0xD8000000
+#define CONFIG_SYS_PCIE2_IO_SIZE	0x00800000
  
 #ifdef CONFIG_PCI
 #define CONFIG_NET_MULTI
...	...	@@ -13,6 +13,7 @@
13	13	#include <common.h>
14	14	#include <mpc83xx.h>
15	15	#include <pci.h>
	16	+#include <asm/io.h>
16	17
17	18	#if defined(CONFIG_PCI)
18	19	static struct pci_region pci_regions[] = {
19	20
20	21
21	22
...	...	@@ -36,12 +37,46 @@
36	37	}
37	38	};
38	39
	40	+static struct pci_region pcie_regions_0[] = {
	41	+ {
	42	+ .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
	43	+ .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
	44	+ .size = CONFIG_SYS_PCIE1_MEM_SIZE,
	45	+ .flags = PCI_REGION_MEM,
	46	+ },
	47	+ {
	48	+ .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
	49	+ .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
	50	+ .size = CONFIG_SYS_PCIE1_IO_SIZE,
	51	+ .flags = PCI_REGION_IO,
	52	+ },
	53	+};
	54	+
	55	+static struct pci_region pcie_regions_1[] = {
	56	+ {
	57	+ .bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
	58	+ .phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
	59	+ .size = CONFIG_SYS_PCIE2_MEM_SIZE,
	60	+ .flags = PCI_REGION_MEM,
	61	+ },
	62	+ {
	63	+ .bus_start = CONFIG_SYS_PCIE2_IO_BASE,
	64	+ .phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
	65	+ .size = CONFIG_SYS_PCIE2_IO_SIZE,
	66	+ .flags = PCI_REGION_IO,
	67	+ },
	68	+};
	69	+
39	70	void pci_init_board(void)
40	71	{
41	72	volatile immap_t immr = (volatile immap_t )CONFIG_SYS_IMMR;
	73	+ volatile sysconf83xx_t *sysconf = &immr->sysconf;
42	74	volatile clk83xx_t clk = (volatile clk83xx_t )&immr->clk;
43	75	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
	76	+ volatile law83xx_t *pcie_law = sysconf->pcielaw;
44	77	struct pci_region *reg[] = { pci_regions };
	78	+ struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
	79	+ u32 spridr = in_be32(&immr->sysconf.spridr);
45	80
46	81	/* Enable all 5 PCI_CLK_OUTPUTS */
47	82	clk->occr \|= 0xf8000000;
...	...	@@ -55,6 +90,28 @@
55	90	pci_law[1].ar = LBLAWAR_EN \| LBLAWAR_1MB;
56	91
57	92	mpc83xx_pci_init(1, reg, 0);
	93	+
	94	+ /* There is no PEX in MPC8379 parts. */
	95	+ if (PARTID_NO_E(spridr) == SPR_8379)
	96	+ return;
	97	+
	98	+ /* Configure the clock for PCIE controller */
	99	+ clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM \| SCCR_PCIEXP2CM,
	100	+ SCCR_PCIEXP1CM_1 \| SCCR_PCIEXP2CM_1);
	101	+
	102	+ /* Deassert the resets in the control register */
	103	+ out_be32(&sysconf->pecr1, 0xE0008000);
	104	+ out_be32(&sysconf->pecr2, 0xE0008000);
	105	+ udelay(2000);
	106	+
	107	+ /* Configure PCI Express Local Access Windows */
	108	+ out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
	109	+ out_be32(&pcie_law[0].ar, LBLAWAR_EN \| LBLAWAR_512MB);
	110	+
	111	+ out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
	112	+ out_be32(&pcie_law[1].ar, LBLAWAR_EN \| LBLAWAR_512MB);
	113	+
	114	+ mpc83xx_pcie_init(2, pcie_reg, 0);
58	115	}
59	116	#endif /* CONFIG_PCI */
...	...	@@ -49,6 +49,7 @@
49	49	#else
50	50	#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
51	51	#define CONFIG_83XX_GENERIC_PCI 1
	52	+#define CONFIG_83XX_GENERIC_PCIE 1
52	53	#endif
53	54
54	55	#ifndef CONFIG_SYS_CLK_FREQ
...	...	@@ -374,6 +375,26 @@
374	375	#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
375	376	#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
376	377	#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
	378	+
	379	+#define CONFIG_SYS_PCIE1_BASE 0xA0000000
	380	+#define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000
	381	+#define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000
	382	+#define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000
	383	+#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000
	384	+#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
	385	+#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
	386	+#define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000
	387	+#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
	388	+
	389	+#define CONFIG_SYS_PCIE2_BASE 0xC0000000
	390	+#define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000
	391	+#define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000
	392	+#define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000
	393	+#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000
	394	+#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
	395	+#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
	396	+#define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000
	397	+#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
377	398
378	399	#ifdef CONFIG_PCI
379	400	#define CONFIG_NET_MULTI