hrcon: Add support for the DH variant

hrcon DH(dual head) has two video outputs per FPGA. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>

hrcon: Add support for the DH variant
hrcon DH(dual head) has two video outputs per FPGA. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc>
Dirk Eibach · Tom Rini
1 parent b847f5b622
Showing 7 changed files with 225 additions and 37 deletions Side-by-side Diff
board/gdsys/common/osd.c
board/gdsys/mpc8308/MAINTAINERS
board/gdsys/mpc8308/hrcon.c
configs/hrcon_dh_defconfig
drivers/i2c/soft_i2c.c
include/configs/hrcon.h
include/gdsys_fpga.h
@@ -28,12 +28,45 @@
  
 #define PIXCLK_640_480_60 25180000
  
+#ifdef CONFIG_SYS_OSD_DH
+#define MAX_OSD_SCREEN 8
+#define OSD_DH_BASE 4
+#else
+#define MAX_OSD_SCREEN 4
+#endif
+
+#ifdef CONFIG_SYS_OSD_DH
+#define OSD_SET_REG(screen, fld, val) \
+	do { \
+		if (screen >= OSD_DH_BASE) \
+			FPGA_SET_REG(screen - OSD_DH_BASE, osd1.fld, val); \
+		else \
+			FPGA_SET_REG(screen, osd0.fld, val); \
+	} while (0)
+#else
+#define OSD_SET_REG(screen, fld, val) \
+		FPGA_SET_REG(screen, osd0.fld, val)
+#endif
+
+#ifdef CONFIG_SYS_OSD_DH
+#define OSD_GET_REG(screen, fld, val) \
+	do {					\
+		if (screen >= OSD_DH_BASE) \
+			FPGA_GET_REG(screen - OSD_DH_BASE, osd1.fld, val); \
+		else \
+			FPGA_GET_REG(screen, osd0.fld, val); \
+	} while (0)
+#else
+#define OSD_GET_REG(screen, fld, val) \
+		FPGA_GET_REG(screen, osd0.fld, val)
+#endif
+
 unsigned int base_width;
 unsigned int base_height;
 size_t bufsize;
 u16 *buf;
  
-unsigned int max_osd_screen = CONFIG_SYS_OSD_SCREENS - 1;
+unsigned int osd_screen_mask = 0;
  
 #ifdef CONFIG_SYS_ICS8N3QV01_I2C
 int ics8n3qv01_i2c[] = CONFIG_SYS_ICS8N3QV01_I2C;
@@ -47,6 +80,9 @@
 int dp501_i2c[] = CONFIG_SYS_DP501_I2C;
 #endif
  
+#ifdef CONFIG_SYS_DP501_BASE
+int dp501_base[] = CONFIG_SYS_DP501_BASE;
+#endif
  
 #ifdef CONFIG_SYS_MPC92469AC
 static void mpc92469ac_calc_parameters(unsigned int fout,
@@ -216,7 +252,15 @@
 	for (k = 0; k < charcount; ++k) {
 		if (offset + k >= bufsize)
 			return -1;
-		FPGA_SET_REG(screen, videomem[offset + k], data[k]);
+#ifdef CONFIG_SYS_OSD_DH
+		if (screen >= OSD_DH_BASE)
+			FPGA_SET_REG(screen - OSD_DH_BASE,
+				     videomem1[offset + k], data[k]);
+		else
+			FPGA_SET_REG(screen, videomem0[offset + k], data[k]);
+#else
+		FPGA_SET_REG(screen, videomem0[offset + k], data[k]);
+#endif
 	}
  
 	return charcount;
@@ -226,7 +270,12 @@
 {
 	unsigned screen;
  
-	for (screen = 0; screen <= max_osd_screen; ++screen) {
+	if (argc < 5) {
+		cmd_usage(cmdtp);
+		return 1;
+	}
+
+	for (screen = 0; screen < MAX_OSD_SCREEN; ++screen) {
 		unsigned x;
 		unsigned y;
 		unsigned charcount;
@@ -236,10 +285,8 @@
 		char *text;
 		int res;
  
-		if (argc < 5) {
-			cmd_usage(cmdtp);
-			return 1;
-		}
+		if (!(osd_screen_mask & (1 << screen)))
+			continue;
  
 		x = simple_strtoul(argv[1], NULL, 16);
 		y = simple_strtoul(argv[2], NULL, 16);
  
@@ -266,9 +313,16 @@
 	int old_bus = i2c_get_bus_num();
 	bool pixclock_present = false;
 	bool output_driver_present = false;
+#ifdef CONFIG_SYS_DP501_I2C
+#ifdef CONFIG_SYS_DP501_BASE
+	uint8_t dp501_addr = dp501_base[screen];
+#else
+	uint8_t dp501_addr = DP501_I2C_ADDR;
+#endif
+#endif
  
-	FPGA_GET_REG(0, osd.version, &version);
-	FPGA_GET_REG(0, osd.features, &features);
+	OSD_GET_REG(0, version, &version);
+	OSD_GET_REG(0, features, &features);
  
 	base_width = ((features & 0x3f00) >> 8) + 1;
 	base_height = (features & 0x001f) + 1;
  
@@ -277,9 +331,15 @@
 	if (!buf)
 		return -1;
  
+#ifdef CONFIG_SYS_OSD_DH
+	printf("OSD%d-%d: Digital-OSD version %01d.%02d, %d" "x%d characters\n",
+	       (screen >= OSD_DH_BASE) ? (screen - OSD_DH_BASE) : screen,
+	       (screen > 3) ? 1 : 0, version/100, version%100, base_width,
+	       base_height);
+#else
 	printf("OSD%d:  Digital-OSD version %01d.%02d, %d" "x%d characters\n",
-		screen, version/100, version%100, base_width, base_height);
-
+	       screen, version/100, version%100, base_width, base_height);
+#endif
 	/* setup pixclock */
  
 #ifdef CONFIG_SYS_MPC92469AC
@@ -330,8 +390,8 @@
  
 #ifdef CONFIG_SYS_DP501_I2C
 	i2c_set_bus_num(dp501_i2c[screen]);
-	if (!i2c_probe(DP501_I2C_ADDR)) {
-		dp501_powerup(DP501_I2C_ADDR);
+	if (!i2c_probe(dp501_addr)) {
+		dp501_powerup(dp501_addr);
 		output_driver_present = true;
 	}
 #endif
  
  
@@ -339,14 +399,14 @@
 	if (!output_driver_present)
 		printf("       no output driver found\n");
  
-	FPGA_SET_REG(screen, osd.control, 0x0049);
+	OSD_SET_REG(screen, control, 0x0049);
  
-	FPGA_SET_REG(screen, osd.xy_size, ((32 - 1) << 8) | (16 - 1));
-	FPGA_SET_REG(screen, osd.x_pos, 0x007f);
-	FPGA_SET_REG(screen, osd.y_pos, 0x005f);
+	OSD_SET_REG(screen, xy_size, ((32 - 1) << 8) | (16 - 1));
+	OSD_SET_REG(screen, x_pos, 0x007f);
+	OSD_SET_REG(screen, y_pos, 0x005f);
  
-	if (screen > max_osd_screen)
-		max_osd_screen = screen;
+	if (pixclock_present && output_driver_present)
+		osd_screen_mask |= 1 << screen;
  
 	i2c_set_bus_num(old_bus);
  
@@ -357,7 +417,12 @@
 {
 	unsigned screen;
  
-	for (screen = 0; screen <= max_osd_screen; ++screen) {
+	if ((argc < 4) || (strlen(argv[3]) % 4)) {
+		cmd_usage(cmdtp);
+		return 1;
+	}
+
+	for (screen = 0; screen < MAX_OSD_SCREEN; ++screen) {
 		unsigned x;
 		unsigned y;
 		unsigned k;
@@ -367,10 +432,8 @@
 		unsigned count = (argc > 4) ?
 			simple_strtoul(argv[4], NULL, 16) : 1;
  
-		if ((argc < 4) || (strlen(argv[3]) % 4)) {
-			cmd_usage(cmdtp);
-			return 1;
-		}
+		if (!(osd_screen_mask & (1 << screen)))
+			continue;
  
 		x = simple_strtoul(argv[1], NULL, 16);
 		y = simple_strtoul(argv[2], NULL, 16);
@@ -4,6 +4,7 @@
 F:	board/gdsys/mpc8308/
 F:	include/configs/hrcon.h
 F:	configs/hrcon_defconfig
+F:	configs/hrcon_dh_defconfig
 F:	include/configs/strider.h
 F:	configs/strider_cpu_defconfig
 F:	configs/strider_con_defconfig
@@ -128,6 +128,7 @@
  
 	/* Turn on Parade DP501 */
 	pca9698_direction_output(0x20, 10, 1);
+	pca9698_direction_output(0x20, 11, 1);
  
 	ch0_rgmii2_present = !pca9698_get_value(0x20, 30);
  
@@ -174,6 +175,9 @@
  
 	ioep_fpga_print_info(0);
 	osd_probe(0);
+#ifdef CONFIG_SYS_OSD_DH
+	osd_probe(4);
+#endif
  
 	if (slaves <= 0)
 		return 0;
@@ -185,6 +189,9 @@
  
 		ioep_fpga_print_info(k);
 		osd_probe(k);
+#ifdef CONFIG_SYS_OSD_DH
+		osd_probe(k + 4);
+#endif
 		if (hw_type_cat) {
 			miiphy_register(bb_miiphy_buses[k].name,
 					bb_miiphy_read, bb_miiphy_write);
  
  
  
  
@@ -196,26 +203,42 @@
 }
  
 /*
- * provide access to fpga gpios (for I2C bitbang)
+ * provide access to fpga gpios and controls (for I2C bitbang)
  * (these may look all too simple but make iocon.h much more readable)
  */
 void fpga_gpio_set(unsigned int bus, int pin)
 {
-	FPGA_SET_REG(bus, gpio.set, pin);
+	FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, gpio.set, pin);
 }
  
 void fpga_gpio_clear(unsigned int bus, int pin)
 {
-	FPGA_SET_REG(bus, gpio.clear, pin);
+	FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, gpio.clear, pin);
 }
  
 int fpga_gpio_get(unsigned int bus, int pin)
 {
 	u16 val;
  
-	FPGA_GET_REG(bus, gpio.read, &val);
+	FPGA_GET_REG(bus >= 4 ? (bus - 4) : bus, gpio.read, &val);
  
 	return val & pin;
+}
+
+void fpga_control_set(unsigned int bus, int pin)
+{
+	u16 val;
+
+	FPGA_GET_REG(bus >= 4 ? (bus - 4) : bus, control, &val);
+	FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, control, val | pin);
+}
+
+void fpga_control_clear(unsigned int bus, int pin)
+{
+	u16 val;
+
+	FPGA_GET_REG(bus >= 4 ? (bus - 4) : bus, control, &val);
+	FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, control, val & ~pin);
 }
  
 void mpc8308_init(void)
+CONFIG_SYS_EXTRA_OPTIONS="HRCON_DH"
+
+CONFIG_PPC=y
+CONFIG_MPC83xx=y
+CONFIG_TARGET_HRCON=y
@@ -473,4 +473,32 @@
 			 CONFIG_SYS_I2C_SOFT_SLAVE_4,
 			 3)
 #endif
+#if defined(I2C_SOFT_DECLARATIONS5)
+U_BOOT_I2C_ADAP_COMPLETE(soft4, soft_i2c_init, soft_i2c_probe,
+			 soft_i2c_read, soft_i2c_write, NULL,
+			 CONFIG_SYS_I2C_SOFT_SPEED_5,
+			 CONFIG_SYS_I2C_SOFT_SLAVE_5,
+			 4)
+#endif
+#if defined(I2C_SOFT_DECLARATIONS6)
+U_BOOT_I2C_ADAP_COMPLETE(soft5, soft_i2c_init, soft_i2c_probe,
+			 soft_i2c_read, soft_i2c_write, NULL,
+			 CONFIG_SYS_I2C_SOFT_SPEED_6,
+			 CONFIG_SYS_I2C_SOFT_SLAVE_6,
+			 5)
+#endif
+#if defined(I2C_SOFT_DECLARATIONS7)
+U_BOOT_I2C_ADAP_COMPLETE(soft6, soft_i2c_init, soft_i2c_probe,
+			 soft_i2c_read, soft_i2c_write, NULL,
+			 CONFIG_SYS_I2C_SOFT_SPEED_7,
+			 CONFIG_SYS_I2C_SOFT_SLAVE_7,
+			 6)
+#endif
+#if defined(I2C_SOFT_DECLARATIONS8)
+U_BOOT_I2C_ADAP_COMPLETE(soft7, soft_i2c_init, soft_i2c_probe,
+			 soft_i2c_read, soft_i2c_write, NULL,
+			 CONFIG_SYS_I2C_SOFT_SPEED_8,
+			 CONFIG_SYS_I2C_SOFT_SLAVE_8,
+			 7)
+#endif
@@ -20,7 +20,11 @@
  
 #define	CONFIG_SYS_TEXT_BASE	0xFE000000
  
+#ifdef CONFIG_HRCON_DH
+#define CONFIG_IDENT_STRING	" hrcon dh 0.01"
+#else
 #define CONFIG_IDENT_STRING	" hrcon 0.01"
+#endif
  
  
 #define CONFIG_BOARD_EARLY_INIT_F
@@ -343,6 +347,22 @@
 #define CONFIG_SYS_I2C_IHS_SPEED_3		50000
 #define CONFIG_SYS_I2C_IHS_SLAVE_3		0x7F
  
+#ifdef CONFIG_HRCON_DH
+#define CONFIG_SYS_I2C_IHS_DUAL
+#define CONFIG_SYS_I2C_IHS_CH0_1
+#define CONFIG_SYS_I2C_IHS_SPEED_0_1		50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_0_1		0x7F
+#define CONFIG_SYS_I2C_IHS_CH1_1
+#define CONFIG_SYS_I2C_IHS_SPEED_1_1		50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_1_1		0x7F
+#define CONFIG_SYS_I2C_IHS_CH2_1
+#define CONFIG_SYS_I2C_IHS_SPEED_2_1		50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_2_1		0x7F
+#define CONFIG_SYS_I2C_IHS_CH3_1
+#define CONFIG_SYS_I2C_IHS_SPEED_3_1		50000
+#define CONFIG_SYS_I2C_IHS_SLAVE_3_1		0x7F
+#endif
+
 /*
  * Software (bit-bang) I2C driver configuration
  */
  
  
  
  
@@ -359,16 +379,48 @@
 #define CONFIG_SYS_I2C_SOFT_SPEED_4		50000
 #define CONFIG_SYS_I2C_SOFT_SLAVE_4		0x7F
  
+#ifdef CONFIG_HRCON_DH
+#define I2C_SOFT_DECLARATIONS5
+#define CONFIG_SYS_I2C_SOFT_SPEED_5		50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_5		0x7F
+#define I2C_SOFT_DECLARATIONS6
+#define CONFIG_SYS_I2C_SOFT_SPEED_6		50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_6		0x7F
+#define I2C_SOFT_DECLARATIONS7
+#define CONFIG_SYS_I2C_SOFT_SPEED_7		50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_7		0x7F
+#define I2C_SOFT_DECLARATIONS8
+#define CONFIG_SYS_I2C_SOFT_SPEED_8		50000
+#define CONFIG_SYS_I2C_SOFT_SLAVE_8		0x7F
+#endif
+
+#ifdef CONFIG_HRCON_DH
+#define CONFIG_SYS_ICS8N3QV01_I2C		{9, 10, 11, 12, 13, 14, 15, 16}
+#define CONFIG_SYS_DP501_I2C			{1, 3, 5, 7, 2, 4, 6, 8}
+#else
 #define CONFIG_SYS_ICS8N3QV01_I2C		{5, 6, 7, 8}
 #define CONFIG_SYS_DP501_I2C			{1, 2, 3, 4}
+#endif
  
 #ifndef __ASSEMBLY__
 void fpga_gpio_set(unsigned int bus, int pin);
 void fpga_gpio_clear(unsigned int bus, int pin);
 int fpga_gpio_get(unsigned int bus, int pin);
+void fpga_control_set(unsigned int bus, int pin);
+void fpga_control_clear(unsigned int bus, int pin);
 #endif
  
+#ifdef CONFIG_HRCON_DH
+#define I2C_ACTIVE \
+	do { \
+		if (I2C_ADAP_HWNR > 3) \
+			fpga_control_set(I2C_ADAP_HWNR, 0x0004); \
+		else \
+			fpga_control_clear(I2C_ADAP_HWNR, 0x0004); \
+	} while (0)
+#else
 #define I2C_ACTIVE	{ }
+#endif
 #define I2C_TRISTATE	{ }
 #define I2C_READ \
 	(fpga_gpio_get(I2C_ADAP_HWNR, 0x0040) ? 1 : 0)
@@ -400,6 +452,10 @@
 #define CONFIG_SYS_OSD_SCREENS		1
 #define CONFIG_SYS_DP501_DIFFERENTIAL
 #define CONFIG_SYS_DP501_VCAPCTRL0	0x01 /* DDR mode 0, DE for H/VSYNC */
+
+#ifdef CONFIG_HRCON_DH
+#define CONFIG_SYS_OSD_DH
+#endif
  
 /*
  * General PCI
@@ -157,9 +157,9 @@
 	u16 mc_rx_data;		/* 0x0072 */
 	u16 reserved_5[69];	/* 0x0074 */
 	u16 reflection_high;	/* 0x00fe */
-	struct ihs_osd osd;	/* 0x0100 */
+	struct ihs_osd osd0;	/* 0x0100 */
 	u16 reserved_6[889];	/* 0x010e */
-	u16 videomem[31736];	/* 0x0800 */
+	u16 videomem0[2048];	/* 0x0800 */
 };
 #endif
  
@@ -171,7 +171,9 @@
 	u16 fpga_features;	/* 0x0006 */
 	u16 reserved_0[1];	/* 0x0008 */
 	u16 top_interrupt;	/* 0x000a */
-	u16 reserved_1[4];	/* 0x000c */
+	u16 reserved_1[2];	/* 0x000c */
+	u16 control;		/* 0x0010 */
+	u16 extended_control;	/* 0x0012 */
 	struct ihs_gpio gpio;	/* 0x0014 */
 	u16 mpc3w_control;	/* 0x001a */
 	u16 reserved_2[2];	/* 0x001c */
  
@@ -191,9 +193,19 @@
 	u16 mc_rx_data;		/* 0x0072 */
 	u16 reserved_5[69];	/* 0x0074 */
 	u16 reflection_high;	/* 0x00fe */
-	struct ihs_osd osd;	/* 0x0100 */
+	struct ihs_osd osd0;	/* 0x0100 */
+#ifdef CONFIG_SYS_OSD_DH
+	u16 reserved_6[57];	/* 0x010e */
+	struct ihs_osd osd1;	/* 0x0180 */
+	u16 reserved_7[9];	/* 0x018e */
+	struct ihs_i2c i2c1;	/* 0x01a0 */
+	u16 reserved_8[1834];	/* 0x01ac */
+	u16 videomem0[2048];	/* 0x1000 */
+	u16 videomem1[2048];	/* 0x2000 */
+#else
 	u16 reserved_6[889];	/* 0x010e */
-	u16 videomem[31736];	/* 0x0800 */
+	u16 videomem0[2048];	/* 0x0800 */
+#endif
 };
 #endif
  
  
@@ -254,9 +266,9 @@
 	u16 mc_rx_cmd_status;	/* 0x0070 */
 	u16 mc_rx_data;		/* 0x0072 */
 	u16 reserved_5[70];	/* 0x0074 */
-	struct ihs_osd osd;	/* 0x0100 */
+	struct ihs_osd osd0;	/* 0x0100 */
 	u16 reserved_6[889];	/* 0x010e */
-	u16 videomem[31736];	/* 0x0800 */
+	u16 videomem0[2048];	/* 0x0800 */
 };
 #endif
  
  
@@ -275,9 +287,9 @@
 	u16 reserved_3[2];	/* 0x006c */
 	struct ihs_i2c i2c1;	/* 0x0070 */
 	u16 reserved_4[194];	/* 0x007c */
-	struct ihs_osd osd;	/* 0x0200 */
+	struct ihs_osd osd0;	/* 0x0200 */
 	u16 reserved_5[761];	/* 0x020e */
-	u16 videomem[31736];	/* 0x0800 */
+	u16 videomem0[2048];	/* 0x0800 */
 };
 #endif
...	...	@@ -28,12 +28,45 @@
28	28
29	29	#define PIXCLK_640_480_60 25180000
30	30
	31	+#ifdef CONFIG_SYS_OSD_DH
	32	+#define MAX_OSD_SCREEN 8
	33	+#define OSD_DH_BASE 4
	34	+#else
	35	+#define MAX_OSD_SCREEN 4
	36	+#endif
	37	+
	38	+#ifdef CONFIG_SYS_OSD_DH
	39	+#define OSD_SET_REG(screen, fld, val) \
	40	+ do { \
	41	+ if (screen >= OSD_DH_BASE) \
	42	+ FPGA_SET_REG(screen - OSD_DH_BASE, osd1.fld, val); \
	43	+ else \
	44	+ FPGA_SET_REG(screen, osd0.fld, val); \
	45	+ } while (0)
	46	+#else
	47	+#define OSD_SET_REG(screen, fld, val) \
	48	+ FPGA_SET_REG(screen, osd0.fld, val)
	49	+#endif
	50	+
	51	+#ifdef CONFIG_SYS_OSD_DH
	52	+#define OSD_GET_REG(screen, fld, val) \
	53	+ do { \
	54	+ if (screen >= OSD_DH_BASE) \
	55	+ FPGA_GET_REG(screen - OSD_DH_BASE, osd1.fld, val); \
	56	+ else \
	57	+ FPGA_GET_REG(screen, osd0.fld, val); \
	58	+ } while (0)
	59	+#else
	60	+#define OSD_GET_REG(screen, fld, val) \
	61	+ FPGA_GET_REG(screen, osd0.fld, val)
	62	+#endif
	63	+
31	64	unsigned int base_width;
32	65	unsigned int base_height;
33	66	size_t bufsize;
34	67	u16 *buf;
35	68
36		-unsigned int max_osd_screen = CONFIG_SYS_OSD_SCREENS - 1;
	69	+unsigned int osd_screen_mask = 0;
37	70
38	71	#ifdef CONFIG_SYS_ICS8N3QV01_I2C
39	72	int ics8n3qv01_i2c[] = CONFIG_SYS_ICS8N3QV01_I2C;
...	...	@@ -47,6 +80,9 @@
47	80	int dp501_i2c[] = CONFIG_SYS_DP501_I2C;
48	81	#endif
49	82
	83	+#ifdef CONFIG_SYS_DP501_BASE
	84	+int dp501_base[] = CONFIG_SYS_DP501_BASE;
	85	+#endif
50	86
51	87	#ifdef CONFIG_SYS_MPC92469AC
52	88	static void mpc92469ac_calc_parameters(unsigned int fout,
...	...	@@ -216,7 +252,15 @@
216	252	for (k = 0; k < charcount; ++k) {
217	253	if (offset + k >= bufsize)
218	254	return -1;
219		- FPGA_SET_REG(screen, videomem[offset + k], data[k]);
	255	+#ifdef CONFIG_SYS_OSD_DH
	256	+ if (screen >= OSD_DH_BASE)
	257	+ FPGA_SET_REG(screen - OSD_DH_BASE,
	258	+ videomem1[offset + k], data[k]);
	259	+ else
	260	+ FPGA_SET_REG(screen, videomem0[offset + k], data[k]);
	261	+#else
	262	+ FPGA_SET_REG(screen, videomem0[offset + k], data[k]);
	263	+#endif
220	264	}
221	265
222	266	return charcount;
...	...	@@ -226,7 +270,12 @@
226	270	{
227	271	unsigned screen;
228	272
229		- for (screen = 0; screen <= max_osd_screen; ++screen) {
	273	+ if (argc < 5) {
	274	+ cmd_usage(cmdtp);
	275	+ return 1;
	276	+ }
	277	+
	278	+ for (screen = 0; screen < MAX_OSD_SCREEN; ++screen) {
230	279	unsigned x;
231	280	unsigned y;
232	281	unsigned charcount;
...	...	@@ -236,10 +285,8 @@
236	285	char *text;
237	286	int res;
238	287
239		- if (argc < 5) {
240		- cmd_usage(cmdtp);
241		- return 1;
242		- }
	288	+ if (!(osd_screen_mask & (1 << screen)))
	289	+ continue;
243	290
244	291	x = simple_strtoul(argv[1], NULL, 16);
245	292	y = simple_strtoul(argv[2], NULL, 16);
246	293
...	...	@@ -266,9 +313,16 @@
266	313	int old_bus = i2c_get_bus_num();
267	314	bool pixclock_present = false;
268	315	bool output_driver_present = false;
	316	+#ifdef CONFIG_SYS_DP501_I2C
	317	+#ifdef CONFIG_SYS_DP501_BASE
	318	+ uint8_t dp501_addr = dp501_base[screen];
	319	+#else
	320	+ uint8_t dp501_addr = DP501_I2C_ADDR;
	321	+#endif
	322	+#endif
269	323
270		- FPGA_GET_REG(0, osd.version, &version);
271		- FPGA_GET_REG(0, osd.features, &features);
	324	+ OSD_GET_REG(0, version, &version);
	325	+ OSD_GET_REG(0, features, &features);
272	326
273	327	base_width = ((features & 0x3f00) >> 8) + 1;
274	328	base_height = (features & 0x001f) + 1;
275	329
...	...	@@ -277,9 +331,15 @@
277	331	if (!buf)
278	332	return -1;
279	333
	334	+#ifdef CONFIG_SYS_OSD_DH
	335	+ printf("OSD%d-%d: Digital-OSD version %01d.%02d, %d" "x%d characters\n",
	336	+ (screen >= OSD_DH_BASE) ? (screen - OSD_DH_BASE) : screen,
	337	+ (screen > 3) ? 1 : 0, version/100, version%100, base_width,
	338	+ base_height);
	339	+#else
280	340	printf("OSD%d: Digital-OSD version %01d.%02d, %d" "x%d characters\n",
281		- screen, version/100, version%100, base_width, base_height);
282		-
	341	+ screen, version/100, version%100, base_width, base_height);
	342	+#endif
283	343	/* setup pixclock */
284	344
285	345	#ifdef CONFIG_SYS_MPC92469AC
...	...	@@ -330,8 +390,8 @@
330	390
331	391	#ifdef CONFIG_SYS_DP501_I2C
332	392	i2c_set_bus_num(dp501_i2c[screen]);
333		- if (!i2c_probe(DP501_I2C_ADDR)) {
334		- dp501_powerup(DP501_I2C_ADDR);
	393	+ if (!i2c_probe(dp501_addr)) {
	394	+ dp501_powerup(dp501_addr);
335	395	output_driver_present = true;
336	396	}
337	397	#endif
338	398
339	399
...	...	@@ -339,14 +399,14 @@
339	399	if (!output_driver_present)
340	400	printf(" no output driver found\n");
341	401
342		- FPGA_SET_REG(screen, osd.control, 0x0049);
	402	+ OSD_SET_REG(screen, control, 0x0049);
343	403
344		- FPGA_SET_REG(screen, osd.xy_size, ((32 - 1) << 8) \| (16 - 1));
345		- FPGA_SET_REG(screen, osd.x_pos, 0x007f);
346		- FPGA_SET_REG(screen, osd.y_pos, 0x005f);
	404	+ OSD_SET_REG(screen, xy_size, ((32 - 1) << 8) \| (16 - 1));
	405	+ OSD_SET_REG(screen, x_pos, 0x007f);
	406	+ OSD_SET_REG(screen, y_pos, 0x005f);
347	407
348		- if (screen > max_osd_screen)
349		- max_osd_screen = screen;
	408	+ if (pixclock_present && output_driver_present)
	409	+ osd_screen_mask \|= 1 << screen;
350	410
351	411	i2c_set_bus_num(old_bus);
352	412
...	...	@@ -357,7 +417,12 @@
357	417	{
358	418	unsigned screen;
359	419
360		- for (screen = 0; screen <= max_osd_screen; ++screen) {
	420	+ if ((argc < 4) \|\| (strlen(argv[3]) % 4)) {
	421	+ cmd_usage(cmdtp);
	422	+ return 1;
	423	+ }
	424	+
	425	+ for (screen = 0; screen < MAX_OSD_SCREEN; ++screen) {
361	426	unsigned x;
362	427	unsigned y;
363	428	unsigned k;
...	...	@@ -367,10 +432,8 @@
367	432	unsigned count = (argc > 4) ?
368	433	simple_strtoul(argv[4], NULL, 16) : 1;
369	434
370		- if ((argc < 4) \|\| (strlen(argv[3]) % 4)) {
371		- cmd_usage(cmdtp);
372		- return 1;
373		- }
	435	+ if (!(osd_screen_mask & (1 << screen)))
	436	+ continue;
374	437
375	438	x = simple_strtoul(argv[1], NULL, 16);
376	439	y = simple_strtoul(argv[2], NULL, 16);
...	...	@@ -4,6 +4,7 @@
4	4	F: board/gdsys/mpc8308/
5	5	F: include/configs/hrcon.h
6	6	F: configs/hrcon_defconfig
	7	+F: configs/hrcon_dh_defconfig
7	8	F: include/configs/strider.h
8	9	F: configs/strider_cpu_defconfig
9	10	F: configs/strider_con_defconfig
...	...	@@ -128,6 +128,7 @@
128	128
129	129	/* Turn on Parade DP501 */
130	130	pca9698_direction_output(0x20, 10, 1);
	131	+ pca9698_direction_output(0x20, 11, 1);
131	132
132	133	ch0_rgmii2_present = !pca9698_get_value(0x20, 30);
133	134
...	...	@@ -174,6 +175,9 @@
174	175
175	176	ioep_fpga_print_info(0);
176	177	osd_probe(0);
	178	+#ifdef CONFIG_SYS_OSD_DH
	179	+ osd_probe(4);
	180	+#endif
177	181
178	182	if (slaves <= 0)
179	183	return 0;
...	...	@@ -185,6 +189,9 @@
185	189
186	190	ioep_fpga_print_info(k);
187	191	osd_probe(k);
	192	+#ifdef CONFIG_SYS_OSD_DH
	193	+ osd_probe(k + 4);
	194	+#endif
188	195	if (hw_type_cat) {
189	196	miiphy_register(bb_miiphy_buses[k].name,
190	197	bb_miiphy_read, bb_miiphy_write);
191	198
192	199
193	200
194	201
...	...	@@ -196,26 +203,42 @@
196	203	}
197	204
198	205	/*
199		- * provide access to fpga gpios (for I2C bitbang)
	206	+ * provide access to fpga gpios and controls (for I2C bitbang)
200	207	* (these may look all too simple but make iocon.h much more readable)
201	208	*/
202	209	void fpga_gpio_set(unsigned int bus, int pin)
203	210	{
204		- FPGA_SET_REG(bus, gpio.set, pin);
	211	+ FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, gpio.set, pin);
205	212	}
206	213
207	214	void fpga_gpio_clear(unsigned int bus, int pin)
208	215	{
209		- FPGA_SET_REG(bus, gpio.clear, pin);
	216	+ FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, gpio.clear, pin);
210	217	}
211	218
212	219	int fpga_gpio_get(unsigned int bus, int pin)
213	220	{
214	221	u16 val;
215	222
216		- FPGA_GET_REG(bus, gpio.read, &val);
	223	+ FPGA_GET_REG(bus >= 4 ? (bus - 4) : bus, gpio.read, &val);
217	224
218	225	return val & pin;
	226	+}
	227	+
	228	+void fpga_control_set(unsigned int bus, int pin)
	229	+{
	230	+ u16 val;
	231	+
	232	+ FPGA_GET_REG(bus >= 4 ? (bus - 4) : bus, control, &val);
	233	+ FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, control, val \| pin);
	234	+}
	235	+
	236	+void fpga_control_clear(unsigned int bus, int pin)
	237	+{
	238	+ u16 val;
	239	+
	240	+ FPGA_GET_REG(bus >= 4 ? (bus - 4) : bus, control, &val);
	241	+ FPGA_SET_REG(bus >= 4 ? (bus - 4) : bus, control, val & ~pin);
219	242	}
220	243
221	244	void mpc8308_init(void)
	1	+CONFIG_SYS_EXTRA_OPTIONS="HRCON_DH"
	2	+
	3	+CONFIG_PPC=y
	4	+CONFIG_MPC83xx=y
	5	+CONFIG_TARGET_HRCON=y
...	...	@@ -473,4 +473,32 @@
473	473	CONFIG_SYS_I2C_SOFT_SLAVE_4,
474	474	3)
475	475	#endif
	476	+#if defined(I2C_SOFT_DECLARATIONS5)
	477	+U_BOOT_I2C_ADAP_COMPLETE(soft4, soft_i2c_init, soft_i2c_probe,
	478	+ soft_i2c_read, soft_i2c_write, NULL,
	479	+ CONFIG_SYS_I2C_SOFT_SPEED_5,
	480	+ CONFIG_SYS_I2C_SOFT_SLAVE_5,
	481	+ 4)
	482	+#endif
	483	+#if defined(I2C_SOFT_DECLARATIONS6)
	484	+U_BOOT_I2C_ADAP_COMPLETE(soft5, soft_i2c_init, soft_i2c_probe,
	485	+ soft_i2c_read, soft_i2c_write, NULL,
	486	+ CONFIG_SYS_I2C_SOFT_SPEED_6,
	487	+ CONFIG_SYS_I2C_SOFT_SLAVE_6,
	488	+ 5)
	489	+#endif
	490	+#if defined(I2C_SOFT_DECLARATIONS7)
	491	+U_BOOT_I2C_ADAP_COMPLETE(soft6, soft_i2c_init, soft_i2c_probe,
	492	+ soft_i2c_read, soft_i2c_write, NULL,
	493	+ CONFIG_SYS_I2C_SOFT_SPEED_7,
	494	+ CONFIG_SYS_I2C_SOFT_SLAVE_7,
	495	+ 6)
	496	+#endif
	497	+#if defined(I2C_SOFT_DECLARATIONS8)
	498	+U_BOOT_I2C_ADAP_COMPLETE(soft7, soft_i2c_init, soft_i2c_probe,
	499	+ soft_i2c_read, soft_i2c_write, NULL,
	500	+ CONFIG_SYS_I2C_SOFT_SPEED_8,
	501	+ CONFIG_SYS_I2C_SOFT_SLAVE_8,
	502	+ 7)
	503	+#endif
...	...	@@ -20,7 +20,11 @@
20	20
21	21	#define CONFIG_SYS_TEXT_BASE 0xFE000000
22	22
	23	+#ifdef CONFIG_HRCON_DH
	24	+#define CONFIG_IDENT_STRING " hrcon dh 0.01"
	25	+#else
23	26	#define CONFIG_IDENT_STRING " hrcon 0.01"
	27	+#endif
24	28
25	29
26	30	#define CONFIG_BOARD_EARLY_INIT_F
...	...	@@ -343,6 +347,22 @@
343	347	#define CONFIG_SYS_I2C_IHS_SPEED_3 50000
344	348	#define CONFIG_SYS_I2C_IHS_SLAVE_3 0x7F
345	349
	350	+#ifdef CONFIG_HRCON_DH
	351	+#define CONFIG_SYS_I2C_IHS_DUAL
	352	+#define CONFIG_SYS_I2C_IHS_CH0_1
	353	+#define CONFIG_SYS_I2C_IHS_SPEED_0_1 50000
	354	+#define CONFIG_SYS_I2C_IHS_SLAVE_0_1 0x7F
	355	+#define CONFIG_SYS_I2C_IHS_CH1_1
	356	+#define CONFIG_SYS_I2C_IHS_SPEED_1_1 50000
	357	+#define CONFIG_SYS_I2C_IHS_SLAVE_1_1 0x7F
	358	+#define CONFIG_SYS_I2C_IHS_CH2_1
	359	+#define CONFIG_SYS_I2C_IHS_SPEED_2_1 50000
	360	+#define CONFIG_SYS_I2C_IHS_SLAVE_2_1 0x7F
	361	+#define CONFIG_SYS_I2C_IHS_CH3_1
	362	+#define CONFIG_SYS_I2C_IHS_SPEED_3_1 50000
	363	+#define CONFIG_SYS_I2C_IHS_SLAVE_3_1 0x7F
	364	+#endif
	365	+
346	366	/*
347	367	* Software (bit-bang) I2C driver configuration
348	368	*/
349	369
350	370
351	371
352	372
...	...	@@ -359,16 +379,48 @@
359	379	#define CONFIG_SYS_I2C_SOFT_SPEED_4 50000
360	380	#define CONFIG_SYS_I2C_SOFT_SLAVE_4 0x7F
361	381
	382	+#ifdef CONFIG_HRCON_DH
	383	+#define I2C_SOFT_DECLARATIONS5
	384	+#define CONFIG_SYS_I2C_SOFT_SPEED_5 50000
	385	+#define CONFIG_SYS_I2C_SOFT_SLAVE_5 0x7F
	386	+#define I2C_SOFT_DECLARATIONS6
	387	+#define CONFIG_SYS_I2C_SOFT_SPEED_6 50000
	388	+#define CONFIG_SYS_I2C_SOFT_SLAVE_6 0x7F
	389	+#define I2C_SOFT_DECLARATIONS7
	390	+#define CONFIG_SYS_I2C_SOFT_SPEED_7 50000
	391	+#define CONFIG_SYS_I2C_SOFT_SLAVE_7 0x7F
	392	+#define I2C_SOFT_DECLARATIONS8
	393	+#define CONFIG_SYS_I2C_SOFT_SPEED_8 50000
	394	+#define CONFIG_SYS_I2C_SOFT_SLAVE_8 0x7F
	395	+#endif
	396	+
	397	+#ifdef CONFIG_HRCON_DH
	398	+#define CONFIG_SYS_ICS8N3QV01_I2C {9, 10, 11, 12, 13, 14, 15, 16}
	399	+#define CONFIG_SYS_DP501_I2C {1, 3, 5, 7, 2, 4, 6, 8}
	400	+#else
362	401	#define CONFIG_SYS_ICS8N3QV01_I2C {5, 6, 7, 8}
363	402	#define CONFIG_SYS_DP501_I2C {1, 2, 3, 4}
	403	+#endif
364	404
365	405	#ifndef __ASSEMBLY__
366	406	void fpga_gpio_set(unsigned int bus, int pin);
367	407	void fpga_gpio_clear(unsigned int bus, int pin);
368	408	int fpga_gpio_get(unsigned int bus, int pin);
	409	+void fpga_control_set(unsigned int bus, int pin);
	410	+void fpga_control_clear(unsigned int bus, int pin);
369	411	#endif
370	412
	413	+#ifdef CONFIG_HRCON_DH
	414	+#define I2C_ACTIVE \
	415	+ do { \
	416	+ if (I2C_ADAP_HWNR > 3) \
	417	+ fpga_control_set(I2C_ADAP_HWNR, 0x0004); \
	418	+ else \
	419	+ fpga_control_clear(I2C_ADAP_HWNR, 0x0004); \
	420	+ } while (0)
	421	+#else
371	422	#define I2C_ACTIVE { }
	423	+#endif
372	424	#define I2C_TRISTATE { }
373	425	#define I2C_READ \
374	426	(fpga_gpio_get(I2C_ADAP_HWNR, 0x0040) ? 1 : 0)
...	...	@@ -400,6 +452,10 @@
400	452	#define CONFIG_SYS_OSD_SCREENS 1
401	453	#define CONFIG_SYS_DP501_DIFFERENTIAL
402	454	#define CONFIG_SYS_DP501_VCAPCTRL0 0x01 /* DDR mode 0, DE for H/VSYNC */
	455	+
	456	+#ifdef CONFIG_HRCON_DH
	457	+#define CONFIG_SYS_OSD_DH
	458	+#endif
403	459
404	460	/*
405	461	* General PCI
...	...	@@ -157,9 +157,9 @@
157	157	u16 mc_rx_data; /* 0x0072 */
158	158	u16 reserved_5[69]; /* 0x0074 */
159	159	u16 reflection_high; /* 0x00fe */
160		- struct ihs_osd osd; /* 0x0100 */
	160	+ struct ihs_osd osd0; /* 0x0100 */
161	161	u16 reserved_6[889]; /* 0x010e */
162		- u16 videomem[31736]; /* 0x0800 */
	162	+ u16 videomem0[2048]; /* 0x0800 */
163	163	};
164	164	#endif
165	165
...	...	@@ -171,7 +171,9 @@
171	171	u16 fpga_features; /* 0x0006 */
172	172	u16 reserved_0[1]; /* 0x0008 */
173	173	u16 top_interrupt; /* 0x000a */
174		- u16 reserved_1[4]; /* 0x000c */
	174	+ u16 reserved_1[2]; /* 0x000c */
	175	+ u16 control; /* 0x0010 */
	176	+ u16 extended_control; /* 0x0012 */
175	177	struct ihs_gpio gpio; /* 0x0014 */
176	178	u16 mpc3w_control; /* 0x001a */
177	179	u16 reserved_2[2]; /* 0x001c */
178	180
...	...	@@ -191,9 +193,19 @@
191	193	u16 mc_rx_data; /* 0x0072 */
192	194	u16 reserved_5[69]; /* 0x0074 */
193	195	u16 reflection_high; /* 0x00fe */
194		- struct ihs_osd osd; /* 0x0100 */
	196	+ struct ihs_osd osd0; /* 0x0100 */
	197	+#ifdef CONFIG_SYS_OSD_DH
	198	+ u16 reserved_6[57]; /* 0x010e */
	199	+ struct ihs_osd osd1; /* 0x0180 */
	200	+ u16 reserved_7[9]; /* 0x018e */
	201	+ struct ihs_i2c i2c1; /* 0x01a0 */
	202	+ u16 reserved_8[1834]; /* 0x01ac */
	203	+ u16 videomem0[2048]; /* 0x1000 */
	204	+ u16 videomem1[2048]; /* 0x2000 */
	205	+#else
195	206	u16 reserved_6[889]; /* 0x010e */
196		- u16 videomem[31736]; /* 0x0800 */
	207	+ u16 videomem0[2048]; /* 0x0800 */
	208	+#endif
197	209	};
198	210	#endif
199	211
200	212
...	...	@@ -254,9 +266,9 @@
254	266	u16 mc_rx_cmd_status; /* 0x0070 */
255	267	u16 mc_rx_data; /* 0x0072 */
256	268	u16 reserved_5[70]; /* 0x0074 */
257		- struct ihs_osd osd; /* 0x0100 */
	269	+ struct ihs_osd osd0; /* 0x0100 */
258	270	u16 reserved_6[889]; /* 0x010e */
259		- u16 videomem[31736]; /* 0x0800 */
	271	+ u16 videomem0[2048]; /* 0x0800 */
260	272	};
261	273	#endif
262	274
263	275
...	...	@@ -275,9 +287,9 @@
275	287	u16 reserved_3[2]; /* 0x006c */
276	288	struct ihs_i2c i2c1; /* 0x0070 */
277	289	u16 reserved_4[194]; /* 0x007c */
278		- struct ihs_osd osd; /* 0x0200 */
	290	+ struct ihs_osd osd0; /* 0x0200 */
279	291	u16 reserved_5[761]; /* 0x020e */
280		- u16 videomem[31736]; /* 0x0800 */
	292	+ u16 videomem0[2048]; /* 0x0800 */
281	293	};
282	294	#endif
283	295