Commit 7f36c88f64ee1affd4db78b2c2f4a616abceb84c
Committed by
Tom Rini
Tom Rini
1 parent
a5d439c2d3
Exists in
master
and in
53 other branches
ARM: DRA7xx: Update pinmux data
Updating pinmux data as specified in the latest DM Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Balaji T K <balajitk@ti.com>
Showing 2 changed files with 29 additions and 16 deletions Side-by-side Diff
arch/arm/include/asm/arch-omap5/mux_dra7xx.h
| ... | ... | @@ -28,11 +28,14 @@ |
| 28 | 28 | |
| 29 | 29 | #include <asm/types.h> |
| 30 | 30 | |
| 31 | +#define FSC (1 << 19) | |
| 32 | +#define SSC (0 << 19) | |
| 33 | + | |
| 31 | 34 | #define IEN (1 << 18) |
| 32 | 35 | #define IDIS (0 << 18) |
| 33 | 36 | |
| 34 | -#define PTU (3 << 16) | |
| 35 | -#define PTD (1 << 16) | |
| 37 | +#define PTU (1 << 17) | |
| 38 | +#define PTD (0 << 17) | |
| 36 | 39 | #define PEN (1 << 16) |
| 37 | 40 | #define PDIS (0 << 16) |
| 38 | 41 |
board/ti/dra7xx/mux_data.h
| ... | ... | @@ -29,20 +29,30 @@ |
| 29 | 29 | #include <asm/arch/mux_dra7xx.h> |
| 30 | 30 | |
| 31 | 31 | const struct pad_conf_entry core_padconf_array_essential[] = { |
| 32 | - {MMC1_CLK, (PTU | IEN | M0)}, /* MMC1_CLK */ | |
| 33 | - {MMC1_CMD, (PTU | IEN | M0)}, /* MMC1_CMD */ | |
| 34 | - {MMC1_DAT0, (PTU | IEN | M0)}, /* MMC1_DAT0 */ | |
| 35 | - {MMC1_DAT1, (PTU | IEN | M0)}, /* MMC1_DAT1 */ | |
| 36 | - {MMC1_DAT2, (PTU | IEN | M0)}, /* MMC1_DAT2 */ | |
| 37 | - {MMC1_DAT3, (PTU | IEN | M0)}, /* MMC1_DAT3 */ | |
| 38 | - {MMC1_SDCD, (PTU | IEN | M0)}, /* MMC1_SDCD */ | |
| 39 | - {MMC1_SDWP, (PTU | IEN | M0)}, /* MMC1_SDWP */ | |
| 40 | - {UART1_RXD, (PTU | IEN | M0)}, /* UART1_RXD */ | |
| 41 | - {UART1_TXD, (M0)}, /* UART1_TXD */ | |
| 42 | - {UART1_CTSN, (PTU | IEN | M0)}, /* UART1_CTSN */ | |
| 43 | - {UART1_RTSN, (M0)}, /* UART1_RTSN */ | |
| 44 | - {I2C1_SDA, (PTU | IEN | M0)}, /* I2C1_SDA */ | |
| 45 | - {I2C1_SCL, (PTU | IEN | M0)}, /* I2C1_SCL */ | |
| 32 | + {MMC1_CLK, (IEN | PTU | PDIS | M0)}, /* MMC1_CLK */ | |
| 33 | + {MMC1_CMD, (IEN | PTU | PDIS | M0)}, /* MMC1_CMD */ | |
| 34 | + {MMC1_DAT0, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT0 */ | |
| 35 | + {MMC1_DAT1, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT1 */ | |
| 36 | + {MMC1_DAT2, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT2 */ | |
| 37 | + {MMC1_DAT3, (IEN | PTU | PDIS | M0)}, /* MMC1_DAT3 */ | |
| 38 | + {MMC1_SDCD, (FSC | IEN | PTU | PDIS | M0)}, /* MMC1_SDCD */ | |
| 39 | + {MMC1_SDWP, (FSC | IEN | PTD | PEN | M14)}, /* MMC1_SDWP */ | |
| 40 | + {GPMC_A19, (IEN | PTU | PDIS | M1)}, /* mmc2_dat4 */ | |
| 41 | + {GPMC_A20, (IEN | PTU | PDIS | M1)}, /* mmc2_dat5 */ | |
| 42 | + {GPMC_A21, (IEN | PTU | PDIS | M1)}, /* mmc2_dat6 */ | |
| 43 | + {GPMC_A22, (IEN | PTU | PDIS | M1)}, /* mmc2_dat7 */ | |
| 44 | + {GPMC_A23, (IEN | PTU | PDIS | M1)}, /* mmc2_clk */ | |
| 45 | + {GPMC_A24, (IEN | PTU | PDIS | M1)}, /* mmc2_dat0 */ | |
| 46 | + {GPMC_A25, (IEN | PTU | PDIS | M1)}, /* mmc2_dat1 */ | |
| 47 | + {GPMC_A26, (IEN | PTU | PDIS | M1)}, /* mmc2_dat2 */ | |
| 48 | + {GPMC_A27, (IEN | PTU | PDIS | M1)}, /* mmc2_dat3 */ | |
| 49 | + {GPMC_CS1, (IEN | PTU | PDIS | M1)}, /* mmm2_cmd */ | |
| 50 | + {UART1_RXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_RXD */ | |
| 51 | + {UART1_TXD, (FSC | IEN | PTU | PDIS | M0)}, /* UART1_TXD */ | |
| 52 | + {UART1_CTSN, (IEN | PTU | PDIS | M3)}, /* UART1_CTSN */ | |
| 53 | + {UART1_RTSN, (IEN | PTU | PDIS | M3)}, /* UART1_RTSN */ | |
| 54 | + {I2C1_SDA, (IEN | PTU | PDIS | M0)}, /* I2C1_SDA */ | |
| 55 | + {I2C1_SCL, (IEN | PTU | PDIS | M0)}, /* I2C1_SCL */ | |
| 46 | 56 | }; |
| 47 | 57 | #endif /* _MUX_DATA_DRA7XX_H_ */ |