Eric Lee / smarc-uboot | Embedian Git Server

Commit 7f4fd26bf2068ad2732f77445fc4d13a9d7ab3aa

Authored by Simon Glass 2015-08-31 06:55:32 +0800

Exists in v2017.01-smarct4x and in 31 other branches

rockchip: rk3288: Add header files for PMU and GRF

PMU is the power management unit and GRF is the general register file. Both
are heavily used in U-Boot. Add header files with register definitions.

Signed-off-by: Simon Glass <sjg@chromium.org>

Showing 2 changed files with 857 additions and 0 deletions Side-by-side Diff

arch/arm/include/asm/arch-rockchip/grf_rk3288.h
arch/arm/include/asm/arch-rockchip/pmu_rk3288.h

arch/arm/include/asm/arch-rockchip/grf_rk3288.h

Diff comments View file @ 7f4fd26

	1	+/*
	2	+ * (C) Copyright 2015 Google, Inc
	3	+ * Copyright 2014 Rockchip Inc.
	4	+ *
	5	+ * SPDX-License-Identifier: GPL-2.0
	6	+ */
	7	+
	8	+#ifndef _ASM_ARCH_GRF_RK3288_H
	9	+#define _ASM_ARCH_GRF_RK3288_H
	10	+
	11	+struct rk3288_grf_gpio_lh {
	12	+ u32 l;
	13	+ u32 h;
	14	+};
	15	+
	16	+struct rk3288_grf {
	17	+ u32 reserved[3];
	18	+ u32 gpio1d_iomux;
	19	+ u32 gpio2a_iomux;
	20	+ u32 gpio2b_iomux;
	21	+
	22	+ u32 gpio2c_iomux;
	23	+ u32 reserved2;
	24	+ u32 gpio3a_iomux;
	25	+ u32 gpio3b_iomux;
	26	+
	27	+ u32 gpio3c_iomux;
	28	+ u32 gpio3dl_iomux;
	29	+ u32 gpio3dh_iomux;
	30	+ u32 gpio4al_iomux;
	31	+
	32	+ u32 gpio4ah_iomux;
	33	+ u32 gpio4bl_iomux;
	34	+ u32 reserved3;
	35	+ u32 gpio4c_iomux;
	36	+
	37	+ u32 gpio4d_iomux;
	38	+ u32 reserved4;
	39	+ u32 gpio5b_iomux;
	40	+ u32 gpio5c_iomux;
	41	+
	42	+ u32 reserved5;
	43	+ u32 gpio6a_iomux;
	44	+ u32 gpio6b_iomux;
	45	+ u32 gpio6c_iomux;
	46	+ u32 reserved6;
	47	+ u32 gpio7a_iomux;
	48	+ u32 gpio7b_iomux;
	49	+ u32 gpio7cl_iomux;
	50	+ u32 gpio7ch_iomux;
	51	+ u32 reserved7;
	52	+ u32 gpio8a_iomux;
	53	+ u32 gpio8b_iomux;
	54	+ u32 reserved8[30];
	55	+ struct rk3288_grf_gpio_lh gpio_sr[8];
	56	+ u32 gpio1_p[8][4];
	57	+ u32 gpio1_e[8][4];
	58	+ u32 gpio_smt;
	59	+ u32 soc_con0;
	60	+ u32 soc_con1;
	61	+ u32 soc_con2;
	62	+ u32 soc_con3;
	63	+ u32 soc_con4;
	64	+ u32 soc_con5;
	65	+ u32 soc_con6;
	66	+ u32 soc_con7;
	67	+ u32 soc_con8;
	68	+ u32 soc_con9;
	69	+ u32 soc_con10;
	70	+ u32 soc_con11;
	71	+ u32 soc_con12;
	72	+ u32 soc_con13;
	73	+ u32 soc_con14;
	74	+ u32 soc_status[22];
	75	+ u32 reserved9[2];
	76	+ u32 peridmac_con[4];
	77	+ u32 ddrc0_con0;
	78	+ u32 ddrc1_con0;
	79	+ u32 cpu_con[5];
	80	+ u32 reserved10[3];
	81	+ u32 cpu_status0;
	82	+ u32 reserved11;
	83	+ u32 uoc0_con[5];
	84	+ u32 uoc1_con[5];
	85	+ u32 uoc2_con[4];
	86	+ u32 uoc3_con[2];
	87	+ u32 uoc4_con[2];
	88	+ u32 pvtm_con[3];
	89	+ u32 pvtm_status[3];
	90	+ u32 io_vsel;
	91	+ u32 saradc_testbit;
	92	+ u32 tsadc_testbit_l;
	93	+ u32 tsadc_testbit_h;
	94	+ u32 os_reg[4];
	95	+ u32 reserved12;
	96	+ u32 soc_con15;
	97	+ u32 soc_con16;
	98	+};
	99	+
	100	+struct rk3288_sgrf {
	101	+ u32 soc_con0;
	102	+ u32 soc_con1;
	103	+ u32 soc_con2;
	104	+ u32 soc_con3;
	105	+ u32 soc_con4;
	106	+ u32 soc_con5;
	107	+ u32 reserved1[(0x20-0x18)/4];
	108	+ u32 busdmac_con[2];
	109	+ u32 reserved2[(0x40-0x28)/4];
	110	+ u32 cpu_con[3];
	111	+ u32 reserved3[(0x50-0x4c)/4];
	112	+ u32 soc_con6;
	113	+ u32 soc_con7;
	114	+ u32 soc_con8;
	115	+ u32 soc_con9;
	116	+ u32 soc_con10;
	117	+ u32 soc_con11;
	118	+ u32 soc_con12;
	119	+ u32 soc_con13;
	120	+ u32 soc_con14;
	121	+ u32 soc_con15;
	122	+ u32 soc_con16;
	123	+ u32 soc_con17;
	124	+ u32 soc_con18;
	125	+ u32 soc_con19;
	126	+ u32 soc_con20;
	127	+ u32 soc_con21;
	128	+ u32 reserved4[(0x100-0x90)/4];
	129	+ u32 soc_status[2];
	130	+ u32 reserved5[(0x120-0x108)/4];
	131	+ u32 fast_boot_addr;
	132	+};
	133	+
	134	+/* GRF_GPIO1D_IOMUX */
	135	+enum {
	136	+ GPIO1D3_SHIFT = 6,
	137	+ GPIO1D3_MASK = 1,
	138	+ GPIO1D3_GPIO = 0,
	139	+ GPIO1D3_LCDC0_DCLK,
	140	+
	141	+ GPIO1D2_SHIFT = 4,
	142	+ GPIO1D2_MASK = 1,
	143	+ GPIO1D2_GPIO = 0,
	144	+ GPIO1D2_LCDC0_DEN,
	145	+
	146	+ GPIO1D1_SHIFT = 2,
	147	+ GPIO1D1_MASK = 1,
	148	+ GPIO1D1_GPIO = 0,
	149	+ GPIO1D1_LCDC0_VSYNC,
	150	+
	151	+ GPIO1D0_SHIFT = 0,
	152	+ GPIO1D0_MASK = 1,
	153	+ GPIO1D0_GPIO = 0,
	154	+ GPIO1D0_LCDC0_HSYNC,
	155	+};
	156	+
	157	+/* GRF_GPIO2C_IOMUX */
	158	+enum {
	159	+ GPIO2C1_SHIFT = 2,
	160	+ GPIO2C1_MASK = 1,
	161	+ GPIO2C1_GPIO = 0,
	162	+ GPIO2C1_I2C3CAM_SDA,
	163	+
	164	+ GPIO2C0_SHIFT = 0,
	165	+ GPIO2C0_MASK = 1,
	166	+ GPIO2C0_GPIO = 0,
	167	+ GPIO2C0_I2C3CAM_SCL,
	168	+};
	169	+
	170	+/* GRF_GPIO3A_IOMUX */
	171	+enum {
	172	+ GPIO3A7_SHIFT = 14,
	173	+ GPIO3A7_MASK = 3,
	174	+ GPIO3A7_GPIO = 0,
	175	+ GPIO3A7_FLASH0_DATA7,
	176	+ GPIO3A7_EMMC_DATA7,
	177	+
	178	+ GPIO3A6_SHIFT = 12,
	179	+ GPIO3A6_MASK = 3,
	180	+ GPIO3A6_GPIO = 0,
	181	+ GPIO3A6_FLASH0_DATA6,
	182	+ GPIO3A6_EMMC_DATA6,
	183	+
	184	+ GPIO3A5_SHIFT = 10,
	185	+ GPIO3A5_MASK = 3,
	186	+ GPIO3A5_GPIO = 0,
	187	+ GPIO3A5_FLASH0_DATA5,
	188	+ GPIO3A5_EMMC_DATA5,
	189	+
	190	+ GPIO3A4_SHIFT = 8,
	191	+ GPIO3A4_MASK = 3,
	192	+ GPIO3A4_GPIO = 0,
	193	+ GPIO3A4_FLASH0_DATA4,
	194	+ GPIO3A4_EMMC_DATA4,
	195	+
	196	+ GPIO3A3_SHIFT = 6,
	197	+ GPIO3A3_MASK = 3,
	198	+ GPIO3A3_GPIO = 0,
	199	+ GPIO3A3_FLASH0_DATA3,
	200	+ GPIO3A3_EMMC_DATA3,
	201	+
	202	+ GPIO3A2_SHIFT = 4,
	203	+ GPIO3A2_MASK = 3,
	204	+ GPIO3A2_GPIO = 0,
	205	+ GPIO3A2_FLASH0_DATA2,
	206	+ GPIO3A2_EMMC_DATA2,
	207	+
	208	+ GPIO3A1_SHIFT = 2,
	209	+ GPIO3A1_MASK = 3,
	210	+ GPIO3A1_GPIO = 0,
	211	+ GPIO3A1_FLASH0_DATA1,
	212	+ GPIO3A1_EMMC_DATA1,
	213	+
	214	+ GPIO3A0_SHIFT = 0,
	215	+ GPIO3A0_MASK = 3,
	216	+ GPIO3A0_GPIO = 0,
	217	+ GPIO3A0_FLASH0_DATA0,
	218	+ GPIO3A0_EMMC_DATA0,
	219	+};
	220	+
	221	+/* GRF_GPIO3B_IOMUX */
	222	+enum {
	223	+ GPIO3B7_SHIFT = 14,
	224	+ GPIO3B7_MASK = 1,
	225	+ GPIO3B7_GPIO = 0,
	226	+ GPIO3B7_FLASH0_CSN1,
	227	+
	228	+ GPIO3B6_SHIFT = 12,
	229	+ GPIO3B6_MASK = 1,
	230	+ GPIO3B6_GPIO = 0,
	231	+ GPIO3B6_FLASH0_CSN0,
	232	+
	233	+ GPIO3B5_SHIFT = 10,
	234	+ GPIO3B5_MASK = 1,
	235	+ GPIO3B5_GPIO = 0,
	236	+ GPIO3B5_FLASH0_WRN,
	237	+
	238	+ GPIO3B4_SHIFT = 8,
	239	+ GPIO3B4_MASK = 1,
	240	+ GPIO3B4_GPIO = 0,
	241	+ GPIO3B4_FLASH0_CLE,
	242	+
	243	+ GPIO3B3_SHIFT = 6,
	244	+ GPIO3B3_MASK = 1,
	245	+ GPIO3B3_GPIO = 0,
	246	+ GPIO3B3_FLASH0_ALE,
	247	+
	248	+ GPIO3B2_SHIFT = 4,
	249	+ GPIO3B2_MASK = 1,
	250	+ GPIO3B2_GPIO = 0,
	251	+ GPIO3B2_FLASH0_RDN,
	252	+
	253	+ GPIO3B1_SHIFT = 2,
	254	+ GPIO3B1_MASK = 3,
	255	+ GPIO3B1_GPIO = 0,
	256	+ GPIO3B1_FLASH0_WP,
	257	+ GPIO3B1_EMMC_PWREN,
	258	+
	259	+ GPIO3B0_SHIFT = 0,
	260	+ GPIO3B0_MASK = 1,
	261	+ GPIO3B0_GPIO = 0,
	262	+ GPIO3B0_FLASH0_RDY,
	263	+};
	264	+
	265	+/* GRF_GPIO3C_IOMUX */
	266	+enum {
	267	+ GPIO3C2_SHIFT = 4,
	268	+ GPIO3C2_MASK = 3,
	269	+ GPIO3C2_GPIO = 0,
	270	+ GPIO3C2_FLASH0_DQS,
	271	+ GPIO3C2_EMMC_CLKOUT,
	272	+
	273	+ GPIO3C1_SHIFT = 2,
	274	+ GPIO3C1_MASK = 3,
	275	+ GPIO3C1_GPIO = 0,
	276	+ GPIO3C1_FLASH0_CSN3,
	277	+ GPIO3C1_EMMC_RSTNOUT,
	278	+
	279	+ GPIO3C0_SHIFT = 0,
	280	+ GPIO3C0_MASK = 3,
	281	+ GPIO3C0_GPIO = 0,
	282	+ GPIO3C0_FLASH0_CSN2,
	283	+ GPIO3C0_EMMC_CMD,
	284	+};
	285	+
	286	+/* GRF_GPIO4C_IOMUX */
	287	+enum {
	288	+ GPIO4C7_SHIFT = 14,
	289	+ GPIO4C7_MASK = 1,
	290	+ GPIO4C7_GPIO = 0,
	291	+ GPIO4C7_SDIO0_DATA3,
	292	+
	293	+ GPIO4C6_SHIFT = 12,
	294	+ GPIO4C6_MASK = 1,
	295	+ GPIO4C6_GPIO = 0,
	296	+ GPIO4C6_SDIO0_DATA2,
	297	+
	298	+ GPIO4C5_SHIFT = 10,
	299	+ GPIO4C5_MASK = 1,
	300	+ GPIO4C5_GPIO = 0,
	301	+ GPIO4C5_SDIO0_DATA1,
	302	+
	303	+ GPIO4C4_SHIFT = 8,
	304	+ GPIO4C4_MASK = 1,
	305	+ GPIO4C4_GPIO = 0,
	306	+ GPIO4C4_SDIO0_DATA0,
	307	+
	308	+ GPIO4C3_SHIFT = 6,
	309	+ GPIO4C3_MASK = 1,
	310	+ GPIO4C3_GPIO = 0,
	311	+ GPIO4C3_UART0BT_RTSN,
	312	+
	313	+ GPIO4C2_SHIFT = 4,
	314	+ GPIO4C2_MASK = 1,
	315	+ GPIO4C2_GPIO = 0,
	316	+ GPIO4C2_UART0BT_CTSN,
	317	+
	318	+ GPIO4C1_SHIFT = 2,
	319	+ GPIO4C1_MASK = 1,
	320	+ GPIO4C1_GPIO = 0,
	321	+ GPIO4C1_UART0BT_SOUT,
	322	+
	323	+ GPIO4C0_SHIFT = 0,
	324	+ GPIO4C0_MASK = 1,
	325	+ GPIO4C0_GPIO = 0,
	326	+ GPIO4C0_UART0BT_SIN,
	327	+};
	328	+
	329	+/* GRF_GPIO5B_IOMUX */
	330	+enum {
	331	+ GPIO5B7_SHIFT = 14,
	332	+ GPIO5B7_MASK = 3,
	333	+ GPIO5B7_GPIO = 0,
	334	+ GPIO5B7_SPI0_RXD,
	335	+ GPIO5B7_TS0_DATA7,
	336	+ GPIO5B7_UART4EXP_SIN,
	337	+
	338	+ GPIO5B6_SHIFT = 12,
	339	+ GPIO5B6_MASK = 3,
	340	+ GPIO5B6_GPIO = 0,
	341	+ GPIO5B6_SPI0_TXD,
	342	+ GPIO5B6_TS0_DATA6,
	343	+ GPIO5B6_UART4EXP_SOUT,
	344	+
	345	+ GPIO5B5_SHIFT = 10,
	346	+ GPIO5B5_MASK = 3,
	347	+ GPIO5B5_GPIO = 0,
	348	+ GPIO5B5_SPI0_CSN0,
	349	+ GPIO5B5_TS0_DATA5,
	350	+ GPIO5B5_UART4EXP_RTSN,
	351	+
	352	+ GPIO5B4_SHIFT = 8,
	353	+ GPIO5B4_MASK = 3,
	354	+ GPIO5B4_GPIO = 0,
	355	+ GPIO5B4_SPI0_CLK,
	356	+ GPIO5B4_TS0_DATA4,
	357	+ GPIO5B4_UART4EXP_CTSN,
	358	+
	359	+ GPIO5B3_SHIFT = 6,
	360	+ GPIO5B3_MASK = 3,
	361	+ GPIO5B3_GPIO = 0,
	362	+ GPIO5B3_UART1BB_RTSN,
	363	+ GPIO5B3_TS0_DATA3,
	364	+
	365	+ GPIO5B2_SHIFT = 4,
	366	+ GPIO5B2_MASK = 3,
	367	+ GPIO5B2_GPIO = 0,
	368	+ GPIO5B2_UART1BB_CTSN,
	369	+ GPIO5B2_TS0_DATA2,
	370	+
	371	+ GPIO5B1_SHIFT = 2,
	372	+ GPIO5B1_MASK = 3,
	373	+ GPIO5B1_GPIO = 0,
	374	+ GPIO5B1_UART1BB_SOUT,
	375	+ GPIO5B1_TS0_DATA1,
	376	+
	377	+ GPIO5B0_SHIFT = 0,
	378	+ GPIO5B0_MASK = 3,
	379	+ GPIO5B0_GPIO = 0,
	380	+ GPIO5B0_UART1BB_SIN,
	381	+ GPIO5B0_TS0_DATA0,
	382	+};
	383	+
	384	+/* GRF_GPIO5C_IOMUX */
	385	+enum {
	386	+ GPIO5C3_SHIFT = 6,
	387	+ GPIO5C3_MASK = 1,
	388	+ GPIO5C3_GPIO = 0,
	389	+ GPIO5C3_TS0_ERR,
	390	+
	391	+ GPIO5C2_SHIFT = 4,
	392	+ GPIO5C2_MASK = 1,
	393	+ GPIO5C2_GPIO = 0,
	394	+ GPIO5C2_TS0_CLK,
	395	+
	396	+ GPIO5C1_SHIFT = 2,
	397	+ GPIO5C1_MASK = 1,
	398	+ GPIO5C1_GPIO = 0,
	399	+ GPIO5C1_TS0_VALID,
	400	+
	401	+ GPIO5C0_SHIFT = 0,
	402	+ GPIO5C0_MASK = 3,
	403	+ GPIO5C0_GPIO = 0,
	404	+ GPIO5C0_SPI0_CSN1,
	405	+ GPIO5C0_TS0_SYNC,
	406	+};
	407	+
	408	+/* GRF_GPIO6B_IOMUX */
	409	+enum {
	410	+ GPIO6B3_SHIFT = 6,
	411	+ GPIO6B3_MASK = 1,
	412	+ GPIO6B3_GPIO = 0,
	413	+ GPIO6B3_SPDIF_TX,
	414	+
	415	+ GPIO6B2_SHIFT = 4,
	416	+ GPIO6B2_MASK = 1,
	417	+ GPIO6B2_GPIO = 0,
	418	+ GPIO6B2_I2C1AUDIO_SCL,
	419	+
	420	+ GPIO6B1_SHIFT = 2,
	421	+ GPIO6B1_MASK = 1,
	422	+ GPIO6B1_GPIO = 0,
	423	+ GPIO6B1_I2C1AUDIO_SDA,
	424	+
	425	+ GPIO6B0_SHIFT = 0,
	426	+ GPIO6B0_MASK = 1,
	427	+ GPIO6B0_GPIO = 0,
	428	+ GPIO6B0_I2S_CLK,
	429	+};
	430	+
	431	+/* GRF_GPIO6C_IOMUX */
	432	+enum {
	433	+ GPIO6C6_SHIFT = 12,
	434	+ GPIO6C6_MASK = 1,
	435	+ GPIO6C6_GPIO = 0,
	436	+ GPIO6C6_SDMMC0_DECTN,
	437	+
	438	+ GPIO6C5_SHIFT = 10,
	439	+ GPIO6C5_MASK = 1,
	440	+ GPIO6C5_GPIO = 0,
	441	+ GPIO6C5_SDMMC0_CMD,
	442	+
	443	+ GPIO6C4_SHIFT = 8,
	444	+ GPIO6C4_MASK = 3,
	445	+ GPIO6C4_GPIO = 0,
	446	+ GPIO6C4_SDMMC0_CLKOUT,
	447	+ GPIO6C4_JTAG_TDO,
	448	+
	449	+ GPIO6C3_SHIFT = 6,
	450	+ GPIO6C3_MASK = 3,
	451	+ GPIO6C3_GPIO = 0,
	452	+ GPIO6C3_SDMMC0_DATA3,
	453	+ GPIO6C3_JTAG_TCK,
	454	+
	455	+ GPIO6C2_SHIFT = 4,
	456	+ GPIO6C2_MASK = 3,
	457	+ GPIO6C2_GPIO = 0,
	458	+ GPIO6C2_SDMMC0_DATA2,
	459	+ GPIO6C2_JTAG_TDI,
	460	+
	461	+ GPIO6C1_SHIFT = 2,
	462	+ GPIO6C1_MASK = 3,
	463	+ GPIO6C1_GPIO = 0,
	464	+ GPIO6C1_SDMMC0_DATA1,
	465	+ GPIO6C1_JTAG_TRSTN,
	466	+
	467	+ GPIO6C0_SHIFT = 0,
	468	+ GPIO6C0_MASK = 3,
	469	+ GPIO6C0_GPIO = 0,
	470	+ GPIO6C0_SDMMC0_DATA0,
	471	+ GPIO6C0_JTAG_TMS,
	472	+};
	473	+
	474	+/* GRF_GPIO7A_IOMUX */
	475	+enum {
	476	+ GPIO7A7_SHIFT = 14,
	477	+ GPIO7A7_MASK = 3,
	478	+ GPIO7A7_GPIO = 0,
	479	+ GPIO7A7_UART3GPS_SIN,
	480	+ GPIO7A7_GPS_MAG,
	481	+ GPIO7A7_HSADCT1_DATA0,
	482	+
	483	+ GPIO7A1_SHIFT = 2,
	484	+ GPIO7A1_MASK = 1,
	485	+ GPIO7A1_GPIO = 0,
	486	+ GPIO7A1_PWM_1,
	487	+
	488	+ GPIO7A0_SHIFT = 0,
	489	+ GPIO7A0_MASK = 3,
	490	+ GPIO7A0_GPIO = 0,
	491	+ GPIO7A0_PWM_0,
	492	+ GPIO7A0_VOP0_PWM,
	493	+ GPIO7A0_VOP1_PWM,
	494	+};
	495	+
	496	+/* GRF_GPIO7B_IOMUX */
	497	+enum {
	498	+ GPIO7B7_SHIFT = 14,
	499	+ GPIO7B7_MASK = 3,
	500	+ GPIO7B7_GPIO = 0,
	501	+ GPIO7B7_ISP_SHUTTERTRIG,
	502	+ GPIO7B7_SPI1_TXD,
	503	+
	504	+ GPIO7B6_SHIFT = 12,
	505	+ GPIO7B6_MASK = 3,
	506	+ GPIO7B6_GPIO = 0,
	507	+ GPIO7B6_ISP_PRELIGHTTRIG,
	508	+ GPIO7B6_SPI1_RXD,
	509	+
	510	+ GPIO7B5_SHIFT = 10,
	511	+ GPIO7B5_MASK = 3,
	512	+ GPIO7B5_GPIO = 0,
	513	+ GPIO7B5_ISP_FLASHTRIGOUT,
	514	+ GPIO7B5_SPI1_CSN0,
	515	+
	516	+ GPIO7B4_SHIFT = 8,
	517	+ GPIO7B4_MASK = 3,
	518	+ GPIO7B4_GPIO = 0,
	519	+ GPIO7B4_ISP_SHUTTEREN,
	520	+ GPIO7B4_SPI1_CLK,
	521	+
	522	+ GPIO7B3_SHIFT = 6,
	523	+ GPIO7B3_MASK = 3,
	524	+ GPIO7B3_GPIO = 0,
	525	+ GPIO7B3_USB_DRVVBUS1,
	526	+ GPIO7B3_EDP_HOTPLUG,
	527	+
	528	+ GPIO7B2_SHIFT = 4,
	529	+ GPIO7B2_MASK = 3,
	530	+ GPIO7B2_GPIO = 0,
	531	+ GPIO7B2_UART3GPS_RTSN,
	532	+ GPIO7B2_USB_DRVVBUS0,
	533	+
	534	+ GPIO7B1_SHIFT = 2,
	535	+ GPIO7B1_MASK = 3,
	536	+ GPIO7B1_GPIO = 0,
	537	+ GPIO7B1_UART3GPS_CTSN,
	538	+ GPIO7B1_GPS_RFCLK,
	539	+ GPIO7B1_GPST1_CLK,
	540	+
	541	+ GPIO7B0_SHIFT = 0,
	542	+ GPIO7B0_MASK = 3,
	543	+ GPIO7B0_GPIO = 0,
	544	+ GPIO7B0_UART3GPS_SOUT,
	545	+ GPIO7B0_GPS_SIG,
	546	+ GPIO7B0_HSADCT1_DATA1,
	547	+};
	548	+
	549	+/* GRF_GPIO7CL_IOMUX */
	550	+enum {
	551	+ GPIO7C3_SHIFT = 12,
	552	+ GPIO7C3_MASK = 3,
	553	+ GPIO7C3_GPIO = 0,
	554	+ GPIO7C3_I2C5HDMI_SDA,
	555	+ GPIO7C3_EDPHDMII2C_SDA,
	556	+
	557	+ GPIO7C2_SHIFT = 8,
	558	+ GPIO7C2_MASK = 1,
	559	+ GPIO7C2_GPIO = 0,
	560	+ GPIO7C2_I2C4TP_SCL,
	561	+
	562	+ GPIO7C1_SHIFT = 4,
	563	+ GPIO7C1_MASK = 1,
	564	+ GPIO7C1_GPIO = 0,
	565	+ GPIO7C1_I2C4TP_SDA,
	566	+
	567	+ GPIO7C0_SHIFT = 0,
	568	+ GPIO7C0_MASK = 3,
	569	+ GPIO7C0_GPIO = 0,
	570	+ GPIO7C0_ISP_FLASHTRIGIN,
	571	+ GPIO7C0_EDPHDMI_CECINOUTT1,
	572	+};
	573	+
	574	+/* GRF_GPIO7CH_IOMUX */
	575	+enum {
	576	+ GPIO7C7_SHIFT = 12,
	577	+ GPIO7C7_MASK = 7,
	578	+ GPIO7C7_GPIO = 0,
	579	+ GPIO7C7_UART2DBG_SOUT,
	580	+ GPIO7C7_UART2DBG_SIROUT,
	581	+ GPIO7C7_PWM_3,
	582	+ GPIO7C7_EDPHDMI_CECINOUT,
	583	+
	584	+ GPIO7C6_SHIFT = 8,
	585	+ GPIO7C6_MASK = 3,
	586	+ GPIO7C6_GPIO = 0,
	587	+ GPIO7C6_UART2DBG_SIN,
	588	+ GPIO7C6_UART2DBG_SIRIN,
	589	+ GPIO7C6_PWM_2,
	590	+
	591	+ GPIO7C4_SHIFT = 0,
	592	+ GPIO7C4_MASK = 3,
	593	+ GPIO7C4_GPIO = 0,
	594	+ GPIO7C4_I2C5HDMI_SCL,
	595	+ GPIO7C4_EDPHDMII2C_SCL,
	596	+};
	597	+
	598	+/* GRF_GPIO8A_IOMUX */
	599	+enum {
	600	+ GPIO8A7_SHIFT = 14,
	601	+ GPIO8A7_MASK = 3,
	602	+ GPIO8A7_GPIO = 0,
	603	+ GPIO8A7_SPI2_CSN0,
	604	+ GPIO8A7_SC_DETECT,
	605	+ GPIO8A7_RESERVE,
	606	+
	607	+ GPIO8A6_SHIFT = 12,
	608	+ GPIO8A6_MASK = 3,
	609	+ GPIO8A6_GPIO = 0,
	610	+ GPIO8A6_SPI2_CLK,
	611	+ GPIO8A6_SC_IO,
	612	+ GPIO8A6_RESERVE,
	613	+
	614	+ GPIO8A5_SHIFT = 10,
	615	+ GPIO8A5_MASK = 3,
	616	+ GPIO8A5_GPIO = 0,
	617	+ GPIO8A5_I2C2SENSOR_SCL,
	618	+ GPIO8A5_SC_CLK,
	619	+
	620	+ GPIO8A4_SHIFT = 8,
	621	+ GPIO8A4_MASK = 3,
	622	+ GPIO8A4_GPIO = 0,
	623	+ GPIO8A4_I2C2SENSOR_SDA,
	624	+ GPIO8A4_SC_RST,
	625	+
	626	+ GPIO8A3_SHIFT = 6,
	627	+ GPIO8A3_MASK = 3,
	628	+ GPIO8A3_GPIO = 0,
	629	+ GPIO8A3_SPI2_CSN1,
	630	+ GPIO8A3_SC_IOT1,
	631	+
	632	+ GPIO8A2_SHIFT = 4,
	633	+ GPIO8A2_MASK = 1,
	634	+ GPIO8A2_GPIO = 0,
	635	+ GPIO8A2_SC_DETECTT1,
	636	+
	637	+ GPIO8A1_SHIFT = 2,
	638	+ GPIO8A1_MASK = 3,
	639	+ GPIO8A1_GPIO = 0,
	640	+ GPIO8A1_PS2_DATA,
	641	+ GPIO8A1_SC_VCC33V,
	642	+
	643	+ GPIO8A0_SHIFT = 0,
	644	+ GPIO8A0_MASK = 3,
	645	+ GPIO8A0_GPIO = 0,
	646	+ GPIO8A0_PS2_CLK,
	647	+ GPIO8A0_SC_VCC18V,
	648	+};
	649	+
	650	+/* GRF_GPIO8B_IOMUX */
	651	+enum {
	652	+ GPIO8B1_SHIFT = 2,
	653	+ GPIO8B1_MASK = 3,
	654	+ GPIO8B1_GPIO = 0,
	655	+ GPIO8B1_SPI2_TXD,
	656	+ GPIO8B1_SC_CLK,
	657	+
	658	+ GPIO8B0_SHIFT = 0,
	659	+ GPIO8B0_MASK = 3,
	660	+ GPIO8B0_GPIO = 0,
	661	+ GPIO8B0_SPI2_RXD,
	662	+ GPIO8B0_SC_RST,
	663	+};
	664	+
	665	+/* GRF_SOC_CON0 */
	666	+enum {
	667	+ PAUSE_MMC_PERI_SHIFT = 0xf,
	668	+ PAUSE_MMC_PERI_MASK = 1,
	669	+
	670	+ PAUSE_EMEM_PERI_SHIFT = 0xe,
	671	+ PAUSE_EMEM_PERI_MASK = 1,
	672	+
	673	+ PAUSE_USB_PERI_SHIFT = 0xd,
	674	+ PAUSE_USB_PERI_MASK = 1,
	675	+
	676	+ GRF_FORCE_JTAG_SHIFT = 0xc,
	677	+ GRF_FORCE_JTAG_MASK = 1,
	678	+
	679	+ GRF_CORE_IDLE_REQ_MODE_SEL1_SHIFT = 0xb,
	680	+ GRF_CORE_IDLE_REQ_MODE_SEL1_MASK = 1,
	681	+
	682	+ GRF_CORE_IDLE_REQ_MODE_SEL0_SHIFT = 0xa,
	683	+ GRF_CORE_IDLE_REQ_MODE_SEL0_MASK = 1,
	684	+
	685	+ DDR1_16BIT_EN_SHIFT = 9,
	686	+ DDR1_16BIT_EN_MASK = 1,
	687	+
	688	+ DDR0_16BIT_EN_SHIFT = 8,
	689	+ DDR0_16BIT_EN_MASK = 1,
	690	+
	691	+ VCODEC_SHIFT = 7,
	692	+ VCODEC_MASK = 1,
	693	+ VCODEC_SELECT_VEPU_ACLK = 0,
	694	+ VCODEC_SELECT_VDPU_ACLK,
	695	+
	696	+ UPCTL1_C_ACTIVE_IN_SHIFT = 6,
	697	+ UPCTL1_C_ACTIVE_IN_MASK = 1,
	698	+ UPCTL1_C_ACTIVE_IN_MAY = 0,
	699	+ UPCTL1_C_ACTIVE_IN_WILL,
	700	+
	701	+ UPCTL0_C_ACTIVE_IN_SHIFT = 5,
	702	+ UPCTL0_C_ACTIVE_IN_MASK = 1,
	703	+ UPCTL0_C_ACTIVE_IN_MAY = 0,
	704	+ UPCTL0_C_ACTIVE_IN_WILL,
	705	+
	706	+ MSCH1_MAINDDR3_SHIFT = 4,
	707	+ MSCH1_MAINDDR3_MASK = 1,
	708	+ MSCH1_MAINDDR3_DDR3 = 1,
	709	+
	710	+ MSCH0_MAINDDR3_SHIFT = 3,
	711	+ MSCH0_MAINDDR3_MASK = 1,
	712	+ MSCH0_MAINDDR3_DDR3 = 1,
	713	+
	714	+ MSCH1_MAINPARTIALPOP_SHIFT = 2,
	715	+ MSCH1_MAINPARTIALPOP_MASK = 1,
	716	+
	717	+ MSCH0_MAINPARTIALPOP_SHIFT = 1,
	718	+ MSCH0_MAINPARTIALPOP_MASK = 1,
	719	+};
	720	+
	721	+/* GRF_SOC_CON2 */
	722	+enum {
	723	+ UPCTL1_LPDDR3_ODT_EN_SHIFT = 0xd,
	724	+ UPCTL1_LPDDR3_ODT_EN_MASK = 1,
	725	+ UPCTL1_LPDDR3_ODT_EN_ODT = 1,
	726	+
	727	+ UPCTL1_BST_DIABLE_SHIFT = 0xc,
	728	+ UPCTL1_BST_DIABLE_MASK = 1,
	729	+ UPCTL1_BST_DIABLE_DISABLE = 1,
	730	+
	731	+ LPDDR3_EN1_SHIFT = 0xb,
	732	+ LPDDR3_EN1_MASK = 1,
	733	+ LPDDR3_EN1_LPDDR3 = 1,
	734	+
	735	+ UPCTL0_LPDDR3_ODT_EN_SHIFT = 0xa,
	736	+ UPCTL0_LPDDR3_ODT_EN_MASK = 1,
	737	+ UPCTL0_LPDDR3_ODT_EN_ODT_ENABLE = 1,
	738	+
	739	+ UPCTL0_BST_DIABLE_SHIFT = 9,
	740	+ UPCTL0_BST_DIABLE_MASK = 1,
	741	+ UPCTL0_BST_DIABLE_DISABLE = 1,
	742	+
	743	+ LPDDR3_EN0_SHIFT = 8,
	744	+ LPDDR3_EN0_MASK = 1,
	745	+ LPDDR3_EN0_LPDDR3 = 1,
	746	+
	747	+ GRF_POC_FLASH0_CTRL_SHIFT = 7,
	748	+ GRF_POC_FLASH0_CTRL_MASK = 1,
	749	+ GRF_POC_FLASH0_CTRL_GPIO3C_3 = 0,
	750	+ GRF_POC_FLASH0_CTRL_GRF_IO_VSEL,
	751	+
	752	+ SIMCARD_MUX_SHIFT = 6,
	753	+ SIMCARD_MUX_MASK = 1,
	754	+ SIMCARD_MUX_USE_A = 1,
	755	+ SIMCARD_MUX_USE_B = 0,
	756	+
	757	+ GRF_SPDIF_2CH_EN_SHIFT = 1,
	758	+ GRF_SPDIF_2CH_EN_MASK = 1,
	759	+ GRF_SPDIF_2CH_EN_8CH = 0,
	760	+ GRF_SPDIF_2CH_EN_2CH,
	761	+
	762	+ PWM_SHIFT = 0,
	763	+ PWM_MASK = 1,
	764	+ PWM_RK = 1,
	765	+ PWM_PWM = 0,
	766	+};
	767	+
	768	+#endif

arch/arm/include/asm/arch-rockchip/pmu_rk3288.h

Diff comments View file @ 7f4fd26

	1	+/*
	2	+ * Copyright (c) 2015 Google, Inc
	3	+ *
	4	+ * Copyright 2014 Rockchip Inc.
	5	+ *
	6	+ * SPDX-License-Identifier: GPL-2.0+
	7	+ */
	8	+
	9	+#ifndef _ASM_ARCH_PMU_RK3288_H
	10	+#define _ASM_ARCH_PMU_RK3288_H
	11	+
	12	+struct rk3288_pmu {
	13	+ u32 wakeup_cfg[2];
	14	+ u32 pwrdn_con;
	15	+ u32 pwrdn_st;
	16	+
	17	+ u32 idle_req;
	18	+ u32 idle_st;
	19	+ u32 pwrmode_con;
	20	+ u32 pwr_state;
	21	+
	22	+ u32 osc_cnt;
	23	+ u32 pll_cnt;
	24	+ u32 stabl_cnt;
	25	+ u32 ddr0io_pwron_cnt;
	26	+
	27	+ u32 ddr1io_pwron_cnt;
	28	+ u32 core_pwrdn_cnt;
	29	+ u32 core_pwrup_cnt;
	30	+ u32 gpu_pwrdn_cnt;
	31	+
	32	+ u32 gpu_pwrup_cnt;
	33	+ u32 wakeup_rst_clr_cnt;
	34	+ u32 sft_con;
	35	+ u32 ddr_sref_st;
	36	+
	37	+ u32 int_con;
	38	+ u32 int_st;
	39	+ u32 boot_addr_sel;
	40	+ u32 grf_con;
	41	+
	42	+ u32 gpio_sr;
	43	+ u32 gpio0pull[3];
	44	+
	45	+ u32 gpio0drv[3];
	46	+ u32 gpio_op;
	47	+
	48	+ u32 gpio0_sel18; /* 0x80 */
	49	+ u32 gpio0a_iomux;
	50	+ u32 gpio0b_iomux;
	51	+ u32 gpio0c_iomux;
	52	+ u32 gpio0d_iomux;
	53	+ u32 sys_reg[4];
	54	+};
	55	+check_member(rk3288_pmu, sys_reg[3], 0x00a0);
	56	+
	57	+/* PMU_GPIO0_B_IOMUX */
	58	+enum {
	59	+ GPIO0_B7_SHIFT = 14,
	60	+ GPIO0_B7_MASK = 1,
	61	+ GPIO0_B7_GPIOB7 = 0,
	62	+ GPIO0_B7_I2C0PMU_SDA,
	63	+
	64	+ GPIO0_B5_SHIFT = 10,
	65	+ GPIO0_B5_MASK = 1,
	66	+ GPIO0_B5_GPIOB5 = 0,
	67	+ GPIO0_B5_CLK_27M,
	68	+
	69	+ GPIO0_B2_SHIFT = 4,
	70	+ GPIO0_B2_MASK = 1,
	71	+ GPIO0_B2_GPIOB2 = 0,
	72	+ GPIO0_B2_TSADC_INT,
	73	+};
	74	+
	75	+/* PMU_GPIO0_C_IOMUX */
	76	+enum {
	77	+ GPIO0_C1_SHIFT = 2,
	78	+ GPIO0_C1_MASK = 3,
	79	+ GPIO0_C1_GPIOC1 = 0,
	80	+ GPIO0_C1_TEST_CLKOUT,
	81	+ GPIO0_C1_CLKT1_27M,
	82	+
	83	+ GPIO0_C0_SHIFT = 0,
	84	+ GPIO0_C0_MASK = 1,
	85	+ GPIO0_C0_GPIOC0 = 0,
	86	+ GPIO0_C0_I2C0PMU_SCL,
	87	+};
	88	+
	89	+#endif