Eric Lee / smarc-uboot

14
Download as
Browse Code ยป

Commit 8116f34387f8164dd72656fb8278e6df9fdf4c05

Authored by Fabio Estevam
Committed by Ye Li
1 parent bddbcaf32a
Exists in smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga and in 5 other branches smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga

MLK-18318: mx7ulp: Enable QSPI interrupt as a wakeup source on MX7ULP 

MX7ULP needs to have the QSPI interrupt configured as a wakeup source
in the SIM_WKPU_WAKEUP_ENABLE register, otherwise the QSPI interrupts
do not wakeup the CPU from idle mode leading to poor performance in
Linux.

The SIM_WKPU_WAKEUP_ENABLE register only exists in B0 silicon, so
make sure to only write to this register in the B0 version (or greater).

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
(cherry picked from commit 1ab33446d6843f560fb6d14c781f6417225f8f3d)

Showing 2 changed files with 7 additions and 0 deletions Side-by-side Diff

arch/arm/include/asm/arch-mx7ulp/imx-regs.h
Diff comments   View file @ 8116f34
... ... @@ -131,6 +131,9 @@
131 131 #define SIM_SOPT1_PMIC_STBY_REQ (1<<2)
132 132 #define SIM_SOPT1_A7_SW_RESET (1<<0)
133 133  
  134 +#define WKPU_WAKEUP_EN 0x88
  135 +#define WKPU_QSPI_CHANNEL BIT(20)
  136 +
134 137 #define IOMUXC_PCR_MUX_ALT_SHIFT (8)
135 138 #define IOMUXC_PCR_MUX_ALT_MASK (0xF00)
136 139 #define IOMUXC_PSMI_IMUX_ALT_SHIFT (0)
board/freescale/mx7ulp_evk/mx7ulp_evk.c
Diff comments   View file @ 8116f34
... ... @@ -66,6 +66,10 @@
66 66 writel(0x03000003, (PCC1_RBASE + 0x94));
67 67 writel(0x43000003, (PCC1_RBASE + 0x94));
68 68 }
  69 +
  70 + /* Enable QSPI as a wakeup source on B0 */
  71 + if (soc_rev() >= CHIP_REV_2_0)
  72 + setbits_le32(SIM0_RBASE + WKPU_WAKEUP_EN, WKPU_QSPI_CHANNEL);
69 73 return 0;
70 74 }
71 75 #endif