dm: x86: Add a driver for Intel PCH9

At some point we may need to distinguish between different types of PCHs, but for existing supported platforms we only need to worry about version 7 and version 9 bridges. Add a driver for the PCH9. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

dm: x86: Add a driver for Intel PCH9
At some point we may need to distinguish between different types of PCHs, but for existing supported platforms we only need to worry about version 7 and version 9 bridges. Add a driver for the PCH9. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass · Bin Meng
1 parent 1ff4f321b6
Showing 2 changed files with 44 additions and 0 deletions Side-by-side Diff
drivers/pch/Makefile
drivers/pch/pch9.c
@@ -4,4 +4,5 @@
  
 obj-y += pch-uclass.o
 obj-y += pch7.o
+obj-y += pch9.o
+/*
+ * Copyright (C) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <pch.h>
+
+#define SBASE_ADDR	0x54
+
+static int pch9_get_sbase(struct udevice *dev, ulong *sbasep)
+{
+	uint32_t sbase_addr;
+
+	dm_pci_read_config32(dev, SBASE_ADDR, &sbase_addr);
+	*sbasep = sbase_addr & 0xfffffe00;
+
+	return 0;
+}
+
+static enum pch_version pch9_get_version(struct udevice *dev)
+{
+	return PCHV_9;
+}
+
+static const struct pch_ops pch9_ops = {
+	.get_sbase	= pch9_get_sbase,
+	.get_version	= pch9_get_version,
+};
+
+static const struct udevice_id pch9_ids[] = {
+	{ .compatible = "intel,pch9" },
+	{ }
+};
+
+U_BOOT_DRIVER(pch9_drv) = {
+	.name		= "intel-pch9",
+	.id		= UCLASS_PCH,
+	.of_match	= pch9_ids,
+	.ops		= &pch9_ops,
+};
...	...	@@ -4,4 +4,5 @@
4	4
5	5	obj-y += pch-uclass.o
6	6	obj-y += pch7.o
	7	+obj-y += pch9.o
	1	+/*
	2	+ * Copyright (C) 2014 Google, Inc
	3	+ *
	4	+ * SPDX-License-Identifier: GPL-2.0+
	5	+ */
	6	+
	7	+#include <common.h>
	8	+#include <dm.h>
	9	+#include <pch.h>
	10	+
	11	+#define SBASE_ADDR 0x54
	12	+
	13	+static int pch9_get_sbase(struct udevice dev, ulong sbasep)
	14	+{
	15	+ uint32_t sbase_addr;
	16	+
	17	+ dm_pci_read_config32(dev, SBASE_ADDR, &sbase_addr);
	18	+ *sbasep = sbase_addr & 0xfffffe00;
	19	+
	20	+ return 0;
	21	+}
	22	+
	23	+static enum pch_version pch9_get_version(struct udevice *dev)
	24	+{
	25	+ return PCHV_9;
	26	+}
	27	+
	28	+static const struct pch_ops pch9_ops = {
	29	+ .get_sbase = pch9_get_sbase,
	30	+ .get_version = pch9_get_version,
	31	+};
	32	+
	33	+static const struct udevice_id pch9_ids[] = {
	34	+ { .compatible = "intel,pch9" },
	35	+ { }
	36	+};
	37	+
	38	+U_BOOT_DRIVER(pch9_drv) = {
	39	+ .name = "intel-pch9",
	40	+ .id = UCLASS_PCH,
	41	+ .of_match = pch9_ids,
	42	+ .ops = &pch9_ops,
	43	+};