Eric Lee / smarc-uboot

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Commit 8348e79865963a15dcb794f9a950f500c0b6f743

Authored by Hou Zhiqiang
Committed by Prabhakar Kushwaha
1 parent 626f3875e7
Exists in smarc_8mq_lf_v2020.04 and in 9 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

armv8: layerscape: use PCIe address macro for precompile PCIe MMU entry 

Change to use PCIe address macro to determine if precompile the PCIe
MMU table entry.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>

Showing 1 changed file with 3 additions and 1 deletions Side-by-side Diff

arch/arm/cpu/armv8/fsl-layerscape/cpu.c
Diff comments   View file @ 8348e79
... ... @@ -251,7 +251,7 @@
251 251 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
252 252 PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
253 253 },
254   -#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A)
  254 +#ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
255 255 { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
256 256 CONFIG_SYS_PCIE4_PHYS_SIZE,
257 257 PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
258 258  
... ... @@ -453,11 +453,13 @@
453 453 final_map[i].virt = 0x3000000000ULL;
454 454 final_map[i].size = 0x800000000ULL;
455 455 break;
  456 +#ifdef CONFIG_SYS_PCIE4_PHYS_ADDR
456 457 case CONFIG_SYS_PCIE4_PHYS_ADDR:
457 458 final_map[i].phys = 0x3800000000ULL;
458 459 final_map[i].virt = 0x3800000000ULL;
459 460 final_map[i].size = 0x800000000ULL;
460 461 break;
  462 +#endif
461 463 default:
462 464 break;
463 465 }