Eric Lee / smarc-uboot

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Commit 83b4cfa3d629dff0264366263c5e94d9a50ad80b

Authored by Wolfgang Denk
1 parent 6b44466cde
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

Coding style cleanup. Refresh CHANGELOG.

Showing 7 changed files with 339 additions and 181 deletions Side-by-side Diff

  1 +commit b3f9ec86e388207fd03dcdf7b145b9ed080bf024
  2 +Author: Stefan Roese <sr@denx.de>
  3 +Date: Tue Jun 19 17:22:44 2007 +0200
  4 +
  5 + ppc4xx: Add bootstrap command for AMCC Sequoia (440EPx) eval board
  6 +
  7 + This patch adds a board command to configure the I2C bootstrap EEPROM
  8 + values. Right now 533 and 667MHz are supported for booting either via NOR
  9 + or NAND FLASH. Here the usage:
  10 +
  11 + => bootstrap 533 nor ;to configure the board for 533MHz NOR booting
  12 + => bootstrap 667 nand ;to configure the board for 667MHz NNAND booting
  13 +
  14 + Signed-off-by: Stefan Roese <sr@denx.de>
  15 +
  16 +commit df8a24cdd30151505cf57bbee5289e91bf53bd1b
  17 +Author: Stefan Roese <sr@denx.de>
  18 +Date: Tue Jun 19 16:42:31 2007 +0200
  19 +
  20 + [ppc4xx] Fix problem with NAND booting on AMCC Acadia
  21 +
  22 + The latest changes showed a problem with the location of the NAND-SPL
  23 + image in the OCM and the init-data area (incl. cache). This patch
  24 + fixes this problem.
  25 +
  26 + Signed-off-by: Stefan Roese <sr@denx.de>
  27 +
  28 +commit 86ba99e34194394052d24c04dc40d1263d29a26f
  29 +Author: Stefan Roese <sr@denx.de>
  30 +Date: Tue Jun 19 16:40:58 2007 +0200
  31 +
  32 + [ppc4xx] Change board/amcc/acadia/cpr.c to pll.c
  33 +
  34 + Signed-off-by: Stefan Roese <sr@denx.de>
  35 +
  36 +commit e73846b7cf1e29ae635bf9bb5570269663df2ee5
  37 +Author: Stefan Roese <sr@denx.de>
  38 +Date: Fri Jun 15 11:33:41 2007 +0200
  39 +
  40 + [ppc4xx] Change lwmon5 port to work with recent 440 exception rework
  41 +
  42 + Now CONFIG_440 has to be defined in all PPC440 board config files.
  43 +
  44 + Signed-off-by: Stefan Roese <sr@denx.de>
  45 +
  46 +commit efa35cf12d914d4caba942acd5a6c45f217de302
  47 +Author: Grzegorz Bernacki <gjb@semihalf.com>
  48 +Date: Fri Jun 15 11:19:28 2007 +0200
  49 +
  50 + ppc4xx: Clean up 440 exceptions handling
  51 +
  52 + - Introduced dedicated switches for building 440 and 405 images required
  53 + for 440-specific machine instructions like 'rfmci' etc.
  54 +
  55 + - Exception vectors moved to the proper location (_start moved away from
  56 + the critical exception handler space, which it occupied)
  57 +
  58 + - CriticalInput now serviced (with default handler)
  59 +
  60 + - MachineCheck properly serviced (added a dedicated handler and return
  61 + subroutine)
  62 +
  63 + - Overall cleanup of exceptions declared with STD_EXCEPTION macro (unused,
  64 + unhandled and those not relevant for 4xx were eliminated)
  65 +
  66 + - Eliminated Linux leftovers, removed dead code
  67 +
  68 + Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
  69 + Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
  70 + Signed-off-by: Stefan Roese <sr@denx.de>
  71 +
  72 +commit b765ffb773f5a3cd5aa94ec76b6a05276b8cd5b2
  73 +Author: Stefan Roese <sr@denx.de>
  74 +Date: Fri Jun 15 08:18:01 2007 +0200
  75 +
  76 + [ppc4xx] Add initial lwmon5 board support
  77 +
  78 + This patch adds initial support for the Liebherr lwmon5 board euqipped
  79 + with an AMCC 440EPx PowerPC.
  80 +
  81 + Signed-off-by: Stefan Roese <sr@denx.de>
  82 +
  83 +commit 85f737376d5ff3d5f0d45a8b657686326d175307
  84 +Author: Stefan Roese <sr@denx.de>
  85 +Date: Fri Jun 15 07:39:43 2007 +0200
  86 +
  87 + [ppc4xx] Extend 44x GPIO setup with default output state
  88 +
  89 + The board config array CFG_440_GPIO_TABLE for the ppc440 GPIO setup
  90 + is extended with the default GPIO output state (level).
  91 +
  92 + Signed-off-by: Stefan Roese <sr@denx.de>
  93 +
  94 +commit dbca208518e5e7f01a6420588d1cd6e60db74c2b
  95 +Author: Stefan Roese <sr@denx.de>
  96 +Date: Thu Jun 14 11:14:32 2007 +0200
  97 +
  98 + [ppc4xx] Extend program_tlb() with virtual & physical addresses
  99 +
  100 + Now program_tlb() allows to program a TLB (or multiple) with
  101 + different virtual and physical addresses. With this change, now one
  102 + physical region (e.g. SDRAM) can be mapped 2 times, once with caches
  103 + diabled and once with caches enabled.
  104 +
  105 + Signed-off-by: Stefan Roese <sr@denx.de>
  106 +
  107 +commit 9912121f7ed804ea58fd62f3f230b5dcfc357d88
  108 +Author: Detlev Zundel <dzu@denx.de>
  109 +Date: Wed May 23 19:02:41 2007 +0200
  110 +
  111 + Change 'repeatable' attribute of some commands to sensible values.
  112 +
  113 + Most prominently this changes 'erase' to be non-repeatable.
  114 +
  115 + Signed-off-by: Detlev Zundel <dzu@denx.de>
  116 +
  117 +commit 5afb202093f6a001797db92cf695b93a70ea9ab4
  118 +Author: Detlev Zundel <dzu@denx.de>
  119 +Date: Wed May 23 18:47:48 2007 +0200
  120 +
  121 + Fix 'run' not to continue after interrupted command
  122 +
  123 + Signed-off-by: Detlev Zundel <dzu@denx.de>
  124 +
  125 +commit 8f8416fada9faf94b9a92f21fe6000643cb521d5
  126 +Author: Bartlomiej Sieka <tur@semihalf.com>
  127 +Date: Fri Jun 8 14:52:22 2007 +0200
  128 +
  129 + TQM5200: Add Flat Device Tree support, update default env. accordingly.
  130 +
  131 + Signed-off-by: Jan Wrobel <wrr@semihalf.com>
  132 + Acked-by: Bartlomiej Sieka <tur@semihalf.com>
  133 +
  134 +commit 9045f33c023f698660a2e45d1b2194c0711abebc
  135 +Author: Wolfgang Denk <wd@denx.de>
  136 +Date: Fri Jun 8 10:24:58 2007 +0200
  137 +
  138 + Fix config problems on SC3 board; make ide_reset_timeout work.
  139 +
  140 +commit fba3fb0449b8a54542aed1e729de76e7f5a2ff1b
  141 +Author: Benoรฎt Monin <bmonin@adeneo.eu>
  142 +Date: Fri Jun 8 09:55:24 2007 +0200
  143 +
  144 + [PATCH] fix gpio setting when using CFG_440_GPIO_TABLE
  145 +
  146 + Set the correct value in GPIOx_TCR when configuring the gpio
  147 + with CFG_440_GPIO_TABLE.
  148 +
  149 + Signed-off-by: Benoit Monin <bmonin@adeneo.eu>
  150 + Signed-off-by: Stefan Roese <sr@denx.de>
  151 +
  152 +commit 725671ccd2cd04c9ebc50c9e5a94dd8cbade66b7
  153 +Author: Wolfgang Denk <wd@denx.de>
  154 +Date: Wed Jun 6 16:26:56 2007 +0200
  155 +
  156 + Coding Style cleanup; generate new CHANGELOG file.
  157 +
  158 + Signed-off-by: Wolfgang Denk <wd@denx.de>
  159 +
1 160 commit c440bfe6d6d92d66478a7e84402b31f48413617b
2 161 Author: Stefan Roese <sr@denx.de>
3 162 Date: Wed Jun 6 11:42:13 2007 +0200
board/lwmon5/lwmon5.c
Diff comments   View file @ 83b4cfa
... ... @@ -34,9 +34,9 @@
34 34 u32 sdr0_pfc1, sdr0_pfc2;
35 35 u32 reg;
36 36  
37   - /* PLB Write pipelining disabled. Denali Core workaround */
38   - mtdcr(plb0_acr, 0xDE000000);
39   - mtdcr(plb1_acr, 0xDE000000);
  37 + /* PLB Write pipelining disabled. Denali Core workaround */
  38 + mtdcr(plb0_acr, 0xDE000000);
  39 + mtdcr(plb1_acr, 0xDE000000);
40 40  
41 41 /*--------------------------------------------------------------------
42 42 * Setup the interrupt controller polarities, triggers, etc.
43 43  
... ... @@ -86,9 +86,9 @@
86 86 mtsdr(SDR0_PFC4, 0x80000000);
87 87  
88 88 /* PCI arbiter disabled */
89   - /* PCI Host Configuration disbaled */
  89 + /* PCI Host Configuration disbaled */
90 90 mfsdr(sdr_pci0, reg);
91   - reg = 0;
  91 + reg = 0;
92 92 mtsdr(sdr_pci0, 0x00000000 | reg);
93 93  
94 94 gpio_write_bit(CFG_GPIO_FLASH_WP, 1);
board/lwmon5/sdram.c
Diff comments   View file @ 83b4cfa
1 1 /*
2 2 * (C) Copyright 2006
3   - * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
  3 + * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
4 4 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
5   - * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
6   - * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
7   - * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
  5 + * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
  6 + * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
  7 + * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
8 8 *
9 9 * (C) Copyright 2007
10 10 * Stefan Roese, DENX Software Engineering, sr@denx.de.
11 11  
... ... @@ -49,9 +49,9 @@
49 49 * everything correctly.
50 50 */
51 51 #ifdef CFG_ENABLE_SDRAM_CACHE
52   -#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */
  52 +#define MY_TLB_WORD2_I_ENABLE 0 /* enable caching on SDRAM */
53 53 #else
54   -#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
  54 +#define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE /* disable caching on SDRAM */
55 55 #endif
56 56  
57 57 void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
... ... @@ -325,8 +325,8 @@
325 325  
326 326 debug("DQS calibration - Window detected:\n");
327 327 debug("max_passing_cases = %d\n", max_passing_cases);
328   - debug("wr_dqs_shift = %d\n", wr_dqs_shift);
329   - debug("dll_dqs_delay_X = %d\n", dll_dqs_delay_X);
  328 + debug("wr_dqs_shift = %d\n", wr_dqs_shift);
  329 + debug("dll_dqs_delay_X = %d\n", dll_dqs_delay_X);
330 330 debug("dll_dqs_delay_X window = %d - %d\n",
331 331 dll_dqs_delay_X_start_window, dll_dqs_delay_X_end_window);
332 332  
333 333  
334 334  
... ... @@ -561,16 +561,16 @@
561 561  
562 562 wait_for_dlllock();
563 563  
564   - /*
  564 + /*
565 565 * Program tlb entries for this size (dynamic)
566 566 */
567   - program_tlb(0, 0, CFG_MBYTES_SDRAM << 20, MY_TLB_WORD2_I_ENABLE);
  567 + program_tlb(0, 0, CFG_MBYTES_SDRAM << 20, MY_TLB_WORD2_I_ENABLE);
568 568  
569 569 /*
570 570 * Setup 2nd TLB with same physical address but different virtual address
571 571 * with cache enabled. This is done for fast ECC generation.
572 572 */
573   - program_tlb(0, CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20, 0);
  573 + program_tlb(0, CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20, 0);
574 574  
575 575 #ifdef CONFIG_DDR_DATA_EYE
576 576 /*
... ... @@ -22,26 +22,27 @@
22 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 23 * MA 02111-1307 USA
24 24 */
25   -/*------------------------------------------------------------------------------+ */
26   -/* */
27   -/* This source code has been made available to you by IBM on an AS-IS */
28   -/* basis. Anyone receiving this source is licensed under IBM */
29   -/* copyrights to use it in any way he or she deems fit, including */
30   -/* copying it, modifying it, compiling it, and redistributing it either */
31   -/* with or without modifications. No license under IBM patents or */
32   -/* patent applications is to be implied by the copyright license. */
33   -/* */
34   -/* Any user of this software should understand that IBM cannot provide */
35   -/* technical support for this software and will not be responsible for */
36   -/* any consequences resulting from the use of this software. */
37   -/* */
38   -/* Any person who transfers this source code or any derivative work */
39   -/* must include the IBM copyright notice, this paragraph, and the */
40   -/* preceding two paragraphs in the transferred software. */
41   -/* */
42   -/* COPYRIGHT I B M CORPORATION 1995 */
43   -/* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M */
44   -/*------------------------------------------------------------------------------- */
  25 +/*------------------------------------------------------------------------------+
  26 + *
  27 + * This source code has been made available to you by IBM on an AS-IS
  28 + * basis. Anyone receiving this source is licensed under IBM
  29 + * copyrights to use it in any way he or she deems fit, including
  30 + * copying it, modifying it, compiling it, and redistributing it either
  31 + * with or without modifications. No license under IBM patents or
  32 + * patent applications is to be implied by the copyright license.
  33 + *
  34 + * Any user of this software should understand that IBM cannot provide
  35 + * technical support for this software and will not be responsible for
  36 + * any consequences resulting from the use of this software.
  37 + *
  38 + * Any person who transfers this source code or any derivative work
  39 + * must include the IBM copyright notice, this paragraph, and the
  40 + * preceding two paragraphs in the transferred software.
  41 + *
  42 + * COPYRIGHT I B M CORPORATION 1995
  43 + * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
  44 + *-------------------------------------------------------------------------------
  45 + */
45 46  
46 47 /* U-Boot - Startup Code for AMCC 4xx PowerPC based Embedded Boards
47 48 *
48 49  
... ... @@ -110,11 +111,11 @@
110 111 # endif
111 112 #endif /* CFG_INIT_DCACHE_CS */
112 113  
113   -#define function_prolog(func_name) .text; \
  114 +#define function_prolog(func_name) .text; \
114 115 .align 2; \
115 116 .globl func_name; \
116 117 func_name:
117   -#define function_epilog(func_name) .type func_name,@function; \
  118 +#define function_epilog(func_name) .type func_name,@function; \
118 119 .size func_name,.-func_name
119 120  
120 121 /* We don't want the MMU yet.
... ... @@ -295,7 +296,7 @@
295 296 li r1,0x0c00
296 297 mtspr ivor8,r1 /* System call */
297 298 li r1,0x0a00
298   - mtspr ivor9,r1 /* Auxiliary Processor unavailable */
  299 + mtspr ivor9,r1 /* Auxiliary Processor unavailable */
299 300 li r1,0x0900
300 301 mtspr ivor10,r1 /* Decrementer */
301 302 li r1,0x1300
302 303  
... ... @@ -514,9 +515,9 @@
514 515  
515 516 #ifdef CONFIG_440
516 517 /* Machine check */
517   - MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
  518 + MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
518 519 #else
519   - CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException)
  520 + CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException)
520 521 #endif /* CONFIG_440 */
521 522  
522 523 /* Data Storage exception. */
523 524  
524 525  
... ... @@ -895,15 +896,15 @@
895 896 mtdcr ocmplb3cr2,r3 /* Set PLB Access */
896 897 isync
897 898  
898   - lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */
  899 + lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */
899 900 ori r3,r3,CFG_OCM_DATA_ADDR@l
900   - ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
901   - mtdcr ocmdscr1, r3 /* Set Data Side */
902   - mtdcr ocmiscr1, r3 /* Set Instruction Side */
  901 + ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
  902 + mtdcr ocmdscr1, r3 /* Set Data Side */
  903 + mtdcr ocmiscr1, r3 /* Set Instruction Side */
903 904 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
904   - mtdcr ocmdscr2, r3 /* Set Data Side */
905   - mtdcr ocmiscr2, r3 /* Set Instruction Side */
906   - addis r3,0,0x0800 /* OCM Data Parity Disable - 1 Wait State */
  905 + mtdcr ocmdscr2, r3 /* Set Data Side */
  906 + mtdcr ocmiscr2, r3 /* Set Instruction Side */
  907 + addis r3,0,0x0800 /* OCM Data Parity Disable - 1 Wait State */
907 908 mtdcr ocmdsisdpc,r3
908 909  
909 910 isync
... ... @@ -922,7 +923,7 @@
922 923 mtdcr ocmdscntl, r4 /* set data-side IRAM config */
923 924 isync
924 925  
925   - lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */
  926 + lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */
926 927 ori r3,r3,CFG_OCM_DATA_ADDR@l
927 928 mtdcr ocmdsarc, r3
928 929 addis r4, 0, 0xC000 /* OCM data area enabled */
... ... @@ -1170,8 +1171,8 @@
1170 1171 REST_GPR(31, r1)
1171 1172 lwz r2,_NIP(r1) /* Restore environment */
1172 1173 lwz r0,_MSR(r1)
1173   - mtspr csrr0,r2
1174   - mtspr csrr1,r0
  1174 + mtspr csrr0,r2
  1175 + mtspr csrr1,r0
1175 1176 lwz r0,GPR0(r1)
1176 1177 lwz r2,GPR2(r1)
1177 1178 lwz r1,GPR1(r1)
... ... @@ -1180,34 +1181,34 @@
1180 1181  
1181 1182 #ifdef CONFIG_440
1182 1183 mck_return:
1183   - mfmsr r28 /* Disable interrupts */
1184   - li r4,0
1185   - ori r4,r4,MSR_EE
1186   - andc r28,r28,r4
1187   - SYNC /* Some chip revs need this... */
1188   - mtmsr r28
1189   - SYNC
1190   - lwz r2,_CTR(r1)
1191   - lwz r0,_LINK(r1)
1192   - mtctr r2
1193   - mtlr r0
1194   - lwz r2,_XER(r1)
1195   - lwz r0,_CCR(r1)
1196   - mtspr XER,r2
1197   - mtcrf 0xFF,r0
1198   - REST_10GPRS(3, r1)
1199   - REST_10GPRS(13, r1)
1200   - REST_8GPRS(23, r1)
1201   - REST_GPR(31, r1)
1202   - lwz r2,_NIP(r1) /* Restore environment */
1203   - lwz r0,_MSR(r1)
1204   - mtspr mcsrr0,r2
1205   - mtspr mcsrr1,r0
1206   - lwz r0,GPR0(r1)
1207   - lwz r2,GPR2(r1)
1208   - lwz r1,GPR1(r1)
1209   - SYNC
1210   - rfmci
  1184 + mfmsr r28 /* Disable interrupts */
  1185 + li r4,0
  1186 + ori r4,r4,MSR_EE
  1187 + andc r28,r28,r4
  1188 + SYNC /* Some chip revs need this... */
  1189 + mtmsr r28
  1190 + SYNC
  1191 + lwz r2,_CTR(r1)
  1192 + lwz r0,_LINK(r1)
  1193 + mtctr r2
  1194 + mtlr r0
  1195 + lwz r2,_XER(r1)
  1196 + lwz r0,_CCR(r1)
  1197 + mtspr XER,r2
  1198 + mtcrf 0xFF,r0
  1199 + REST_10GPRS(3, r1)
  1200 + REST_10GPRS(13, r1)
  1201 + REST_8GPRS(23, r1)
  1202 + REST_GPR(31, r1)
  1203 + lwz r2,_NIP(r1) /* Restore environment */
  1204 + lwz r0,_MSR(r1)
  1205 + mtspr mcsrr0,r2
  1206 + mtspr mcsrr1,r0
  1207 + lwz r0,GPR0(r1)
  1208 + lwz r2,GPR2(r1)
  1209 + lwz r1,GPR1(r1)
  1210 + SYNC
  1211 + rfmci
1211 1212 #endif /* CONFIG_440 */
1212 1213  
1213 1214  
1214 1215  
1215 1216  
... ... @@ -1222,11 +1223,11 @@
1222 1223 #ifdef CONFIG_440
1223 1224 .globl dcache_disable
1224 1225 dcache_disable:
1225   - blr
  1226 + blr
1226 1227  
1227   - .globl dcache_status
  1228 + .globl dcache_status
1228 1229 dcache_status:
1229   - blr
  1230 + blr
1230 1231 #else
1231 1232 flush_dcache:
1232 1233 addis r9,r0,0x0002 /* set mask for EE and CE msr bits */
1233 1234  
1234 1235  
1235 1236  
1236 1237  
1237 1238  
1238 1239  
1239 1240  
1240 1241  
... ... @@ -1616,32 +1617,32 @@
1616 1617  
1617 1618 #ifdef CONFIG_440
1618 1619 li r7, .L_FPUnavailable - _start + _START_OFFSET
1619   - bl trap_reloc
  1620 + bl trap_reloc
1620 1621  
1621 1622 li r7, .L_Decrementer - _start + _START_OFFSET
1622   - bl trap_reloc
  1623 + bl trap_reloc
1623 1624  
1624 1625 li r7, .L_APU - _start + _START_OFFSET
1625   - bl trap_reloc
  1626 + bl trap_reloc
1626 1627  
1627   - li r7, .L_InstructionTLBError - _start + _START_OFFSET
1628   - bl trap_reloc
  1628 + li r7, .L_InstructionTLBError - _start + _START_OFFSET
  1629 + bl trap_reloc
1629 1630  
1630   - li r7, .L_DataTLBError - _start + _START_OFFSET
1631   - bl trap_reloc
  1631 + li r7, .L_DataTLBError - _start + _START_OFFSET
  1632 + bl trap_reloc
1632 1633 #else /* CONFIG_440 */
1633 1634 li r7, .L_PIT - _start + _START_OFFSET
1634   - bl trap_reloc
  1635 + bl trap_reloc
1635 1636  
1636 1637 li r7, .L_InstructionTLBMiss - _start + _START_OFFSET
1637   - bl trap_reloc
  1638 + bl trap_reloc
1638 1639  
1639 1640 li r7, .L_DataTLBMiss - _start + _START_OFFSET
1640   - bl trap_reloc
  1641 + bl trap_reloc
1641 1642 #endif /* CONFIG_440 */
1642 1643  
1643   - li r7, .L_DebugBreakpoint - _start + _START_OFFSET
1644   - bl trap_reloc
  1644 + li r7, .L_DebugBreakpoint - _start + _START_OFFSET
  1645 + bl trap_reloc
1645 1646  
1646 1647 #if !defined(CONFIG_440)
1647 1648 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
... ... @@ -1684,13 +1685,13 @@
1684 1685 +----------------------------------------------------------------------------*/
1685 1686 function_prolog(dcbz_area)
1686 1687 rlwinm. r5,r4,0,27,31
1687   - rlwinm r5,r4,27,5,31
1688   - beq ..d_ra2
1689   - addi r5,r5,0x0001
1690   -..d_ra2:mtctr r5
1691   -..d_ag2:dcbz r0,r3
1692   - addi r3,r3,32
1693   - bdnz ..d_ag2
  1688 + rlwinm r5,r4,27,5,31
  1689 + beq ..d_ra2
  1690 + addi r5,r5,0x0001
  1691 +..d_ra2:mtctr r5
  1692 +..d_ag2:dcbz r0,r3
  1693 + addi r3,r3,32
  1694 + bdnz ..d_ag2
1694 1695 sync
1695 1696 blr
1696 1697 function_epilog(dcbz_area)
1697 1698  
1698 1699  
... ... @@ -1699,26 +1700,26 @@
1699 1700 | dflush. Assume 32K at vector address is cachable.
1700 1701 +----------------------------------------------------------------------------*/
1701 1702 function_prolog(dflush)
1702   - mfmsr r9
1703   - rlwinm r8,r9,0,15,13
1704   - rlwinm r8,r8,0,17,15
1705   - mtmsr r8
1706   - addi r3,r0,0x0000
1707   - mtspr dvlim,r3
1708   - mfspr r3,ivpr
1709   - addi r4,r0,1024
1710   - mtctr r4
  1703 + mfmsr r9
  1704 + rlwinm r8,r9,0,15,13
  1705 + rlwinm r8,r8,0,17,15
  1706 + mtmsr r8
  1707 + addi r3,r0,0x0000
  1708 + mtspr dvlim,r3
  1709 + mfspr r3,ivpr
  1710 + addi r4,r0,1024
  1711 + mtctr r4
1711 1712 ..dflush_loop:
1712   - lwz r6,0x0(r3)
1713   - addi r3,r3,32
1714   - bdnz ..dflush_loop
1715   - addi r3,r3,-32
1716   - mtctr r4
1717   -..ag: dcbf r0,r3
1718   - addi r3,r3,-32
1719   - bdnz ..ag
  1713 + lwz r6,0x0(r3)
  1714 + addi r3,r3,32
  1715 + bdnz ..dflush_loop
  1716 + addi r3,r3,-32
  1717 + mtctr r4
  1718 +..ag: dcbf r0,r3
  1719 + addi r3,r3,-32
  1720 + bdnz ..ag
1720 1721 sync
1721   - mtmsr r9
  1722 + mtmsr r9
1722 1723 blr
1723 1724 function_epilog(dflush)
1724 1725 #endif /* CONFIG_440 */
... ... @@ -89,22 +89,22 @@
89 89 void
90 90 print_backtrace(unsigned long *sp)
91 91 {
92   - int cnt = 0;
93   - unsigned long i;
  92 + int cnt = 0;
  93 + unsigned long i;
94 94  
95   - printf("Call backtrace: ");
96   - while (sp) {
97   - if ((uint)sp > END_OF_MEM)
98   - break;
  95 + printf("Call backtrace: ");
  96 + while (sp) {
  97 + if ((uint)sp > END_OF_MEM)
  98 + break;
99 99  
100   - i = sp[1];
101   - if (cnt++ % 7 == 0)
102   - printf("\n");
103   - printf("%08lX ", i);
104   - if (cnt > 32) break;
105   - sp = (unsigned long *)*sp;
106   - }
107   - printf("\n");
  100 + i = sp[1];
  101 + if (cnt++ % 7 == 0)
  102 + printf("\n");
  103 + printf("%08lX ", i);
  104 + if (cnt > 32) break;
  105 + sp = (unsigned long *)*sp;
  106 + }
  107 + printf("\n");
108 108 }
109 109  
110 110 void show_regs(struct pt_regs * regs)
111 111  
... ... @@ -121,14 +121,12 @@
121 121  
122 122 printf("\n");
123 123 for (i = 0; i < 32; i++) {
124   - if ((i % 8) == 0)
125   - {
  124 + if ((i % 8) == 0) {
126 125 printf("GPR%02d: ", i);
127 126 }
128 127  
129 128 printf("%08lX ", regs->gpr[i]);
130   - if ((i % 8) == 7)
131   - {
  129 + if ((i % 8) == 7) {
132 130 printf("\n");
133 131 }
134 132 }
... ... @@ -147,7 +145,7 @@
147 145 MachineCheckException(struct pt_regs *regs)
148 146 {
149 147 unsigned long fixup, val;
150   -
  148 +
151 149 /* Probing PCI using config cycles cause this exception
152 150 * when a device is not present. Catch it and return to
153 151 * the PCI exception handler.
154 152  
155 153  
... ... @@ -172,16 +170,16 @@
172 170 if (val& ESR_IMCP) {
173 171 printf("Instruction");
174 172 mtspr(ESR, val & ~ESR_IMCP);
175   - } else
  173 + } else {
176 174 printf("Data");
  175 + }
177 176 printf(" machine check.\n");
178 177  
179 178 #elif defined(CONFIG_440)
180 179 if (val& ESR_IMCP){
181 180 printf("Instruction Synchronous Machine Check exception\n");
182 181 mtspr(SPRN_ESR, val & ~ESR_IMCP);
183   - }
184   - else {
  182 + } else {
185 183 val = mfspr(MCSR);
186 184 if (val & MCSR_IB)
187 185 printf("Instruction Read PLB Error\n");
... ... @@ -297,17 +295,17 @@
297 295  
298 296 __asm__ __volatile__( \
299 297 "1: lwz %0,0(%1)\n" \
300   - " eieio\n" \
301   - " li %0,0\n" \
302   - "2:\n" \
303   - ".section .fixup,\"ax\"\n" \
304   - "3: li %0,-1\n" \
305   - " b 2b\n" \
306   - ".section __ex_table,\"a\"\n" \
307   - " .align 2\n" \
308   - " .long 1b,3b\n" \
309   - ".text" \
310   - : "=r" (retval) : "r"(addr));
  298 + " eieio\n" \
  299 + " li %0,0\n" \
  300 + "2:\n" \
  301 + ".section .fixup,\"ax\"\n" \
  302 + "3: li %0,-1\n" \
  303 + " b 2b\n" \
  304 + ".section __ex_table,\"a\"\n" \
  305 + " .align 2\n" \
  306 + " .long 1b,3b\n" \
  307 + ".text" \
  308 + : "=r" (retval) : "r"(addr));
311 309  
312 310 return (retval);
313 311 #endif
include/configs/katmai.h
Diff comments   View file @ 83b4cfa
... ... @@ -29,7 +29,7 @@
29 29  
30 30 #ifndef __CONFIG_H
31 31 #define __CONFIG_H
32   -//#define DEBUG
  32 +
33 33 /*-----------------------------------------------------------------------
34 34 * High Level Configuration Options
35 35 *----------------------------------------------------------------------*/
include/ppc_asm.tmpl
Diff comments   View file @ 83b4cfa
... ... @@ -113,11 +113,11 @@
113 113  
114 114 #if defined(CONFIG_5xx)
115 115 /* Some special purpose registers */
116   -#define DER 149 /* Debug Enable Register */
117   -#define COUNTA 150 /* Breakpoint Counter */
118   -#define COUNTB 151 /* Breakpoint Counter */
119   -#define LCTRL1 156 /* Load/Store Support */
120   -#define LCTRL2 157 /* Load/Store Support */
  116 +#define DER 149 /* Debug Enable Register */
  117 +#define COUNTA 150 /* Breakpoint Counter */
  118 +#define COUNTB 151 /* Breakpoint Counter */
  119 +#define LCTRL1 156 /* Load/Store Support */
  120 +#define LCTRL2 157 /* Load/Store Support */
121 121 #define ICTRL 158 /* I-Bus Support Control Register */
122 122 #define EID 81
123 123 #endif /* CONFIG_5xx */
124 124  
125 125  
126 126  
127 127  
128 128  
129 129  
... ... @@ -266,39 +266,39 @@
266 266 addi r3,r1,STACK_FRAME_OVERHEAD; \
267 267 li r20,MSR_KERNEL; \
268 268 rlwimi r20,r23,0,25,25; \
269   - blrl; \
  269 + blrl; \
270 270 .L_ ## label : \
271 271 .long hdlr - _start + _START_OFFSET; \
272 272 .long int_return - _start + _START_OFFSET
273 273  
274 274 #define CRIT_EXCEPTION(n, label, hdlr) \
275   - . = n; \
  275 + . = n; \
276 276 label: \
277   - EXCEPTION_PROLOG(csrr0, csrr1); \
278   - lwz r3,GOT(transfer_to_handler); \
279   - mtlr r3; \
280   - addi r3,r1,STACK_FRAME_OVERHEAD; \
281   - li r20,(MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)); \
282   - rlwimi r20,r23,0,25,25; \
283   - blrl; \
  277 + EXCEPTION_PROLOG(csrr0, csrr1); \
  278 + lwz r3,GOT(transfer_to_handler); \
  279 + mtlr r3; \
  280 + addi r3,r1,STACK_FRAME_OVERHEAD; \
  281 + li r20,(MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)); \
  282 + rlwimi r20,r23,0,25,25; \
  283 + blrl; \
284 284 .L_ ## label : \
285   - .long hdlr - _start + _START_OFFSET; \
286   - .long crit_return - _start + _START_OFFSET
  285 + .long hdlr - _start + _START_OFFSET; \
  286 + .long crit_return - _start + _START_OFFSET
287 287  
288 288 #ifdef CONFIG_440
289 289 #define MCK_EXCEPTION(n, label, hdlr) \
290   - . = n; \
  290 + . = n; \
291 291 label: \
292   - EXCEPTION_PROLOG(MCSRR0, MCSRR1); \
293   - lwz r3,GOT(transfer_to_handler); \
294   - mtlr r3; \
295   - addi r3,r1,STACK_FRAME_OVERHEAD; \
296   - li r20,(MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)); \
297   - rlwimi r20,r23,0,25,25; \
298   - blrl; \
  292 + EXCEPTION_PROLOG(MCSRR0, MCSRR1); \
  293 + lwz r3,GOT(transfer_to_handler); \
  294 + mtlr r3; \
  295 + addi r3,r1,STACK_FRAME_OVERHEAD; \
  296 + li r20,(MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)); \
  297 + rlwimi r20,r23,0,25,25; \
  298 + blrl; \
299 299 .L_ ## label : \
300   - .long hdlr - _start + _START_OFFSET; \
301   - .long mck_return - _start + _START_OFFSET
  300 + .long hdlr - _start + _START_OFFSET; \
  301 + .long mck_return - _start + _START_OFFSET
302 302 #endif /* CONFIG_440 */
303 303  
304 304 #endif /* __PPC_ASM_TMPL__ */