Eric Lee / smarc-uboot

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Commit 83efc138dea4a667fcf6b295c35201a539ddb209

Authored by Adrian Alonso
Committed by Peng Fan
1 parent eb2fc68b8e
Exists in smarc-m6.0.1_2.1.0-ga and in 2 other branches imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga

MLK-10522-3: imx: mx7d_12x12_ddr3_arm2: add target board support 

* Add mx7d_12x12_ddr3_arm2 target board support
* Initial support for mx7d_12x12_ddr3_arm2 target
  board add support for base hardware eMMC, SD and
  ECSPI boot.

Signed-off-by: Adrian Alonso <aalonso@freescale.com>
Signed-off-by: Ye.Li <B37916@freescale.com>
(cherry picked from commit 51d69f7996cc6e6da8bb3f0af751549cb2435e44)

Conflicts:
	boards.cfg

Showing 6 changed files with 750 additions and 0 deletions Side-by-side Diff

board/freescale/mx7d_12x12_ddr3_arm2/Makefile
Diff comments   View file @ 83efc13
  1 +# (C) Copyright 2015 Freescale Semiconductor, Inc.
  2 +#
  3 +# SPDX-License-Identifier: GPL-2.0+
  4 +#
  5 +
  6 +obj-y := mx7d_12x12_ddr3_arm2.o
  7 +
  8 +extra-$(CONFIG_USE_PLUGIN) := plugin.bin
  9 +$(obj)/plugin.bin: $(obj)/plugin.o
  10 + $(OBJCOPY) -O binary --gap-fill 0xff $< $@
board/freescale/mx7d_12x12_ddr3_arm2/imximage.cfg
Diff comments   View file @ 83efc13
  1 +/*
  2 + * Copyright (C) 2015 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + *
  6 + * Refer docs/README.imxmage for more details about how-to configure
  7 + * and create imximage boot image
  8 + *
  9 + * The syntax is taken as close as possible with the kwbimage
  10 + */
  11 +
  12 +#define __ASSEMBLY__
  13 +#include <config.h>
  14 +
  15 +/* image version */
  16 +
  17 +IMAGE_VERSION 2
  18 +
  19 +/*
  20 + * Boot Device : one of
  21 + * sd/onenand, nor
  22 + */
  23 +
  24 +#ifdef CONFIG_SYS_BOOT_EIMNOR
  25 +BOOT_FROM nor
  26 +#else
  27 +BOOT_FROM sd
  28 +#endif
  29 +
  30 +#ifdef CONFIG_USE_PLUGIN
  31 +/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
  32 +PLUGIN board/freescale/mx7d_12x12_ddr3_arm2/plugin.bin 0x00910000
  33 +#else
  34 +
  35 +#ifdef CONFIG_SECURE_BOOT
  36 +CSF 0x2000
  37 +#endif
  38 +
  39 +/*
  40 + * Device Configuration Data (DCD)
  41 + *
  42 + * Each entry must have the format:
  43 + * Addr-type Address Value
  44 + *
  45 + * where:
  46 + * Addr-type register length (1,2 or 4 bytes)
  47 + * Address absolute address of the register
  48 + * value value to be stored in the register
  49 + */
  50 +
  51 +DATA 4 0x30340004 0x4F400005
  52 +
  53 +DATA 4 0x30391000 0x00000002
  54 +DATA 4 0x307a0000 0x03040001
  55 +DATA 4 0x307a01a0 0x80400003
  56 +DATA 4 0x307a01a4 0x00100020
  57 +DATA 4 0x307a01a8 0x80100004
  58 +DATA 4 0x307a0064 0x0040005e
  59 +DATA 4 0x307a0490 0x00000001
  60 +DATA 4 0x307a00d0 0x00020001
  61 +DATA 4 0x307a00d4 0x00010000
  62 +DATA 4 0x307a00dc 0x09300004
  63 +DATA 4 0x307a00e0 0x04080000
  64 +DATA 4 0x307a00e4 0x00090004
  65 +DATA 4 0x307a00f4 0x0000033f
  66 +DATA 4 0x307a0100 0x0908120a
  67 +DATA 4 0x307a0104 0x0002020e
  68 +DATA 4 0x307a0108 0x03040407
  69 +DATA 4 0x307a010c 0x00002006
  70 +DATA 4 0x307a0110 0x04020204
  71 +DATA 4 0x307a0114 0x03030202
  72 +DATA 4 0x307a0120 0x03030803
  73 +DATA 4 0x307a0180 0x00800020
  74 +DATA 4 0x307a0190 0x02098204
  75 +DATA 4 0x307a0194 0x00030303
  76 +DATA 4 0x307a0200 0x00000016
  77 +DATA 4 0x307a0204 0x00171717
  78 +DATA 4 0x307a0214 0x04040404
  79 +DATA 4 0x307a0218 0x00040404
  80 +DATA 4 0x307a0240 0x06000601
  81 +DATA 4 0x307a0244 0x00001323
  82 +DATA 4 0x30391000 0x00000000
  83 +DATA 4 0x30790000 0x17420f40
  84 +DATA 4 0x30790004 0x10210100
  85 +DATA 4 0x30790010 0x00060807
  86 +DATA 4 0x3079009c 0x00000d6e
  87 +DATA 4 0x30790020 0x08080808
  88 +DATA 4 0x30790030 0x08080808
  89 +DATA 4 0x30790050 0x01000010
  90 +DATA 4 0x30790050 0x00000010
  91 +
  92 +DATA 4 0x307900c0 0x0e407304
  93 +DATA 4 0x307900c0 0x0e447304
  94 +DATA 4 0x307900c0 0x0e447306
  95 +
  96 +CHECK_BITS_SET 4 0x307900c4 0x1
  97 +
  98 +DATA 4 0x307900c0 0x0e447304
  99 +DATA 4 0x307900c0 0x0e407304
  100 +
  101 +DATA 4 0x30384130 0x00000000
  102 +DATA 4 0x30340020 0x00000178
  103 +DATA 4 0x30384130 0x00000002
  104 +DATA 4 0x30790018 0x0000000f
  105 +
  106 +CHECK_BITS_SET 4 0x307a0004 0x1
  107 +#endif
board/freescale/mx7d_12x12_ddr3_arm2/mx7d_12x12_ddr3_arm2.c
Diff comments   View file @ 83efc13
  1 +/*
  2 + * Copyright (C) 2015 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <asm/arch/clock.h>
  8 +#include <asm/arch/imx-regs.h>
  9 +#include <asm/arch/mx7-pins.h>
  10 +#include <asm/arch/sys_proto.h>
  11 +#include <asm/gpio.h>
  12 +#include <asm/imx-common/iomux-v3.h>
  13 +#include <asm/imx-common/boot_mode.h>
  14 +#include <asm/io.h>
  15 +#include <linux/sizes.h>
  16 +#include <common.h>
  17 +#include <fsl_esdhc.h>
  18 +#include <mmc.h>
  19 +#include <miiphy.h>
  20 +#include <netdev.h>
  21 +#ifdef CONFIG_SYS_I2C_MXC
  22 +#include <i2c.h>
  23 +#include <asm/imx-common/mxc_i2c.h>
  24 +#endif
  25 +#include <asm/arch/crm_regs.h>
  26 +
  27 +DECLARE_GLOBAL_DATA_PTR;
  28 +
  29 +#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \
  30 + PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
  31 +#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
  32 + PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
  33 +#define USDHC_PAD_VSELECT (PAD_CTL_DSE_3P3V_32OHM | \
  34 + PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
  35 +#define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
  36 + PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM)
  37 +#define SPI_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
  38 +
  39 +#ifdef CONFIG_SYS_I2C_MXC
  40 +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  41 +/* I2C1 for PMIC */
  42 +struct i2c_pads_info i2c_pad_info1 = {
  43 + .scl = {
  44 + .i2c_mode = MX7D_PAD_GPIO1_IO04__I2C1_SCL | PC,
  45 + .gpio_mode = MX7D_PAD_GPIO1_IO04__GPIO1_IO4 | PC,
  46 + .gp = IMX_GPIO_NR(1, 4),
  47 + },
  48 + .sda = {
  49 + .i2c_mode = MX7D_PAD_GPIO1_IO05__I2C1_SDA | PC,
  50 + .gpio_mode = MX7D_PAD_GPIO1_IO05__GPIO1_IO5 | PC,
  51 + .gp = IMX_GPIO_NR(1, 5),
  52 + },
  53 +};
  54 +
  55 +/* I2C2 */
  56 +struct i2c_pads_info i2c_pad_info2 = {
  57 + .scl = {
  58 + .i2c_mode = MX7D_PAD_GPIO1_IO06__I2C2_SCL | PC,
  59 + .gpio_mode = MX7D_PAD_GPIO1_IO06__GPIO1_IO6 | PC,
  60 + .gp = IMX_GPIO_NR(1, 6),
  61 + },
  62 + .sda = {
  63 + .i2c_mode = MX7D_PAD_GPIO1_IO07__I2C2_SDA | PC,
  64 + .gpio_mode = MX7D_PAD_GPIO1_IO07__GPIO1_IO7 | PC,
  65 + .gp = IMX_GPIO_NR(1, 7),
  66 + },
  67 +};
  68 +#endif
  69 +
  70 +int dram_init(void)
  71 +{
  72 + gd->ram_size = PHYS_SDRAM_SIZE;
  73 +
  74 + return 0;
  75 +}
  76 +
  77 +static iomux_v3_cfg_t const uart1_pads[] = {
  78 + MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  79 + MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  80 +};
  81 +
  82 +static iomux_v3_cfg_t const usdhc2_emmc_pads[] = {
  83 + MX7D_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  84 + MX7D_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  85 + MX7D_PAD_SD2_DATA0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  86 + MX7D_PAD_SD2_DATA1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  87 + MX7D_PAD_SD2_DATA2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  88 + MX7D_PAD_SD2_DATA3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  89 + MX7D_PAD_ECSPI1_SCLK__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  90 + MX7D_PAD_ECSPI1_MOSI__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  91 + MX7D_PAD_ECSPI1_MISO__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  92 + MX7D_PAD_ECSPI1_SS0__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  93 +
  94 + MX7D_PAD_SD2_RESET_B__GPIO5_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
  95 +};
  96 +
  97 +static iomux_v3_cfg_t const usdhc3_pads[] = {
  98 + MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  99 + MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  100 + MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  101 + MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  102 + MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  103 + MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  104 +
  105 + MX7D_PAD_GPIO1_IO14__GPIO1_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
  106 + MX7D_PAD_GPIO1_IO15__GPIO1_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
  107 +};
  108 +
  109 +static iomux_v3_cfg_t const wdog_pads[] = {
  110 + MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL),
  111 +};
  112 +
  113 +static void setup_iomux_uart(void)
  114 +{
  115 + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  116 +}
  117 +
  118 +#ifdef CONFIG_FSL_ESDHC
  119 +
  120 +#define USDHC3_CD_GPIO IMX_GPIO_NR(1, 14)
  121 +#define USDHC2_PWR_GPIO IMX_GPIO_NR(5, 11)
  122 +
  123 +static struct fsl_esdhc_cfg usdhc_cfg[2] = {
  124 + {USDHC2_BASE_ADDR},
  125 + {USDHC3_BASE_ADDR, 0, 4},
  126 +};
  127 +
  128 +int mmc_get_env_devno(void)
  129 +{
  130 + u32 soc_sbmr = readl(SRC_BASE_ADDR + 0x58);
  131 + u32 dev_no;
  132 + u32 bootsel;
  133 +
  134 + bootsel = (soc_sbmr & 0x0000F000) >> 12;
  135 +
  136 + /* If not boot from sd/mmc, use default value */
  137 + if ((bootsel != BOOT_TYPE_SD) && (bootsel != BOOT_TYPE_MMC))
  138 + return CONFIG_SYS_MMC_ENV_DEV;
  139 +
  140 + /* BOOT_CFG2[2] and BOOT_CFG2[3] */
  141 + dev_no = (soc_sbmr & 0x00000C00) >> 10;
  142 +
  143 + return dev_no - 1;
  144 +}
  145 +
  146 +int mmc_map_to_kernel_blk(int dev_no)
  147 +{
  148 + return dev_no + 1;
  149 +}
  150 +
  151 +int board_mmc_getcd(struct mmc *mmc)
  152 +{
  153 + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  154 + int ret = 0;
  155 +
  156 + switch (cfg->esdhc_base) {
  157 + case USDHC2_BASE_ADDR:
  158 + ret = 1; /* uSDHC2 emmc always present */
  159 + break;
  160 + case USDHC3_BASE_ADDR:
  161 + ret = !gpio_get_value(USDHC3_CD_GPIO);
  162 + break;
  163 + }
  164 +
  165 + return ret;
  166 +}
  167 +int board_mmc_init(bd_t *bis)
  168 +{
  169 + int i;
  170 + /*
  171 + * According to the board_mmc_init() the following map is done:
  172 + * (U-boot device node) (Physical Port)
  173 + * mmc0 USDHC2 (eMMC)
  174 + * mmc1 USDHC3
  175 + */
  176 + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
  177 + switch (i) {
  178 + case 0:
  179 + imx_iomux_v3_setup_multiple_pads(
  180 + usdhc2_emmc_pads, ARRAY_SIZE(usdhc2_emmc_pads));
  181 + gpio_direction_output(USDHC2_PWR_GPIO, 1);
  182 + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  183 + break;
  184 + case 1:
  185 + imx_iomux_v3_setup_multiple_pads(
  186 + usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
  187 + gpio_direction_input(USDHC3_CD_GPIO);
  188 + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  189 + break;
  190 + default:
  191 + printf("Warning: you configured more USDHC controllers"
  192 + "(%d) than supported by the board\n", i + 1);
  193 + return 0;
  194 + }
  195 +
  196 + if (fsl_esdhc_initialize(bis, &usdhc_cfg[i]))
  197 + printf("Warning: failed to initialize mmc dev %d\n", i);
  198 + }
  199 +
  200 + return 0;
  201 +}
  202 +
  203 +int check_mmc_autodetect(void)
  204 +{
  205 + char *autodetect_str = getenv("mmcautodetect");
  206 +
  207 + if ((autodetect_str != NULL) &&
  208 + (strcmp(autodetect_str, "yes") == 0)) {
  209 + return 1;
  210 + }
  211 +
  212 + return 0;
  213 +}
  214 +
  215 +void board_late_mmc_init(void)
  216 +{
  217 + char cmd[32];
  218 + char mmcblk[32];
  219 + u32 dev_no = mmc_get_env_devno();
  220 +
  221 + if (!check_mmc_autodetect())
  222 + return;
  223 +
  224 + setenv_ulong("mmcdev", dev_no);
  225 +
  226 + /* Set mmcblk env */
  227 + sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw",
  228 + mmc_map_to_kernel_blk(dev_no));
  229 + setenv("mmcroot", mmcblk);
  230 +
  231 + sprintf(cmd, "mmc dev %d", dev_no);
  232 + run_command(cmd, 0);
  233 +}
  234 +
  235 +#endif
  236 +
  237 +#ifdef CONFIG_SYS_USE_SPINOR
  238 +iomux_v3_cfg_t const ecspi1_pads[] = {
  239 + MX7D_PAD_SD1_RESET_B__ECSPI4_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
  240 + MX7D_PAD_SD1_WP__ECSPI4_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
  241 + MX7D_PAD_SD1_CD_B__ECSPI4_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
  242 + /* Chip selects CS0:CS3 */
  243 + MX7D_PAD_SD1_CLK__GPIO5_IO3 | MUX_PAD_CTRL(NO_PAD_CTRL),
  244 + MX7D_PAD_SD1_CMD__GPIO5_IO4 | MUX_PAD_CTRL(NO_PAD_CTRL),
  245 + MX7D_PAD_SD1_DATA0__GPIO5_IO5 | MUX_PAD_CTRL(NO_PAD_CTRL),
  246 + MX7D_PAD_SD1_DATA1__GPIO5_IO6 | MUX_PAD_CTRL(NO_PAD_CTRL),
  247 +};
  248 +
  249 +void setup_spinor(void)
  250 +{
  251 + imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
  252 + ARRAY_SIZE(ecspi1_pads));
  253 + gpio_direction_output(IMX_GPIO_NR(5, 3), 0);
  254 +}
  255 +#endif
  256 +
  257 +int board_early_init_f(void)
  258 +{
  259 + setup_iomux_uart();
  260 +
  261 +#ifdef CONFIG_SYS_I2C_MXC
  262 + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
  263 + setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
  264 +#endif
  265 +
  266 + return 0;
  267 +}
  268 +
  269 +int board_init(void)
  270 +{
  271 + /* address of boot parameters */
  272 + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  273 +
  274 +#ifdef CONFIG_SYS_USE_SPINOR
  275 + setup_spinor();
  276 +#endif
  277 +
  278 + return 0;
  279 +}
  280 +
  281 +#ifdef CONFIG_CMD_BMODE
  282 +static const struct boot_mode board_boot_modes[] = {
  283 + /* 4 bit bus width */
  284 + {"emmc", MAKE_CFGVAL(0x10, 0x22, 0x00, 0x00)},
  285 + {"sd3", MAKE_CFGVAL(0x10, 0x1a, 0x00, 0x00)},
  286 + {NULL, 0},
  287 +};
  288 +#endif
  289 +
  290 +#ifdef CONFIG_PFUZE3000_PMIC_I2C
  291 +#define PFUZE_DEVICEID 0x0
  292 +#define PFUZE_REVID 0x3
  293 +#define PFUZE_FABID 0x4
  294 +
  295 +#define PFUZE_LDOGCTL 0x69
  296 +
  297 +static int setup_pmic_voltages(void)
  298 +{
  299 + unsigned char value, rev_id = 0;
  300 +
  301 + i2c_set_bus_num(CONFIG_PMIC_I2C_BUS);
  302 +
  303 + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_PMIC_I2C_SLAVE);
  304 + if (!i2c_probe(CONFIG_PMIC_I2C_SLAVE)) {
  305 + if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE_DEVICEID, 1, &value, 1)) {
  306 + printf("Read device ID error!\n");
  307 + return -1;
  308 + }
  309 + if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE_REVID, 1, &rev_id, 1)) {
  310 + printf("Read Rev ID error!\n");
  311 + return -1;
  312 + }
  313 + printf("Found PFUZE300! deviceid 0x%x, revid 0x%x\n", value, rev_id);
  314 +
  315 + /* disable Low Power Mode during standby mode */
  316 + if (i2c_read(CONFIG_PMIC_I2C_SLAVE, PFUZE_LDOGCTL, 1, &value, 1)) {
  317 + printf("Read LDOCTL error!\n");
  318 + return -1;
  319 + }
  320 + value |= 0x1;
  321 + if (i2c_write(CONFIG_PMIC_I2C_SLAVE, PFUZE_LDOGCTL, 1, &value, 1)) {
  322 + printf("Set LDOCTL error!\n");
  323 + return -1;
  324 + }
  325 + }
  326 +
  327 + return 0;
  328 +}
  329 +#endif
  330 +
  331 +int board_late_init(void)
  332 +{
  333 +#ifdef CONFIG_CMD_BMODE
  334 + add_board_boot_modes(board_boot_modes);
  335 +#endif
  336 +
  337 +#ifdef CONFIG_PFUZE3000_PMIC_I2C
  338 + int ret = 0;
  339 +
  340 + ret = setup_pmic_voltages();
  341 + if (ret)
  342 + return ret;
  343 +#endif
  344 +
  345 +#ifdef CONFIG_ENV_IS_IN_MMC
  346 + board_late_mmc_init();
  347 +#endif
  348 +
  349 + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
  350 +
  351 + set_wdog_reset((struct wdog_regs *)WDOG1_BASE_ADDR);
  352 +
  353 + return 0;
  354 +}
  355 +
  356 +u32 get_board_rev(void)
  357 +{
  358 + return get_cpu_rev();
  359 +}
  360 +
  361 +int checkboard(void)
  362 +{
  363 + puts("Board: MX7D 12x12 DDR3 ARM2\n");
  364 +
  365 + return 0;
  366 +}
  367 +
  368 +#ifdef CONFIG_USB_EHCI_MX7
  369 +iomux_v3_cfg_t const usb_otg1_pads[] = {
  370 + MX7D_PAD_UART3_TX_DATA__USB_OTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
  371 +};
  372 +
  373 +iomux_v3_cfg_t const usb_otg2_pads[] = {
  374 + MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
  375 +};
  376 +
  377 +int board_ehci_hcd_init(int port)
  378 +{
  379 + switch (port) {
  380 + case 0:
  381 + imx_iomux_v3_setup_multiple_pads(usb_otg1_pads,
  382 + ARRAY_SIZE(usb_otg1_pads));
  383 + break;
  384 + case 1:
  385 + imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
  386 + ARRAY_SIZE(usb_otg2_pads));
  387 + break;
  388 + default:
  389 + printf("MXC USB port %d not yet supported\n", port);
  390 + return 1;
  391 + }
  392 + return 0;
  393 +}
  394 +#endif
board/freescale/mx7d_12x12_ddr3_arm2/plugin.S
Diff comments   View file @ 83efc13
  1 +/*
  2 + * Copyright (C) 2015 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <config.h>
  8 +
  9 +/* DDR script */
  10 +.macro imx7d_12x12_ddr3_arm2_ddr_setting
  11 + /* Configure ocram_epdc */
  12 + ldr r0, =IOMUXC_GPR_BASE_ADDR
  13 + ldr r1, =0x4f400005
  14 + str r1, [r0, #0x4]
  15 +
  16 + ldr r0, =SRC_BASE_ADDR
  17 + ldr r1, =0x2
  18 + ldr r2, =0x1000
  19 + str r1, [r0, r2]
  20 +
  21 + ldr r0, =DDRC_IPS_BASE_ADDR
  22 + ldr r1, =0x03040001
  23 + str r1, [r0]
  24 + ldr r1, =0x80400003
  25 + str r1, [r0, #0x1a0]
  26 + ldr r1, =0x00100020
  27 + str r1, [r0, #0x1a4]
  28 + ldr r1, =0x80100004
  29 + str r1, [r0, #0x1a8]
  30 + ldr r1, =0x0040005e
  31 + str r1, [r0, #0x64]
  32 + ldr r1, =0x1
  33 + str r1, [r0, #0x490]
  34 + ldr r1, =0x00020001
  35 + str r1, [r0, #0xd0]
  36 + ldr r1, =0x00010000
  37 + str r1, [r0, #0xd4]
  38 + ldr r1, =0x09300004
  39 + str r1, [r0, #0xdc]
  40 + ldr r1, =0x04080000
  41 + str r1, [r0, #0xe0]
  42 + ldr r1, =0x00090004
  43 + str r1, [r0, #0xe4]
  44 + ldr r1, =0x33f
  45 + str r1, [r0, #0xf4]
  46 + ldr r1, =0x0908120a
  47 + str r1, [r0, #0x100]
  48 + ldr r1, =0x0002020e
  49 + str r1, [r0, #0x104]
  50 + ldr r1, =0x03040407
  51 + str r1, [r0, #0x108]
  52 + ldr r1, =0x00002006
  53 + str r1, [r0, #0x10c]
  54 + ldr r1, =0x04020204
  55 + str r1, [r0, #0x110]
  56 + ldr r1, =0x03030202
  57 + str r1, [r0, #0x114]
  58 + ldr r1, =0x03030803
  59 + str r1, [r0, #0x120]
  60 + ldr r1, =0x00800020
  61 + str r1, [r0, #0x180]
  62 + ldr r1, =0x02098204
  63 + str r1, [r0, #0x190]
  64 + ldr r1, =0x00030303
  65 + str r1, [r0, #0x194]
  66 +
  67 + ldr r1, =0x00000016
  68 + str r1, [r0, #0x200]
  69 + ldr r1, =0x00171717
  70 + str r1, [r0, #0x204]
  71 + ldr r1, =0x04040404
  72 + str r1, [r0, #0x214]
  73 + ldr r1, =0x00040404
  74 + str r1, [r0, #0x218]
  75 +
  76 + ldr r1, =0x06000601
  77 + str r1, [r0, #0x240]
  78 + ldr r1, =0x00001323
  79 + str r1, [r0, #0x244]
  80 +
  81 + ldr r0, =SRC_BASE_ADDR
  82 + mov r1, #0x0
  83 + ldr r2, =0x1000
  84 + str r1, [r0, r2]
  85 +
  86 + ldr r0, =DDRPHY_IPS_BASE_ADDR
  87 + ldr r1, =0x17420f40
  88 + str r1, [r0]
  89 + ldr r1, =0x10210100
  90 + str r1, [r0, #0x4]
  91 + ldr r1, =0x00060807
  92 + str r1, [r0, #0x10]
  93 + ldr r1, =0x00000d6e
  94 + str r1, [r0, #0x9c]
  95 + ldr r1, =0x08080808
  96 + str r1, [r0, #0x20]
  97 + ldr r1, =0x08080808
  98 + str r1, [r0, #0x30]
  99 + ldr r1, =0x01000010
  100 + str r1, [r0, #0x50]
  101 +
  102 + ldr r1, =0x0e407304
  103 + str r1, [r0, #0xc0]
  104 + ldr r1, =0x0e447304
  105 + str r1, [r0, #0xc0]
  106 + ldr r1, =0x0e447306
  107 + str r1, [r0, #0xc0]
  108 +
  109 +wait_zq:
  110 + ldr r1, [r0, #0xc4]
  111 + tst r1, #0x1
  112 + beq wait_zq
  113 +
  114 + ldr r1, =0x0e447304
  115 + str r1, [r0, #0xc0]
  116 + ldr r1, =0x0e407304
  117 + str r1, [r0, #0xc0]
  118 +
  119 + ldr r0, =CCM_BASE_ADDR
  120 + mov r1, #0x0
  121 + ldr r2, =0x4130
  122 + str r1, [r0, r2]
  123 + ldr r0, =IOMUXC_GPR_BASE_ADDR
  124 + mov r1, #0x178
  125 + str r1, [r0, #0x20]
  126 + ldr r0, =CCM_BASE_ADDR
  127 + mov r1, #0x2
  128 + ldr r2, =0x4130
  129 + str r1, [r0, r2]
  130 + ldr r0, =DDRPHY_IPS_BASE_ADDR
  131 + ldr r1, =0x0000000f
  132 + str r1, [r0, #0x18]
  133 +
  134 + ldr r0, =DDRC_IPS_BASE_ADDR
  135 +wait_stat:
  136 + ldr r1, [r0, #0x4]
  137 + tst r1, #0x1
  138 + beq wait_stat
  139 +.endm
  140 +
  141 +.macro imx7_clock_gating
  142 +.endm
  143 +
  144 +.macro imx7_qos_setting
  145 + ldr r0, =QOSC_IPS_BASE_ADDR
  146 + ldr r1, =0x0
  147 + str r1, [r0, #0x0]
  148 + str r1, [r0, #0x060]
  149 + str r1, [r0, #0x3400]
  150 + str r1, [r0, #0x2c00]
  151 + str r1, [r0, #0x3c00]
  152 +
  153 + ldr r1, =0x0f020722
  154 + str r1, [r0, #0x34d0]
  155 + str r1, [r0, #0x34e0]
  156 +
  157 + ldr r1, =0x1
  158 + str r1, [r0, #0x2c00]
  159 + str r1, [r0, #0x3c00]
  160 +
  161 + ldr r1, =0x0f020222
  162 + str r1, [r0, #0x2c50]
  163 + str r1, [r0, #0x3c50]
  164 + str r1, [r0, #0x2c60]
  165 + str r1, [r0, #0x3c60]
  166 + ldr r1, =0x0f020422
  167 + str r1, [r0, #0x2c70]
  168 + str r1, [r0, #0x3c70]
  169 +.endm
  170 +
  171 +.macro imx7_ddr_setting
  172 + imx7d_12x12_ddr3_arm2_ddr_setting
  173 +.endm
  174 +
  175 +/* include the common plugin code here */
  176 +#include <asm/arch/mx7_plugin.S>
configs/mx7d_12x12_ddr3_arm2_defconfig
Diff comments   View file @ 83efc13
  1 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7d_12x12_ddr3_arm2/imximage.cfg,MX7D,DEFAULT_FDT_FILE="imx7d-12x12-ddr3-arm2.dtb""
  2 +CONFIG_ARM=y
  3 +CONFIG_TARGET_MX7D_12X12_DDR3_ARM2=y
  4 +CONFIG_SYS_MALLOC_F=y
  5 +CONFIG_SYS_MALLOC_F_LEN=0x400
  6 +CONFIG_DM=y
  7 +CONFIG_DM_THERMAL=y
include/configs/mx7d_12x12_ddr3_arm2.h
Diff comments   View file @ 83efc13
  1 +/*
  2 + * Copyright (C) 2015 Freescale Semiconductor, Inc.
  3 + *
  4 + * Configuration settings for the Freescale i.MX7D 12x12 DDR3 ARM2 board.
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#ifndef __MX7D_12X12_DDR3_ARM2_CONFIG_H
  10 +#define __MX7D_12X12_DDR3_ARM2_CONFIG_H
  11 +
  12 +#define CONFIG_SYS_FSL_USDHC_NUM 2
  13 +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC3 */
  14 +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
  15 +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC3 */
  16 +
  17 +#define PHYS_SDRAM_SIZE SZ_1G
  18 +#define CONFIG_CMD_MEMTEST
  19 +#define CONFIG_SYS_MEMTEST_START 0x80000000
  20 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000)
  21 +
  22 +#ifdef CONFIG_SYS_BOOT_SPINOR
  23 +#define CONFIG_SYS_USE_SPINOR
  24 +#define CONFIG_ENV_IS_IN_SPI_FLASH
  25 +#else
  26 +#define CONFIG_ENV_IS_IN_MMC
  27 +#endif
  28 +
  29 +/* I2C configs */
  30 +#define CONFIG_CMD_I2C
  31 +#ifdef CONFIG_CMD_I2C
  32 +#define CONFIG_SYS_I2C
  33 +#define CONFIG_SYS_I2C_MXC
  34 +#define CONFIG_SYS_I2C_SPEED 100000
  35 +/* PMIC */
  36 +#define CONFIG_PFUZE3000_PMIC_I2C
  37 +#ifdef CONFIG_PFUZE3000_PMIC_I2C
  38 +#define CONFIG_PMIC_I2C_BUS 0
  39 +#define CONFIG_PMIC_I2C_SLAVE 0x8
  40 +#endif
  41 +#endif
  42 +
  43 +#ifdef CONFIG_SYS_USE_SPINOR
  44 +#define CONFIG_CMD_SF
  45 +#define CONFIG_SPI_FLASH
  46 +#define CONFIG_SPI_FLASH_ATMEL
  47 +#define CONFIG_MXC_SPI
  48 +#define CONFIG_SF_DEFAULT_BUS 3
  49 +#define CONFIG_SF_DEFAULT_SPEED 20000000
  50 +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
  51 +#define CONFIG_SF_DEFAULT_CS (0|(IMX_GPIO_NR(5, 3)<<8))
  52 +#endif
  53 +
  54 +#include "mx7d_arm2.h"
  55 +
  56 +#endif