Eric Lee / smarc-uboot

Download as
Browse Code ยป

Commit 849fc424713d176f90af0b05f6161bc3803ca887

Authored by Alison Wang
Committed by Jason
1 parent 33d4411931
Exists in master and in 55 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, emb_lf_v2023.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

ColdFire: Clean up checkpatch warnings for MCF5227x 

Signed-off-by: Alison Wang <b18965@freescale.com>

Showing 5 changed files with 123 additions and 115 deletions Side-by-side Diff

arch/m68k/cpu/mcf5227x/cpu.c
Diff comments   View file @ 849fc42
... ... @@ -3,7 +3,7 @@
3 3 * (C) Copyright 2000-2003
4 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 5 *
6   - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  6 + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
7 7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
8 8 *
9 9 * See file CREDITS for list of people who contributed to this
10 10  
11 11  
... ... @@ -30,14 +30,15 @@
30 30 #include <command.h>
31 31  
32 32 #include <asm/immap.h>
  33 +#include <asm/io.h>
33 34  
34 35 DECLARE_GLOBAL_DATA_PTR;
35 36  
36 37 int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
37 38 {
38   - volatile rcm_t *rcm = (rcm_t *) (MMAP_RCM);
  39 + rcm_t *rcm = (rcm_t *) (MMAP_RCM);
39 40 udelay(1000);
40   - rcm->rcr |= RCM_RCR_SOFTRST;
  41 + setbits_8(&rcm->rcr, RCM_RCR_SOFTRST);
41 42  
42 43 /* we don't return! */
43 44 return 0;
44 45  
... ... @@ -45,14 +46,14 @@
45 46  
46 47 int checkcpu(void)
47 48 {
48   - volatile ccm_t *ccm = (ccm_t *) MMAP_CCM;
  49 + ccm_t *ccm = (ccm_t *) MMAP_CCM;
49 50 u16 msk;
50 51 u16 id = 0;
51 52 u8 ver;
52 53  
53 54 puts("CPU: ");
54   - msk = (ccm->cir >> 6);
55   - ver = (ccm->cir & 0x003f);
  55 + msk = (in_be16(&ccm->cir) >> 6);
  56 + ver = (in_be16(&ccm->cir) & 0x003f);
56 57 switch (msk) {
57 58 case 0x6c:
58 59 id = 52277;
arch/m68k/cpu/mcf5227x/cpu_init.c
Diff comments   View file @ 849fc42
... ... @@ -3,7 +3,7 @@
3 3 * (C) Copyright 2000-2003
4 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 5 *
6   - * (C) Copyright 2004-2007 Freescale Semiconductor, Inc.
  6 + * (C) Copyright 2004-2007, 2012 Freescale Semiconductor, Inc.
7 7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
8 8 *
9 9 * See file CREDITS for list of people who contributed to this
... ... @@ -29,6 +29,7 @@
29 29 #include <watchdog.h>
30 30  
31 31 #include <asm/immap.h>
  32 +#include <asm/io.h>
32 33 #include <asm/rtc.h>
33 34  
34 35 /*
35 36  
36 37  
37 38  
38 39  
39 40  
40 41  
41 42  
42 43  
43 44  
... ... @@ -40,70 +41,70 @@
40 41 */
41 42 void cpu_init_f(void)
42 43 {
43   - volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
44   - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
45   - volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
46   - volatile pll_t *pll = (volatile pll_t *)MMAP_PLL;
  44 + scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
  45 + gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  46 + fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
  47 + pll_t *pll = (pll_t *)MMAP_PLL;
47 48  
48 49 #if !defined(CONFIG_CF_SBF)
49 50 /* Workaround, must place before fbcs */
50   - pll->psr = 0x12;
  51 + out_be32(&pll->psr, 0x12);
51 52  
52   - scm1->mpr = 0x77777777;
53   - scm1->pacra = 0;
54   - scm1->pacrb = 0;
55   - scm1->pacrc = 0;
56   - scm1->pacrd = 0;
57   - scm1->pacre = 0;
58   - scm1->pacrf = 0;
59   - scm1->pacrg = 0;
60   - scm1->pacri = 0;
  53 + out_be32(&scm1->mpr, 0x77777777);
  54 + out_be32(&scm1->pacra, 0);
  55 + out_be32(&scm1->pacrb, 0);
  56 + out_be32(&scm1->pacrc, 0);
  57 + out_be32(&scm1->pacrd, 0);
  58 + out_be32(&scm1->pacre, 0);
  59 + out_be32(&scm1->pacrf, 0);
  60 + out_be32(&scm1->pacrg, 0);
  61 + out_be32(&scm1->pacri, 0);
61 62  
62 63 #if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
63 64 && defined(CONFIG_SYS_CS0_CTRL))
64   - fbcs->csar0 = CONFIG_SYS_CS0_BASE;
65   - fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
66   - fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
  65 + out_be32(&fbcs->csar0, CONFIG_SYS_CS0_BASE);
  66 + out_be32(&fbcs->cscr0, CONFIG_SYS_CS0_CTRL);
  67 + out_be32(&fbcs->csmr0, CONFIG_SYS_CS0_MASK);
67 68 #endif
68 69 #endif /* CONFIG_CF_SBF */
69 70  
70 71 #if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
71 72 && defined(CONFIG_SYS_CS1_CTRL))
72   - fbcs->csar1 = CONFIG_SYS_CS1_BASE;
73   - fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
74   - fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
  73 + out_be32(&fbcs->csar1, CONFIG_SYS_CS1_BASE);
  74 + out_be32(&fbcs->cscr1, CONFIG_SYS_CS1_CTRL);
  75 + out_be32(&fbcs->csmr1, CONFIG_SYS_CS1_MASK);
75 76 #endif
76 77  
77 78 #if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
78 79 && defined(CONFIG_SYS_CS2_CTRL))
79   - fbcs->csar2 = CONFIG_SYS_CS2_BASE;
80   - fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
81   - fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
  80 + out_be32(&fbcs->csar2, CONFIG_SYS_CS2_BASE);
  81 + out_be32(&fbcs->cscr2, CONFIG_SYS_CS2_CTRL);
  82 + out_be32(&fbcs->csmr2, CONFIG_SYS_CS2_MASK);
82 83 #endif
83 84  
84 85 #if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
85 86 && defined(CONFIG_SYS_CS3_CTRL))
86   - fbcs->csar3 = CONFIG_SYS_CS3_BASE;
87   - fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
88   - fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
  87 + out_be32(&fbcs->csar3, CONFIG_SYS_CS3_BASE);
  88 + out_be32(&fbcs->cscr3, CONFIG_SYS_CS3_CTRL);
  89 + out_be32(&fbcs->csmr3, CONFIG_SYS_CS3_MASK);
89 90 #endif
90 91  
91 92 #if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
92 93 && defined(CONFIG_SYS_CS4_CTRL))
93   - fbcs->csar4 = CONFIG_SYS_CS4_BASE;
94   - fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
95   - fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
  94 + out_be32(&fbcs->csar4, CONFIG_SYS_CS4_BASE);
  95 + out_be32(&fbcs->cscr4, CONFIG_SYS_CS4_CTRL);
  96 + out_be32(&fbcs->csmr4, CONFIG_SYS_CS4_MASK);
96 97 #endif
97 98  
98 99 #if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
99 100 && defined(CONFIG_SYS_CS5_CTRL))
100   - fbcs->csar5 = CONFIG_SYS_CS5_BASE;
101   - fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
102   - fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
  101 + out_be32(&fbcs->csar5, CONFIG_SYS_CS5_BASE);
  102 + out_be32(&fbcs->cscr5, CONFIG_SYS_CS5_CTRL);
  103 + out_be32(&fbcs->csmr5, CONFIG_SYS_CS5_MASK);
103 104 #endif
104 105  
105 106 #ifdef CONFIG_FSL_I2C
106   - gpio->par_i2c = GPIO_PAR_I2C_SCL_SCL | GPIO_PAR_I2C_SDA_SDA;
  107 + out_8(&gpio->par_i2c, GPIO_PAR_I2C_SCL_SCL | GPIO_PAR_I2C_SDA_SDA);
107 108 #endif
108 109  
109 110 icache_enable();
110 111  
... ... @@ -115,11 +116,11 @@
115 116 int cpu_init_r(void)
116 117 {
117 118 #ifdef CONFIG_MCFRTC
118   - volatile rtc_t *rtc = (volatile rtc_t *)(CONFIG_SYS_MCFRTC_BASE);
119   - volatile rtcex_t *rtcex = (volatile rtcex_t *)&rtc->extended;
  119 + rtc_t *rtc = (rtc_t *)(CONFIG_SYS_MCFRTC_BASE);
  120 + rtcex_t *rtcex = (rtcex_t *)&rtc->extended;
120 121  
121   - rtcex->gocu = (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xFFFF;
122   - rtcex->gocl = CONFIG_SYS_RTC_OSCILLATOR & 0xFFFF;
  122 + out_be32(&rtcex->gocu, (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xffff);
  123 + out_be32(&rtcex->gocl, CONFIG_SYS_RTC_OSCILLATOR & 0xffff);
123 124 #endif
124 125  
125 126 return (0);
126 127  
127 128  
128 129  
... ... @@ -127,27 +128,27 @@
127 128  
128 129 void uart_port_conf(int port)
129 130 {
130   - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  131 + gpio_t *gpio = (gpio_t *) MMAP_GPIO;
131 132  
132 133 /* Setup Ports: */
133 134 switch (port) {
134 135 case 0:
135   - gpio->par_uart &=
136   - (GPIO_PAR_UART_U0TXD_UNMASK & GPIO_PAR_UART_U0RXD_UNMASK);
137   - gpio->par_uart |=
138   - (GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
  136 + clrbits_be16(&gpio->par_uart,
  137 + ~(GPIO_PAR_UART_U0TXD_UNMASK & GPIO_PAR_UART_U0RXD_UNMASK));
  138 + setbits_be16(&gpio->par_uart,
  139 + GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
139 140 break;
140 141 case 1:
141   - gpio->par_uart &=
142   - (GPIO_PAR_UART_U1TXD_UNMASK & GPIO_PAR_UART_U1RXD_UNMASK);
143   - gpio->par_uart |=
144   - (GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
  142 + clrbits_be16(&gpio->par_uart,
  143 + ~(GPIO_PAR_UART_U1TXD_UNMASK & GPIO_PAR_UART_U1RXD_UNMASK));
  144 + setbits_be16(&gpio->par_uart,
  145 + GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
145 146 break;
146 147 case 2:
147   - gpio->par_dspi &=
148   - (GPIO_PAR_DSPI_SIN_UNMASK & GPIO_PAR_DSPI_SOUT_UNMASK);
149   - gpio->par_dspi =
150   - (GPIO_PAR_DSPI_SIN_U2RXD | GPIO_PAR_DSPI_SOUT_U2TXD);
  148 + clrbits_8(&gpio->par_dspi,
  149 + ~(GPIO_PAR_DSPI_SIN_UNMASK & GPIO_PAR_DSPI_SOUT_UNMASK));
  150 + out_8(&gpio->par_dspi,
  151 + GPIO_PAR_DSPI_SIN_U2RXD | GPIO_PAR_DSPI_SOUT_U2TXD);
151 152 break;
152 153 }
153 154 }
154 155  
155 156  
156 157  
157 158  
158 159  
159 160  
... ... @@ -155,32 +156,32 @@
155 156 #ifdef CONFIG_CF_DSPI
156 157 void cfspi_port_conf(void)
157 158 {
158   - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  159 + gpio_t *gpio = (gpio_t *) MMAP_GPIO;
159 160  
160   - gpio->par_dspi =
161   - GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
162   - GPIO_PAR_DSPI_SCK_SCK;
  161 + out_8(&gpio->par_dspi,
  162 + GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
  163 + GPIO_PAR_DSPI_SCK_SCK);
163 164 }
164 165  
165 166 int cfspi_claim_bus(uint bus, uint cs)
166 167 {
167   - volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
168   - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  168 + dspi_t *dspi = (dspi_t *) MMAP_DSPI;
  169 + gpio_t *gpio = (gpio_t *) MMAP_GPIO;
169 170  
170   - if ((dspi->sr & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
  171 + if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
171 172 return -1;
172 173  
173 174 /* Clear FIFO and resume transfer */
174   - dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF);
  175 + clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
175 176  
176 177 switch (cs) {
177 178 case 0:
178   - gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_UNMASK;
179   - gpio->par_dspi |= GPIO_PAR_DSPI_PCS0_PCS0;
  179 + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_UNMASK);
  180 + setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
180 181 break;
181 182 case 2:
182   - gpio->par_timer &= GPIO_PAR_TIMER_T2IN_UNMASK;
183   - gpio->par_timer |= GPIO_PAR_TIMER_T2IN_DSPIPCS2;
  183 + clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK);
  184 + setbits_8(&gpio->par_timer, GPIO_PAR_TIMER_T2IN_DSPIPCS2);
184 185 break;
185 186 }
186 187  
187 188  
188 189  
189 190  
... ... @@ -189,17 +190,18 @@
189 190  
190 191 void cfspi_release_bus(uint bus, uint cs)
191 192 {
192   - volatile dspi_t *dspi = (dspi_t *) MMAP_DSPI;
193   - volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  193 + dspi_t *dspi = (dspi_t *) MMAP_DSPI;
  194 + gpio_t *gpio = (gpio_t *) MMAP_GPIO;
194 195  
195   - dspi->mcr &= ~(DSPI_MCR_CTXF | DSPI_MCR_CRXF); /* Clear FIFO */
  196 + /* Clear FIFO */
  197 + clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
196 198  
197 199 switch (cs) {
198 200 case 0:
199   - gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0;
  201 + clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
200 202 break;
201 203 case 2:
202   - gpio->par_timer &= GPIO_PAR_TIMER_T2IN_UNMASK;
  204 + clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK);
203 205 break;
204 206 }
205 207 }
arch/m68k/cpu/mcf5227x/interrupts.c
Diff comments   View file @ 849fc42
... ... @@ -3,7 +3,7 @@
3 3 * (C) Copyright 2000-2004
4 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 5 *
6   - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  6 + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
7 7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
8 8 *
9 9 * See file CREDITS for list of people who contributed to this
10 10  
11 11  
... ... @@ -28,14 +28,15 @@
28 28 /* CPU specific interrupt routine */
29 29 #include <common.h>
30 30 #include <asm/immap.h>
  31 +#include <asm/io.h>
31 32  
32 33 int interrupt_init(void)
33 34 {
34   - volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
  35 + int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
35 36  
36 37 /* Make sure all interrupts are disabled */
37   - intp->imrh0 |= 0xFFFFFFFF;
38   - intp->imrl0 |= 0xFFFFFFFF;
  38 + setbits_be32(&intp->imrh0, 0xffffffff);
  39 + setbits_be32(&intp->imrl0, 0xffffffff);
39 40  
40 41 enable_interrupts();
41 42 return 0;
42 43  
... ... @@ -44,10 +45,10 @@
44 45 #if defined(CONFIG_MCFTMR)
45 46 void dtimer_intr_setup(void)
46 47 {
47   - volatile int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
  48 + int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
48 49  
49   - intp->icr0[CONFIG_SYS_TMRINTR_NO] = CONFIG_SYS_TMRINTR_PRI;
50   - intp->imrh0 &= ~CONFIG_SYS_TMRINTR_MASK;
  50 + out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI);
  51 + clrbits_be32(&intp->imrh0, CONFIG_SYS_TMRINTR_MASK);
51 52 }
52 53 #endif
arch/m68k/cpu/mcf5227x/speed.c
Diff comments   View file @ 849fc42
1 1 /*
2 2 *
3   - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  3 + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
4 4 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
5 5 *
6 6 * See file CREDITS for list of people who contributed to this
... ... @@ -26,6 +26,7 @@
26 26 #include <asm/processor.h>
27 27  
28 28 #include <asm/immap.h>
  29 +#include <asm/io.h>
29 30  
30 31 DECLARE_GLOBAL_DATA_PTR;
31 32  
... ... @@ -44,7 +45,7 @@
44 45  
45 46 void clock_enter_limp(int lpdiv)
46 47 {
47   - volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM;
  48 + ccm_t *ccm = (ccm_t *)MMAP_CCM;
48 49 int i, j;
49 50  
50 51 /* Check bounds of divider */
51 52  
... ... @@ -57,10 +58,10 @@
57 58 for (i = 0, j = lpdiv; j != 1; j >>= 1, i++) ;
58 59  
59 60 /* Apply the divider to the system clock */
60   - ccm->cdr = (ccm->cdr & 0xF0FF) | CCM_CDR_LPDIV(i);
  61 + clrsetbits_be16(&ccm->cdr, 0x0f00, CCM_CDR_LPDIV(i));
61 62  
62 63 /* Enable Limp Mode */
63   - ccm->misccr |= CCM_MISCCR_LIMP;
  64 + setbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
64 65 }
65 66  
66 67 /*
67 68  
68 69  
... ... @@ -69,14 +70,15 @@
69 70 */
70 71 void clock_exit_limp(void)
71 72 {
72   - volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM;
73   - volatile pll_t *pll = (volatile pll_t *)MMAP_PLL;
  73 + ccm_t *ccm = (ccm_t *)MMAP_CCM;
  74 + pll_t *pll = (pll_t *)MMAP_PLL;
74 75  
75 76 /* Exit Limp mode */
76   - ccm->misccr &= ~CCM_MISCCR_LIMP;
  77 + clrbits_be16(&ccm->misccr, CCM_MISCCR_LIMP);
77 78  
78 79 /* Wait for the PLL to lock */
79   - while (!(pll->psr & PLL_PSR_LOCK)) ;
  80 + while (!(in_be32(&pll->psr) & PLL_PSR_LOCK))
  81 + ;
80 82 }
81 83  
82 84 /*
83 85  
... ... @@ -85,12 +87,12 @@
85 87 int get_clocks(void)
86 88 {
87 89  
88   - volatile ccm_t *ccm = (volatile ccm_t *)MMAP_CCM;
89   - volatile pll_t *pll = (volatile pll_t *)MMAP_PLL;
  90 + ccm_t *ccm = (ccm_t *)MMAP_CCM;
  91 + pll_t *pll = (pll_t *)MMAP_PLL;
90 92 int vco, temp, pcrvalue, pfdr;
91 93 u8 bootmode;
92 94  
93   - pcrvalue = pll->pcr & 0xFF0F0FFF;
  95 + pcrvalue = in_be32(&pll->pcr) & 0xFF0F0FFF;
94 96 pfdr = pcrvalue >> 24;
95 97  
96 98 if (pfdr == 0x1E)
97 99  
98 100  
99 101  
100 102  
101 103  
102 104  
103 105  
... ... @@ -102,32 +104,32 @@
102 104  
103 105 if (bootmode == 0) {
104 106 /* Normal mode */
105   - vco = ((pll->pcr & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
  107 + vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
106 108 if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) {
107 109 /* Default value */
108   - pcrvalue = (pll->pcr & 0x00FFFFFF);
  110 + pcrvalue = (in_be32(&pll->pcr) & 0x00FFFFFF);
109 111 pcrvalue |= 0x1E << 24;
110   - pll->pcr = pcrvalue;
  112 + out_be32(&pll->pcr, pcrvalue);
111 113 vco =
112   - ((pll->pcr & 0xFF000000) >> 24) *
  114 + ((in_be32(&pll->pcr) & 0xFF000000) >> 24) *
113 115 CONFIG_SYS_INPUT_CLKSRC;
114 116 }
115 117 gd->vco_clk = vco; /* Vco clock */
116 118 } else if (bootmode == 3) {
117 119 /* serial mode */
118   - vco = ((pll->pcr & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
  120 + vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC;
119 121 gd->vco_clk = vco; /* Vco clock */
120 122 }
121 123  
122   - if ((ccm->ccr & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
  124 + if ((in_be16(&ccm->ccr) & CCM_MISCCR_LIMP) == CCM_MISCCR_LIMP) {
123 125 /* Limp mode */
124 126 } else {
125 127 gd->inp_clk = CONFIG_SYS_INPUT_CLKSRC; /* Input clock */
126 128  
127   - temp = (pll->pcr & PLL_PCR_OUTDIV1_MASK) + 1;
  129 + temp = (in_be32(&pll->pcr) & PLL_PCR_OUTDIV1_MASK) + 1;
128 130 gd->cpu_clk = vco / temp; /* cpu clock */
129 131  
130   - temp = ((pll->pcr & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
  132 + temp = ((in_be32(&pll->pcr) & PLL_PCR_OUTDIV2_MASK) >> 4) + 1;
131 133 gd->flb_clk = vco / temp; /* flexbus clock */
132 134 gd->bus_clk = gd->flb_clk;
133 135 }
board/freescale/m52277evb/m52277evb.c
Diff comments   View file @ 849fc42
... ... @@ -2,7 +2,7 @@
2 2 * (C) Copyright 2000-2003
3 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 4 *
5   - * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
  5 + * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
6 6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 7 *
8 8 * See file CREDITS for list of people who contributed to this
... ... @@ -26,6 +26,7 @@
26 26  
27 27 #include <common.h>
28 28 #include <asm/immap.h>
  29 +#include <asm/io.h>
29 30  
30 31 DECLARE_GLOBAL_DATA_PTR;
31 32  
... ... @@ -47,8 +48,8 @@
47 48 */
48 49 dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
49 50 #else
50   - volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM);
51   - volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO);
  51 + sdramc_t *sdram = (sdramc_t *)(MMAP_SDRAM);
  52 + gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
52 53 u32 i;
53 54  
54 55 dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
55 56  
56 57  
57 58  
58 59  
59 60  
60 61  
61 62  
62 63  
63 64  
... ... @@ -59,36 +60,37 @@
59 60 }
60 61 i--;
61 62  
62   - gpio->mscr_sdram = CONFIG_SYS_SDRAM_DRV_STRENGTH;
  63 + out_8(&gpio->mscr_sdram, CONFIG_SYS_SDRAM_DRV_STRENGTH);
63 64  
64   - sdram->sdcs0 = (CONFIG_SYS_SDRAM_BASE | i);
  65 + out_be32(&sdram->sdcs0, CONFIG_SYS_SDRAM_BASE | i);
65 66  
66   - sdram->sdcfg1 = CONFIG_SYS_SDRAM_CFG1;
67   - sdram->sdcfg2 = CONFIG_SYS_SDRAM_CFG2;
  67 + out_be32(&sdram->sdcfg1, CONFIG_SYS_SDRAM_CFG1);
  68 + out_be32(&sdram->sdcfg2, CONFIG_SYS_SDRAM_CFG2);
68 69  
69 70 /* Issue PALL */
70   - sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
  71 + out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
71 72 __asm__("nop");
72 73  
73 74 /* Issue LEMR */
74   - sdram->sdmr = CONFIG_SYS_SDRAM_MODE;
  75 + out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_MODE);
75 76 __asm__("nop");
76   - sdram->sdmr = CONFIG_SYS_SDRAM_EMOD;
  77 + out_be32(&sdram->sdmr, CONFIG_SYS_SDRAM_EMOD);
77 78 __asm__("nop");
78 79  
79 80 udelay(1000);
80 81  
81 82 /* Issue PALL */
82   - sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
  83 + out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 2);
83 84 __asm__("nop");
84 85  
85 86 /* Perform two refresh cycles */
86   - sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
  87 + out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
87 88 __asm__("nop");
88   - sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
  89 + out_be32(&sdram->sdcr, CONFIG_SYS_SDRAM_CTRL | 4);
89 90 __asm__("nop");
90 91  
91   - sdram->sdcr = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000C00;
  92 + out_be32(&sdram->sdcr,
  93 + (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00);
92 94  
93 95 udelay(100);
94 96 #endif