Eric Lee / smarc-uboot

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Commit 84b124db3584d8b3f1a42c1506983323bce9983f

Authored by Dinh Nguyen
Committed by Tom Rini
1 parent 2bac27ce94
Exists in smarc_8mq_lf_v2020.04 and in 9 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

dm: cache: Create a uclass for cache 

The cache UCLASS will be used for configure settings that can be found
in a CPU's L2 cache controller.

Add a uclass and a test for cache.

Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>

Showing 9 changed files with 139 additions and 0 deletions Side-by-side Diff

... ... @@ -14,6 +14,8 @@
14 14  
15 15 source "drivers/bootcount/Kconfig"
16 16  
  17 +source "drivers/cache/Kconfig"
  18 +
17 19 source "drivers/clk/Kconfig"
18 20  
19 21 source "drivers/cpu/Kconfig"
... ... @@ -77,6 +77,7 @@
77 77 obj-y += block/
78 78 obj-y += board/
79 79 obj-$(CONFIG_BOOTCOUNT_LIMIT) += bootcount/
  80 +obj-y += cache/
80 81 obj-$(CONFIG_CPU) += cpu/
81 82 obj-y += crypto/
82 83 obj-$(CONFIG_FASTBOOT) += fastboot/
drivers/cache/Kconfig
Diff comments   View file @ 84b124d
  1 +#
  2 +# Cache controllers
  3 +#
  4 +
  5 +menu "Cache Controller drivers"
  6 +
  7 +config CACHE
  8 + bool "Enable Driver Model for Cache controllers"
  9 + depends on DM
  10 + help
  11 + Enable driver model for cache controllers that are found on
  12 + most CPU's. Cache is memory that the CPU can access directly and
  13 + is usually located on the same chip. This uclass can be used for
  14 + configuring settings that be found from a device tree file.
  15 +
  16 +endmenu
drivers/cache/Makefile
Diff comments   View file @ 84b124d
  1 +
  2 +obj-$(CONFIG_CACHE) += cache-uclass.o
  3 +obj-$(CONFIG_SANDBOX) += sandbox_cache.o
drivers/cache/cache-uclass.c
Diff comments   View file @ 84b124d
  1 +// SPDX-License-Identifier: GPL-2.0+
  2 +/*
  3 + * Copyright (C) 2019 Intel Corporation <www.intel.com>
  4 + */
  5 +
  6 +#include <common.h>
  7 +#include <cache.h>
  8 +#include <dm.h>
  9 +
  10 +int cache_get_info(struct udevice *dev, struct cache_info *info)
  11 +{
  12 + struct cache_ops *ops = cache_get_ops(dev);
  13 +
  14 + if (!ops->get_info)
  15 + return -ENOSYS;
  16 +
  17 + return ops->get_info(dev, info);
  18 +}
  19 +
  20 +UCLASS_DRIVER(cache) = {
  21 + .id = UCLASS_CACHE,
  22 + .name = "cache",
  23 + .post_bind = dm_scan_fdt_dev,
  24 +};
drivers/cache/sandbox_cache.c
Diff comments   View file @ 84b124d
  1 +// SPDX-License-Identifier: GPL-2.0
  2 +/*
  3 + * Copyright (C) 2019 Intel Corporation <www.intel.com>
  4 + */
  5 +
  6 +#include <common.h>
  7 +#include <cache.h>
  8 +#include <dm.h>
  9 +#include <errno.h>
  10 +
  11 +DECLARE_GLOBAL_DATA_PTR;
  12 +
  13 +static int sandbox_get_info(struct udevice *dev, struct cache_info *info)
  14 +{
  15 + info->base = 0x11223344;
  16 +
  17 + return 0;
  18 +}
  19 +
  20 +static const struct cache_ops sandbox_cache_ops = {
  21 + .get_info = sandbox_get_info,
  22 +};
  23 +
  24 +static const struct udevice_id sandbox_cache_ids[] = {
  25 + { .compatible = "sandbox,cache" },
  26 + { }
  27 +};
  28 +
  29 +U_BOOT_DRIVER(cache_sandbox) = {
  30 + .name = "cache_sandbox",
  31 + .id = UCLASS_CACHE,
  32 + .of_match = sandbox_cache_ids,
  33 + .ops = &sandbox_cache_ops,
  34 +};
  1 +// SPDX-License-Identifier: GPL-2.0
  2 +/*
  3 + * Copyright (C) 2019 Intel Corporation <www.intel.com>
  4 + */
  5 +
  6 +#ifndef __CACHE_H
  7 +#define __CACHE_H
  8 +
  9 +/*
  10 + * Structure for the cache controller
  11 + */
  12 +struct cache_info {
  13 + phys_addr_t base; /* Base physical address of cache device. */
  14 +};
  15 +
  16 +struct cache_ops {
  17 + /**
  18 + * get_info() - Get basic cache info
  19 + *
  20 + * @dev: Device to check (UCLASS_CACHE)
  21 + * @info: Place to put info
  22 + * @return 0 if OK, -ve on error
  23 + */
  24 + int (*get_info)(struct udevice *dev, struct cache_info *info);
  25 +};
  26 +
  27 +#define cache_get_ops(dev) ((struct cache_ops *)(dev)->driver->ops)
  28 +
  29 +/**
  30 + * cache_get_info() - Get information about a cache controller
  31 + *
  32 + * @dev: Device to check (UCLASS_CACHE)
  33 + * @info: Returns cache info
  34 + * @return 0 if OK, -ve on error
  35 + */
  36 +int cache_get_info(struct udevice *dev, struct cache_info *info);
  37 +
  38 +#endif
include/dm/uclass-id.h
Diff comments   View file @ 84b124d
... ... @@ -34,6 +34,7 @@
34 34 UCLASS_BLK, /* Block device */
35 35 UCLASS_BOARD, /* Device information from hardware */
36 36 UCLASS_BOOTCOUNT, /* Bootcount backing store */
  37 + UCLASS_CACHE, /* Cache controller */
37 38 UCLASS_CLK, /* Clock source, e.g. used by peripherals */
38 39 UCLASS_CPU, /* CPU, typically part of an SoC */
39 40 UCLASS_CROS_EC, /* Chrome OS EC */
  1 +// SPDX-License-Identifier: GPL-2.0
  2 +/*
  3 + * Copyright (C) 2019 Intel Corporation <www.intel.com>
  4 + */
  5 +
  6 +#include <common.h>
  7 +#include <dm.h>
  8 +#include <dm/test.h>
  9 +
  10 +static int dm_test_reset(struct unit_test_state *uts)
  11 +{
  12 + struct udevice *dev_cache;
  13 + struct cache_info;
  14 +
  15 + ut_assertok(uclass_get_device(UCLASS_CACHE, 0, &dev_cache));
  16 + ut_assertok(cache_get_info(dev, &info));
  17 +
  18 + return 0;
  19 +}
  20 +DM_TEST(dm_test_reset, DM_TESTF_SCAN_FDT);