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Commit 85231c087eff5968e37966d6cc751f954301c43d

Authored by Michal Simek
1 parent 10aaa3584b
Exists in smarc_8mq_lf_v2020.04 and in 11 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

arm64: zynqmp: Add support for zc12xx boards 

Add support for zc12xx boards. All of them are internal boards for
silicon validation and share very similar base platforms.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Showing 10 changed files with 1606 additions and 0 deletions Side-by-side Diff

arch/arm/dts/Makefile
Diff comments   View file @ 85231c0
... ... @@ -152,6 +152,9 @@
152 152 zynqmp-zcu102-revA.dtb \
153 153 zynqmp-zcu102-revB.dtb \
154 154 zynqmp-zcu102-rev1.0.dtb \
  155 + zynqmp-zc1232-revA.dtb \
  156 + zynqmp-zc1254-revA.dtb \
  157 + zynqmp-zc1275-revA.dtb \
155 158 zynqmp-zc1751-xm015-dc1.dtb \
156 159 zynqmp-zc1751-xm016-dc2.dtb \
157 160 zynqmp-zc1751-xm017-dc3.dtb \
arch/arm/dts/zynqmp-zc1232-revA.dts
Diff comments   View file @ 85231c0
  1 +// SPDX-License-Identifier: GPL-2.0+
  2 +/*
  3 + * dts file for Xilinx ZynqMP ZC1232
  4 + *
  5 + * (C) Copyright 2017 - 2018, Xilinx, Inc.
  6 + *
  7 + * Michal Simek <michal.simek@xilinx.com>
  8 + */
  9 +
  10 +/dts-v1/;
  11 +
  12 +#include "zynqmp.dtsi"
  13 +#include "zynqmp-clk-ccf.dtsi"
  14 +#include <dt-bindings/phy/phy.h>
  15 +
  16 +/ {
  17 + model = "ZynqMP ZC1232 RevA";
  18 + compatible = "xlnx,zynqmp-zc1232-revA", "xlnx,zynqmp-zc1232", "xlnx,zynqmp";
  19 +
  20 + aliases {
  21 + serial0 = &uart0;
  22 + serial1 = &dcc;
  23 + spi0 = &qspi;
  24 + };
  25 +
  26 + chosen {
  27 + bootargs = "earlycon";
  28 + stdout-path = "serial0:115200n8";
  29 + };
  30 +
  31 + memory@0 {
  32 + device_type = "memory";
  33 + reg = <0x0 0x0 0x0 0x80000000>;
  34 + };
  35 +};
  36 +
  37 +&dcc {
  38 + status = "okay";
  39 +};
  40 +
  41 +&qspi {
  42 + status = "okay";
  43 + flash@0 {
  44 + compatible = "m25p80"; /* 32MB FIXME */
  45 + #address-cells = <1>;
  46 + #size-cells = <1>;
  47 + reg = <0x0>;
  48 + spi-tx-bus-width = <1>;
  49 + spi-rx-bus-width = <4>;
  50 + spi-max-frequency = <108000000>; /* Based on DC1 spec */
  51 + partition@qspi-fsbl-uboot { /* for testing purpose */
  52 + label = "qspi-fsbl-uboot";
  53 + reg = <0x0 0x100000>;
  54 + };
  55 + partition@qspi-linux { /* for testing purpose */
  56 + label = "qspi-linux";
  57 + reg = <0x100000 0x500000>;
  58 + };
  59 + partition@qspi-device-tree { /* for testing purpose */
  60 + label = "qspi-device-tree";
  61 + reg = <0x600000 0x20000>;
  62 + };
  63 + partition@qspi-rootfs { /* for testing purpose */
  64 + label = "qspi-rootfs";
  65 + reg = <0x620000 0x5E0000>;
  66 + };
  67 + };
  68 +};
  69 +
  70 +&sata {
  71 + status = "okay";
  72 + /* SATA OOB timing settings */
  73 + ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
  74 + ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
  75 + ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
  76 + ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
  77 + ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
  78 + ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
  79 + ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
  80 + ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
  81 + phy-names = "sata-phy";
  82 + phys = <&lane0 PHY_TYPE_SATA 0 0 125000000>, <&lane1 PHY_TYPE_SATA 1 1 125000000>;
  83 +};
  84 +
  85 +&uart0 {
  86 + status = "okay";
  87 +};
arch/arm/dts/zynqmp-zc1254-revA.dts
Diff comments   View file @ 85231c0
  1 +// SPDX-License-Identifier: GPL-2.0+
  2 +/*
  3 + * dts file for Xilinx ZynqMP ZC1254
  4 + *
  5 + * (C) Copyright 2015 - 2018, Xilinx, Inc.
  6 + *
  7 + * Michal Simek <michal.simek@xilinx.com>
  8 + * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
  9 + */
  10 +
  11 +/dts-v1/;
  12 +
  13 +#include "zynqmp.dtsi"
  14 +#include "zynqmp-clk-ccf.dtsi"
  15 +
  16 +/ {
  17 + model = "ZynqMP ZC1254 RevA";
  18 + compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp";
  19 +
  20 + aliases {
  21 + serial0 = &uart0;
  22 + serial1 = &dcc;
  23 + spi0 = &qspi;
  24 + };
  25 +
  26 + chosen {
  27 + bootargs = "earlycon";
  28 + stdout-path = "serial0:115200n8";
  29 + };
  30 +
  31 + memory@0 {
  32 + device_type = "memory";
  33 + reg = <0x0 0x0 0x0 0x80000000>;
  34 + };
  35 +};
  36 +
  37 +&dcc {
  38 + status = "okay";
  39 +};
  40 +
  41 +&qspi {
  42 + status = "okay";
  43 + flash@0 {
  44 + compatible = "m25p80"; /* 32MB */
  45 + #address-cells = <1>;
  46 + #size-cells = <1>;
  47 + reg = <0x0>;
  48 + spi-tx-bus-width = <1>;
  49 + spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
  50 + spi-max-frequency = <108000000>; /* Based on DC1 spec */
  51 + partition@qspi-fsbl-uboot { /* for testing purpose */
  52 + label = "qspi-fsbl-uboot";
  53 + reg = <0x0 0x100000>;
  54 + };
  55 + partition@qspi-linux { /* for testing purpose */
  56 + label = "qspi-linux";
  57 + reg = <0x100000 0x500000>;
  58 + };
  59 + partition@qspi-device-tree { /* for testing purpose */
  60 + label = "qspi-device-tree";
  61 + reg = <0x600000 0x20000>;
  62 + };
  63 + partition@qspi-rootfs { /* for testing purpose */
  64 + label = "qspi-rootfs";
  65 + reg = <0x620000 0x5E0000>;
  66 + };
  67 + };
  68 +};
  69 +
  70 +&uart0 {
  71 + status = "okay";
  72 +};
arch/arm/dts/zynqmp-zc1275-revA.dts
Diff comments   View file @ 85231c0
  1 +// SPDX-License-Identifier: GPL-2.0+
  2 +/*
  3 + * dts file for Xilinx ZynqMP ZC1275
  4 + *
  5 + * (C) Copyright 2017 - 2018, Xilinx, Inc.
  6 + *
  7 + * Michal Simek <michal.simek@xilinx.com>
  8 + * Siva Durga Prasad Paladugu <sivadur@xilinx.com>
  9 + */
  10 +
  11 +/dts-v1/;
  12 +
  13 +#include "zynqmp.dtsi"
  14 +#include "zynqmp-clk-ccf.dtsi"
  15 +
  16 +/ {
  17 + model = "ZynqMP ZC1275 RevA";
  18 + compatible = "xlnx,zynqmp-zc1275-revA", "xlnx,zynqmp-zc1275", "xlnx,zynqmp";
  19 +
  20 + aliases {
  21 + serial0 = &uart0;
  22 + serial1 = &dcc;
  23 + spi0 = &qspi;
  24 + };
  25 +
  26 + chosen {
  27 + bootargs = "earlycon";
  28 + stdout-path = "serial0:115200n8";
  29 + };
  30 +
  31 + memory@0 {
  32 + device_type = "memory";
  33 + reg = <0x0 0x0 0x0 0x80000000>;
  34 + };
  35 +};
  36 +
  37 +&dcc {
  38 + status = "okay";
  39 +};
  40 +
  41 +&qspi {
  42 + status = "okay";
  43 + flash@0 {
  44 + compatible = "m25p80"; /* 32MB */
  45 + #address-cells = <1>;
  46 + #size-cells = <1>;
  47 + reg = <0x0>;
  48 + spi-tx-bus-width = <1>;
  49 + spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
  50 + spi-max-frequency = <108000000>; /* Based on DC1 spec */
  51 + partition@qspi-fsbl-uboot { /* for testing purpose */
  52 + label = "qspi-fsbl-uboot";
  53 + reg = <0x0 0x100000>;
  54 + };
  55 + partition@qspi-linux { /* for testing purpose */
  56 + label = "qspi-linux";
  57 + reg = <0x100000 0x500000>;
  58 + };
  59 + partition@qspi-device-tree { /* for testing purpose */
  60 + label = "qspi-device-tree";
  61 + reg = <0x600000 0x20000>;
  62 + };
  63 + partition@qspi-rootfs { /* for testing purpose */
  64 + label = "qspi-rootfs";
  65 + reg = <0x620000 0x5E0000>;
  66 + };
  67 + };
  68 +};
  69 +
  70 +&uart0 {
  71 + status = "okay";
  72 +};
board/xilinx/zynqmp/zynqmp-zc1232-revA/psu_init_gpl.c
Diff comments   View file @ 85231c0
  1 +/*
  2 + * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <asm/arch/psu_init_gpl.h>
  8 +#include <xil_io.h>
  9 +
  10 +static unsigned long psu_pll_init_data(void)
  11 +{
  12 + psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U);
  13 + psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U);
  14 + psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
  15 + psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
  16 + psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
  17 + mask_poll(0xFF5E0040, 0x00000002U);
  18 + psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
  19 + psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U);
  20 + psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x8000C76CU);
  21 + psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU);
  22 + psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00002D00U);
  23 + psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
  24 + psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
  25 + psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
  26 + mask_poll(0xFF5E0040, 0x00000001U);
  27 + psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
  28 + psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
  29 + psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U);
  30 + psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
  31 + psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U);
  32 + psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
  33 + psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
  34 + psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
  35 + mask_poll(0xFD1A0044, 0x00000001U);
  36 + psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
  37 + psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
  38 + psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U);
  39 + psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
  40 + psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U);
  41 + psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
  42 + psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
  43 + psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
  44 + mask_poll(0xFD1A0044, 0x00000002U);
  45 + psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
  46 + psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U);
  47 + psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U);
  48 + psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C62U);
  49 + psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014700U);
  50 + psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
  51 + psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
  52 + psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
  53 + mask_poll(0xFD1A0044, 0x00000004U);
  54 + psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
  55 + psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U);
  56 + psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x8000497FU);
  57 +
  58 + return 1;
  59 +}
  60 +
  61 +static unsigned long psu_clock_init_data(void)
  62 +{
  63 + psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010C00U);
  64 + psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
  65 + psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
  66 + psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U);
  67 + psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U);
  68 + psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
  69 + psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
  70 + psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
  71 + psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
  72 + psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U);
  73 + psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01040F00U);
  74 + psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010500U);
  75 + psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010400U);
  76 + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U);
  77 + psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
  78 + psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U);
  79 + psu_mask_write(0xFD1A00A0, 0x01003F07U, 0x01000200U);
  80 + psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
  81 + psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
  82 + psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U);
  83 + psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U);
  84 + psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U);
  85 + psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U);
  86 + psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U);
  87 + psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
  88 + psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
  89 + psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
  90 + psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
  91 + psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
  92 + psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
  93 +
  94 + return 1;
  95 +}
  96 +
  97 +static unsigned long psu_ddr_init_data(void)
  98 +{
  99 + psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
  100 + psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x81040001U);
  101 + psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
  102 + psu_mask_write(0xFD070020, 0x000003F3U, 0x00000200U);
  103 + psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
  104 + psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
  105 + psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U);
  106 + psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
  107 + psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
  108 + psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
  109 + psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x0081808BU);
  110 + psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
  111 + psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
  112 + psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
  113 + psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0030051FU);
  114 + psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020106U);
  115 + psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x006A0000U);
  116 + psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U);
  117 + psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x01240004U);
  118 + psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00280000U);
  119 + psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00110004U);
  120 + psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x00000000U);
  121 + psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x00000000U);
  122 + psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
  123 + psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
  124 + psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x0F0E2412U);
  125 + psu_mask_write(0xFD070104, 0x001F1F7FU, 0x000D0419U);
  126 + psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x0507070BU);
  127 + psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x00502008U);
  128 + psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x07020408U);
  129 + psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x06060403U);
  130 + psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010004U);
  131 + psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000606U);
  132 + psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x03030909U);
  133 + psu_mask_write(0xFD070124, 0x40070F3FU, 0x0004040DU);
  134 + psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x440C011CU);
  135 + psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
  136 + psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x80AB002BU);
  137 + psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x020196E5U);
  138 + psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x048A8207U);
  139 + psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00020304U);
  140 + psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
  141 + psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
  142 + psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
  143 + psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x004100E1U);
  144 + psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
  145 + psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00000802U);
  146 + psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000000U);
  147 + psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
  148 + psu_mask_write(0xFD070204, 0x001F1F1FU, 0x00080808U);
  149 + psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U);
  150 + psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x00000000U);
  151 + psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
  152 + psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x070F0707U);
  153 + psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x0F070707U);
  154 + psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
  155 + psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000000U);
  156 + psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x07070707U);
  157 + psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x07070707U);
  158 + psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000007U);
  159 + psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000610U);
  160 + psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
  161 + psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
  162 + psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
  163 + psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
  164 + psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
  165 + psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
  166 + psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
  167 + psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
  168 + psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
  169 + psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
  170 + psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
  171 + psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
  172 + psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
  173 + psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
  174 + psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
  175 + psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
  176 + psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
  177 + psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
  178 + psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
  179 + psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
  180 + psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
  181 + psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
  182 + psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
  183 + psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
  184 + psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
  185 + psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
  186 + psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
  187 + psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
  188 + psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
  189 + psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
  190 + psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
  191 + psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
  192 + psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
  193 + psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
  194 + psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
  195 + psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
  196 + psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
  197 + psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
  198 + psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
  199 + psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
  200 + psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
  201 + psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
  202 + psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
  203 + psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
  204 + psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
  205 + psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
  206 + psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
  207 + psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
  208 + psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
  209 + psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
  210 + psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
  211 + psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
  212 + psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
  213 + psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
  214 + psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
  215 + psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
  216 + psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
  217 + psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F10010U);
  218 + psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
  219 + psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
  220 + psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x0AC85590U);
  221 + psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0x41540B00U);
  222 + psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U);
  223 + psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U);
  224 + psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040BU);
  225 + psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x08240E08U);
  226 + psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x281C0404U);
  227 + psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x00070200U);
  228 + psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x82000800U);
  229 + psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x01162B1AU);
  230 + psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00320E08U);
  231 + psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000A0EU);
  232 + psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
  233 + psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
  234 + psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
  235 + psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000000U);
  236 + psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000124U);
  237 + psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000004U);
  238 + psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000028U);
  239 + psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000000U);
  240 + psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
  241 + psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x00000000U);
  242 + psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000000U);
  243 + psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
  244 + psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
  245 + psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
  246 + psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
  247 + psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
  248 + psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800081C7U);
  249 + psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
  250 + psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
  251 + psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
  252 + psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12340800U);
  253 + psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
  254 + psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
  255 + psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
  256 + psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
  257 + psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
  258 + psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0B0U);
  259 + psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF1032019U);
  260 + psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
  261 + psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
  262 + psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
  263 + psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
  264 + psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
  265 + psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
  266 + psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
  267 + psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AA858U);
  268 + psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000077BBU);
  269 + psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
  270 + psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
  271 + psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x000076BBU);
  272 + psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
  273 + psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B00CU);
  274 + psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09093030U);
  275 + psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
  276 + psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
  277 + psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B00CU);
  278 + psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09093030U);
  279 + psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
  280 + psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
  281 + psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
  282 + psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B00CU);
  283 + psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09093030U);
  284 + psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
  285 + psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
  286 + psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
  287 + psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B00CU);
  288 + psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09093030U);
  289 + psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
  290 + psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
  291 + psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
  292 + psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B00CU);
  293 + psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09093030U);
  294 + psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
  295 + psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
  296 + psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
  297 + psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B00CU);
  298 + psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09093030U);
  299 + psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
  300 + psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
  301 + psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
  302 + psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B00CU);
  303 + psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09093030U);
  304 + psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
  305 + psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
  306 + psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
  307 + psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B00CU);
  308 + psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09093030U);
  309 + psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
  310 + psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x40800624U);
  311 + psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x00007F00U);
  312 + psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0E00B00CU);
  313 + psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09093030U);
  314 + psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
  315 + psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
  316 + psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U);
  317 + psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
  318 + psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
  319 + psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70000000U);
  320 + psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
  321 + psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U);
  322 + psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
  323 + psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
  324 + psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70000000U);
  325 + psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
  326 + psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x01100000U);
  327 + psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
  328 + psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
  329 + psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70000000U);
  330 + psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
  331 + psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x01100000U);
  332 + psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
  333 + psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
  334 + psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70000000U);
  335 + psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x2A019FFEU);
  336 + psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x01100000U);
  337 + psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01264300U);
  338 + psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
  339 + psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70000000U);
  340 + psu_mask_write(0xFD0817C4, 0xFFFFFFFFU, 0x01100000U);
  341 + psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
  342 + psu_mask_write(0xFD080004, 0xFFFFFFFFU, 0x00040073U);
  343 +
  344 + return 1;
  345 +}
  346 +
  347 +static unsigned long psu_mio_init_data(void)
  348 +{
  349 + psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U);
  350 + psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U);
  351 + psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U);
  352 + psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U);
  353 + psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U);
  354 + psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U);
  355 + psu_mask_write(0xFF180088, 0x000000FEU, 0x000000C0U);
  356 + psu_mask_write(0xFF18008C, 0x000000FEU, 0x000000C0U);
  357 + psu_mask_write(0xFF180204, 0x0000003FU, 0x00000000U);
  358 + psu_mask_write(0xFF180208, 0x0000000CU, 0x00000004U);
  359 + psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
  360 + psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
  361 + psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
  362 + psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
  363 + psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
  364 + psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
  365 + psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
  366 + psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
  367 + psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
  368 + psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
  369 + psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
  370 + psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
  371 + psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
  372 + psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
  373 + psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
  374 + psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
  375 + psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
  376 + psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
  377 + psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
  378 +
  379 + return 1;
  380 +}
  381 +
  382 +static unsigned long psu_peripherals_init_data(void)
  383 +{
  384 + psu_mask_write(0xFD1A0100, 0x0000807EU, 0x00000000U);
  385 + psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
  386 + psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
  387 + psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U);
  388 + psu_mask_write(0xFF180390, 0x00000004U, 0x00000004U);
  389 + psu_mask_write(0xFF5E0238, 0x00008000U, 0x00000000U);
  390 + psu_mask_write(0xFF5E0238, 0x00007800U, 0x00000000U);
  391 + psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U);
  392 + psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
  393 + psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
  394 + psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
  395 + psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
  396 + psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
  397 + psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
  398 + psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
  399 + psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
  400 + psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
  401 + psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD17U);
  402 + psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
  403 +
  404 + return 1;
  405 +}
  406 +
  407 +static unsigned long psu_serdes_init_data(void)
  408 +{
  409 + psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000FU);
  410 + psu_mask_write(0xFD410004, 0x0000001FU, 0x0000000FU);
  411 + psu_mask_write(0xFD402860, 0x00000080U, 0x00000080U);
  412 + psu_mask_write(0xFD402864, 0x00000081U, 0x00000001U);
  413 + psu_mask_write(0xFD402368, 0x000000FFU, 0x000000E0U);
  414 + psu_mask_write(0xFD40236C, 0x00000007U, 0x00000003U);
  415 + psu_mask_write(0xFD406368, 0x000000FFU, 0x000000E0U);
  416 + psu_mask_write(0xFD40636C, 0x00000007U, 0x00000003U);
  417 + psu_mask_write(0xFD402370, 0x000000FFU, 0x000000C9U);
  418 + psu_mask_write(0xFD402374, 0x000000FFU, 0x000000D2U);
  419 + psu_mask_write(0xFD402378, 0x000000FFU, 0x00000001U);
  420 + psu_mask_write(0xFD40237C, 0x000000B3U, 0x000000B0U);
  421 + psu_mask_write(0xFD406370, 0x000000FFU, 0x000000C9U);
  422 + psu_mask_write(0xFD406374, 0x000000FFU, 0x000000D2U);
  423 + psu_mask_write(0xFD406378, 0x000000FFU, 0x00000001U);
  424 + psu_mask_write(0xFD40637C, 0x000000B3U, 0x000000B0U);
  425 + psu_mask_write(0xFD402360, 0x00000040U, 0x00000040U);
  426 + psu_mask_write(0xFD40106C, 0x0000000FU, 0x0000000FU);
  427 + psu_mask_write(0xFD4000F4, 0x0000000BU, 0x0000000BU);
  428 + psu_mask_write(0xFD406360, 0x00000040U, 0x00000040U);
  429 + psu_mask_write(0xFD40506C, 0x0000000FU, 0x0000000FU);
  430 + psu_mask_write(0xFD4040F4, 0x0000000BU, 0x0000000BU);
  431 + psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U);
  432 + psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U);
  433 + psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U);
  434 + psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U);
  435 + psu_mask_write(0xFD40189C, 0x00000080U, 0x00000080U);
  436 + psu_mask_write(0xFD4018F8, 0x000000FFU, 0x0000007DU);
  437 + psu_mask_write(0xFD4018FC, 0x000000FFU, 0x0000007DU);
  438 + psu_mask_write(0xFD401990, 0x000000FFU, 0x00000001U);
  439 + psu_mask_write(0xFD401924, 0x000000FFU, 0x0000009CU);
  440 + psu_mask_write(0xFD401928, 0x000000FFU, 0x00000039U);
  441 + psu_mask_write(0xFD40198C, 0x000000F0U, 0x00000020U);
  442 + psu_mask_write(0xFD401900, 0x000000FFU, 0x0000007DU);
  443 + psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000064U);
  444 + psu_mask_write(0xFD401980, 0x000000FFU, 0x000000FFU);
  445 + psu_mask_write(0xFD401914, 0x000000FFU, 0x000000F7U);
  446 + psu_mask_write(0xFD401918, 0x00000001U, 0x00000001U);
  447 + psu_mask_write(0xFD401940, 0x000000FFU, 0x000000F7U);
  448 + psu_mask_write(0xFD401944, 0x00000001U, 0x00000001U);
  449 + psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U);
  450 + psu_mask_write(0xFD40589C, 0x00000080U, 0x00000080U);
  451 + psu_mask_write(0xFD4058F8, 0x000000FFU, 0x0000007DU);
  452 + psu_mask_write(0xFD4058FC, 0x000000FFU, 0x0000007DU);
  453 + psu_mask_write(0xFD405990, 0x000000FFU, 0x00000001U);
  454 + psu_mask_write(0xFD405924, 0x000000FFU, 0x0000009CU);
  455 + psu_mask_write(0xFD405928, 0x000000FFU, 0x00000039U);
  456 + psu_mask_write(0xFD40598C, 0x000000F0U, 0x00000020U);
  457 + psu_mask_write(0xFD405900, 0x000000FFU, 0x0000007DU);
  458 + psu_mask_write(0xFD40592C, 0x000000FFU, 0x00000064U);
  459 + psu_mask_write(0xFD405980, 0x000000FFU, 0x000000FFU);
  460 + psu_mask_write(0xFD405914, 0x000000FFU, 0x000000F7U);
  461 + psu_mask_write(0xFD405918, 0x00000001U, 0x00000001U);
  462 + psu_mask_write(0xFD405940, 0x000000FFU, 0x000000F7U);
  463 + psu_mask_write(0xFD405944, 0x00000001U, 0x00000001U);
  464 + psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U);
  465 + psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U);
  466 + psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U);
  467 + psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U);
  468 + psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U);
  469 + psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U);
  470 + psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U);
  471 + psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU);
  472 + psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U);
  473 + psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U);
  474 + psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU);
  475 + psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U);
  476 + psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U);
  477 + psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU);
  478 + psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U);
  479 + psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U);
  480 + psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU);
  481 + psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U);
  482 + psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U);
  483 + psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U);
  484 + psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U);
  485 + psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U);
  486 + psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U);
  487 + psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U);
  488 + psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U);
  489 + psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U);
  490 + psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U);
  491 + psu_mask_write(0xFD410010, 0x00000077U, 0x00000022U);
  492 + psu_mask_write(0xFD4001D8, 0x00000001U, 0x00000001U);
  493 + psu_mask_write(0xFD4041D8, 0x00000001U, 0x00000001U);
  494 + psu_mask_write(0xFD401C14, 0x000000FFU, 0x000000E6U);
  495 + psu_mask_write(0xFD401C40, 0x0000001FU, 0x0000000CU);
  496 + psu_mask_write(0xFD40194C, 0x00000020U, 0x00000020U);
  497 + psu_mask_write(0xFD401950, 0x00000007U, 0x00000006U);
  498 + psu_mask_write(0xFD405C14, 0x000000FFU, 0x000000E6U);
  499 + psu_mask_write(0xFD405C40, 0x0000001FU, 0x0000000CU);
  500 + psu_mask_write(0xFD40594C, 0x00000020U, 0x00000020U);
  501 + psu_mask_write(0xFD405950, 0x00000007U, 0x00000006U);
  502 + psu_mask_write(0xFD404048, 0x000000FFU, 0x00000001U);
  503 + psu_mask_write(0xFD400048, 0x000000FFU, 0x00000001U);
  504 +
  505 + return 1;
  506 +}
  507 +
  508 +static unsigned long psu_resetout_init_data(void)
  509 +{
  510 + psu_mask_write(0xFD3D0100, 0x00000003U, 0x00000001U);
  511 + psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000000U);
  512 + psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U);
  513 + mask_poll(0xFD4023E4, 0x00000010U);
  514 + mask_poll(0xFD4063E4, 0x00000010U);
  515 + psu_mask_write(0xFD0C00AC, 0xFFFFFFFFU, 0x28184018U);
  516 + psu_mask_write(0xFD0C00B0, 0xFFFFFFFFU, 0x0E081406U);
  517 + psu_mask_write(0xFD0C00B4, 0xFFFFFFFFU, 0x064A0813U);
  518 + psu_mask_write(0xFD0C00B8, 0xFFFFFFFFU, 0x3FFC96A4U);
  519 +
  520 + return 1;
  521 +}
  522 +
  523 +static unsigned long psu_resetin_init_data(void)
  524 +{
  525 + psu_mask_write(0xFD1A0100, 0x00000002U, 0x00000002U);
  526 +
  527 + return 1;
  528 +}
  529 +
  530 +static unsigned long psu_afi_config(void)
  531 +{
  532 + psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
  533 + psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
  534 + psu_mask_write(0xFD615000, 0x00000300U, 0x00000200U);
  535 + psu_mask_write(0xFD360000, 0x00000003U, 0x00000000U);
  536 + psu_mask_write(0xFD370000, 0x00000003U, 0x00000000U);
  537 + psu_mask_write(0xFD390000, 0x00000003U, 0x00000000U);
  538 + psu_mask_write(0xFD3A0000, 0x00000003U, 0x00000000U);
  539 + psu_mask_write(0xFF9B0000, 0x00000003U, 0x00000000U);
  540 + psu_mask_write(0xFD360014, 0x00000003U, 0x00000000U);
  541 + psu_mask_write(0xFD370014, 0x00000003U, 0x00000000U);
  542 + psu_mask_write(0xFD390014, 0x00000003U, 0x00000000U);
  543 + psu_mask_write(0xFD3A0014, 0x00000003U, 0x00000000U);
  544 + psu_mask_write(0xFF9B0014, 0x00000003U, 0x00000000U);
  545 +
  546 + return 1;
  547 +}
  548 +
  549 +static unsigned long psu_ddr_phybringup_data(void)
  550 +{
  551 + unsigned int regval = 0;
  552 +
  553 + while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
  554 + ;
  555 + prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
  556 +
  557 + while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
  558 + ;
  559 + Xil_Out32(0xFD0701B0U, 0x00000001U);
  560 + Xil_Out32(0xFD070320U, 0x00000001U);
  561 + while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
  562 + ;
  563 + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
  564 + Xil_Out32(0xFD080004, 0x0004FE01);
  565 + regval = Xil_In32(0xFD080030);
  566 + while (regval != 0x80000FFF)
  567 + regval = Xil_In32(0xFD080030);
  568 + Xil_Out32(0xFD070180U, 0x00AB002BU);
  569 + Xil_Out32(0xFD070060U, 0x00000000U);
  570 + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
  571 +
  572 + return 1;
  573 +}
  574 +
  575 +static int serdes_enb_coarse_saturation(void)
  576 +{
  577 + Xil_Out32(0xFD402094, 0x00000010);
  578 + Xil_Out32(0xFD406094, 0x00000010);
  579 + Xil_Out32(0xFD40A094, 0x00000010);
  580 + Xil_Out32(0xFD40E094, 0x00000010);
  581 + return 1;
  582 +}
  583 +
  584 +static int serdes_fixcal_code(void)
  585 +{
  586 + int maskstatus = 1;
  587 + unsigned int match_pmos_code[23];
  588 + unsigned int match_nmos_code[23];
  589 + unsigned int match_ical_code[7];
  590 + unsigned int match_rcal_code[7];
  591 + unsigned int p_code = 0;
  592 + unsigned int n_code = 0;
  593 + unsigned int i_code = 0;
  594 + unsigned int r_code = 0;
  595 + unsigned int repeat_count = 0;
  596 + unsigned int L3_TM_CALIB_DIG20 = 0;
  597 + unsigned int L3_TM_CALIB_DIG19 = 0;
  598 + unsigned int L3_TM_CALIB_DIG18 = 0;
  599 + unsigned int L3_TM_CALIB_DIG16 = 0;
  600 + unsigned int L3_TM_CALIB_DIG15 = 0;
  601 + unsigned int L3_TM_CALIB_DIG14 = 0;
  602 + int i = 0;
  603 +
  604 + for (i = 0; i < 23; i++) {
  605 + match_pmos_code[i] = 0;
  606 + match_nmos_code[i] = 0;
  607 + }
  608 + for (i = 0; i < 7; i++) {
  609 + match_ical_code[i] = 0;
  610 + match_rcal_code[i] = 0;
  611 + }
  612 +
  613 + do {
  614 + Xil_Out32(0xFD410010, 0x00000000);
  615 + Xil_Out32(0xFD410014, 0x00000000);
  616 +
  617 + Xil_Out32(0xFD410010, 0x00000001);
  618 + Xil_Out32(0xFD410014, 0x00000000);
  619 +
  620 + maskstatus = mask_poll(0xFD40EF14, 0x2);
  621 + if (maskstatus == 0) {
  622 + /* xil_printf("#SERDES initialization timed out\n\r");*/
  623 + return maskstatus;
  624 + }
  625 +
  626 + p_code = mask_read(0xFD40EF18, 0xFFFFFFFF);
  627 + n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF);
  628 +
  629 + i_code = mask_read(0xFD40EF24, 0xFFFFFFFF);
  630 + r_code = mask_read(0xFD40EF28, 0xFFFFFFFF);
  631 +
  632 + if ((p_code >= 0x26) && (p_code <= 0x3C))
  633 + match_pmos_code[p_code - 0x26] += 1;
  634 +
  635 + if ((n_code >= 0x26) && (n_code <= 0x3C))
  636 + match_nmos_code[n_code - 0x26] += 1;
  637 +
  638 + if ((i_code >= 0xC) && (i_code <= 0x12))
  639 + match_ical_code[i_code - 0xC] += 1;
  640 +
  641 + if ((r_code >= 0x6) && (r_code <= 0xC))
  642 + match_rcal_code[r_code - 0x6] += 1;
  643 +
  644 + } while (repeat_count++ < 10);
  645 +
  646 + for (i = 0; i < 23; i++) {
  647 + if (match_pmos_code[i] >= match_pmos_code[0]) {
  648 + match_pmos_code[0] = match_pmos_code[i];
  649 + p_code = 0x26 + i;
  650 + }
  651 + if (match_nmos_code[i] >= match_nmos_code[0]) {
  652 + match_nmos_code[0] = match_nmos_code[i];
  653 + n_code = 0x26 + i;
  654 + }
  655 + }
  656 +
  657 + for (i = 0; i < 7; i++) {
  658 + if (match_ical_code[i] >= match_ical_code[0]) {
  659 + match_ical_code[0] = match_ical_code[i];
  660 + i_code = 0xC + i;
  661 + }
  662 + if (match_rcal_code[i] >= match_rcal_code[0]) {
  663 + match_rcal_code[0] = match_rcal_code[i];
  664 + r_code = 0x6 + i;
  665 + }
  666 + }
  667 +
  668 + L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0);
  669 + L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7);
  670 +
  671 + L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18);
  672 + L3_TM_CALIB_DIG19 =
  673 + L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6) | 0x20 | 0x4 |
  674 + ((n_code >> 3) & 0x3);
  675 +
  676 + L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F);
  677 + L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10;
  678 +
  679 + L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8);
  680 + L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7);
  681 +
  682 + L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30);
  683 + L3_TM_CALIB_DIG15 =
  684 + L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7) | 0x40 | 0x8 |
  685 + ((i_code >> 1) & 0x7);
  686 +
  687 + L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F);
  688 + L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40;
  689 +
  690 + Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20);
  691 + Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19);
  692 + Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18);
  693 + Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16);
  694 + Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15);
  695 + Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14);
  696 + return maskstatus;
  697 +}
  698 +
  699 +static int init_serdes(void)
  700 +{
  701 + int status = 1;
  702 +
  703 + status &= psu_resetin_init_data();
  704 +
  705 + status &= serdes_fixcal_code();
  706 + status &= serdes_enb_coarse_saturation();
  707 +
  708 + status &= psu_serdes_init_data();
  709 + status &= psu_resetout_init_data();
  710 +
  711 + return status;
  712 +}
  713 +
  714 +static void init_peripheral(void)
  715 +{
  716 + unsigned int tmp_regval;
  717 +
  718 + tmp_regval = Xil_In32(0xFD690040);
  719 + tmp_regval &= ~0x00000001;
  720 + Xil_Out32(0xFD690040, tmp_regval);
  721 +
  722 + tmp_regval = Xil_In32(0xFD690030);
  723 + tmp_regval &= ~0x00000001;
  724 + Xil_Out32(0xFD690030, tmp_regval);
  725 +}
  726 +
  727 +int psu_init(void)
  728 +{
  729 + int status = 1;
  730 +
  731 + status &= psu_mio_init_data();
  732 + status &= psu_pll_init_data();
  733 + status &= psu_clock_init_data();
  734 + status &= psu_ddr_init_data();
  735 + status &= psu_ddr_phybringup_data();
  736 + status &= psu_peripherals_init_data();
  737 + status &= init_serdes();
  738 + init_peripheral();
  739 +
  740 + status &= psu_afi_config();
  741 +
  742 + if (status == 0)
  743 + return 1;
  744 + return 0;
  745 +}
board/xilinx/zynqmp/zynqmp-zc1254-revA/psu_init_gpl.c
Diff comments   View file @ 85231c0
  1 +/*
  2 + * (c) Copyright 2015 Xilinx, Inc. All rights reserved.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <asm/arch/psu_init_gpl.h>
  8 +#include <xil_io.h>
  9 +
  10 +static unsigned long psu_pll_init_data(void)
  11 +{
  12 + psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E60EC6CU);
  13 + psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00013000U);
  14 + psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U);
  15 + psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U);
  16 + psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U);
  17 + mask_poll(0xFF5E0040, 0x00000002U);
  18 + psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U);
  19 + psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000200U);
  20 + psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E4B0C82U);
  21 + psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00015A00U);
  22 + psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U);
  23 + psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U);
  24 + psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U);
  25 + mask_poll(0xFF5E0040, 0x00000001U);
  26 + psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U);
  27 + psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U);
  28 + psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U);
  29 + psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014200U);
  30 + psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U);
  31 + psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U);
  32 + psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U);
  33 + mask_poll(0xFD1A0044, 0x00000001U);
  34 + psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U);
  35 + psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U);
  36 + psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U);
  37 + psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014800U);
  38 + psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U);
  39 + psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U);
  40 + psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U);
  41 + mask_poll(0xFD1A0044, 0x00000002U);
  42 + psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U);
  43 + psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U);
  44 + psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C62U);
  45 + psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014000U);
  46 + psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U);
  47 + psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U);
  48 + psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U);
  49 + mask_poll(0xFD1A0044, 0x00000004U);
  50 + psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U);
  51 + psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000200U);
  52 +
  53 + return 1;
  54 +}
  55 +
  56 +static unsigned long psu_clock_init_data(void)
  57 +{
  58 + psu_mask_write(0xFF5E0068, 0x013F3F07U, 0x01010500U);
  59 + psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U);
  60 + psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U);
  61 + psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000300U);
  62 + psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000900U);
  63 + psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U);
  64 + psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U);
  65 + psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U);
  66 + psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U);
  67 + psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010802U);
  68 + psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U);
  69 + psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U);
  70 + psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000104U);
  71 + psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U);
  72 + psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U);
  73 + psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000600U);
  74 + psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000203U);
  75 + psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000203U);
  76 + psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000203U);
  77 + psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000202U);
  78 + psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U);
  79 + psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U);
  80 + psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U);
  81 + psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U);
  82 + psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U);
  83 + psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U);
  84 +
  85 + return 1;
  86 +}
  87 +
  88 +static unsigned long psu_ddr_init_data(void)
  89 +{
  90 + psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U);
  91 + psu_mask_write(0xFD070000, 0xE30FBE3DU, 0x81040001U);
  92 + psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U);
  93 + psu_mask_write(0xFD070020, 0x000003F3U, 0x00000100U);
  94 + psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00800000U);
  95 + psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U);
  96 + psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00403210U);
  97 + psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U);
  98 + psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U);
  99 + psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U);
  100 + psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x00308034U);
  101 + psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U);
  102 + psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U);
  103 + psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U);
  104 + psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0030051FU);
  105 + psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00020063U);
  106 + psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x00290000U);
  107 + psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00000E05U);
  108 + psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x05200004U);
  109 + psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00000000U);
  110 + psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00110004U);
  111 + psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x00000000U);
  112 + psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x00000000U);
  113 + psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U);
  114 + psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000066FU);
  115 + psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x07080D07U);
  116 + psu_mask_write(0xFD070104, 0x001F1F7FU, 0x0005020BU);
  117 + psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x03030607U);
  118 + psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x00502006U);
  119 + psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x13020204U);
  120 + psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x03030202U);
  121 + psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010003U);
  122 + psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000303U);
  123 + psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x02020909U);
  124 + psu_mask_write(0xFD070124, 0x40070F3FU, 0x0004040DU);
  125 + psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x440C011CU);
  126 + psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U);
  127 + psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x80800020U);
  128 + psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x02009896U);
  129 + psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x04828202U);
  130 + psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00020304U);
  131 + psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U);
  132 + psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U);
  133 + psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x00400003U);
  134 + psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x003800D4U);
  135 + psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000000U);
  136 + psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x0000003DU);
  137 + psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000000U);
  138 + psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU);
  139 + psu_mask_write(0xFD070204, 0x001F1F1FU, 0x00080808U);
  140 + psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U);
  141 + psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x00000000U);
  142 + psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU);
  143 + psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x070F0707U);
  144 + psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x0F070707U);
  145 + psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU);
  146 + psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000000U);
  147 + psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x07070707U);
  148 + psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x07070707U);
  149 + psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000007U);
  150 + psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x06000604U);
  151 + psu_mask_write(0xFD070244, 0x00003333U, 0x00000001U);
  152 + psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U);
  153 + psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U);
  154 + psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U);
  155 + psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U);
  156 + psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U);
  157 + psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U);
  158 + psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U);
  159 + psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U);
  160 + psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U);
  161 + psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U);
  162 + psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U);
  163 + psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U);
  164 + psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U);
  165 + psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU);
  166 + psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU);
  167 + psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U);
  168 + psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU);
  169 + psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U);
  170 + psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU);
  171 + psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU);
  172 + psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U);
  173 + psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U);
  174 + psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U);
  175 + psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU);
  176 + psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU);
  177 + psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U);
  178 + psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U);
  179 + psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U);
  180 + psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU);
  181 + psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU);
  182 + psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U);
  183 + psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U);
  184 + psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU);
  185 + psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U);
  186 + psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU);
  187 + psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU);
  188 + psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU);
  189 + psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U);
  190 + psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U);
  191 + psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU);
  192 + psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U);
  193 + psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU);
  194 + psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU);
  195 + psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU);
  196 + psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U);
  197 + psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U);
  198 + psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU);
  199 + psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U);
  200 + psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU);
  201 + psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U);
  202 + psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U);
  203 + psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U);
  204 + psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU);
  205 + psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U);
  206 + psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U);
  207 + psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x07001E00U);
  208 + psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F05D90U);
  209 + psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U);
  210 + psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U);
  211 + psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x64032010U);
  212 + psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0x38801C20U);
  213 + psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x06124000U);
  214 + psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04061U);
  215 + psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x000000D3U);
  216 + psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0800040BU);
  217 + psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x040E0604U);
  218 + psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x28100004U);
  219 + psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x00040200U);
  220 + psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x82000800U);
  221 + psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x00682B0AU);
  222 + psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x00152504U);
  223 + psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000506U);
  224 + psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U);
  225 + psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U);
  226 + psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U);
  227 + psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000000U);
  228 + psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000520U);
  229 + psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000004U);
  230 + psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000000U);
  231 + psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000000U);
  232 + psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000000U);
  233 + psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x00000000U);
  234 + psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000000U);
  235 + psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000000U);
  236 + psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x0000004DU);
  237 + psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U);
  238 + psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x0000004DU);
  239 + psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000000U);
  240 + psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800081C7U);
  241 + psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U);
  242 + psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U);
  243 + psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U);
  244 + psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12340800U);
  245 + psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x00000005U);
  246 + psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U);
  247 + psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x0A000000U);
  248 + psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000009U);
  249 + psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x0A000000U);
  250 + psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300B0B0U);
  251 + psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF1032019U);
  252 + psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U);
  253 + psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U);
  254 + psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U);
  255 + psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U);
  256 + psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U);
  257 + psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U);
  258 + psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U);
  259 + psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x0088E858U);
  260 + psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x000077BBU);
  261 + psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U);
  262 + psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U);
  263 + psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x000076BBU);
  264 + psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U);
  265 + psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00B00CU);
  266 + psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09093030U);
  267 + psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU);
  268 + psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U);
  269 + psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00B00CU);
  270 + psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09093030U);
  271 + psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU);
  272 + psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U);
  273 + psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU);
  274 + psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00B00CU);
  275 + psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09093030U);
  276 + psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU);
  277 + psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U);
  278 + psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU);
  279 + psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00B00CU);
  280 + psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09093030U);
  281 + psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU);
  282 + psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x40800604U);
  283 + psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x00007FFFU);
  284 + psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0E00B00CU);
  285 + psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09093030U);
  286 + psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU);
  287 + psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x40800604U);
  288 + psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x00007FFFU);
  289 + psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0E00B00CU);
  290 + psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09093030U);
  291 + psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU);
  292 + psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x40800604U);
  293 + psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x00007FFFU);
  294 + psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0E00B00CU);
  295 + psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09093030U);
  296 + psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU);
  297 + psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x40800604U);
  298 + psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x00007FFFU);
  299 + psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0E00B00CU);
  300 + psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09093030U);
  301 + psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU);
  302 + psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x40800624U);
  303 + psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x00007F00U);
  304 + psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0E00B00CU);
  305 + psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09093030U);
  306 + psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU);
  307 + psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU);
  308 + psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x06124000U);
  309 + psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U);
  310 + psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x00041800U);
  311 + psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x70000000U);
  312 + psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU);
  313 + psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x06124000U);
  314 + psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U);
  315 + psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x00041800U);
  316 + psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x70000000U);
  317 + psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x2A019FFEU);
  318 + psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x06124000U);
  319 + psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01264300U);
  320 + psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x00041800U);
  321 + psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70000000U);
  322 + psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x2A019FFEU);
  323 + psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x06124000U);
  324 + psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01264300U);
  325 + psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x00041800U);
  326 + psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70000000U);
  327 + psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x2A019FFEU);
  328 + psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x06124000U);
  329 + psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01264300U);
  330 + psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x00041800U);
  331 + psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70000000U);
  332 + psu_mask_write(0xFD0817C4, 0xFFFFFFFFU, 0x06124000U);
  333 + psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U);
  334 +
  335 + return 1;
  336 +}
  337 +
  338 +static unsigned long psu_mio_init_data(void)
  339 +{
  340 + psu_mask_write(0xFF180000, 0x000000FEU, 0x00000002U);
  341 + psu_mask_write(0xFF180004, 0x000000FEU, 0x00000002U);
  342 + psu_mask_write(0xFF180008, 0x000000FEU, 0x00000002U);
  343 + psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000002U);
  344 + psu_mask_write(0xFF180010, 0x000000FEU, 0x00000002U);
  345 + psu_mask_write(0xFF180014, 0x000000FEU, 0x00000002U);
  346 + psu_mask_write(0xFF180018, 0x000000FEU, 0x00000002U);
  347 + psu_mask_write(0xFF180088, 0x000000FEU, 0x000000C0U);
  348 + psu_mask_write(0xFF18008C, 0x000000FEU, 0x000000C0U);
  349 + psu_mask_write(0xFF180204, 0x0000007FU, 0x00000000U);
  350 + psu_mask_write(0xFF180208, 0x0000000CU, 0x00000004U);
  351 + psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU);
  352 + psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU);
  353 + psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U);
  354 + psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU);
  355 + psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU);
  356 + psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U);
  357 + psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU);
  358 + psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU);
  359 + psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U);
  360 + psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU);
  361 + psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU);
  362 + psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U);
  363 + psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU);
  364 + psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU);
  365 + psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U);
  366 + psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU);
  367 + psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU);
  368 + psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U);
  369 + psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U);
  370 +
  371 + return 1;
  372 +}
  373 +
  374 +static unsigned long psu_peripherals_init_data(void)
  375 +{
  376 + psu_mask_write(0xFD1A0100, 0x0000007CU, 0x00000000U);
  377 + psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U);
  378 + psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U);
  379 + psu_mask_write(0xFF5E0238, 0x00000001U, 0x00000000U);
  380 + psu_mask_write(0xFF180390, 0x00000004U, 0x00000000U);
  381 + psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U);
  382 + psu_mask_write(0xFF000034, 0x000000FFU, 0x00000005U);
  383 + psu_mask_write(0xFF000018, 0x0000FFFFU, 0x0000008FU);
  384 + psu_mask_write(0xFF000000, 0x000001FFU, 0x00000017U);
  385 + psu_mask_write(0xFF000004, 0x000003FFU, 0x00000020U);
  386 + psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U);
  387 + psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU);
  388 + psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U);
  389 + psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U);
  390 + psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U);
  391 + psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x01FC9F08U);
  392 + psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U);
  393 +
  394 + return 1;
  395 +}
  396 +
  397 +static unsigned long psu_afi_config(void)
  398 +{
  399 + psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U);
  400 + psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U);
  401 + psu_mask_write(0xFD615000, 0x00000300U, 0x00000000U);
  402 +
  403 + return 1;
  404 +}
  405 +
  406 +static unsigned long psu_ddr_phybringup_data(void)
  407 +{
  408 + unsigned int regval = 0;
  409 + unsigned int pll_retry = 10;
  410 + unsigned int pll_locked = 0;
  411 +
  412 + while ((pll_retry > 0) && (!pll_locked)) {
  413 + Xil_Out32(0xFD080004, 0x00040010);
  414 + Xil_Out32(0xFD080004, 0x00040011);
  415 +
  416 + while ((Xil_In32(0xFD080030) & 0x1) != 1)
  417 + ;
  418 +
  419 + pll_locked = (Xil_In32(0xFD080030) & 0x80000000) >> 31;
  420 + pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) >> 16;
  421 + pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16;
  422 + pll_locked &= (Xil_In32(0xFD080BE0) & 0x10000) >> 16;
  423 + pll_locked &= (Xil_In32(0xFD080DE0) & 0x10000) >> 16;
  424 + pll_retry--;
  425 + }
  426 + Xil_Out32(0xFD0800C0, Xil_In32(0xFD0800C0) | (pll_retry << 16));
  427 + Xil_Out32(0xFD080004U, 0x00040063U);
  428 +
  429 + while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU)
  430 + ;
  431 + prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U);
  432 +
  433 + while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU)
  434 + ;
  435 + Xil_Out32(0xFD0701B0U, 0x00000001U);
  436 + Xil_Out32(0xFD070320U, 0x00000001U);
  437 + while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U)
  438 + ;
  439 + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U);
  440 + Xil_Out32(0xFD080004, 0x0004FE01);
  441 + regval = Xil_In32(0xFD080030);
  442 + while (regval != 0x80000FFF)
  443 + regval = Xil_In32(0xFD080030);
  444 + Xil_Out32(0xFD070180U, 0x00800020U);
  445 + Xil_Out32(0xFD070060U, 0x00000000U);
  446 + prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U);
  447 +
  448 + return 1;
  449 +}
  450 +
  451 +int psu_init(void)
  452 +{
  453 + int status = 1;
  454 +
  455 + status &= psu_mio_init_data();
  456 + status &= psu_pll_init_data();
  457 + status &= psu_clock_init_data();
  458 + status &= psu_ddr_init_data();
  459 + status &= psu_ddr_phybringup_data();
  460 + status &= psu_peripherals_init_data();
  461 +
  462 + status &= psu_afi_config();
  463 +
  464 + if (status == 0)
  465 + return 1;
  466 + return 0;
  467 +}
board/xilinx/zynqmp/zynqmp-zc1275-revA
Diff comments   View file @ 85231c0
  1 +zynqmp-zc1254-revA
configs/xilinx_zynqmp_zc1232_revA_defconfig
Diff comments   View file @ 85231c0
  1 +CONFIG_ARM=y
  2 +CONFIG_ARCH_ZYNQMP=y
  3 +CONFIG_SYS_TEXT_BASE=0x8000000
  4 +CONFIG_SYS_MALLOC_F_LEN=0x8000
  5 +# CONFIG_SPL_LIBDISK_SUPPORT is not set
  6 +CONFIG_SPL=y
  7 +CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1232 revA"
  8 +# CONFIG_SPL_FAT_SUPPORT is not set
  9 +CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1232-revA"
  10 +CONFIG_DEBUG_UART=y
  11 +CONFIG_DISTRO_DEFAULTS=y
  12 +CONFIG_FIT=y
  13 +CONFIG_FIT_VERBOSE=y
  14 +CONFIG_SPL_LOAD_FIT=y
  15 +# CONFIG_DISPLAY_CPUINFO is not set
  16 +# CONFIG_DISPLAY_BOARDINFO is not set
  17 +CONFIG_SPL_OS_BOOT=y
  18 +CONFIG_SPL_RAM_SUPPORT=y
  19 +CONFIG_SPL_RAM_DEVICE=y
  20 +CONFIG_SPL_ATF=y
  21 +CONFIG_SYS_PROMPT="ZynqMP> "
  22 +CONFIG_CMD_MEMTEST=y
  23 +CONFIG_CMD_CLK=y
  24 +# CONFIG_CMD_FLASH is not set
  25 +CONFIG_CMD_FPGA_LOADBP=y
  26 +CONFIG_CMD_FPGA_LOADP=y
  27 +# CONFIG_CMD_NET is not set
  28 +# CONFIG_CMD_NFS is not set
  29 +CONFIG_CMD_TIME=y
  30 +CONFIG_CMD_TIMER=y
  31 +CONFIG_SPL_OF_CONTROL=y
  32 +CONFIG_OF_EMBED=y
  33 +CONFIG_SPL_DM=y
  34 +# CONFIG_BLK is not set
  35 +CONFIG_CLK_ZYNQMP=y
  36 +CONFIG_FPGA_XILINX=y
  37 +CONFIG_FPGA_ZYNQMPPL=y
  38 +CONFIG_MISC=y
  39 +CONFIG_DM_MMC=y
  40 +CONFIG_SPI_FLASH=y
  41 +CONFIG_SPI_FLASH_BAR=y
  42 +CONFIG_SF_DUAL_FLASH=y
  43 +CONFIG_SPI_FLASH_MACRONIX=y
  44 +CONFIG_SPI_FLASH_SPANSION=y
  45 +CONFIG_SPI_FLASH_STMICRO=y
  46 +CONFIG_SPI_FLASH_WINBOND=y
  47 +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
  48 +CONFIG_DEBUG_UART_ZYNQ=y
  49 +CONFIG_DEBUG_UART_BASE=0xff000000
  50 +CONFIG_DEBUG_UART_CLOCK=100000000
  51 +CONFIG_DEBUG_UART_ANNOUNCE=y
  52 +CONFIG_ZYNQ_SERIAL=y
  53 +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
configs/xilinx_zynqmp_zc1254_revA_defconfig
Diff comments   View file @ 85231c0
  1 +CONFIG_ARM=y
  2 +CONFIG_ARCH_ZYNQMP=y
  3 +CONFIG_SYS_TEXT_BASE=0x8000000
  4 +CONFIG_SYS_MALLOC_F_LEN=0x8000
  5 +# CONFIG_SPL_LIBDISK_SUPPORT is not set
  6 +CONFIG_SPL=y
  7 +CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1254 revA"
  8 +# CONFIG_SPL_FAT_SUPPORT is not set
  9 +CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1254-revA"
  10 +CONFIG_DEBUG_UART=y
  11 +CONFIG_DISTRO_DEFAULTS=y
  12 +CONFIG_FIT=y
  13 +CONFIG_FIT_VERBOSE=y
  14 +CONFIG_SPL_LOAD_FIT=y
  15 +# CONFIG_DISPLAY_CPUINFO is not set
  16 +# CONFIG_DISPLAY_BOARDINFO is not set
  17 +CONFIG_SPL_OS_BOOT=y
  18 +CONFIG_SPL_RAM_SUPPORT=y
  19 +CONFIG_SPL_RAM_DEVICE=y
  20 +CONFIG_SPL_ATF=y
  21 +CONFIG_SYS_PROMPT="ZynqMP> "
  22 +CONFIG_CMD_MEMTEST=y
  23 +CONFIG_CMD_CLK=y
  24 +# CONFIG_CMD_FLASH is not set
  25 +CONFIG_CMD_FPGA_LOADBP=y
  26 +CONFIG_CMD_FPGA_LOADP=y
  27 +# CONFIG_CMD_NET is not set
  28 +# CONFIG_CMD_NFS is not set
  29 +CONFIG_CMD_TIME=y
  30 +CONFIG_CMD_TIMER=y
  31 +CONFIG_SPL_OF_CONTROL=y
  32 +CONFIG_OF_EMBED=y
  33 +CONFIG_SPL_DM=y
  34 +# CONFIG_BLK is not set
  35 +CONFIG_CLK_ZYNQMP=y
  36 +CONFIG_FPGA_XILINX=y
  37 +CONFIG_FPGA_ZYNQMPPL=y
  38 +CONFIG_MISC=y
  39 +CONFIG_DM_MMC=y
  40 +CONFIG_SPI_FLASH=y
  41 +CONFIG_SPI_FLASH_BAR=y
  42 +CONFIG_SF_DUAL_FLASH=y
  43 +CONFIG_SPI_FLASH_MACRONIX=y
  44 +CONFIG_SPI_FLASH_SPANSION=y
  45 +CONFIG_SPI_FLASH_STMICRO=y
  46 +CONFIG_SPI_FLASH_WINBOND=y
  47 +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
  48 +CONFIG_DEBUG_UART_ZYNQ=y
  49 +CONFIG_DEBUG_UART_BASE=0xff000000
  50 +CONFIG_DEBUG_UART_CLOCK=100000000
  51 +CONFIG_DEBUG_UART_ANNOUNCE=y
  52 +CONFIG_ZYNQ_SERIAL=y
  53 +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
configs/xilinx_zynqmp_zc1275_revA_defconfig
Diff comments   View file @ 85231c0
  1 +CONFIG_ARM=y
  2 +CONFIG_ARCH_ZYNQMP=y
  3 +CONFIG_SYS_TEXT_BASE=0x8000000
  4 +CONFIG_SYS_MALLOC_F_LEN=0x8000
  5 +# CONFIG_SPL_LIBDISK_SUPPORT is not set
  6 +CONFIG_SPL=y
  7 +CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1275 revA"
  8 +# CONFIG_SPL_FAT_SUPPORT is not set
  9 +CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1275-revA"
  10 +CONFIG_DEBUG_UART=y
  11 +CONFIG_DISTRO_DEFAULTS=y
  12 +CONFIG_FIT=y
  13 +CONFIG_FIT_VERBOSE=y
  14 +CONFIG_SPL_LOAD_FIT=y
  15 +# CONFIG_DISPLAY_CPUINFO is not set
  16 +# CONFIG_DISPLAY_BOARDINFO is not set
  17 +CONFIG_SPL_OS_BOOT=y
  18 +CONFIG_SPL_RAM_SUPPORT=y
  19 +CONFIG_SPL_RAM_DEVICE=y
  20 +CONFIG_SPL_ATF=y
  21 +CONFIG_SYS_PROMPT="ZynqMP> "
  22 +CONFIG_CMD_MEMTEST=y
  23 +CONFIG_CMD_CLK=y
  24 +# CONFIG_CMD_FLASH is not set
  25 +CONFIG_CMD_FPGA_LOADBP=y
  26 +CONFIG_CMD_FPGA_LOADP=y
  27 +# CONFIG_CMD_NET is not set
  28 +# CONFIG_CMD_NFS is not set
  29 +CONFIG_CMD_TIME=y
  30 +CONFIG_CMD_TIMER=y
  31 +CONFIG_SPL_OF_CONTROL=y
  32 +CONFIG_OF_EMBED=y
  33 +CONFIG_SPL_DM=y
  34 +# CONFIG_BLK is not set
  35 +CONFIG_CLK_ZYNQMP=y
  36 +CONFIG_FPGA_XILINX=y
  37 +CONFIG_FPGA_ZYNQMPPL=y
  38 +CONFIG_MISC=y
  39 +CONFIG_DM_MMC=y
  40 +CONFIG_SPI_FLASH=y
  41 +CONFIG_SPI_FLASH_BAR=y
  42 +CONFIG_SF_DUAL_FLASH=y
  43 +CONFIG_SPI_FLASH_MACRONIX=y
  44 +CONFIG_SPI_FLASH_SPANSION=y
  45 +CONFIG_SPI_FLASH_STMICRO=y
  46 +CONFIG_SPI_FLASH_WINBOND=y
  47 +# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
  48 +CONFIG_DEBUG_UART_ZYNQ=y
  49 +CONFIG_DEBUG_UART_BASE=0xff000000
  50 +CONFIG_DEBUG_UART_CLOCK=100000000
  51 +CONFIG_DEBUG_UART_ANNOUNCE=y
  52 +CONFIG_ZYNQ_SERIAL=y
  53 +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y