Commit 853ce2ee9c53b97694804e60450c15d40df9b502
Committed by
Tom Rini
Tom Rini
1 parent
df05ff7789
Exists in
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49 other branches
board: delete unused header files
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Stefan Roese <sr@denx.de> Acked-by: Matthias Fuchs <matthias.fuchs@esd.eu>
Showing 9 changed files with 0 additions and 530 deletions Side-by-side Diff
board/cogent/kbm.h
| 1 | -/* keyboard/mouse not implemented yet */ | |
| 2 | - | |
| 3 | -extern int cma_kbm_not_implemented; | |
| 4 | - | |
| 5 | -/**************** DEFINES for H8542B Keyboard/Mouse Controller ***************/ | |
| 6 | - | |
| 7 | -/* | |
| 8 | - * note the auxillary port is used to control the mouse | |
| 9 | - */ | |
| 10 | - | |
| 11 | -/* 8542B Commands (Sent to the Command Port) */ | |
| 12 | -#define HT8542_CMD_SET_BYTE 0x60 /* Set the command byte */ | |
| 13 | -#define HT8542_CMD_GET_BYTE 0x20 /* Get the command byte */ | |
| 14 | -#define HT8542_CMD_KBD_OBUFF 0xD2 /* Write to HT8542 Kbd Output Buffer */ | |
| 15 | -#define HT8542_CMD_AUX_OBUFF 0xD3 /* Write to HT8542 Mse Output Buffer */ | |
| 16 | -#define HT8542_CMD_AUX_WRITE 0xD4 /* Write to Mouse Port */ | |
| 17 | -#define HT8542_CMD_AUX_OFF 0xA7 /* Disable Mouse Port */ | |
| 18 | -#define HT8542_CMD_AUX_ON 0xA8 /* Re-Enable Mouse Port */ | |
| 19 | -#define HT8542_CMD_AUX_TEST 0xA9 /* Test for the presence of a Mouse */ | |
| 20 | -#define HT8542_CMD_DIAG 0xAA /* Start Diagnostics */ | |
| 21 | -#define HT8542_CMD_KBD_TEST 0xAB /* Test for presence of a keyboard */ | |
| 22 | -#define HT8542_CMD_KBD_OFF 0xAD /* Disable Kbd Port (use KBD_DAT_ON) */ | |
| 23 | -#define HT8542_CMD_KBD_ON 0xAE /* Enable Kbd Port (use KBD_DAT_OFF) */ | |
| 24 | - | |
| 25 | -/* HT8542B cmd byte set by KBD_CMD_SET_BYTE and retrieved by KBD_CMD_GET_BYTE */ | |
| 26 | -#define HT8542_CMD_BYTE_TRANS 0x40 | |
| 27 | -#define HT8542_CMD_BYTE_AUX_OFF 0x20 /* 1 = mse port disabled, 0 = enabled */ | |
| 28 | -#define HT8542_CMD_BYTE_KBD_OFF 0x10 /* 1 = kbd port disabled, 0 = enabled */ | |
| 29 | -#define HT8542_CMD_BYTE_OVER 0x08 /* 1 = override keyboard lock */ | |
| 30 | -#define HT8542_CMD_BYTE_RES 0x04 /* reserved */ | |
| 31 | -#define HT8542_CMD_BYTE_AUX_INT 0x02 /* 1 = enable mouse interrupt */ | |
| 32 | -#define HT8542_CMD_BYTE_KBD_INT 0x01 /* 1 = enable keyboard interrupt */ | |
| 33 | - | |
| 34 | -/* Keyboard Commands (Sent to the Data Port) */ | |
| 35 | -#define KBD_CMD_LED 0xED /* Set Keyboard LEDS with next byte */ | |
| 36 | -#define KBD_CMD_ECHO 0xEE /* Echo - we get 0xFA, 0xEE back */ | |
| 37 | -#define KBD_CMD_MODE 0xF0 /* set scan code mode with next byte */ | |
| 38 | -#define KBD_CMD_ID 0xF2 /* get keyboard/mouse ID */ | |
| 39 | -#define KBD_CMD_RPT 0xF3 /* Set Repeat Rate and Delay 2nd Byte */ | |
| 40 | -#define KBD_CMD_ON 0xF4 /* Enable keyboard */ | |
| 41 | -#define KBD_CMD_OFF 0xF5 /* Disables Scanning, Resets to Def */ | |
| 42 | -#define KBD_CMD_DEF 0xF6 /* Reverts kbd to default settings */ | |
| 43 | -#define KBD_CMD_RST 0xFF /* Reset - should get 0xFA, 0xAA back */ | |
| 44 | - | |
| 45 | -/* Set LED second bit defines */ | |
| 46 | -#define KBD_CMD_LED_SCROLL 0x01 /* Set SCROLL LOCK LED on */ | |
| 47 | -#define KBD_CMD_LED_NUM 0x02 /* Set NUM LOCK LED on */ | |
| 48 | -#define KBD_CMD_LED_CAPS 0x04 /* Set CAPS LOCK LED on */ | |
| 49 | - | |
| 50 | -/* Set Mode second byte defines */ | |
| 51 | -#define KBD_CMD_MODE_STAT 0x00 /* get current scan code mode */ | |
| 52 | -#define KBD_CMD_MODE_SCAN1 0x01 /* set mode to scan code 1 */ | |
| 53 | -#define KBD_CMD_MODE_SCAN2 0x02 /* set mode to scan code 2 */ | |
| 54 | -#define KBD_CMD_MODE_SCAN3 0x03 /* set mode to scan code 3 */ | |
| 55 | - | |
| 56 | -/* Keyboard/Mouse ID Codes */ | |
| 57 | -#define KBD_CMD_ID_1ST 0xAB /* 1st byte is 0xAB, 2nd is actual ID */ | |
| 58 | -#define KBD_CMD_ID_KBD 0x83 /* Keyboard */ | |
| 59 | -#define KBD_CMD_ID_MOUSE 0x00 /* Mouse */ | |
| 60 | - | |
| 61 | -/* Keyboard Data Return Defines */ | |
| 62 | -#define KBD_STAT_OVER 0x00 /* Buffer Overrun */ | |
| 63 | -#define KBD_STAT_DIAG_OK 0x55 /* Internal Self Test OK */ | |
| 64 | -#define KBD_STAT_RST_OK 0xAA /* Reset Complete */ | |
| 65 | -#define KBD_STAT_ECHO 0xEE /* Echo Command Return */ | |
| 66 | -#define KBD_STAT_BRK 0xF0 /* Prefix for Break Key Code */ | |
| 67 | -#define KBD_STAT_ACK 0xFA /* Received after all commands */ | |
| 68 | -#define KBD_STAT_DIAG_FAIL 0xFD /* Internal Self Test Failed */ | |
| 69 | -#define KBD_STAT_RESEND 0xFE /* Resend Last Command */ | |
| 70 | - | |
| 71 | -/* HT8542B Status Register Bit Defines */ | |
| 72 | -#define HT8542_STAT_OBF 0x01 /* 1 = output buffer is full */ | |
| 73 | -#define HT8542_STAT_IBF 0x02 /* 1 = input buffer is full */ | |
| 74 | -#define HT8542_STAT_SYS 0x04 /* system flag - unused */ | |
| 75 | -#define HT8542_STAT_CMD 0x08 /* 1 = cmd in input buffer, 0 = data */ | |
| 76 | -#define HT8542_STAT_INH 0x10 /* 1 = Inhibit - unused */ | |
| 77 | -#define HT8542_STAT_TX 0x20 /* 1 = Transmit Timeout has occured */ | |
| 78 | -#define HT8542_STAT_RX 0x40 /* 1 = Receive Timeout has occured */ | |
| 79 | -#define HT8542_STAT_PERR 0x80 /* 1 = Parity Error from Keyboard */ |
board/cray/L1/L1.h
| 1 | -/* | |
| 2 | - * (C) Copyright 2000 | |
| 3 | - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
| 4 | - * | |
| 5 | - * SPDX-License-Identifier: GPL-2.0+ | |
| 6 | - */ | |
| 7 | - | |
| 8 | -/**************************************************************************** | |
| 9 | - * FLASH Memory Map as used by CRAY L1, 4MB AMD29F032B flash chip | |
| 10 | - * | |
| 11 | - * Start Address Length | |
| 12 | - * +++++++++++++++++++++++++ 0xFFC0_0000 Start of Flash ----------------- | |
| 13 | - * | Failsafe Linux Image | (1M) | |
| 14 | - * +=======================+ 0xFFD0_0000 | |
| 15 | - * | (Reserved FlashFiles) | (1M) | |
| 16 | - * +=======================+ 0xFFE0_0000 | |
| 17 | - * | Failsafe RootFS | (1M) | |
| 18 | - * +=======================+ 0xFFF0_0000 | |
| 19 | - * | | | |
| 20 | - * | U N U S E D | | |
| 21 | - * | | | |
| 22 | - * +-----------------------+ 0xFFFD_0000 U-Boot image header (64 bytes) | |
| 23 | - * | environment settings | (64k) | |
| 24 | - * +-----------------------+ 0xFFFE_0000 U-Boot image header (64 bytes) | |
| 25 | - * | U-Boot | 0xFFFE_0040 _start of U-Boot | |
| 26 | - * | | 0xFFFE_FFFC reset vector - branch to _start | |
| 27 | - * +++++++++++++++++++++++++ 0xFFFF_FFFF End of Flash ----------------- | |
| 28 | - *****************************************************************************/ |
board/esd/common/s1d13806_640_480_8bpp.h
| 1 | -/* | |
| 2 | - * Copyright (c) 2000,2001 Epson Research and Development, Inc. | |
| 3 | - * | |
| 4 | - * SPDX-License-Identifier: GPL-2.0+ | |
| 5 | - * | |
| 6 | - * File generated by S1D13806CFG.EXE | |
| 7 | - * Panel: (active) 640x480 59Hz TFT Single 18-bit (PCLK=CLKI2=25.000MHz) | |
| 8 | - * Memory: Embedded SDRAM (MCLK=CLKI=49.152MHz) (BUSCLK=33.333MHz) | |
| 9 | - */ | |
| 10 | - | |
| 11 | -static S1D_REGS regs_13806_640_320_16bpp[] = | |
| 12 | -{ | |
| 13 | - {0x0001,0x00}, /* Miscellaneous Register */ | |
| 14 | - {0x01FC,0x00}, /* Display Mode Register */ | |
| 15 | - {0x0004,0x18}, /* General IO Pins Configuration Register 0 */ | |
| 16 | - {0x0005,0x00}, /* General IO Pins Configuration Register 1 */ | |
| 17 | - {0x0008,0x18}, /* General IO Pins Control Register 0 */ | |
| 18 | - {0x0009,0x00}, /* General IO Pins Control Register 1 */ | |
| 19 | - {0x0010,0x00}, /* Memory Clock Configuration Register */ | |
| 20 | - {0x0014,0x02}, /* LCD Pixel Clock Configuration Register */ | |
| 21 | - {0x0018,0x02}, /* CRT/TV Pixel Clock Configuration Register */ | |
| 22 | - {0x001C,0x02}, /* MediaPlug Clock Configuration Register */ | |
| 23 | - {0x001E,0x01}, /* CPU To Memory Wait State Select Register */ | |
| 24 | - {0x0021,0x03}, /* DRAM Refresh Rate Register */ | |
| 25 | - {0x002A,0x00}, /* DRAM Timings Control Register 0 */ | |
| 26 | - {0x002B,0x01}, /* DRAM Timings Control Register 1 */ | |
| 27 | - {0x0020,0x80}, /* Memory Configuration Register */ | |
| 28 | - {0x0030,0x25}, /* Panel Type Register */ | |
| 29 | - {0x0031,0x00}, /* MOD Rate Register */ | |
| 30 | - {0x0032,0x4F}, /* LCD Horizontal Display Width Register */ | |
| 31 | - {0x0034,0x13}, /* LCD Horizontal Non-Display Period Register */ | |
| 32 | - {0x0035,0x00}, /* TFT FPLINE Start Position Register */ | |
| 33 | - {0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */ | |
| 34 | - {0x0038,0xDF}, /* LCD Vertical Display Height Register 0 */ | |
| 35 | - {0x0039,0x01}, /* LCD Vertical Display Height Register 1 */ | |
| 36 | - {0x003A,0x24}, /* LCD Vertical Non-Display Period Register */ | |
| 37 | - {0x003B,0x00}, /* TFT FPFRAME Start Position Register */ | |
| 38 | - {0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */ | |
| 39 | - {0x0040,0x03}, /* LCD Display Mode Register (8bpp) */ | |
| 40 | - {0x0041,0x00}, /* LCD Miscellaneous Register */ | |
| 41 | - {0x0042,0x00}, /* LCD Display Start Address Register 0 */ | |
| 42 | - {0x0043,0x00}, /* LCD Display Start Address Register 1 */ | |
| 43 | - {0x0044,0x00}, /* LCD Display Start Address Register 2 */ | |
| 44 | - {0x0046,0x80}, /* LCD Memory Address Offset Register 0 */ | |
| 45 | - {0x0047,0x02}, /* LCD Memory Address Offset Register 1 */ | |
| 46 | - {0x0048,0x00}, /* LCD Pixel Panning Register */ | |
| 47 | - {0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */ | |
| 48 | - {0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */ | |
| 49 | - {0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */ | |
| 50 | - {0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */ | |
| 51 | - {0x0053,0x01}, /* CRT/TV HRTC Start Position Register */ | |
| 52 | - {0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */ | |
| 53 | - {0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */ | |
| 54 | - {0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */ | |
| 55 | - {0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */ | |
| 56 | - {0x0059,0x09}, /* CRT/TV VRTC Start Position Register */ | |
| 57 | - {0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */ | |
| 58 | - {0x005B,0x10}, /* TV Output Control Register */ | |
| 59 | - {0x0060,0x05}, /* CRT/TV Display Mode Register */ | |
| 60 | - {0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */ | |
| 61 | - {0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */ | |
| 62 | - {0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */ | |
| 63 | - {0x0066,0x80}, /* CRT/TV Memory Address Offset Register 0 */ | |
| 64 | - {0x0067,0x02}, /* CRT/TV Memory Address Offset Register 1 */ | |
| 65 | - {0x0068,0x00}, /* CRT/TV Pixel Panning Register */ | |
| 66 | - {0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */ | |
| 67 | - {0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */ | |
| 68 | - {0x0070,0x00}, /* LCD Ink/Cursor Control Register */ | |
| 69 | - {0x0071,0x01}, /* LCD Ink/Cursor Start Address Register */ | |
| 70 | - {0x0072,0x00}, /* LCD Cursor X Position Register 0 */ | |
| 71 | - {0x0073,0x00}, /* LCD Cursor X Position Register 1 */ | |
| 72 | - {0x0074,0x00}, /* LCD Cursor Y Position Register 0 */ | |
| 73 | - {0x0075,0x00}, /* LCD Cursor Y Position Register 1 */ | |
| 74 | - {0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */ | |
| 75 | - {0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */ | |
| 76 | - {0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */ | |
| 77 | - {0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */ | |
| 78 | - {0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */ | |
| 79 | - {0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */ | |
| 80 | - {0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */ | |
| 81 | - {0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */ | |
| 82 | - {0x0081,0x01}, /* CRT/TV Ink/Cursor Start Address Register */ | |
| 83 | - {0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */ | |
| 84 | - {0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */ | |
| 85 | - {0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */ | |
| 86 | - {0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */ | |
| 87 | - {0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */ | |
| 88 | - {0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */ | |
| 89 | - {0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */ | |
| 90 | - {0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */ | |
| 91 | - {0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */ | |
| 92 | - {0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */ | |
| 93 | - {0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */ | |
| 94 | - {0x0100,0x00}, /* BitBlt Control Register 0 */ | |
| 95 | - {0x0101,0x00}, /* BitBlt Control Register 1 */ | |
| 96 | - {0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */ | |
| 97 | - {0x0103,0x00}, /* BitBlt Operation Register */ | |
| 98 | - {0x0104,0x00}, /* BitBlt Source Start Address Register 0 */ | |
| 99 | - {0x0105,0x00}, /* BitBlt Source Start Address Register 1 */ | |
| 100 | - {0x0106,0x00}, /* BitBlt Source Start Address Register 2 */ | |
| 101 | - {0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */ | |
| 102 | - {0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */ | |
| 103 | - {0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */ | |
| 104 | - {0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */ | |
| 105 | - {0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */ | |
| 106 | - {0x0110,0x00}, /* BitBlt Width Register 0 */ | |
| 107 | - {0x0111,0x00}, /* BitBlt Width Register 1 */ | |
| 108 | - {0x0112,0x00}, /* BitBlt Height Register 0 */ | |
| 109 | - {0x0113,0x00}, /* BitBlt Height Register 1 */ | |
| 110 | - {0x0114,0x00}, /* BitBlt Background Color Register 0 */ | |
| 111 | - {0x0115,0x00}, /* BitBlt Background Color Register 1 */ | |
| 112 | - {0x0118,0x00}, /* BitBlt Foreground Color Register 0 */ | |
| 113 | - {0x0119,0x00}, /* BitBlt Foreground Color Register 1 */ | |
| 114 | - {0x01E0,0x00}, /* Look-Up Table Mode Register */ | |
| 115 | - {0x01E2,0x00}, /* Look-Up Table Address Register */ | |
| 116 | - {0x01F0,0x10}, /* Power Save Configuration Register */ | |
| 117 | - {0x01F1,0x00}, /* Power Save Status Register */ | |
| 118 | - {0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */ | |
| 119 | - {0x01FC,0x01}, /* Display Mode Register */ | |
| 120 | -}; |
board/etin/debris/speed.h
| 1 | -/* | |
| 2 | - * (C) Copyright 2000 | |
| 3 | - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
| 4 | - * | |
| 5 | - * SPDX-License-Identifier: GPL-2.0+ | |
| 6 | - */ | |
| 7 | - | |
| 8 | -/*----------------------------------------------------------------------- | |
| 9 | - * Timer value for timer 2, ICLK = 10 | |
| 10 | - * | |
| 11 | - * SPEED_FCOUNT2 = GCLK / (16 * (TIMER_TMR_PS + 1)) | |
| 12 | - * SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1 | |
| 13 | - * | |
| 14 | - * SPEED_FCOUNT2 timer 2 counting frequency | |
| 15 | - * GCLK CPU clock | |
| 16 | - * SPEED_TMR2_PS prescaler | |
| 17 | - */ | |
| 18 | -#define SPEED_TMR2_PS (250 - 1) /* divide by 250 */ | |
| 19 | - | |
| 20 | -/*----------------------------------------------------------------------- | |
| 21 | - * Timer value for PIT | |
| 22 | - * | |
| 23 | - * PIT_TIME = SPEED_PITC / PITRTCLK | |
| 24 | - * PITRTCLK = 8192 | |
| 25 | - */ | |
| 26 | -#define SPEED_PITC (82 << 16) /* start counting from 82 */ | |
| 27 | - | |
| 28 | -/* | |
| 29 | - * The new value for PTA is calculated from | |
| 30 | - * | |
| 31 | - * PTA = (gclk * Trefresh) / (2 ^ (2 * DFBRG) * PTP * NCS) | |
| 32 | - * | |
| 33 | - * gclk CPU clock (not bus clock !) | |
| 34 | - * Trefresh Refresh cycle * 4 (four word bursts used) | |
| 35 | - * DFBRG For normal mode (no clock reduction) always 0 | |
| 36 | - * PTP Prescaler (already adjusted for no. of banks and 4K / 8K refresh) | |
| 37 | - * NCS Number of SDRAM banks (chip selects) on this UPM. | |
| 38 | - */ |
board/genietv/genietv.h
| 1 | -/* | |
| 2 | - * The GENIETV is using the following physical memorymap (copied from | |
| 3 | - * the FADS configuration): | |
| 4 | - * | |
| 5 | - * ff020000 -> ff02ffff : pcmcia | |
| 6 | - * ff010000 -> ff01ffff : BCSR connected to CS1, setup by 8xxROM | |
| 7 | - * ff000000 -> ff00ffff : IMAP internal in the cpu | |
| 8 | - * 02800000 -> 0287ffff : flash connected to CS0 | |
| 9 | - * 00000000 -> nnnnnnnn : sdram setup by U-Boot | |
| 10 | - * | |
| 11 | - * CS pins are connected as follows: | |
| 12 | - * | |
| 13 | - * CS0 -512Kb boot flash | |
| 14 | - * CS1 - SDRAM #1 | |
| 15 | - * CS2 - SDRAM #2 | |
| 16 | - * CS3 - Flash #1 | |
| 17 | - * CS4 - Flash #2 | |
| 18 | - * CS5 - LON (if present) | |
| 19 | - * CS6 - PCMCIA #1 | |
| 20 | - * CS7 - PCMCIA #2 | |
| 21 | - * | |
| 22 | - * Ports are configured as follows: | |
| 23 | - * | |
| 24 | - * PA7 - SDRAM banks enable | |
| 25 | - */ |
board/hidden_dragon/speed.h
| 1 | -/* | |
| 2 | - * (C) Copyright 2000 | |
| 3 | - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
| 4 | - * | |
| 5 | - * SPDX-License-Identifier: GPL-2.0+ | |
| 6 | - */ | |
| 7 | - | |
| 8 | -/*----------------------------------------------------------------------- | |
| 9 | - * Timer value for timer 2, ICLK = 10 | |
| 10 | - * | |
| 11 | - * SPEED_FCOUNT2 = GCLK / (16 * (TIMER_TMR_PS + 1)) | |
| 12 | - * SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1 | |
| 13 | - * | |
| 14 | - * SPEED_FCOUNT2 timer 2 counting frequency | |
| 15 | - * GCLK CPU clock | |
| 16 | - * SPEED_TMR2_PS prescaler | |
| 17 | - */ | |
| 18 | -#define SPEED_TMR2_PS (250 - 1) /* divide by 250 */ | |
| 19 | - | |
| 20 | -/*----------------------------------------------------------------------- | |
| 21 | - * Timer value for PIT | |
| 22 | - * | |
| 23 | - * PIT_TIME = SPEED_PITC / PITRTCLK | |
| 24 | - * PITRTCLK = 8192 | |
| 25 | - */ | |
| 26 | -#define SPEED_PITC (82 << 16) /* start counting from 82 */ | |
| 27 | - | |
| 28 | -/* | |
| 29 | - * The new value for PTA is calculated from | |
| 30 | - * | |
| 31 | - * PTA = (gclk * Trefresh) / (2 ^ (2 * DFBRG) * PTP * NCS) | |
| 32 | - * | |
| 33 | - * gclk CPU clock (not bus clock !) | |
| 34 | - * Trefresh Refresh cycle * 4 (four word bursts used) | |
| 35 | - * DFBRG For normal mode (no clock reduction) always 0 | |
| 36 | - * PTP Prescaler (already adjusted for no. of banks and 4K / 8K refresh) | |
| 37 | - * NCS Number of SDRAM banks (chip selects) on this UPM. | |
| 38 | - */ |
board/inka4x0/hyb25d512160bf-5.h
| 1 | -/* | |
| 2 | - * Copyright (C) 2007 Semihalf | |
| 3 | - * Written by Marian Balakowicz <m8@semihalf.com> | |
| 4 | - * | |
| 5 | - * SPDX-License-Identifier: GPL-2.0+ | |
| 6 | - */ | |
| 7 | - | |
| 8 | -#define SDRAM_DDR 1 /* is DDR */ | |
| 9 | - | |
| 10 | -/* Settings for XLB = 132 MHz */ | |
| 11 | -#define SDRAM_MODE 0x018D0000 | |
| 12 | -#define SDRAM_EMODE 0x40090000 | |
| 13 | -#define SDRAM_CONTROL 0x714F0F00 | |
| 14 | -#define SDRAM_CONFIG1 0x73711930 | |
| 15 | -#define SDRAM_CONFIG2 0x46770000 | |
| 16 | -#define SDRAM_TAPDELAY 0x10000000 |
board/prodrive/p3mx/ppc_error_no.h
| 1 | -/* | |
| 2 | - * (C) Copyright 2003 | |
| 3 | - * Ingo Assmus <ingo.assmus@keymile.com> | |
| 4 | - * | |
| 5 | - * SPDX-License-Identifier: GPL-2.0+ | |
| 6 | - */ | |
| 7 | - | |
| 8 | -/* | |
| 9 | - * BK Id: SCCS/s.errno.h 1.9 06/05/01 21:45:21 paulus | |
| 10 | - */ | |
| 11 | -#ifndef _MV_PPC_ERRNO_H | |
| 12 | -#define _MV_PPC_ERRNO_H | |
| 13 | - | |
| 14 | -#define EPERM 1 /* Operation not permitted */ | |
| 15 | -#define ENOENT 2 /* No such file or directory */ | |
| 16 | -#define ESRCH 3 /* No such process */ | |
| 17 | -#define EINTR 4 /* Interrupted system call */ | |
| 18 | -#define EIO 5 /* I/O error */ | |
| 19 | -#define ENXIO 6 /* No such device or address */ | |
| 20 | -#define E2BIG 7 /* Arg list too long */ | |
| 21 | -#define ENOEXEC 8 /* Exec format error */ | |
| 22 | -#define EBADF 9 /* Bad file number */ | |
| 23 | -#define ECHILD 10 /* No child processes */ | |
| 24 | -#define EAGAIN 11 /* Try again */ | |
| 25 | -#define ENOMEM 12 /* Out of memory */ | |
| 26 | -#define EACCES 13 /* Permission denied */ | |
| 27 | -#define EFAULT 14 /* Bad address */ | |
| 28 | -#define ENOTBLK 15 /* Block device required */ | |
| 29 | -#define EBUSY 16 /* Device or resource busy */ | |
| 30 | -#define EEXIST 17 /* File exists */ | |
| 31 | -#define EXDEV 18 /* Cross-device link */ | |
| 32 | -#define ENODEV 19 /* No such device */ | |
| 33 | -#define ENOTDIR 20 /* Not a directory */ | |
| 34 | -#define EISDIR 21 /* Is a directory */ | |
| 35 | -#define EINVAL 22 /* Invalid argument */ | |
| 36 | -#define ENFILE 23 /* File table overflow */ | |
| 37 | -#define EMFILE 24 /* Too many open files */ | |
| 38 | -#define ENOTTY 25 /* Not a typewriter */ | |
| 39 | -#define ETXTBSY 26 /* Text file busy */ | |
| 40 | -#define EFBIG 27 /* File too large */ | |
| 41 | -#define ENOSPC 28 /* No space left on device */ | |
| 42 | -#define ESPIPE 29 /* Illegal seek */ | |
| 43 | -#define EROFS 30 /* Read-only file system */ | |
| 44 | -#define EMLINK 31 /* Too many links */ | |
| 45 | -#define EPIPE 32 /* Broken pipe */ | |
| 46 | -#define EDOM 33 /* Math argument out of domain of func */ | |
| 47 | -#define ERANGE 34 /* Math result not representable */ | |
| 48 | -#define EDEADLK 35 /* Resource deadlock would occur */ | |
| 49 | -#define ENAMETOOLONG 36 /* File name too long */ | |
| 50 | -#define ENOLCK 37 /* No record locks available */ | |
| 51 | -#define ENOSYS 38 /* Function not implemented */ | |
| 52 | -#define ENOTEMPTY 39 /* Directory not empty */ | |
| 53 | -#define ELOOP 40 /* Too many symbolic links encountered */ | |
| 54 | -#define EWOULDBLOCK EAGAIN /* Operation would block */ | |
| 55 | -#define ENOMSG 42 /* No message of desired type */ | |
| 56 | -#define EIDRM 43 /* Identifier removed */ | |
| 57 | -#define ECHRNG 44 /* Channel number out of range */ | |
| 58 | -#define EL2NSYNC 45 /* Level 2 not synchronized */ | |
| 59 | -#define EL3HLT 46 /* Level 3 halted */ | |
| 60 | -#define EL3RST 47 /* Level 3 reset */ | |
| 61 | -#define ELNRNG 48 /* Link number out of range */ | |
| 62 | -#define EUNATCH 49 /* Protocol driver not attached */ | |
| 63 | -#define ENOCSI 50 /* No CSI structure available */ | |
| 64 | -#define EL2HLT 51 /* Level 2 halted */ | |
| 65 | -#define EBADE 52 /* Invalid exchange */ | |
| 66 | -#define EBADR 53 /* Invalid request descriptor */ | |
| 67 | -#define EXFULL 54 /* Exchange full */ | |
| 68 | -#define ENOANO 55 /* No anode */ | |
| 69 | -#define EBADRQC 56 /* Invalid request code */ | |
| 70 | -#define EBADSLT 57 /* Invalid slot */ | |
| 71 | -#define EDEADLOCK 58 /* File locking deadlock error */ | |
| 72 | -#define EBFONT 59 /* Bad font file format */ | |
| 73 | -#define ENOSTR 60 /* Device not a stream */ | |
| 74 | -#define ENODATA 61 /* No data available */ | |
| 75 | -#define ETIME 62 /* Timer expired */ | |
| 76 | -#define ENOSR 63 /* Out of streams resources */ | |
| 77 | -#define ENONET 64 /* Machine is not on the network */ | |
| 78 | -#define ENOPKG 65 /* Package not installed */ | |
| 79 | -#define EREMOTE 66 /* Object is remote */ | |
| 80 | -#define ENOLINK 67 /* Link has been severed */ | |
| 81 | -#define EADV 68 /* Advertise error */ | |
| 82 | -#define ESRMNT 69 /* Srmount error */ | |
| 83 | -#define ECOMM 70 /* Communication error on send */ | |
| 84 | -#define EPROTO 71 /* Protocol error */ | |
| 85 | -#define EMULTIHOP 72 /* Multihop attempted */ | |
| 86 | -#define EDOTDOT 73 /* RFS specific error */ | |
| 87 | -#define EBADMSG 74 /* Not a data message */ | |
| 88 | -#define EOVERFLOW 75 /* Value too large for defined data type */ | |
| 89 | -#define ENOTUNIQ 76 /* Name not unique on network */ | |
| 90 | -#define EBADFD 77 /* File descriptor in bad state */ | |
| 91 | -#define EREMCHG 78 /* Remote address changed */ | |
| 92 | -#define ELIBACC 79 /* Can not access a needed shared library */ | |
| 93 | -#define ELIBBAD 80 /* Accessing a corrupted shared library */ | |
| 94 | -#define ELIBSCN 81 /* .lib section in a.out corrupted */ | |
| 95 | -#define ELIBMAX 82 /* Attempting to link in too many shared libraries */ | |
| 96 | -#define ELIBEXEC 83 /* Cannot exec a shared library directly */ | |
| 97 | -#define EILSEQ 84 /* Illegal byte sequence */ | |
| 98 | -#define ERESTART 85 /* Interrupted system call should be restarted */ | |
| 99 | -#define ESTRPIPE 86 /* Streams pipe error */ | |
| 100 | -#define EUSERS 87 /* Too many users */ | |
| 101 | -#define ENOTSOCK 88 /* Socket operation on non-socket */ | |
| 102 | -#define EDESTADDRREQ 89 /* Destination address required */ | |
| 103 | -#define EMSGSIZE 90 /* Message too long */ | |
| 104 | -#define EPROTOTYPE 91 /* Protocol wrong type for socket */ | |
| 105 | -#define ENOPROTOOPT 92 /* Protocol not available */ | |
| 106 | -#define EPROTONOSUPPORT 93 /* Protocol not supported */ | |
| 107 | -#define ESOCKTNOSUPPORT 94 /* Socket type not supported */ | |
| 108 | -#define EOPNOTSUPP 95 /* Operation not supported on transport endpoint */ | |
| 109 | -#define EPFNOSUPPORT 96 /* Protocol family not supported */ | |
| 110 | -#define EAFNOSUPPORT 97 /* Address family not supported by protocol */ | |
| 111 | -#define EADDRINUSE 98 /* Address already in use */ | |
| 112 | -#define EADDRNOTAVAIL 99 /* Cannot assign requested address */ | |
| 113 | -#define ENETDOWN 100 /* Network is down */ | |
| 114 | -#define ENETUNREACH 101 /* Network is unreachable */ | |
| 115 | -#define ENETRESET 102 /* Network dropped connection because of reset */ | |
| 116 | -#define ECONNABORTED 103 /* Software caused connection abort */ | |
| 117 | -#define ECONNRESET 104 /* Connection reset by peer */ | |
| 118 | -#define ENOBUFS 105 /* No buffer space available */ | |
| 119 | -#define EISCONN 106 /* Transport endpoint is already connected */ | |
| 120 | -#define ENOTCONN 107 /* Transport endpoint is not connected */ | |
| 121 | -#define ESHUTDOWN 108 /* Cannot send after transport endpoint shutdown */ | |
| 122 | -#define ETOOMANYREFS 109 /* Too many references: cannot splice */ | |
| 123 | -#define ETIMEDOUT 110 /* Connection timed out */ | |
| 124 | -#define ECONNREFUSED 111 /* Connection refused */ | |
| 125 | -#define EHOSTDOWN 112 /* Host is down */ | |
| 126 | -#define EHOSTUNREACH 113 /* No route to host */ | |
| 127 | -#define EALREADY 114 /* Operation already in progress */ | |
| 128 | -#define EINPROGRESS 115 /* Operation now in progress */ | |
| 129 | -#define ESTALE 116 /* Stale NFS file handle */ | |
| 130 | -#define EUCLEAN 117 /* Structure needs cleaning */ | |
| 131 | -#define ENOTNAM 118 /* Not a XENIX named type file */ | |
| 132 | -#define ENAVAIL 119 /* No XENIX semaphores available */ | |
| 133 | -#define EISNAM 120 /* Is a named type file */ | |
| 134 | -#define EREMOTEIO 121 /* Remote I/O error */ | |
| 135 | -#define EDQUOT 122 /* Quota exceeded */ | |
| 136 | - | |
| 137 | -#define ENOMEDIUM 123 /* No medium found */ | |
| 138 | -#define EMEDIUMTYPE 124 /* Wrong medium type */ | |
| 139 | - | |
| 140 | -/* Should never be seen by user programs */ | |
| 141 | -#define ERESTARTSYS 512 | |
| 142 | -#define ERESTARTNOINTR 513 | |
| 143 | -#define ERESTARTNOHAND 514 /* restart if no handler.. */ | |
| 144 | -#define ENOIOCTLCMD 515 /* No ioctl command */ | |
| 145 | - | |
| 146 | -#define _LAST_ERRNO 515 | |
| 147 | - | |
| 148 | -#endif |
board/sandpoint/speed.h
| 1 | -/* | |
| 2 | - * (C) Copyright 2000 | |
| 3 | - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
| 4 | - * | |
| 5 | - * SPDX-License-Identifier: GPL-2.0+ | |
| 6 | - */ | |
| 7 | - | |
| 8 | -/*----------------------------------------------------------------------- | |
| 9 | - * Timer value for timer 2, ICLK = 10 | |
| 10 | - * | |
| 11 | - * SPEED_FCOUNT2 = GCLK / (16 * (TIMER_TMR_PS + 1)) | |
| 12 | - * SPEED_TMR3_PS = (GCLK / (16 * SPEED_FCOUNT3)) - 1 | |
| 13 | - * | |
| 14 | - * SPEED_FCOUNT2 timer 2 counting frequency | |
| 15 | - * GCLK CPU clock | |
| 16 | - * SPEED_TMR2_PS prescaler | |
| 17 | - */ | |
| 18 | -#define SPEED_TMR2_PS (250 - 1) /* divide by 250 */ | |
| 19 | - | |
| 20 | -/*----------------------------------------------------------------------- | |
| 21 | - * Timer value for PIT | |
| 22 | - * | |
| 23 | - * PIT_TIME = SPEED_PITC / PITRTCLK | |
| 24 | - * PITRTCLK = 8192 | |
| 25 | - */ | |
| 26 | -#define SPEED_PITC (82 << 16) /* start counting from 82 */ | |
| 27 | - | |
| 28 | -/* | |
| 29 | - * The new value for PTA is calculated from | |
| 30 | - * | |
| 31 | - * PTA = (gclk * Trefresh) / (2 ^ (2 * DFBRG) * PTP * NCS) | |
| 32 | - * | |
| 33 | - * gclk CPU clock (not bus clock !) | |
| 34 | - * Trefresh Refresh cycle * 4 (four word bursts used) | |
| 35 | - * DFBRG For normal mode (no clock reduction) always 0 | |
| 36 | - * PTP Prescaler (already adjusted for no. of banks and 4K / 8K refresh) | |
| 37 | - * NCS Number of SDRAM banks (chip selects) on this UPM. | |
| 38 | - */ |