Eric Lee / smarc-uboot

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Commit 85ab0452fefc8c48b0b4f35200cb2590b4693ab3

Authored by Felix Brack
Committed by Tom Rini
1 parent c8a73a26d6
Exists in smarc_8mq_lf_v2020.04 and in 17 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

arm: add support for PDU001 

This patch adds support for the PDU001 board.

Signed-off-by: Felix Brack <fb@ltec.ch>
Reviewed-by: Tom Rini <trini@konsulko.com>

Showing 14 changed files with 1342 additions and 1 deletions Side-by-side Diff

... ... @@ -1291,6 +1291,7 @@
1291 1291 source "board/cavium/thunderx/Kconfig"
1292 1292 source "board/cirrus/edb93xx/Kconfig"
1293 1293 source "board/creative/xfi3/Kconfig"
  1294 +source "board/eets/pdu001/Kconfig"
1294 1295 source "board/freescale/ls2080a/Kconfig"
1295 1296 source "board/freescale/ls2080aqds/Kconfig"
1296 1297 source "board/freescale/ls2080ardb/Kconfig"
arch/arm/dts/Makefile
Diff comments   View file @ 85ab045
... ... @@ -161,7 +161,8 @@
161 161 am335x-bonegreen.dtb \
162 162 am335x-icev2.dtb \
163 163 am335x-pxm50.dtb \
164   - am335x-rut.dtb
  164 + am335x-rut.dtb \
  165 + am335x-pdu001.dtb
165 166 dtb-$(CONFIG_AM43XX) += am437x-gp-evm.dtb am437x-sk-evm.dtb \
166 167 am43x-epos-evm.dtb \
167 168 am437x-idk-evm.dtb
arch/arm/dts/am335x-pdu001-u-boot.dtsi
Diff comments   View file @ 85ab045
  1 +/*
  2 + * Copyright (C) 2018 EETS GmbH - https://www.eets.ch/
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +/ {
  8 + ocp {
  9 + u-boot,dm-pre-reloc;
  10 + };
  11 +};
  12 +
  13 +&l4_wkup {
  14 + u-boot,dm-pre-reloc;
  15 +};
  16 +
  17 +&scm {
  18 + u-boot,dm-pre-reloc;
  19 +};
  20 +
  21 +&am33xx_pinmux {
  22 + u-boot,dm-pre-reloc;
  23 +};
  24 +
  25 +&uart3_pins {
  26 + u-boot,dm-pre-reloc;
  27 +};
  28 +
  29 +&uart3 {
  30 + u-boot,dm-pre-reloc;
  31 +};
  32 +
  33 +&mmc1_pins {
  34 + u-boot,dm-pre-reloc;
  35 +};
  36 +
  37 +&mmc2_pins {
  38 + u-boot,dm-pre-reloc;
  39 +};
arch/arm/dts/am335x-pdu001.dts
Diff comments   View file @ 85ab045
  1 +/*
  2 + * pdu001.dts
  3 + *
  4 + * EETS GmbH PDU001 board device tree file
  5 + *
  6 + * Copyright (C) 2018 EETS GmbH - http://www.eets.ch/
  7 + *
  8 + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  9 + *
  10 + * SPDX-License-Identifier: GPL-2.0+
  11 + */
  12 +
  13 +/dts-v1/;
  14 +
  15 +#include "am33xx.dtsi"
  16 +#include <dt-bindings/interrupt-controller/irq.h>
  17 +#include <dt-bindings/leds/leds-pca9532.h>
  18 +
  19 +/ {
  20 + model = "EETS,PDU001";
  21 + compatible = "eets,pdu001", "ti,am33xx";
  22 +
  23 + chosen {
  24 + stdout-path = &uart3;
  25 + };
  26 +
  27 + cpus {
  28 + cpu@0 {
  29 + cpu0-supply = <&vdd1_reg>;
  30 + };
  31 + };
  32 +
  33 + memory {
  34 + device_type = "memory";
  35 + reg = <0x80000000 0x10000000>; /* 256 MB */
  36 + };
  37 +
  38 + vbat: fixedregulator@0 {
  39 + compatible = "regulator-fixed";
  40 + regulator-name = "vbat";
  41 + regulator-min-microvolt = <3600000>;
  42 + regulator-max-microvolt = <3600000>;
  43 + regulator-boot-on;
  44 + };
  45 +
  46 + lis3_reg: fixedregulator@1 {
  47 + compatible = "regulator-fixed";
  48 + regulator-name = "lis3_reg";
  49 + regulator-boot-on;
  50 + };
  51 +
  52 + panel {
  53 + compatible = "ti,tilcdc,panel";
  54 + status = "okay";
  55 + pinctrl-names = "default";
  56 + pinctrl-0 = <&lcd_pins_s0>;
  57 + panel-info {
  58 + ac-bias = <255>;
  59 + ac-bias-intrpt = <0>;
  60 + dma-burst-sz = <16>;
  61 + bpp = <16>;
  62 + fdd = <0x80>;
  63 + sync-edge = <0>;
  64 + sync-ctrl = <1>;
  65 + raster-order = <0>;
  66 + fifo-th = <0>;
  67 + };
  68 +
  69 + display-timings {
  70 + 240x320p16 {
  71 + clock-frequency = <6500000>;
  72 + hactive = <240>;
  73 + vactive = <320>;
  74 + hfront-porch = <6>;
  75 + hback-porch = <6>;
  76 + hsync-len = <1>;
  77 + vback-porch = <6>;
  78 + vfront-porch = <6>;
  79 + vsync-len = <1>;
  80 + hsync-active = <0>;
  81 + vsync-active = <0>;
  82 + pixelclk-active = <1>;
  83 + de-active = <0>;
  84 + };
  85 + };
  86 + };
  87 +};
  88 +
  89 +&am33xx_pinmux {
  90 + pinctrl-names = "default";
  91 + pinctrl-0 = <&clkout2_pin>;
  92 +
  93 + i2c0_pins: pinmux_i2c0_pins {
  94 + pinctrl-single,pins = <
  95 + AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
  96 + AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
  97 + >;
  98 + };
  99 +
  100 + i2c1_pins: pinmux_i2c1_pins {
  101 + pinctrl-single,pins = <
  102 + AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d1.i2c1_sda */
  103 + AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_cs0.i2c1_scl */
  104 + >;
  105 + };
  106 +
  107 + i2c2_pins: pinmux_i2c2_pins {
  108 + pinctrl-single,pins = <
  109 + AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_clk.i2c2_sda */
  110 + AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d0.i2c2_scl */
  111 + >;
  112 + };
  113 +
  114 + spi1_pins: pinmux_spi1_pins {
  115 + pinctrl-single,pins = <
  116 + AM33XX_IOPAD(0x990, PIN_OUTPUT | MUX_MODE3) /* mcasp0_aclkx.spi1_sclk */
  117 + AM33XX_IOPAD(0x994, PIN_OUTPUT | MUX_MODE3) /* mcasp0_fsx.spi1_d0 */
  118 + AM33XX_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcasp0_axr0.spi1_d1 */
  119 + AM33XX_IOPAD(0x99C, PIN_OUTPUT | MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 */
  120 + >;
  121 + };
  122 +
  123 + uart0_pins: pinmux_uart0_pins {
  124 + pinctrl-single,pins = <
  125 + AM33XX_IOPAD(0x96C, PIN_OUTPUT | MUX_MODE7) /* uart0_rtsn.gpio1_9 */
  126 + AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
  127 + AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
  128 + >;
  129 + };
  130 +
  131 + uart1_pins: pinmux_uart1_pins {
  132 + pinctrl-single,pins = <
  133 + AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */
  134 + AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */
  135 + >;
  136 + };
  137 +
  138 + uart3_pins: pinmux_uart3_pins {
  139 + pinctrl-single,pins = <
  140 + AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE1) /* spi0_cs1.uart3_rxd */
  141 + AM33XX_IOPAD(0x964, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* ecap0_in_pwm0_out.uart3_txd */
  142 + >;
  143 + };
  144 +
  145 + clkout2_pin: pinmux_clkout2_pin {
  146 + pinctrl-single,pins = <
  147 + AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
  148 + >;
  149 + };
  150 +
  151 + cpsw_default: cpsw_default {
  152 + pinctrl-single,pins = <
  153 + /* Port 1 (emac0) */
  154 + AM33XX_IOPAD(0x908, PIN_INPUT | MUX_MODE0) /* mii1_col.mii1_col */
  155 + AM33XX_IOPAD(0x90C, PIN_INPUT | MUX_MODE0) /* mii1_crs.mii1_crs */
  156 + AM33XX_IOPAD(0x910, PIN_INPUT | MUX_MODE0) /* mii1_rxer.mii1_rxer */
  157 + AM33XX_IOPAD(0x914, PIN_OUTPUT | MUX_MODE0) /* mii1_txen.mii1_txen */
  158 + AM33XX_IOPAD(0x918, PIN_INPUT | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */
  159 + AM33XX_IOPAD(0x91c, PIN_OUTPUT | MUX_MODE0) /* mii1_txd3.mii1_txd3 */
  160 + AM33XX_IOPAD(0x920, PIN_OUTPUT | MUX_MODE0) /* mii1_txd2.mii1_txd2 */
  161 + AM33XX_IOPAD(0x924, PIN_OUTPUT | MUX_MODE0) /* mii1_txd1.mii1_txd1 */
  162 + AM33XX_IOPAD(0x928, PIN_OUTPUT | MUX_MODE0) /* mii1_txd0.mii1_txd0 */
  163 + AM33XX_IOPAD(0x92c, PIN_INPUT | MUX_MODE0) /* mii1_txclk.mii1_txclk */
  164 + AM33XX_IOPAD(0x930, PIN_INPUT | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */
  165 + AM33XX_IOPAD(0x934, PIN_INPUT | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */
  166 + AM33XX_IOPAD(0x938, PIN_INPUT | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */
  167 + AM33XX_IOPAD(0x93c, PIN_INPUT | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */
  168 + AM33XX_IOPAD(0x940, PIN_INPUT | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */
  169 +
  170 + /* Port 2 (emac1) */
  171 + AM33XX_IOPAD(0x840, PIN_OUTPUT | MUX_MODE1) /* mii2_txen.gpmc_a0 */
  172 + AM33XX_IOPAD(0x844, PIN_INPUT | MUX_MODE1) /* mii2_rxdv.gpmc_a1 */
  173 + AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE1) /* mii2_txd3.gpmc_a2 */
  174 + AM33XX_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE1) /* mii2_txd2.gpmc_a3 */
  175 + AM33XX_IOPAD(0x850, PIN_OUTPUT | MUX_MODE1) /* mii2_txd1.gpmc_a4 */
  176 + AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE1) /* mii2_txd0.gpmc_a5 */
  177 + AM33XX_IOPAD(0x858, PIN_INPUT | MUX_MODE1) /* mii2_txclk.gpmc_a6 */
  178 + AM33XX_IOPAD(0x85c, PIN_INPUT | MUX_MODE1) /* mii2_rxclk.gpmc_a7 */
  179 + AM33XX_IOPAD(0x860, PIN_INPUT | MUX_MODE1) /* mii2_rxd3.gpmc_a8 */
  180 + AM33XX_IOPAD(0x864, PIN_INPUT | MUX_MODE1) /* mii2_rxd2.gpmc_a9 */
  181 + AM33XX_IOPAD(0x868, PIN_INPUT | MUX_MODE1) /* mii2_rxd1.gpmc_a10 */
  182 + AM33XX_IOPAD(0x86C, PIN_INPUT | MUX_MODE1) /* mii2_rxd0.gpmc_a11 */
  183 + AM33XX_IOPAD(0x870, PIN_INPUT | MUX_MODE1) /* mii2_crs.gpmc_wait0 */
  184 + AM33XX_IOPAD(0x874, PIN_INPUT | MUX_MODE1) /* mii2_rxer.gpmc_wpn */
  185 + AM33XX_IOPAD(0x878, PIN_INPUT | MUX_MODE1) /* mii2_col.gpmc_ben1 */
  186 + >;
  187 + };
  188 +
  189 + davinci_mdio_default: davinci_mdio_default {
  190 + pinctrl-single,pins = <
  191 + AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
  192 + AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
  193 + >;
  194 + };
  195 +
  196 + mmc1_pins: pinmux_mmc1_pins {
  197 + /* eMMC */
  198 + pinctrl-single,pins = <
  199 + AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3 */
  200 + AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2 */
  201 + AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1 */
  202 + AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0 */
  203 + AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk */
  204 + AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd */
  205 + >;
  206 + };
  207 +
  208 + mmc2_pins: pinmux_mmc2_pins {
  209 + /* SD cardcage */
  210 + pinctrl-single,pins = <
  211 + AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
  212 + AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
  213 + AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
  214 + AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
  215 + AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
  216 + AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
  217 + /* card change signal for frontpanel SD cardcage */
  218 + AM33XX_IOPAD(0x890, PIN_INPUT | MUX_MODE7) /* gpmc_advn_ale.gpio2_2 */
  219 + >;
  220 + };
  221 +
  222 + lcd_pins_s0: lcd_pins_s0 {
  223 + pinctrl-single,pins = <
  224 + AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */
  225 + AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */
  226 + AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */
  227 + AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */
  228 + AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */
  229 + AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */
  230 + AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */
  231 + AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */
  232 + AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */
  233 + AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */
  234 + AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */
  235 + AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */
  236 + AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */
  237 + AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */
  238 + AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */
  239 + AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */
  240 + AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */
  241 + AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */
  242 + AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */
  243 + AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */
  244 + >;
  245 + };
  246 +
  247 + dcan0_pins: pinmux_dcan0_pins {
  248 + pinctrl-single,pins = <
  249 + AM33XX_IOPAD(0x978, PIN_OUTPUT | MUX_MODE2) /* uart1_ctsn.d_can0_tx */
  250 + AM33XX_IOPAD(0x97c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* uart1_rtsn.d_can0_rx */
  251 + >;
  252 + };
  253 +};
  254 +
  255 +&uart0 {
  256 + pinctrl-names = "default";
  257 + pinctrl-0 = <&uart0_pins>;
  258 +
  259 + rts-gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
  260 + rs485-rts-active-high;
  261 + rs485-rts-delay = <0 0>;
  262 + linux,rs485-enabled-at-boot-time;
  263 +
  264 + status = "okay";
  265 +};
  266 +
  267 +&uart1 {
  268 + pinctrl-names = "default";
  269 + pinctrl-0 = <&uart1_pins>;
  270 +
  271 + status = "okay";
  272 +};
  273 +
  274 +&uart3 {
  275 + pinctrl-names = "default";
  276 + pinctrl-0 = <&uart3_pins>;
  277 +
  278 + status = "okay";
  279 +};
  280 +
  281 +&i2c0 {
  282 + pinctrl-names = "default";
  283 + pinctrl-0 = <&i2c0_pins>;
  284 +
  285 + status = "okay";
  286 + clock-frequency = <400000>;
  287 +
  288 + tps: tps@2d {
  289 + reg = <0x2d>;
  290 + };
  291 +
  292 + m2_eeprom: m2_eeprom@50 {
  293 + compatible = "atmel,24c256";
  294 + reg = <0x50>;
  295 + status = "okay";
  296 + };
  297 +};
  298 +
  299 +&i2c1 {
  300 + pinctrl-names = "default";
  301 + pinctrl-0 = <&i2c1_pins>;
  302 +
  303 + status = "okay";
  304 + clock-frequency = <100000>;
  305 +
  306 + board_24aa025e48: board_24aa025e48@50 {
  307 + compatible = "microchip,24aa025e48";
  308 + reg = <0x50>;
  309 + };
  310 +
  311 + backplane_24aa025e48: backplane_24aa025e48@53 {
  312 + compatible = "microchip,24aa025e48";
  313 + reg = <0x53>;
  314 + };
  315 +
  316 + pca9532: pca9532@60 {
  317 + compatible = "nxp,pca9532";
  318 + reg = <0x60>;
  319 + psc0 = <0x97>;
  320 + pwm0 = <0x80>;
  321 + psc1 = <0x97>;
  322 + pwm1 = <0x10>;
  323 +
  324 + run.red@0 {
  325 + type = <PCA9532_TYPE_LED>;
  326 + };
  327 + run.green@1 {
  328 + type = <PCA9532_TYPE_LED>;
  329 + default-state = "on";
  330 + };
  331 + s2.red@2 {
  332 + type = <PCA9532_TYPE_LED>;
  333 + };
  334 + s2.green@3 {
  335 + type = <PCA9532_TYPE_LED>;
  336 + };
  337 + s1.yellow@4 {
  338 + type = <PCA9532_TYPE_LED>;
  339 + };
  340 + s1.green@5 {
  341 + type = <PCA9532_TYPE_LED>;
  342 + };
  343 + };
  344 +
  345 + pca9530: pca9530@61 {
  346 + compatible = "nxp,pca9530";
  347 + reg = <0x61>;
  348 +
  349 + tft-panel@0 {
  350 + type = <PCA9532_TYPE_LED>;
  351 + linux,default-trigger = "backlight";
  352 + default-state = "on";
  353 + };
  354 + };
  355 +
  356 + mcp79400: mcp79400@6f {
  357 + compatible = "microchip,mcp7940x";
  358 + reg = <0x6f>;
  359 + };
  360 +};
  361 +
  362 +&i2c2 {
  363 + pinctrl-names = "default";
  364 + pinctrl-0 = <&i2c2_pins>;
  365 +
  366 + status = "okay";
  367 + clock-frequency = <100000>;
  368 +};
  369 +
  370 +&spi1 {
  371 + pinctrl-names = "default";
  372 + pinctrl-0 = <&spi1_pins>;
  373 + ti,pindir-d0-out-d1-in;
  374 + status = "okay";
  375 +
  376 + cfaf240320a032t {
  377 + compatible = "orise,otm3225a";
  378 + reg = <0>;
  379 + spi-max-frequency = <1000000>;
  380 + // SPI mode 3
  381 + spi-cpol;
  382 + spi-cpha;
  383 + status = "okay";
  384 + };
  385 +};
  386 +
  387 +&usb {
  388 + status = "okay";
  389 +};
  390 +
  391 +&usb_ctrl_mod {
  392 + status = "okay";
  393 +};
  394 +
  395 +&usb0_phy {
  396 + status = "okay";
  397 +};
  398 +
  399 +&usb1_phy {
  400 + status = "okay";
  401 +};
  402 +
  403 +&usb0 {
  404 + status = "okay";
  405 +};
  406 +
  407 +&usb1 {
  408 + status = "okay";
  409 +};
  410 +
  411 +&cppi41dma {
  412 + status = "okay";
  413 +};
  414 +
  415 +/*
  416 + * Disable soc's rtc as we have no VBAT for it. This makes the board
  417 + * rtc (Microchip MCP79400) the default rtc device 'rtc0'.
  418 + */
  419 +&rtc {
  420 + status = "disabled";
  421 +};
  422 +
  423 +&lcdc {
  424 + status = "okay";
  425 +};
  426 +
  427 +&elm {
  428 + status = "okay";
  429 +};
  430 +
  431 +#include "tps65910.dtsi"
  432 +
  433 +&tps {
  434 + vcc1-supply = <&vbat>;
  435 + vcc2-supply = <&vbat>;
  436 + vcc3-supply = <&vbat>;
  437 + vcc4-supply = <&vbat>;
  438 + vcc5-supply = <&vbat>;
  439 + vcc6-supply = <&vbat>;
  440 + vcc7-supply = <&vbat>;
  441 + vccio-supply = <&vbat>;
  442 +
  443 + regulators {
  444 + vrtc_reg: regulator@0 {
  445 + regulator-name = "ldo_vrtc";
  446 + regulator-always-on;
  447 + };
  448 +
  449 + vio_reg: regulator@1 {
  450 + regulator-name = "buck_vdd_ddr";
  451 + regulator-always-on;
  452 + };
  453 +
  454 + vdd1_reg: regulator@2 {
  455 + /* VDD_MPU voltage limits */
  456 + regulator-name = "buck_vdd_mpu";
  457 + regulator-min-microvolt = <912500>;
  458 + regulator-max-microvolt = <1312500>;
  459 + regulator-boot-on;
  460 + regulator-always-on;
  461 + };
  462 +
  463 + vdd2_reg: regulator@3 {
  464 + /* VDD_CORE voltage limits */
  465 + regulator-name = "buck_vdd_core";
  466 + regulator-min-microvolt = <912500>;
  467 + regulator-max-microvolt = <1150000>;
  468 + regulator-boot-on;
  469 + regulator-always-on;
  470 + };
  471 +
  472 + vdd3_reg: regulator@4 {
  473 + regulator-name = "boost_res";
  474 + regulator-always-on;
  475 + };
  476 +
  477 + vdig1_reg: regulator@5 {
  478 + regulator-name = "ldo_vdig1";
  479 + regulator-always-on;
  480 + };
  481 +
  482 + vdig2_reg: regulator@6 {
  483 + regulator-name = "ldo_vdig2";
  484 + regulator-always-on;
  485 + };
  486 +
  487 + vpll_reg: regulator@7 {
  488 + regulator-name = "ldo_vpll";
  489 + regulator-always-on;
  490 + };
  491 +
  492 + vdac_reg: regulator@8 {
  493 + regulator-name = "ldo_vdac";
  494 + regulator-always-on;
  495 + };
  496 +
  497 + vaux1_reg: regulator@9 {
  498 + regulator-name = "ldo_vaux1";
  499 + regulator-always-on;
  500 + };
  501 +
  502 + vaux2_reg: regulator@10 {
  503 + regulator-name = "ldo_vaux2";
  504 + regulator-always-on;
  505 + };
  506 +
  507 + vaux33_reg: regulator@11 {
  508 + regulator-name = "ldo_vaux33";
  509 + regulator-always-on;
  510 + };
  511 +
  512 + vmmc_reg: regulator@12 {
  513 + regulator-name = "ldo_vmmc";
  514 + regulator-min-microvolt = <1800000>;
  515 + regulator-max-microvolt = <3300000>;
  516 + regulator-always-on;
  517 + };
  518 +
  519 + vbb_reg: regulator@13 {
  520 + regulator-name = "bat_vbb";
  521 + };
  522 + };
  523 +};
  524 +
  525 +&mac {
  526 + pinctrl-names = "default";
  527 + pinctrl-0 = <&cpsw_default>;
  528 + dual_emac; /* no switch, two distinct MACs */
  529 + status = "okay";
  530 +};
  531 +
  532 +&davinci_mdio {
  533 + pinctrl-names = "default";
  534 + pinctrl-0 = <&davinci_mdio_default>;
  535 + status = "okay";
  536 +};
  537 +
  538 +&cpsw_emac0 {
  539 + phy_id = <&davinci_mdio>, <0>;
  540 + phy-mode = "mii";
  541 + dual_emac_res_vlan = <1>;
  542 +};
  543 +
  544 +&cpsw_emac1 {
  545 + phy_id = <&davinci_mdio>, <1>;
  546 + phy-mode = "mii";
  547 + dual_emac_res_vlan = <2>;
  548 +};
  549 +
  550 +&tscadc {
  551 + status = "okay";
  552 + tsc {
  553 + ti,wires = <4>;
  554 + ti,x-plate-resistance = <200>;
  555 + ti,coordinate-readouts = <5>;
  556 + ti,wire-config = <0x01 0x10 0x22 0x33>;
  557 + ti,charge-delay = <0x400>;
  558 + };
  559 +
  560 + adc {
  561 + ti,adc-channels = <4 5 6 7>;
  562 + };
  563 +};
  564 +
  565 +&mmc1 {
  566 + status = "okay";
  567 + vmmc-supply = <&vmmc_reg>;
  568 + bus-width = <4>;
  569 + pinctrl-names = "default";
  570 + pinctrl-0 = <&mmc1_pins>;
  571 + non-removable;
  572 +};
  573 +
  574 +&mmc2 {
  575 + status = "okay";
  576 + vmmc-supply = <&vmmc_reg>;
  577 + bus-width = <4>;
  578 + pinctrl-names = "default";
  579 + pinctrl-0 = <&mmc2_pins>;
  580 + cd-gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
  581 +};
  582 +
  583 +&sham {
  584 + status = "okay";
  585 +};
  586 +
  587 +&aes {
  588 + status = "okay";
  589 +};
  590 +
  591 +&dcan0 {
  592 + status = "okay";
  593 + pinctrl-names = "default";
  594 + pinctrl-0 = <&dcan0_pins>;
  595 +};
arch/arm/mach-omap2/am33xx/Kconfig
Diff comments   View file @ 85ab045
... ... @@ -185,6 +185,15 @@
185 185 select DM_SERIAL
186 186 select DM_GPIO
187 187  
  188 +config TARGET_PDU001
  189 + bool "Support PDU001"
  190 + select DM
  191 + select DM_SERIAL
  192 + help
  193 + Support for PDU001 platform developed by EETS GmbH.
  194 + The PDU001 is a processor and display unit developed around
  195 + the Computing-Module m2 from bytes at work AG.
  196 +
188 197 endchoice
189 198  
190 199 endif
board/eets/pdu001/Kconfig
Diff comments   View file @ 85ab045
  1 +# Copyright (C) 2018 EETS GmbH - http://www.eets.ch/
  2 +#
  3 +# SPDX-License-Identifier: GPL-2.0+
  4 +#
  5 +
  6 +if TARGET_PDU001
  7 +
  8 +config SYS_BOARD
  9 + default "pdu001"
  10 +
  11 +config SYS_VENDOR
  12 + default "eets"
  13 +
  14 +config SYS_SOC
  15 + default "am33xx"
  16 +
  17 +config SYS_CONFIG_NAME
  18 + default "pdu001"
  19 +
  20 +config CONS_INDEX
  21 + int "UART used for console"
  22 + range 1 6
  23 + default 4
  24 + help
  25 + The AM335x SoC has a total of 6 UARTs (UART0 to UART5 as referenced
  26 + in documentation, etc) available to it. The best choice for the
  27 + PDU001 is UART3 as it is wired to the header K2; enter 4 here to
  28 + use UART3. UART0 is connected to the EIA-485 transceiver. If you
  29 + really need to use it, you are advised to remove the transceiver U14
  30 + from the board. UART1 is wired to the backplane and therefore
  31 + accessible from there or by the backplane connector K1 of the PDU.
  32 + Any other UART then UART3 (enter 4 here), UART1 (enter 2 here) or
  33 + UART0 (enter 1 here) are not sensible since they are not wired to
  34 + any connector and therefore difficult to access.
  35 +
  36 +choice
  37 + prompt "State of Run LED"
  38 + default PDU001_RUN_LED_RED
  39 + help
  40 + The PDU001 has a bi-color (red/green) LED labeled 'Run' which
  41 + can be used to indicate the operating state of the board. By
  42 + default it will be lit red by U-Boot. Later in the start-up
  43 + process it can be changed to green (or heartbeat or anything else)
  44 + by the kernel or some other software.
  45 +
  46 +config RUN_LED_RED
  47 + bool
  48 + prompt "Red"
  49 + help
  50 + Lit Run LED red.
  51 +
  52 +config RUN_LED_GREEN
  53 + bool
  54 + prompt "Green"
  55 + help
  56 + Lit Run LED green.
  57 +
  58 +config RUN_LED_OFF
  59 + bool
  60 + prompt "Off"
  61 + help
  62 + Do not lit Run LED.
  63 +
  64 +endchoice
  65 +
  66 +endif
board/eets/pdu001/MAINTAINERS
Diff comments   View file @ 85ab045
  1 +PDU001 BOARD
  2 +M: Felix Brack <fb@ltec.ch>
  3 +S: Maintained
  4 +F: board/eets/pdu001/
  5 +F: include/configs/pdu001.h
  6 +F: configs/am335x_pdu001_defconfig
board/eets/pdu001/Makefile
Diff comments   View file @ 85ab045
  1 +#
  2 +# Makefile
  3 +#
  4 +# Copyright (C) 2018 EETS GmbH - http://www.eets.ch/
  5 +#
  6 +# SPDX-License-Identifier: GPL-2.0+
  7 +#
  8 +
  9 +ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
  10 +obj-y := mux.o
  11 +endif
  12 +
  13 +obj-y += board.o
board/eets/pdu001/README
Diff comments   View file @ 85ab045
  1 +# Copyright (C) 2018 EETS GmbH - http://www.eets.ch/
  2 +#
  3 +# SPDX-License-Identifier: GPL-2.0+
  4 +#
  5 +
  6 +Summary
  7 +=======
  8 +
  9 +This document covers the PDU001 target.
  10 +
  11 +Hardware
  12 +========
  13 +
  14 +The PDU-001 (Processor and Display Unit) is a plugin card for 19" racks. It is
  15 +manufactured by EETS GmbH (https://www.eets.ch). The core of the board is a m2
  16 +SOM from bytes at work (https://www.bytesatwork.ch) which in turn is based on
  17 +AM3352 SOC from TI (http://www.ti.com).
  18 +
  19 +Customization
  20 +=============
  21 +
  22 +As usual the console serial interface is set by CONFIG_CONS_INDEX. Best choice
  23 +is 4 here since UART3 is wired to the connector K2.
  24 +The Run LED on the PDU-001 can be turned on red by setting CONFIG_RUN_LED_RED
  25 +or green by setting CONFIG_RUN_LED_GREEN. Setting CONFIG_RUN_LED_OFF will turn
  26 +off the Run LED.
  27 +
  28 +Booting
  29 +=======
  30 +
  31 +The system boots from either eMMC or SD card cage. It will first try to boot
  32 +from the SD card cage. If this fails (missing or unbootable SD card) it will
  33 +try to boot from the internal eMMC. The root file system is always expected to
  34 +be located in the second partition of the device (eMMC or SD card) that pro-
  35 +vided the boot loader.
board/eets/pdu001/board.c
Diff comments   View file @ 85ab045
  1 +/*
  2 + * board.c
  3 + *
  4 + * Board functions for EETS PDU001 board
  5 + *
  6 + * Copyright (C) 2018, EETS GmbH, http://www.eets.ch/
  7 + *
  8 + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  9 + *
  10 + * SPDX-License-Identifier: GPL-2.0+
  11 + */
  12 +
  13 +#include <common.h>
  14 +#include <errno.h>
  15 +#include <spl.h>
  16 +#include <i2c.h>
  17 +#include <environment.h>
  18 +#include <watchdog.h>
  19 +#include <debug_uart.h>
  20 +#include <dm/ofnode.h>
  21 +#include <power/pmic.h>
  22 +#include <power/regulator.h>
  23 +#include <asm/arch/cpu.h>
  24 +#include <asm/arch/hardware.h>
  25 +#include <asm/arch/omap.h>
  26 +#include <asm/arch/ddr_defs.h>
  27 +#include <asm/arch/clock.h>
  28 +#include <asm/arch/gpio.h>
  29 +#include <asm/arch/mmc_host_def.h>
  30 +#include <asm/arch/sys_proto.h>
  31 +#include <asm/arch/mem.h>
  32 +#include <asm/io.h>
  33 +#include <asm/emif.h>
  34 +#include <asm/gpio.h>
  35 +#include "board.h"
  36 +
  37 +DECLARE_GLOBAL_DATA_PTR;
  38 +
  39 +#define I2C_ADDR_NODE_ID 0x50
  40 +#define I2C_REG_NODE_ID_BASE 0xfa
  41 +#define NODE_ID_BYTE_COUNT 6
  42 +
  43 +#define I2C_ADDR_LEDS 0x60
  44 +#define I2C_REG_RUN_LED 0x06
  45 +#define RUN_LED_OFF 0x0
  46 +#define RUN_LED_RED 0x1
  47 +#define RUN_LED_GREEN (0x1 << 2)
  48 +
  49 +#define VDD_MPU_REGULATOR "regulator@2"
  50 +#define VDD_CORE_REGULATOR "regulator@3"
  51 +#define DEFAULT_CORE_VOLTAGE 1137500
  52 +
  53 +/*
  54 + * boot device save register
  55 + * -------------------------
  56 + * The boot device can be quired by 'spl_boot_device()' in
  57 + * 'am33xx_spl_board_init'. However it can't be saved in the u-boot
  58 + * environment here. In turn 'spl_boot_device' can't be called in
  59 + * 'board_late_init' which allows writing to u-boot environment.
  60 + * To get the boot device from 'am33xx_spl_board_init' to
  61 + * 'board_late_init' we therefore use a scratch register from the RTC.
  62 + */
  63 +#define CONFIG_SYS_RTC_SCRATCH0 0x60
  64 +#define BOOT_DEVICE_SAVE_REGISTER (RTC_BASE + CONFIG_SYS_RTC_SCRATCH0)
  65 +
  66 +#ifdef CONFIG_SPL_BUILD
  67 +static void save_boot_device(void)
  68 +{
  69 + *((u32 *)(BOOT_DEVICE_SAVE_REGISTER)) = spl_boot_device();
  70 +}
  71 +#endif
  72 +
  73 +u32 boot_device(void)
  74 +{
  75 + return *((u32 *)(BOOT_DEVICE_SAVE_REGISTER));
  76 +}
  77 +
  78 +/* Store the boot device in the environment variable 'boot_device' */
  79 +static void env_set_boot_device(void)
  80 +{
  81 + switch (boot_device()) {
  82 + case BOOT_DEVICE_MMC1: {
  83 + env_set("boot_device", "emmc");
  84 + break;
  85 + }
  86 + case BOOT_DEVICE_MMC2: {
  87 + env_set("boot_device", "sdcard");
  88 + break;
  89 + }
  90 + default: {
  91 + env_set("boot_device", "unknown");
  92 + break;
  93 + }
  94 + }
  95 +}
  96 +
  97 +static void set_run_led(struct udevice *dev)
  98 +{
  99 + int val = RUN_LED_OFF;
  100 +
  101 + if (IS_ENABLED(CONFIG_RUN_LED_RED))
  102 + val = RUN_LED_RED;
  103 + else if (IS_ENABLED(CONFIG_RUN_LED_GREEN))
  104 + val = RUN_LED_GREEN;
  105 +
  106 + dm_i2c_reg_write(dev, I2C_REG_RUN_LED, val);
  107 +}
  108 +
  109 +/* Set 'serial#' to the EUI-48 value of board node ID chip */
  110 +static void env_set_serial(struct udevice *dev)
  111 +{
  112 + int val;
  113 + char serial[2 * NODE_ID_BYTE_COUNT + 1];
  114 + int n;
  115 +
  116 + for (n = 0; n < sizeof(serial); n += 2) {
  117 + val = dm_i2c_reg_read(dev, I2C_REG_NODE_ID_BASE + n / 2);
  118 + sprintf(serial + n, "%02X", val);
  119 + }
  120 + serial[2 * NODE_ID_BYTE_COUNT] = '\0';
  121 + env_set("serial#", serial);
  122 +}
  123 +
  124 +static void set_mpu_and_core_voltage(void)
  125 +{
  126 + int mpu_vdd;
  127 + int sil_rev;
  128 + struct udevice *dev;
  129 + struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  130 +
  131 + /*
  132 + * The PDU001 (more precisely the computing module m2) uses a
  133 + * TPS65910 PMIC. For all MPU frequencies we support we use a CORE
  134 + * voltage of 1.1375V. For MPU voltage we need to switch based on
  135 + * the frequency we are running at.
  136 + */
  137 +
  138 + /*
  139 + * Depending on MPU clock and PG we will need a different VDD
  140 + * to drive at that speed.
  141 + */
  142 + sil_rev = readl(&cdev->deviceid) >> 28;
  143 + mpu_vdd = am335x_get_mpu_vdd(sil_rev, dpll_mpu_opp100.m);
  144 +
  145 + /* first update the MPU voltage */
  146 + if (!regulator_get_by_devname(VDD_MPU_REGULATOR, &dev)) {
  147 + if (regulator_set_value(dev, mpu_vdd))
  148 + debug("failed to set MPU voltage\n");
  149 + } else {
  150 + debug("invalid MPU voltage ragulator %s\n", VDD_MPU_REGULATOR);
  151 + }
  152 +
  153 + /* second update the CORE voltage */
  154 + if (!regulator_get_by_devname(VDD_CORE_REGULATOR, &dev)) {
  155 + if (regulator_set_value(dev, DEFAULT_CORE_VOLTAGE))
  156 + debug("failed to set CORE voltage\n");
  157 + } else {
  158 + debug("invalid CORE voltage ragulator %s\n",
  159 + VDD_CORE_REGULATOR);
  160 + }
  161 +}
  162 +
  163 +#ifndef CONFIG_SKIP_LOWLEVEL_INIT
  164 +static const struct ddr_data ddr2_data = {
  165 + .datardsratio0 = MT47H128M16RT25E_RD_DQS,
  166 + .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
  167 + .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
  168 +};
  169 +
  170 +static const struct cmd_control ddr2_cmd_ctrl_data = {
  171 + .cmd0csratio = MT47H128M16RT25E_RATIO,
  172 + .cmd1csratio = MT47H128M16RT25E_RATIO,
  173 + .cmd2csratio = MT47H128M16RT25E_RATIO,
  174 +};
  175 +
  176 +static const struct emif_regs ddr2_emif_reg_data = {
  177 + .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
  178 + .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
  179 + .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
  180 + .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
  181 + .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
  182 + .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
  183 +};
  184 +
  185 +#define OSC (V_OSCK / 1000000)
  186 +const struct dpll_params dpll_ddr = {
  187 + 266, OSC - 1, 1, -1, -1, -1, -1};
  188 +const struct dpll_params dpll_ddr_evm_sk = {
  189 + 303, OSC - 1, 1, -1, -1, -1, -1};
  190 +const struct dpll_params dpll_ddr_bone_black = {
  191 + 400, OSC - 1, 1, -1, -1, -1, -1};
  192 +
  193 +void am33xx_spl_board_init(void)
  194 +{
  195 + struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  196 +
  197 + /* Get the frequency */
  198 + dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
  199 +
  200 + /* Set CORE Frequencies to OPP100 */
  201 + do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
  202 +
  203 + /* Set MPU Frequency to what we detected now that voltages are set */
  204 + do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
  205 +
  206 + /* save boot device for later use by 'board_late_init' */
  207 + save_boot_device();
  208 +}
  209 +
  210 +const struct dpll_params *get_dpll_ddr_params(void)
  211 +{
  212 + enable_i2c0_pin_mux();
  213 + i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
  214 +
  215 + return &dpll_ddr;
  216 +}
  217 +
  218 +void set_mux_conf_regs(void)
  219 +{
  220 + /* done first by the ROM and afterwards by the pin controller driver */
  221 + enable_i2c0_pin_mux();
  222 +}
  223 +
  224 +const struct ctrl_ioregs ioregs = {
  225 + .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
  226 + .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
  227 + .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
  228 + .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
  229 + .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
  230 +};
  231 +
  232 +void sdram_init(void)
  233 +{
  234 + config_ddr(266, &ioregs, &ddr2_data,
  235 + &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
  236 +}
  237 +#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
  238 +
  239 +#ifdef CONFIG_DEBUG_UART
  240 +void board_debug_uart_init(void)
  241 +{
  242 + /* done by pin controller driver if not debugging */
  243 + enable_uart_pin_mux(CONFIG_DEBUG_UART_BASE);
  244 +}
  245 +#endif
  246 +
  247 +/*
  248 + * Basic board specific setup. Pinmux has been handled already.
  249 + */
  250 +int board_init(void)
  251 +{
  252 +#ifdef CONFIG_HW_WATCHDOG
  253 + hw_watchdog_init();
  254 +#endif
  255 +
  256 + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  257 + return 0;
  258 +}
  259 +
  260 +#ifdef CONFIG_BOARD_LATE_INIT
  261 +int board_late_init(void)
  262 +{
  263 + struct udevice *dev;
  264 +
  265 + set_mpu_and_core_voltage();
  266 + env_set_boot_device();
  267 +
  268 + /* second I2C bus connects to node ID and front panel LED chip */
  269 + if (!i2c_get_chip_for_busnum(1, I2C_ADDR_LEDS, 1, &dev))
  270 + set_run_led(dev);
  271 + if (!i2c_get_chip_for_busnum(1, I2C_ADDR_NODE_ID, 1, &dev))
  272 + env_set_serial(dev);
  273 +
  274 + return 0;
  275 +}
  276 +#endif
board/eets/pdu001/board.h
Diff comments   View file @ 85ab045
  1 +/*
  2 + * board.h
  3 + *
  4 + * EETS GmbH PDU001 board information header
  5 + *
  6 + * Copyright (C) 2018 EETS GmbH - http://www.eets.ch/
  7 + *
  8 + * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
  9 + *
  10 + * SPDX-License-Identifier: GPL-2.0+
  11 + */
  12 +
  13 +#ifndef _BOARD_H_
  14 +#define _BOARD_H_
  15 +
  16 +/*
  17 + * We have two pin mux functions that must exist. First we need I2C0 to
  18 + * access the TPS65910 PMIC located on the M2 computing module.
  19 + * Second, if we want low-level debugging or a early UART (ie. before the
  20 + * pin controller driver is running), we need one of the UART ports UART0 to
  21 + * UART5 (usually UART3 since it is wired to K2).
  22 + * In case of I2C0 access we explicitly don't rely on the the ROM but we could
  23 + * do so as we use the primary mode (mode 0) for I2C0.
  24 + * All other multiplexing and pin configuration is done by the DT once it
  25 + * gets parsed by the pin controller driver.
  26 + * However we relay on the ROM to configure the pins of MMC0 (eMMC) as well
  27 + * as MMC1 (microSD card-cage) since these are our boot devices.
  28 + */
  29 +void enable_uart0_pin_mux(void);
  30 +void enable_uart1_pin_mux(void);
  31 +void enable_uart2_pin_mux(void);
  32 +void enable_uart3_pin_mux(void);
  33 +void enable_uart4_pin_mux(void);
  34 +void enable_uart5_pin_mux(void);
  35 +void enable_uart_pin_mux(u32 addr);
  36 +void enable_i2c0_pin_mux(void);
  37 +
  38 +#endif
board/eets/pdu001/mux.c
Diff comments   View file @ 85ab045
  1 +/*
  2 + * mux.c
  3 + *
  4 + * Copyright (C) 2018 EETS GmbH - http://www.eets.ch/
  5 + *
  6 + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
  7 + *
  8 + * SPDX-License-Identifier: GPL-2.0+
  9 + */
  10 +
  11 +#include <common.h>
  12 +#include <asm/arch/sys_proto.h>
  13 +#include <asm/arch/hardware.h>
  14 +#include <asm/arch/mux.h>
  15 +#include <asm/io.h>
  16 +#include <i2c.h>
  17 +#include "board.h"
  18 +
  19 +static struct module_pin_mux uart0_pin_mux[] = {
  20 + {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
  21 + {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */
  22 + {-1},
  23 +};
  24 +
  25 +static struct module_pin_mux uart1_pin_mux[] = {
  26 + {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */
  27 + {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */
  28 + {-1},
  29 +};
  30 +
  31 +static struct module_pin_mux uart2_pin_mux[] = {
  32 + {OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */
  33 + {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */
  34 + {-1},
  35 +};
  36 +
  37 +static struct module_pin_mux uart3_pin_mux[] = {
  38 + {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */
  39 + {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */
  40 + {-1},
  41 +};
  42 +
  43 +static struct module_pin_mux uart4_pin_mux[] = {
  44 + {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */
  45 + {OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */
  46 + {-1},
  47 +};
  48 +
  49 +static struct module_pin_mux uart5_pin_mux[] = {
  50 + {OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */
  51 + {OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */
  52 + {-1},
  53 +};
  54 +
  55 +static struct module_pin_mux i2c0_pin_mux[] = {
  56 + {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE |
  57 + PULLUDEN | SLEWCTRL)}, /* I2C_DATA */
  58 + {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE |
  59 + PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */
  60 + {-1},
  61 +};
  62 +
  63 +void enable_uart0_pin_mux(void)
  64 +{
  65 + configure_module_pin_mux(uart0_pin_mux);
  66 +}
  67 +
  68 +void enable_uart1_pin_mux(void)
  69 +{
  70 + configure_module_pin_mux(uart1_pin_mux);
  71 +}
  72 +
  73 +void enable_uart2_pin_mux(void)
  74 +{
  75 + configure_module_pin_mux(uart2_pin_mux);
  76 +}
  77 +
  78 +void enable_uart3_pin_mux(void)
  79 +{
  80 + configure_module_pin_mux(uart3_pin_mux);
  81 +}
  82 +
  83 +void enable_uart4_pin_mux(void)
  84 +{
  85 + configure_module_pin_mux(uart4_pin_mux);
  86 +}
  87 +
  88 +void enable_uart5_pin_mux(void)
  89 +{
  90 + configure_module_pin_mux(uart5_pin_mux);
  91 +}
  92 +
  93 +void enable_uart_pin_mux(u32 addr)
  94 +{
  95 + switch (addr) {
  96 + case CONFIG_SYS_NS16550_COM1:
  97 + enable_uart0_pin_mux();
  98 + break;
  99 + case CONFIG_SYS_NS16550_COM2:
  100 + enable_uart1_pin_mux();
  101 + break;
  102 + case CONFIG_SYS_NS16550_COM3:
  103 + enable_uart2_pin_mux();
  104 + break;
  105 + case CONFIG_SYS_NS16550_COM4:
  106 + enable_uart3_pin_mux();
  107 + break;
  108 + case CONFIG_SYS_NS16550_COM5:
  109 + enable_uart4_pin_mux();
  110 + break;
  111 + case CONFIG_SYS_NS16550_COM6:
  112 + enable_uart5_pin_mux();
  113 + break;
  114 + }
  115 +}
  116 +
  117 +void enable_i2c0_pin_mux(void)
  118 +{
  119 + configure_module_pin_mux(i2c0_pin_mux);
  120 +}
configs/am335x_pdu001_defconfig
Diff comments   View file @ 85ab045
  1 +CONFIG_ARM=y
  2 +CONFIG_ARCH_OMAP2PLUS=y
  3 +CONFIG_SPL_LIBCOMMON_SUPPORT=y
  4 +CONFIG_SPL_LIBGENERIC_SUPPORT=y
  5 +CONFIG_AM33XX=y
  6 +CONFIG_TARGET_PDU001=y
  7 +CONFIG_SPL_MMC_SUPPORT=y
  8 +CONFIG_SPL_SERIAL_SUPPORT=y
  9 +CONFIG_SPL_LIBDISK_SUPPORT=y
  10 +# CONFIG_SPL_NAND_SUPPORT is not set
  11 +CONFIG_SPL_WATCHDOG_SUPPORT=y
  12 +CONFIG_SPL_FAT_SUPPORT=y
  13 +CONFIG_DEFAULT_DEVICE_TREE="am335x-pdu001"
  14 +CONFIG_LOCALVERSION="-EETS-1.0.0"
  15 +CONFIG_BOOTDELAY=1
  16 +CONFIG_SPL=y
  17 +# CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set
  18 +CONFIG_SPL_I2C_SUPPORT=y
  19 +CONFIG_SPL_YMODEM_SUPPORT=y
  20 +CONFIG_HUSH_PARSER=y
  21 +CONFIG_AUTOBOOT_KEYED=y
  22 +CONFIG_AUTOBOOT_PROMPT="Press SPACE to abort autoboot in %d seconds\n"
  23 +CONFIG_AUTOBOOT_STOP_STR=" "
  24 +CONFIG_CMD_BOOTZ=y
  25 +# CONFIG_CMD_ELF is not set
  26 +# CONFIG_CMD_XIMG is not set
  27 +CONFIG_CMD_MEMINFO=y
  28 +# CONFIG_CMD_FLASH is not set
  29 +# CONFIG_CMD_FPGA is not set
  30 +CONFIG_CMD_I2C=y
  31 +CONFIG_CMD_MMC=y
  32 +# CONFIG_CMD_NET is not set
  33 +# CONFIG_CMD_NFS is not set
  34 +CONFIG_CMD_PMIC=y
  35 +CONFIG_CMD_REGULATOR=y
  36 +CONFIG_CMD_FAT=y
  37 +CONFIG_OF_CONTROL=y
  38 +CONFIG_SPL_OF_CONTROL=y
  39 +CONFIG_OF_EMBED=y
  40 +CONFIG_SPL_DM=y
  41 +CONFIG_DM_GPIO=y
  42 +CONFIG_DM_I2C=y
  43 +CONFIG_MMC_OMAP_HS=y
  44 +CONFIG_MMC_SDHCI=y
  45 +CONFIG_PINCTRL=y
  46 +CONFIG_PINCTRL_SINGLE=y
  47 +CONFIG_DM_PMIC=y
  48 +CONFIG_DM_PMIC_TPS65910=y
  49 +CONFIG_DM_REGULATOR=y
  50 +CONFIG_SPL_DM_REGULATOR=y
  51 +CONFIG_DM_REGULATOR_FIXED=y
  52 +CONFIG_DM_REGULATOR_TPS65910=y
  53 +CONFIG_SYS_NS16550=y
  54 +# CONFIG_USE_TINY_PRINTF is not set
  55 +# CONFIG_EFI_LOADER is not set
include/configs/pdu001.h
Diff comments   View file @ 85ab045
  1 +/*
  2 + * pdu001.h
  3 + *
  4 + * Copyright (C) 2018 EETS GmbH - http://www.eets.ch/
  5 + *
  6 + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
  7 + *
  8 + * SPDX-License-Identifier: GPL-2.0+
  9 + */
  10 +
  11 +#ifndef __CONFIG_PDU001_H
  12 +#define __CONFIG_PDU001_H
  13 +
  14 +#include <configs/ti_am335x_common.h>
  15 +
  16 +/* No more need for I2C legacy compatibility for this board.
  17 + * CONFIG_DM_I2C_COMPAT is defined in ti_armv7_common.h. See the comment there
  18 + * for the right moment to delete the following line.
  19 + */
  20 +#undef CONFIG_DM_I2C_COMPAT
  21 +
  22 +/* Using 32K of volatile storage for environment */
  23 +#define CONFIG_ENV_SIZE 0x4000
  24 +
  25 +#define MACH_TYPE_PDU001 5075
  26 +#define CONFIG_MACH_TYPE MACH_TYPE_PDU001
  27 +#define CONFIG_BOARD_LATE_INIT
  28 +
  29 +/* Clock Defines */
  30 +#define V_OSCK 24000000 /* Clock output from T2 */
  31 +#define V_SCLK (V_OSCK)
  32 +
  33 +#if CONFIG_CONS_INDEX == 1
  34 + #define CONSOLE_DEV "ttyO0"
  35 +#elif CONFIG_CONS_INDEX == 2
  36 + #define CONSOLE_DEV "ttyO1"
  37 +#elif CONFIG_CONS_INDEX == 3
  38 + #define CONSOLE_DEV "ttyO2"
  39 +#elif CONFIG_CONS_INDEX == 4
  40 + #define CONSOLE_DEV "ttyO3"
  41 +#elif CONFIG_CONS_INDEX == 5
  42 + #define CONSOLE_DEV "ttyO4"
  43 +#elif CONFIG_CONS_INDEX == 6
  44 + #define CONSOLE_DEV "ttyO5"
  45 +#endif
  46 +
  47 +#define CONFIG_BOOTCOMMAND \
  48 + "run eval_boot_device;" \
  49 + "setenv bootargs console=${console} " \
  50 + "vt.global_cursor_default=0 " \
  51 + "root=/dev/mmcblk${mmc_boot}p${root_fs_partition} " \
  52 + "rootfstype=ext4 " \
  53 + "rootwait " \
  54 + "rootdelay=1;" \
  55 + "fatload mmc ${mmc_boot} ${fdtaddr} ${fdtfile};" \
  56 + "fatload mmc ${mmc_boot} ${loadaddr} ${bootfile};" \
  57 + "bootz ${loadaddr} - ${fdtaddr}"
  58 +
  59 +#ifndef CONFIG_SPL_BUILD
  60 +#define CONFIG_EXTRA_ENV_SETTINGS \
  61 + DEFAULT_LINUX_BOOT_ENV \
  62 + "fdtfile=am335x-pdu001.dtb\0" \
  63 + "bootfile=zImage\0" \
  64 + "console=" CONSOLE_DEV ",115200n8\0" \
  65 + "root_fs_partition=2\0" \
  66 + "eval_boot_device=" \
  67 + "if test $boot_device = emmc; then " \
  68 + "setenv mmc_boot 0;" \
  69 + "elif test $boot_device = sdcard; then " \
  70 + "setenv mmc_boot 1;" \
  71 + "else " \
  72 + "echo Bootdevice is neither MMC0 nor MMC1;" \
  73 + "reset;" \
  74 + "fi;" \
  75 + "\0"
  76 +#endif
  77 +
  78 +/* NS16550 Configuration */
  79 +#define CONFIG_SYS_NS16550_COM1 UART0_BASE
  80 +#define CONFIG_SYS_NS16550_COM2 UART1_BASE
  81 +#define CONFIG_SYS_NS16550_COM3 UART2_BASE
  82 +#define CONFIG_SYS_NS16550_COM4 UART3_BASE
  83 +#define CONFIG_SYS_NS16550_COM5 UART4_BASE
  84 +#define CONFIG_SYS_NS16550_COM6 UART5_BASE
  85 +#define CONFIG_BAUDRATE 115200
  86 +
  87 +#endif /* ! __CONFIG_PDU001_H */