Eric Lee / smarc-uboot

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Commit 85dd18bf4a84eba574ec29b8f7fb567f557fdbdd

Authored by Eric Lee
1 parent 98106db612
Exists in v2013.10-smarct33

Fixed RMII Clock to be Sourced From Chip Pin

Showing 1 changed file with 2 additions and 1 deletions Inline Diff

board/embedian/smarct335x/board.c
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1 /* 1 /*
2 * board.c 2 * board.c
3 * 3 *
4 * Board functions for TI AM335X based boards 4 * Board functions for TI AM335X based boards
5 * 5 *
6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ 6 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
7 * 7 *
8 * SPDX-License-Identifier: GPL-2.0+ 8 * SPDX-License-Identifier: GPL-2.0+
9 */ 9 */
10 10
11 #include <common.h> 11 #include <common.h>
12 #include <errno.h> 12 #include <errno.h>
13 #include <spl.h> 13 #include <spl.h>
14 #include <asm/arch/cpu.h> 14 #include <asm/arch/cpu.h>
15 #include <asm/arch/hardware.h> 15 #include <asm/arch/hardware.h>
16 #include <asm/arch/omap.h> 16 #include <asm/arch/omap.h>
17 #include <asm/arch/ddr_defs.h> 17 #include <asm/arch/ddr_defs.h>
18 #include <asm/arch/clock.h> 18 #include <asm/arch/clock.h>
19 #include <asm/arch/gpio.h> 19 #include <asm/arch/gpio.h>
20 #include <asm/arch/mmc_host_def.h> 20 #include <asm/arch/mmc_host_def.h>
21 #include <asm/arch/sys_proto.h> 21 #include <asm/arch/sys_proto.h>
22 #include <asm/arch/mem.h> 22 #include <asm/arch/mem.h>
23 #include <asm/io.h> 23 #include <asm/io.h>
24 #include <asm/emif.h> 24 #include <asm/emif.h>
25 #include <asm/gpio.h> 25 #include <asm/gpio.h>
26 #include <i2c.h> 26 #include <i2c.h>
27 #include <miiphy.h> 27 #include <miiphy.h>
28 #include <cpsw.h> 28 #include <cpsw.h>
29 #include <power/tps65217.h> 29 #include <power/tps65217.h>
30 #include <power/tps65910.h> 30 #include <power/tps65910.h>
31 #include "board.h" 31 #include "board.h"
32 32
33 DECLARE_GLOBAL_DATA_PTR; 33 DECLARE_GLOBAL_DATA_PTR;
34 34
35 /* GPIO that controls power to DDR on EVM-SK */ 35 /* GPIO that controls power to DDR on EVM-SK */
36 #define GPIO_DDR_VTT_EN 7 36 #define GPIO_DDR_VTT_EN 7
37 37
38 /* GPIO that controls LCD backlight PWM */ 38 /* GPIO that controls LCD backlight PWM */
39 #define GPIO_LCD_PWM_EN 7 39 #define GPIO_LCD_PWM_EN 7
40 40
41 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; 41 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
42 42
43 /* 43 /*
44 * Read header information from EEPROM into global structure. 44 * Read header information from EEPROM into global structure.
45 */ 45 */
46 static int read_eeprom(struct am335x_baseboard_id *header) 46 static int read_eeprom(struct am335x_baseboard_id *header)
47 { 47 {
48 /* Check if baseboard eeprom is available */ 48 /* Check if baseboard eeprom is available */
49 if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { 49 if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
50 puts("Could not probe the EEPROM; something fundamentally " 50 puts("Could not probe the EEPROM; something fundamentally "
51 "wrong on the I2C bus.\n"); 51 "wrong on the I2C bus.\n");
52 return -ENODEV; 52 return -ENODEV;
53 } 53 }
54 54
55 /* read the eeprom using i2c */ 55 /* read the eeprom using i2c */
56 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header, 56 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
57 sizeof(struct am335x_baseboard_id))) { 57 sizeof(struct am335x_baseboard_id))) {
58 puts("Could not read the EEPROM; something fundamentally" 58 puts("Could not read the EEPROM; something fundamentally"
59 " wrong on the I2C bus.\n"); 59 " wrong on the I2C bus.\n");
60 return -EIO; 60 return -EIO;
61 } 61 }
62 62
63 if (header->magic != 0xEE3355AA) { 63 if (header->magic != 0xEE3355AA) {
64 /* 64 /*
65 * read the eeprom using i2c again, 65 * read the eeprom using i2c again,
66 * but use only a 1 byte address 66 * but use only a 1 byte address
67 */ 67 */
68 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header, 68 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
69 sizeof(struct am335x_baseboard_id))) { 69 sizeof(struct am335x_baseboard_id))) {
70 puts("Could not read the EEPROM; something " 70 puts("Could not read the EEPROM; something "
71 "fundamentally wrong on the I2C bus.\n"); 71 "fundamentally wrong on the I2C bus.\n");
72 return -EIO; 72 return -EIO;
73 } 73 }
74 74
75 if (header->magic != 0xEE3355AA) { 75 if (header->magic != 0xEE3355AA) {
76 printf("Incorrect magic number (0x%x) in EEPROM\n", 76 printf("Incorrect magic number (0x%x) in EEPROM\n",
77 header->magic); 77 header->magic);
78 return -EINVAL; 78 return -EINVAL;
79 } 79 }
80 } 80 }
81 81
82 return 0; 82 return 0;
83 } 83 }
84 84
85 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT) 85 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
86 static const struct ddr_data ddr2_data = { 86 static const struct ddr_data ddr2_data = {
87 .datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) | 87 .datardsratio0 = ((MT47H128M16RT25E_RD_DQS<<30) |
88 (MT47H128M16RT25E_RD_DQS<<20) | 88 (MT47H128M16RT25E_RD_DQS<<20) |
89 (MT47H128M16RT25E_RD_DQS<<10) | 89 (MT47H128M16RT25E_RD_DQS<<10) |
90 (MT47H128M16RT25E_RD_DQS<<0)), 90 (MT47H128M16RT25E_RD_DQS<<0)),
91 .datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) | 91 .datawdsratio0 = ((MT47H128M16RT25E_WR_DQS<<30) |
92 (MT47H128M16RT25E_WR_DQS<<20) | 92 (MT47H128M16RT25E_WR_DQS<<20) |
93 (MT47H128M16RT25E_WR_DQS<<10) | 93 (MT47H128M16RT25E_WR_DQS<<10) |
94 (MT47H128M16RT25E_WR_DQS<<0)), 94 (MT47H128M16RT25E_WR_DQS<<0)),
95 .datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) | 95 .datawiratio0 = ((MT47H128M16RT25E_PHY_WRLVL<<30) |
96 (MT47H128M16RT25E_PHY_WRLVL<<20) | 96 (MT47H128M16RT25E_PHY_WRLVL<<20) |
97 (MT47H128M16RT25E_PHY_WRLVL<<10) | 97 (MT47H128M16RT25E_PHY_WRLVL<<10) |
98 (MT47H128M16RT25E_PHY_WRLVL<<0)), 98 (MT47H128M16RT25E_PHY_WRLVL<<0)),
99 .datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) | 99 .datagiratio0 = ((MT47H128M16RT25E_PHY_GATELVL<<30) |
100 (MT47H128M16RT25E_PHY_GATELVL<<20) | 100 (MT47H128M16RT25E_PHY_GATELVL<<20) |
101 (MT47H128M16RT25E_PHY_GATELVL<<10) | 101 (MT47H128M16RT25E_PHY_GATELVL<<10) |
102 (MT47H128M16RT25E_PHY_GATELVL<<0)), 102 (MT47H128M16RT25E_PHY_GATELVL<<0)),
103 .datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) | 103 .datafwsratio0 = ((MT47H128M16RT25E_PHY_FIFO_WE<<30) |
104 (MT47H128M16RT25E_PHY_FIFO_WE<<20) | 104 (MT47H128M16RT25E_PHY_FIFO_WE<<20) |
105 (MT47H128M16RT25E_PHY_FIFO_WE<<10) | 105 (MT47H128M16RT25E_PHY_FIFO_WE<<10) |
106 (MT47H128M16RT25E_PHY_FIFO_WE<<0)), 106 (MT47H128M16RT25E_PHY_FIFO_WE<<0)),
107 .datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) | 107 .datawrsratio0 = ((MT47H128M16RT25E_PHY_WR_DATA<<30) |
108 (MT47H128M16RT25E_PHY_WR_DATA<<20) | 108 (MT47H128M16RT25E_PHY_WR_DATA<<20) |
109 (MT47H128M16RT25E_PHY_WR_DATA<<10) | 109 (MT47H128M16RT25E_PHY_WR_DATA<<10) |
110 (MT47H128M16RT25E_PHY_WR_DATA<<0)), 110 (MT47H128M16RT25E_PHY_WR_DATA<<0)),
111 .datauserank0delay = MT47H128M16RT25E_PHY_RANK0_DELAY, 111 .datauserank0delay = MT47H128M16RT25E_PHY_RANK0_DELAY,
112 .datadldiff0 = PHY_DLL_LOCK_DIFF, 112 .datadldiff0 = PHY_DLL_LOCK_DIFF,
113 }; 113 };
114 114
115 static const struct cmd_control ddr2_cmd_ctrl_data = { 115 static const struct cmd_control ddr2_cmd_ctrl_data = {
116 .cmd0csratio = MT47H128M16RT25E_RATIO, 116 .cmd0csratio = MT47H128M16RT25E_RATIO,
117 .cmd0dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF, 117 .cmd0dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
118 .cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT, 118 .cmd0iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
119 119
120 .cmd1csratio = MT47H128M16RT25E_RATIO, 120 .cmd1csratio = MT47H128M16RT25E_RATIO,
121 .cmd1dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF, 121 .cmd1dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
122 .cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT, 122 .cmd1iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
123 123
124 .cmd2csratio = MT47H128M16RT25E_RATIO, 124 .cmd2csratio = MT47H128M16RT25E_RATIO,
125 .cmd2dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF, 125 .cmd2dldiff = MT47H128M16RT25E_DLL_LOCK_DIFF,
126 .cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT, 126 .cmd2iclkout = MT47H128M16RT25E_INVERT_CLKOUT,
127 }; 127 };
128 128
129 static const struct emif_regs ddr2_emif_reg_data = { 129 static const struct emif_regs ddr2_emif_reg_data = {
130 .sdram_config = MT47H128M16RT25E_EMIF_SDCFG, 130 .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
131 .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF, 131 .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
132 .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1, 132 .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
133 .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2, 133 .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
134 .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3, 134 .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
135 .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY, 135 .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
136 }; 136 };
137 137
138 static const struct ddr_data ddr3_data = { 138 static const struct ddr_data ddr3_data = {
139 .datardsratio0 = MT41J128MJT125_RD_DQS, 139 .datardsratio0 = MT41J128MJT125_RD_DQS,
140 .datawdsratio0 = MT41J128MJT125_WR_DQS, 140 .datawdsratio0 = MT41J128MJT125_WR_DQS,
141 .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE, 141 .datafwsratio0 = MT41J128MJT125_PHY_FIFO_WE,
142 .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA, 142 .datawrsratio0 = MT41J128MJT125_PHY_WR_DATA,
143 .datadldiff0 = PHY_DLL_LOCK_DIFF, 143 .datadldiff0 = PHY_DLL_LOCK_DIFF,
144 }; 144 };
145 145
146 static const struct ddr_data ddr3_beagleblack_data = { 146 static const struct ddr_data ddr3_beagleblack_data = {
147 .datardsratio0 = MT41K256M16HA125E_RD_DQS, 147 .datardsratio0 = MT41K256M16HA125E_RD_DQS,
148 .datawdsratio0 = MT41K256M16HA125E_WR_DQS, 148 .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
149 .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, 149 .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
150 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, 150 .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
151 .datadldiff0 = PHY_DLL_LOCK_DIFF, 151 .datadldiff0 = PHY_DLL_LOCK_DIFF,
152 }; 152 };
153 153
154 static const struct ddr_data ddr3_evm_data = { 154 static const struct ddr_data ddr3_evm_data = {
155 .datardsratio0 = MT41J512M8RH125_RD_DQS, 155 .datardsratio0 = MT41J512M8RH125_RD_DQS,
156 .datawdsratio0 = MT41J512M8RH125_WR_DQS, 156 .datawdsratio0 = MT41J512M8RH125_WR_DQS,
157 .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE, 157 .datafwsratio0 = MT41J512M8RH125_PHY_FIFO_WE,
158 .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA, 158 .datawrsratio0 = MT41J512M8RH125_PHY_WR_DATA,
159 .datadldiff0 = PHY_DLL_LOCK_DIFF, 159 .datadldiff0 = PHY_DLL_LOCK_DIFF,
160 }; 160 };
161 161
162 static const struct cmd_control ddr3_cmd_ctrl_data = { 162 static const struct cmd_control ddr3_cmd_ctrl_data = {
163 .cmd0csratio = MT41J128MJT125_RATIO, 163 .cmd0csratio = MT41J128MJT125_RATIO,
164 .cmd0dldiff = MT41J128MJT125_DLL_LOCK_DIFF, 164 .cmd0dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
165 .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT, 165 .cmd0iclkout = MT41J128MJT125_INVERT_CLKOUT,
166 166
167 .cmd1csratio = MT41J128MJT125_RATIO, 167 .cmd1csratio = MT41J128MJT125_RATIO,
168 .cmd1dldiff = MT41J128MJT125_DLL_LOCK_DIFF, 168 .cmd1dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
169 .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT, 169 .cmd1iclkout = MT41J128MJT125_INVERT_CLKOUT,
170 170
171 .cmd2csratio = MT41J128MJT125_RATIO, 171 .cmd2csratio = MT41J128MJT125_RATIO,
172 .cmd2dldiff = MT41J128MJT125_DLL_LOCK_DIFF, 172 .cmd2dldiff = MT41J128MJT125_DLL_LOCK_DIFF,
173 .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT, 173 .cmd2iclkout = MT41J128MJT125_INVERT_CLKOUT,
174 }; 174 };
175 175
176 static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = { 176 static const struct cmd_control ddr3_beagleblack_cmd_ctrl_data = {
177 .cmd0csratio = MT41K256M16HA125E_RATIO, 177 .cmd0csratio = MT41K256M16HA125E_RATIO,
178 .cmd0dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF, 178 .cmd0dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
179 .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 179 .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
180 180
181 .cmd1csratio = MT41K256M16HA125E_RATIO, 181 .cmd1csratio = MT41K256M16HA125E_RATIO,
182 .cmd1dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF, 182 .cmd1dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
183 .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 183 .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
184 184
185 .cmd2csratio = MT41K256M16HA125E_RATIO, 185 .cmd2csratio = MT41K256M16HA125E_RATIO,
186 .cmd2dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF, 186 .cmd2dldiff = MT41K256M16HA125E_DLL_LOCK_DIFF,
187 .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 187 .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
188 }; 188 };
189 189
190 static const struct cmd_control ddr3_evm_cmd_ctrl_data = { 190 static const struct cmd_control ddr3_evm_cmd_ctrl_data = {
191 .cmd0csratio = MT41J512M8RH125_RATIO, 191 .cmd0csratio = MT41J512M8RH125_RATIO,
192 .cmd0dldiff = MT41J512M8RH125_DLL_LOCK_DIFF, 192 .cmd0dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
193 .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT, 193 .cmd0iclkout = MT41J512M8RH125_INVERT_CLKOUT,
194 194
195 .cmd1csratio = MT41J512M8RH125_RATIO, 195 .cmd1csratio = MT41J512M8RH125_RATIO,
196 .cmd1dldiff = MT41J512M8RH125_DLL_LOCK_DIFF, 196 .cmd1dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
197 .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT, 197 .cmd1iclkout = MT41J512M8RH125_INVERT_CLKOUT,
198 198
199 .cmd2csratio = MT41J512M8RH125_RATIO, 199 .cmd2csratio = MT41J512M8RH125_RATIO,
200 .cmd2dldiff = MT41J512M8RH125_DLL_LOCK_DIFF, 200 .cmd2dldiff = MT41J512M8RH125_DLL_LOCK_DIFF,
201 .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT, 201 .cmd2iclkout = MT41J512M8RH125_INVERT_CLKOUT,
202 }; 202 };
203 203
204 static struct emif_regs ddr3_emif_reg_data = { 204 static struct emif_regs ddr3_emif_reg_data = {
205 .sdram_config = MT41J128MJT125_EMIF_SDCFG, 205 .sdram_config = MT41J128MJT125_EMIF_SDCFG,
206 .ref_ctrl = MT41J128MJT125_EMIF_SDREF, 206 .ref_ctrl = MT41J128MJT125_EMIF_SDREF,
207 .sdram_tim1 = MT41J128MJT125_EMIF_TIM1, 207 .sdram_tim1 = MT41J128MJT125_EMIF_TIM1,
208 .sdram_tim2 = MT41J128MJT125_EMIF_TIM2, 208 .sdram_tim2 = MT41J128MJT125_EMIF_TIM2,
209 .sdram_tim3 = MT41J128MJT125_EMIF_TIM3, 209 .sdram_tim3 = MT41J128MJT125_EMIF_TIM3,
210 .zq_config = MT41J128MJT125_ZQ_CFG, 210 .zq_config = MT41J128MJT125_ZQ_CFG,
211 .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY | 211 .emif_ddr_phy_ctlr_1 = MT41J128MJT125_EMIF_READ_LATENCY |
212 PHY_EN_DYN_PWRDN, 212 PHY_EN_DYN_PWRDN,
213 }; 213 };
214 214
215 static struct emif_regs ddr3_beagleblack_emif_reg_data = { 215 static struct emif_regs ddr3_beagleblack_emif_reg_data = {
216 .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, 216 .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
217 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, 217 .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
218 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, 218 .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
219 .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, 219 .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
220 .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, 220 .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
221 .zq_config = MT41K256M16HA125E_ZQ_CFG, 221 .zq_config = MT41K256M16HA125E_ZQ_CFG,
222 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY, 222 .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
223 }; 223 };
224 224
225 static struct emif_regs ddr3_evm_emif_reg_data = { 225 static struct emif_regs ddr3_evm_emif_reg_data = {
226 .sdram_config = MT41J512M8RH125_EMIF_SDCFG, 226 .sdram_config = MT41J512M8RH125_EMIF_SDCFG,
227 .ref_ctrl = MT41J512M8RH125_EMIF_SDREF, 227 .ref_ctrl = MT41J512M8RH125_EMIF_SDREF,
228 .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1, 228 .sdram_tim1 = MT41J512M8RH125_EMIF_TIM1,
229 .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2, 229 .sdram_tim2 = MT41J512M8RH125_EMIF_TIM2,
230 .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3, 230 .sdram_tim3 = MT41J512M8RH125_EMIF_TIM3,
231 .zq_config = MT41J512M8RH125_ZQ_CFG, 231 .zq_config = MT41J512M8RH125_ZQ_CFG,
232 .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY | 232 .emif_ddr_phy_ctlr_1 = MT41J512M8RH125_EMIF_READ_LATENCY |
233 PHY_EN_DYN_PWRDN, 233 PHY_EN_DYN_PWRDN,
234 }; 234 };
235 235
236 #ifdef CONFIG_SPL_OS_BOOT 236 #ifdef CONFIG_SPL_OS_BOOT
237 int spl_start_uboot(void) 237 int spl_start_uboot(void)
238 { 238 {
239 /* break into full u-boot on 'c' */ 239 /* break into full u-boot on 'c' */
240 return (serial_tstc() && serial_getc() == 'c'); 240 return (serial_tstc() && serial_getc() == 'c');
241 } 241 }
242 #endif 242 #endif
243 243
244 #define OSC (V_OSCK/1000000) 244 #define OSC (V_OSCK/1000000)
245 const struct dpll_params dpll_ddr = { 245 const struct dpll_params dpll_ddr = {
246 266, OSC-1, 1, -1, -1, -1, -1}; 246 266, OSC-1, 1, -1, -1, -1, -1};
247 const struct dpll_params dpll_ddr_evm_sk = { 247 const struct dpll_params dpll_ddr_evm_sk = {
248 303, OSC-1, 1, -1, -1, -1, -1}; 248 303, OSC-1, 1, -1, -1, -1, -1};
249 const struct dpll_params dpll_ddr_bone_black = { 249 const struct dpll_params dpll_ddr_bone_black = {
250 400, OSC-1, 1, -1, -1, -1, -1}; 250 400, OSC-1, 1, -1, -1, -1, -1};
251 const struct dpll_params dpll_ddr_smarc_t335x = { 251 const struct dpll_params dpll_ddr_smarc_t335x = {
252 400, OSC-1, 1, -1, -1, -1, -1}; 252 400, OSC-1, 1, -1, -1, -1, -1};
253 253
254 void am33xx_spl_board_init(void) 254 void am33xx_spl_board_init(void)
255 { 255 {
256 struct am335x_baseboard_id header; 256 struct am335x_baseboard_id header;
257 int mpu_vdd; 257 int mpu_vdd;
258 258
259 if (read_eeprom(&header) < 0) 259 if (read_eeprom(&header) < 0)
260 puts("Could not get board ID.\n"); 260 puts("Could not get board ID.\n");
261 261
262 /* Get the frequency */ 262 /* Get the frequency */
263 dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); 263 dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
264 264
265 if (board_is_bone(&header) || board_is_bone_lt(&header) || board_is_smarc_t335x(&header) || board_is_smarc_t335x_1g(&header)) { 265 if (board_is_bone(&header) || board_is_bone_lt(&header) || board_is_smarc_t335x(&header) || board_is_smarc_t335x_1g(&header)) {
266 /* BeagleBone and SMARC T335X PMIC Code */ 266 /* BeagleBone and SMARC T335X PMIC Code */
267 int usb_cur_lim; 267 int usb_cur_lim;
268 268
269 /* 269 /*
270 * Only perform PMIC configurations if board rev > A1 270 * Only perform PMIC configurations if board rev > A1
271 * on Beaglebone White 271 * on Beaglebone White
272 */ 272 */
273 if (board_is_bone(&header) && !strncmp(header.version, 273 if (board_is_bone(&header) && !strncmp(header.version,
274 "00A1", 4)) 274 "00A1", 4))
275 return; 275 return;
276 276
277 if (i2c_probe(TPS65217_CHIP_PM)) 277 if (i2c_probe(TPS65217_CHIP_PM))
278 return; 278 return;
279 279
280 /* 280 /*
281 * On Beaglebone White we need to ensure we have AC power 281 * On Beaglebone White we need to ensure we have AC power
282 * before increasing the frequency. 282 * before increasing the frequency.
283 */ 283 */
284 if (board_is_bone(&header)) { 284 if (board_is_bone(&header)) {
285 uchar pmic_status_reg; 285 uchar pmic_status_reg;
286 if (tps65217_reg_read(TPS65217_STATUS, 286 if (tps65217_reg_read(TPS65217_STATUS,
287 &pmic_status_reg)) 287 &pmic_status_reg))
288 return; 288 return;
289 if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) { 289 if (!(pmic_status_reg & TPS65217_PWR_SRC_AC_BITMASK)) {
290 puts("No AC power, disabling frequency switch\n"); 290 puts("No AC power, disabling frequency switch\n");
291 return; 291 return;
292 } 292 }
293 } 293 }
294 294
295 /* 295 /*
296 * Override what we have detected since we know if we have 296 * Override what we have detected since we know if we have
297 * a Beaglebone Black or SMARC T335X 1G they support 1GHz. 297 * a Beaglebone Black or SMARC T335X 1G they support 1GHz.
298 */ 298 */
299 if ((board_is_bone_lt(&header) || board_is_smarc_t335x_1g(&header))) 299 if ((board_is_bone_lt(&header) || board_is_smarc_t335x_1g(&header)))
300 dpll_mpu_opp100.m = MPUPLL_M_1000; 300 dpll_mpu_opp100.m = MPUPLL_M_1000;
301 301
302 /* 302 /*
303 * Increase USB current limit to 1300mA or 1800mA and set 303 * Increase USB current limit to 1300mA or 1800mA and set
304 * the MPU voltage controller as needed. 304 * the MPU voltage controller as needed.
305 */ 305 */
306 if (dpll_mpu_opp100.m == MPUPLL_M_1000) { 306 if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
307 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA; 307 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
308 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV; 308 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
309 } else { 309 } else {
310 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA; 310 usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
311 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV; 311 mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
312 } 312 }
313 313
314 if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE, 314 if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
315 TPS65217_POWER_PATH, 315 TPS65217_POWER_PATH,
316 usb_cur_lim, 316 usb_cur_lim,
317 TPS65217_USB_INPUT_CUR_LIMIT_MASK)) 317 TPS65217_USB_INPUT_CUR_LIMIT_MASK))
318 puts("tps65217_reg_write failure\n"); 318 puts("tps65217_reg_write failure\n");
319 319
320 /* Set DCDC3 (CORE) voltage to 1.125V */ 320 /* Set DCDC3 (CORE) voltage to 1.125V */
321 if (tps65217_voltage_update(TPS65217_DEFDCDC3, 321 if (tps65217_voltage_update(TPS65217_DEFDCDC3,
322 TPS65217_DCDC_VOLT_SEL_1125MV)) { 322 TPS65217_DCDC_VOLT_SEL_1125MV)) {
323 puts("tps65217_voltage_update failure\n"); 323 puts("tps65217_voltage_update failure\n");
324 return; 324 return;
325 } 325 }
326 326
327 /* Set CORE Frequencies to OPP100 */ 327 /* Set CORE Frequencies to OPP100 */
328 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); 328 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
329 329
330 /* Set DCDC2 (MPU) voltage */ 330 /* Set DCDC2 (MPU) voltage */
331 if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) { 331 if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
332 puts("tps65217_voltage_update failure\n"); 332 puts("tps65217_voltage_update failure\n");
333 return; 333 return;
334 } 334 }
335 335
336 /* 336 /*
337 * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone. 337 * Set LDO3, LDO4 output voltage to 3.3V for Beaglebone.
338 * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black and SMARC T335X. 338 * Set LDO3 to 1.8V and LDO4 to 3.3V for Beaglebone Black and SMARC T335X.
339 */ 339 */
340 if (board_is_bone(&header)) { 340 if (board_is_bone(&header)) {
341 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, 341 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
342 TPS65217_DEFLS1, 342 TPS65217_DEFLS1,
343 TPS65217_LDO_VOLTAGE_OUT_3_3, 343 TPS65217_LDO_VOLTAGE_OUT_3_3,
344 TPS65217_LDO_MASK)) 344 TPS65217_LDO_MASK))
345 puts("tps65217_reg_write failure\n"); 345 puts("tps65217_reg_write failure\n");
346 } else { 346 } else {
347 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, 347 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
348 TPS65217_DEFLS1, 348 TPS65217_DEFLS1,
349 TPS65217_LDO_VOLTAGE_OUT_1_8, 349 TPS65217_LDO_VOLTAGE_OUT_1_8,
350 TPS65217_LDO_MASK)) 350 TPS65217_LDO_MASK))
351 puts("tps65217_reg_write failure\n"); 351 puts("tps65217_reg_write failure\n");
352 } 352 }
353 353
354 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2, 354 if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
355 TPS65217_DEFLS2, 355 TPS65217_DEFLS2,
356 TPS65217_LDO_VOLTAGE_OUT_3_3, 356 TPS65217_LDO_VOLTAGE_OUT_3_3,
357 TPS65217_LDO_MASK)) 357 TPS65217_LDO_MASK))
358 puts("tps65217_reg_write failure\n"); 358 puts("tps65217_reg_write failure\n");
359 } else { 359 } else {
360 int sil_rev; 360 int sil_rev;
361 361
362 /* 362 /*
363 * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all 363 * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all
364 * MPU frequencies we support we use a CORE voltage of 364 * MPU frequencies we support we use a CORE voltage of
365 * 1.1375V. For MPU voltage we need to switch based on 365 * 1.1375V. For MPU voltage we need to switch based on
366 * the frequency we are running at. 366 * the frequency we are running at.
367 */ 367 */
368 if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) 368 if (i2c_probe(TPS65910_CTRL_I2C_ADDR))
369 return; 369 return;
370 370
371 /* 371 /*
372 * Depending on MPU clock and PG we will need a different 372 * Depending on MPU clock and PG we will need a different
373 * VDD to drive at that speed. 373 * VDD to drive at that speed.
374 */ 374 */
375 sil_rev = readl(&cdev->deviceid) >> 28; 375 sil_rev = readl(&cdev->deviceid) >> 28;
376 mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, 376 mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev,
377 dpll_mpu_opp100.m); 377 dpll_mpu_opp100.m);
378 378
379 /* Tell the TPS65910 to use i2c */ 379 /* Tell the TPS65910 to use i2c */
380 tps65910_set_i2c_control(); 380 tps65910_set_i2c_control();
381 381
382 /* First update MPU voltage. */ 382 /* First update MPU voltage. */
383 if (tps65910_voltage_update(MPU, mpu_vdd)) 383 if (tps65910_voltage_update(MPU, mpu_vdd))
384 return; 384 return;
385 385
386 /* Second, update the CORE voltage. */ 386 /* Second, update the CORE voltage. */
387 if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3)) 387 if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3))
388 return; 388 return;
389 389
390 /* Set CORE Frequencies to OPP100 */ 390 /* Set CORE Frequencies to OPP100 */
391 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); 391 do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
392 } 392 }
393 393
394 /* Set MPU Frequency to what we detected now that voltages are set */ 394 /* Set MPU Frequency to what we detected now that voltages are set */
395 do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); 395 do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
396 } 396 }
397 397
398 const struct dpll_params *get_dpll_ddr_params(void) 398 const struct dpll_params *get_dpll_ddr_params(void)
399 { 399 {
400 struct am335x_baseboard_id header; 400 struct am335x_baseboard_id header;
401 401
402 enable_i2c0_pin_mux(); 402 enable_i2c0_pin_mux();
403 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 403 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
404 if (read_eeprom(&header) < 0) 404 if (read_eeprom(&header) < 0)
405 puts("Could not get board ID.\n"); 405 puts("Could not get board ID.\n");
406 406
407 if (board_is_evm_sk(&header)) 407 if (board_is_evm_sk(&header))
408 return &dpll_ddr_evm_sk; 408 return &dpll_ddr_evm_sk;
409 else if (board_is_bone_lt(&header)) 409 else if (board_is_bone_lt(&header))
410 return &dpll_ddr_bone_black; 410 return &dpll_ddr_bone_black;
411 else if (board_is_smarc_t335x(&header) || board_is_smarc_t335x_1g(&header)) 411 else if (board_is_smarc_t335x(&header) || board_is_smarc_t335x_1g(&header))
412 return &dpll_ddr_smarc_t335x; 412 return &dpll_ddr_smarc_t335x;
413 else if (board_is_evm_15_or_later(&header)) 413 else if (board_is_evm_15_or_later(&header))
414 return &dpll_ddr_evm_sk; 414 return &dpll_ddr_evm_sk;
415 else 415 else
416 return &dpll_ddr; 416 return &dpll_ddr;
417 } 417 }
418 418
419 void set_uart_mux_conf(void) 419 void set_uart_mux_conf(void)
420 { 420 {
421 #ifdef CONFIG_SERIAL1 421 #ifdef CONFIG_SERIAL1
422 enable_uart0_pin_mux(); 422 enable_uart0_pin_mux();
423 #endif /* CONFIG_SERIAL1 */ 423 #endif /* CONFIG_SERIAL1 */
424 #ifdef CONFIG_SERIAL2 424 #ifdef CONFIG_SERIAL2
425 enable_uart1_pin_mux(); 425 enable_uart1_pin_mux();
426 #endif /* CONFIG_SERIAL2 */ 426 #endif /* CONFIG_SERIAL2 */
427 #ifdef CONFIG_SERIAL3 427 #ifdef CONFIG_SERIAL3
428 enable_uart2_pin_mux(); 428 enable_uart2_pin_mux();
429 #endif /* CONFIG_SERIAL3 */ 429 #endif /* CONFIG_SERIAL3 */
430 #ifdef CONFIG_SERIAL4 430 #ifdef CONFIG_SERIAL4
431 enable_uart3_pin_mux(); 431 enable_uart3_pin_mux();
432 #endif /* CONFIG_SERIAL4 */ 432 #endif /* CONFIG_SERIAL4 */
433 #ifdef CONFIG_SERIAL5 433 #ifdef CONFIG_SERIAL5
434 enable_uart4_pin_mux(); 434 enable_uart4_pin_mux();
435 #endif /* CONFIG_SERIAL5 */ 435 #endif /* CONFIG_SERIAL5 */
436 #ifdef CONFIG_SERIAL6 436 #ifdef CONFIG_SERIAL6
437 enable_uart5_pin_mux(); 437 enable_uart5_pin_mux();
438 #endif /* CONFIG_SERIAL6 */ 438 #endif /* CONFIG_SERIAL6 */
439 } 439 }
440 440
441 void set_mux_conf_regs(void) 441 void set_mux_conf_regs(void)
442 { 442 {
443 __maybe_unused struct am335x_baseboard_id header; 443 __maybe_unused struct am335x_baseboard_id header;
444 444
445 if (read_eeprom(&header) < 0) 445 if (read_eeprom(&header) < 0)
446 puts("Could not get board ID.\n"); 446 puts("Could not get board ID.\n");
447 447
448 enable_board_pin_mux(&header); 448 enable_board_pin_mux(&header);
449 } 449 }
450 450
451 void sdram_init(void) 451 void sdram_init(void)
452 { 452 {
453 __maybe_unused struct am335x_baseboard_id header; 453 __maybe_unused struct am335x_baseboard_id header;
454 454
455 if (read_eeprom(&header) < 0) 455 if (read_eeprom(&header) < 0)
456 puts("Could not get board ID.\n"); 456 puts("Could not get board ID.\n");
457 457
458 if (board_is_evm_sk(&header)) { 458 if (board_is_evm_sk(&header)) {
459 /* 459 /*
460 * EVM SK 1.2A and later use gpio0_7 to enable DDR3. 460 * EVM SK 1.2A and later use gpio0_7 to enable DDR3.
461 * This is safe enough to do on older revs. 461 * This is safe enough to do on older revs.
462 */ 462 */
463 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); 463 gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
464 gpio_direction_output(GPIO_DDR_VTT_EN, 1); 464 gpio_direction_output(GPIO_DDR_VTT_EN, 1);
465 } 465 }
466 466
467 if (board_is_evm_sk(&header)) 467 if (board_is_evm_sk(&header))
468 config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data, 468 config_ddr(303, MT41J128MJT125_IOCTRL_VALUE, &ddr3_data,
469 &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0); 469 &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
470 else if (board_is_bone_lt(&header)) 470 else if (board_is_bone_lt(&header))
471 config_ddr(400, MT41K256M16HA125E_IOCTRL_VALUE, 471 config_ddr(400, MT41K256M16HA125E_IOCTRL_VALUE,
472 &ddr3_beagleblack_data, 472 &ddr3_beagleblack_data,
473 &ddr3_beagleblack_cmd_ctrl_data, 473 &ddr3_beagleblack_cmd_ctrl_data,
474 &ddr3_beagleblack_emif_reg_data, 0); 474 &ddr3_beagleblack_emif_reg_data, 0);
475 else if (board_is_smarc_t335x(&header) || board_is_smarc_t335x_1g(&header)) { 475 else if (board_is_smarc_t335x(&header) || board_is_smarc_t335x_1g(&header)) {
476 /* 476 /*
477 * SMARC T335X rev. 00B0 and later use gpio0_7 as LCD backlight PWM. 477 * SMARC T335X rev. 00B0 and later use gpio0_7 as LCD backlight PWM.
478 * This is safe enough to do on older revs. 478 * This is safe enough to do on older revs.
479 */ 479 */
480 gpio_request(GPIO_LCD_PWM_EN, "lcd_pwm_en"); 480 gpio_request(GPIO_LCD_PWM_EN, "lcd_pwm_en");
481 gpio_direction_output(GPIO_LCD_PWM_EN, 1); 481 gpio_direction_output(GPIO_LCD_PWM_EN, 1);
482 config_ddr(400, MT41K256M16HA125E_IOCTRL_VALUE, 482 config_ddr(400, MT41K256M16HA125E_IOCTRL_VALUE,
483 &ddr3_beagleblack_data, 483 &ddr3_beagleblack_data,
484 &ddr3_beagleblack_cmd_ctrl_data, 484 &ddr3_beagleblack_cmd_ctrl_data,
485 &ddr3_beagleblack_emif_reg_data, 0); 485 &ddr3_beagleblack_emif_reg_data, 0);
486 puts("Set DDR3 to 800MHz.\n");
486 } 487 }
487 else if (board_is_evm_15_or_later(&header)) 488 else if (board_is_evm_15_or_later(&header))
488 config_ddr(303, MT41J512M8RH125_IOCTRL_VALUE, &ddr3_evm_data, 489 config_ddr(303, MT41J512M8RH125_IOCTRL_VALUE, &ddr3_evm_data,
489 &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0); 490 &ddr3_evm_cmd_ctrl_data, &ddr3_evm_emif_reg_data, 0);
490 else 491 else
491 config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data, 492 config_ddr(266, MT47H128M16RT25E_IOCTRL_VALUE, &ddr2_data,
492 &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0); 493 &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
493 } 494 }
494 #endif 495 #endif
495 496
496 /* 497 /*
497 * Basic board specific setup. Pinmux has been handled already. 498 * Basic board specific setup. Pinmux has been handled already.
498 */ 499 */
499 int board_init(void) 500 int board_init(void)
500 { 501 {
501 #ifdef CONFIG_NOR 502 #ifdef CONFIG_NOR
502 const u32 gpmc_nor[GPMC_MAX_REG] = { STNOR_GPMC_CONFIG1, 503 const u32 gpmc_nor[GPMC_MAX_REG] = { STNOR_GPMC_CONFIG1,
503 STNOR_GPMC_CONFIG2, STNOR_GPMC_CONFIG3, STNOR_GPMC_CONFIG4, 504 STNOR_GPMC_CONFIG2, STNOR_GPMC_CONFIG3, STNOR_GPMC_CONFIG4,
504 STNOR_GPMC_CONFIG5, STNOR_GPMC_CONFIG6, STNOR_GPMC_CONFIG7 }; 505 STNOR_GPMC_CONFIG5, STNOR_GPMC_CONFIG6, STNOR_GPMC_CONFIG7 };
505 #endif 506 #endif
506 507
507 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 508 gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
508 509
509 gpmc_init(); 510 gpmc_init();
510 511
511 #ifdef CONFIG_NOR 512 #ifdef CONFIG_NOR
512 /* Reconfigure CS0 for NOR instead of NAND. */ 513 /* Reconfigure CS0 for NOR instead of NAND. */
513 enable_gpmc_cs_config(gpmc_nor, &gpmc_cfg->cs[0], 514 enable_gpmc_cs_config(gpmc_nor, &gpmc_cfg->cs[0],
514 CONFIG_SYS_FLASH_BASE, GPMC_SIZE_16M); 515 CONFIG_SYS_FLASH_BASE, GPMC_SIZE_16M);
515 #endif 516 #endif
516 517
517 return 0; 518 return 0;
518 } 519 }
519 520
520 #ifdef CONFIG_BOARD_LATE_INIT 521 #ifdef CONFIG_BOARD_LATE_INIT
521 int board_late_init(void) 522 int board_late_init(void)
522 { 523 {
523 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 524 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
524 char safe_string[HDR_NAME_LEN + 1]; 525 char safe_string[HDR_NAME_LEN + 1];
525 struct am335x_baseboard_id header; 526 struct am335x_baseboard_id header;
526 527
527 if (read_eeprom(&header) < 0) 528 if (read_eeprom(&header) < 0)
528 puts("Could not get board ID.\n"); 529 puts("Could not get board ID.\n");
529 530
530 /* Now set variables based on the header. */ 531 /* Now set variables based on the header. */
531 strncpy(safe_string, (char *)header.name, sizeof(header.name)); 532 strncpy(safe_string, (char *)header.name, sizeof(header.name));
532 safe_string[sizeof(header.name)] = 0; 533 safe_string[sizeof(header.name)] = 0;
533 setenv("board_name", safe_string); 534 setenv("board_name", safe_string);
534 535
535 strncpy(safe_string, (char *)header.version, sizeof(header.version)); 536 strncpy(safe_string, (char *)header.version, sizeof(header.version));
536 safe_string[sizeof(header.version)] = 0; 537 safe_string[sizeof(header.version)] = 0;
537 setenv("board_rev", safe_string); 538 setenv("board_rev", safe_string);
538 #endif 539 #endif
539 540
540 return 0; 541 return 0;
541 } 542 }
542 #endif 543 #endif
543 544
544 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ 545 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
545 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) 546 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
546 static void cpsw_control(int enabled) 547 static void cpsw_control(int enabled)
547 { 548 {
548 /* VTP can be added here */ 549 /* VTP can be added here */
549 550
550 return; 551 return;
551 } 552 }
552 553
553 static struct cpsw_slave_data cpsw_slaves[] = { 554 static struct cpsw_slave_data cpsw_slaves[] = {
554 { 555 {
555 .slave_reg_ofs = 0x208, 556 .slave_reg_ofs = 0x208,
556 .sliver_reg_ofs = 0xd80, 557 .sliver_reg_ofs = 0xd80,
557 .phy_id = 0, 558 .phy_id = 0,
558 }, 559 },
559 { 560 {
560 .slave_reg_ofs = 0x308, 561 .slave_reg_ofs = 0x308,
561 .sliver_reg_ofs = 0xdc0, 562 .sliver_reg_ofs = 0xdc0,
562 .phy_id = 1, 563 .phy_id = 1,
563 }, 564 },
564 }; 565 };
565 566
566 static struct cpsw_platform_data cpsw_data = { 567 static struct cpsw_platform_data cpsw_data = {
567 .mdio_base = CPSW_MDIO_BASE, 568 .mdio_base = CPSW_MDIO_BASE,
568 .cpsw_base = CPSW_BASE, 569 .cpsw_base = CPSW_BASE,
569 .mdio_div = 0xff, 570 .mdio_div = 0xff,
570 .channels = 8, 571 .channels = 8,
571 .cpdma_reg_ofs = 0x800, 572 .cpdma_reg_ofs = 0x800,
572 .slaves = 1, 573 .slaves = 1,
573 .slave_data = cpsw_slaves, 574 .slave_data = cpsw_slaves,
574 .ale_reg_ofs = 0xd00, 575 .ale_reg_ofs = 0xd00,
575 .ale_entries = 1024, 576 .ale_entries = 1024,
576 .host_port_reg_ofs = 0x108, 577 .host_port_reg_ofs = 0x108,
577 .hw_stats_reg_ofs = 0x900, 578 .hw_stats_reg_ofs = 0x900,
578 .bd_ram_ofs = 0x2000, 579 .bd_ram_ofs = 0x2000,
579 .mac_control = (1 << 5), 580 .mac_control = (1 << 5),
580 .control = cpsw_control, 581 .control = cpsw_control,
581 .host_port_num = 0, 582 .host_port_num = 0,
582 .version = CPSW_CTRL_VERSION_2, 583 .version = CPSW_CTRL_VERSION_2,
583 }; 584 };
584 #endif 585 #endif
585 586
586 #if defined(CONFIG_DRIVER_TI_CPSW) || \ 587 #if defined(CONFIG_DRIVER_TI_CPSW) || \
587 (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) 588 (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET))
588 int board_eth_init(bd_t *bis) 589 int board_eth_init(bd_t *bis)
589 { 590 {
590 int rv, n = 0; 591 int rv, n = 0;
591 uint8_t mac_addr[6]; 592 uint8_t mac_addr[6];
592 uint32_t mac_hi, mac_lo; 593 uint32_t mac_hi, mac_lo;
593 __maybe_unused struct am335x_baseboard_id header; 594 __maybe_unused struct am335x_baseboard_id header;
594 595
595 /* try reading mac address from efuse */ 596 /* try reading mac address from efuse */
596 mac_lo = readl(&cdev->macid0l); 597 mac_lo = readl(&cdev->macid0l);
597 mac_hi = readl(&cdev->macid0h); 598 mac_hi = readl(&cdev->macid0h);
598 mac_addr[0] = mac_hi & 0xFF; 599 mac_addr[0] = mac_hi & 0xFF;
599 mac_addr[1] = (mac_hi & 0xFF00) >> 8; 600 mac_addr[1] = (mac_hi & 0xFF00) >> 8;
600 mac_addr[2] = (mac_hi & 0xFF0000) >> 16; 601 mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
601 mac_addr[3] = (mac_hi & 0xFF000000) >> 24; 602 mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
602 mac_addr[4] = mac_lo & 0xFF; 603 mac_addr[4] = mac_lo & 0xFF;
603 mac_addr[5] = (mac_lo & 0xFF00) >> 8; 604 mac_addr[5] = (mac_lo & 0xFF00) >> 8;
604 605
605 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ 606 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
606 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) 607 (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
607 if (!getenv("ethaddr")) { 608 if (!getenv("ethaddr")) {
608 printf("<ethaddr> not set. Validating first E-fuse MAC\n"); 609 printf("<ethaddr> not set. Validating first E-fuse MAC\n");
609 610
610 if (is_valid_ether_addr(mac_addr)) 611 if (is_valid_ether_addr(mac_addr))
611 eth_setenv_enetaddr("ethaddr", mac_addr); 612 eth_setenv_enetaddr("ethaddr", mac_addr);
612 } 613 }
613 614
614 #ifdef CONFIG_DRIVER_TI_CPSW 615 #ifdef CONFIG_DRIVER_TI_CPSW
615 if (read_eeprom(&header) < 0) 616 if (read_eeprom(&header) < 0)
616 puts("Could not get board ID.\n"); 617 puts("Could not get board ID.\n");
617 618
618 if (board_is_bone(&header) || board_is_bone_lt(&header) || 619 if (board_is_bone(&header) || board_is_bone_lt(&header) ||
619 board_is_idk(&header)) { 620 board_is_idk(&header)) {
620 writel(MII_MODE_ENABLE, &cdev->miisel); 621 writel(MII_MODE_ENABLE, &cdev->miisel);
621 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = 622 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
622 PHY_INTERFACE_MODE_MII; 623 PHY_INTERFACE_MODE_MII;
623 } else if (board_is_smarc_t335x(&header) || board_is_smarc_t335x_1g(&header)) { 624 } else if (board_is_smarc_t335x(&header) || board_is_smarc_t335x_1g(&header)) {
624 writel(RMII_MODE_ENABLE, &cdev->miisel); 625 writel((RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE), &cdev->miisel);
625 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = 626 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
626 PHY_INTERFACE_MODE_RMII; 627 PHY_INTERFACE_MODE_RMII;
627 } else { 628 } else {
628 writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel); 629 writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
629 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if = 630 cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
630 PHY_INTERFACE_MODE_RGMII; 631 PHY_INTERFACE_MODE_RGMII;
631 } 632 }
632 633
633 rv = cpsw_register(&cpsw_data); 634 rv = cpsw_register(&cpsw_data);
634 if (rv < 0) 635 if (rv < 0)
635 printf("Error %d registering CPSW switch\n", rv); 636 printf("Error %d registering CPSW switch\n", rv);
636 else 637 else
637 n += rv; 638 n += rv;
638 #endif 639 #endif
639 640
640 /* 641 /*
641 * 642 *
642 * CPSW RGMII Internal Delay Mode is not supported in all PVT 643 * CPSW RGMII Internal Delay Mode is not supported in all PVT
643 * operating points. So we must set the TX clock delay feature 644 * operating points. So we must set the TX clock delay feature
644 * in the AR8051 PHY. Since we only support a single ethernet 645 * in the AR8051 PHY. Since we only support a single ethernet
645 * device in U-Boot, we only do this for the first instance. 646 * device in U-Boot, we only do this for the first instance.
646 */ 647 */
647 #define AR8051_PHY_DEBUG_ADDR_REG 0x1d 648 #define AR8051_PHY_DEBUG_ADDR_REG 0x1d
648 #define AR8051_PHY_DEBUG_DATA_REG 0x1e 649 #define AR8051_PHY_DEBUG_DATA_REG 0x1e
649 #define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5 650 #define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
650 #define AR8051_RGMII_TX_CLK_DLY 0x100 651 #define AR8051_RGMII_TX_CLK_DLY 0x100
651 652
652 if (board_is_evm_sk(&header) || board_is_gp_evm(&header)) { 653 if (board_is_evm_sk(&header) || board_is_gp_evm(&header)) {
653 const char *devname; 654 const char *devname;
654 devname = miiphy_get_current_dev(); 655 devname = miiphy_get_current_dev();
655 656
656 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG, 657 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_ADDR_REG,
657 AR8051_DEBUG_RGMII_CLK_DLY_REG); 658 AR8051_DEBUG_RGMII_CLK_DLY_REG);
658 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG, 659 miiphy_write(devname, 0x0, AR8051_PHY_DEBUG_DATA_REG,
659 AR8051_RGMII_TX_CLK_DLY); 660 AR8051_RGMII_TX_CLK_DLY);
660 } 661 }
661 #endif 662 #endif
662 #if defined(CONFIG_USB_ETHER) && \ 663 #if defined(CONFIG_USB_ETHER) && \
663 (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT)) 664 (!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
664 if (is_valid_ether_addr(mac_addr)) 665 if (is_valid_ether_addr(mac_addr))
665 eth_setenv_enetaddr("usbnet_devaddr", mac_addr); 666 eth_setenv_enetaddr("usbnet_devaddr", mac_addr);
666 667
667 rv = usb_eth_initialize(bis); 668 rv = usb_eth_initialize(bis);
668 if (rv < 0) 669 if (rv < 0)
669 printf("Error %d registering USB_ETHER\n", rv); 670 printf("Error %d registering USB_ETHER\n", rv);
670 else 671 else
671 n += rv; 672 n += rv;
672 #endif 673 #endif
673 return n; 674 return n;
674 } 675 }
675 #endif 676 #endif
676 677