nds32: Support AG101P serial DM.

Support AG101P serial device tree flow. Signed-off-by: rick <rick@andestech.com>

nds32: Support AG101P serial DM.
Support AG101P serial device tree flow. Signed-off-by: rick <rick@andestech.com>
rick · Andes
1 parent a375ff8e14
Showing 8 changed files with 89 additions and 5 deletions Side-by-side Diff
arch/Kconfig
arch/nds32/cpu/n1213/start.S
arch/nds32/dts/Makefile
arch/nds32/dts/ag101p.dts
arch/nds32/include/asm/config.h
arch/nds32/lib/bootm.c
configs/adp-ag101p_defconfig
include/configs/adp-ag101p.h
@@ -43,6 +43,7 @@
  
 config NDS32
 	bool "NDS32 architecture"
+	select SUPPORT_OF_CONTROL
  
 config NIOS2
 	bool "Nios II architecture"
@@ -161,9 +161,13 @@
  */
 call_board_init_f:
 	li		$sp, CONFIG_SYS_INIT_SP_ADDR
-	li		$r10, GD_SIZE	/* get GD size */
-	sub		$sp, $sp, $r10	/* GD start addr */
-	move	$r10, $sp
+	move	$r0, $sp
+	bal	board_init_f_alloc_reserve
+	move	$sp, $r0
+	bal	board_init_f_init_reserve
+#ifdef CONFIG_DEBUG_UART
+	bal	debug_uart_init
+#endif
 	li		$r0, 0x00000000
  
 #ifdef __PIC__
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+dtb-$(CONFIG_TARGET_ADP_AG101P) += ag101p.dtb
+targets += $(dtb-y)
+
+DTC_FLAGS += -R 4 -p 0x1000
+
+PHONY += dtbs
+dtbs: $(addprefix $(obj)/, $(dtb-y))
+	@:
+
+clean-files := *.dtb
+/dts-v1/;
+/ {
+	compatible = "nds32 ag101p";
+	#address-cells = <1>;
+	#size-cells = <1>;
+	interrupt-parent = <&intc>;
+
+	aliases {
+		uart0 = &serial0;
+	} ;
+
+	chosen {
+		/* bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0x99600000 debug bootmem_debug memblock=debug loglevel=7"; */
+		bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0x99600000 debug loglevel=7";
+		stdout-path = "uart0:38400n8";
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x00000000 0x40000000>;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		cpu@0 {
+			compatible = "andestech,n13";
+			reg = <0>;
+			/* FIXME: to fill correct frqeuency */
+			clock-frequency = <60000000>;
+		};
+	};
+
+	intc: interrupt-controller {
+		compatible = "andestech,atnointc010";
+		#interrupt-cells = <1>;
+		interrupt-controller;
+	};
+
+	serial0: serial@99600000 {
+		compatible = "andestech,uart16550", "ns16550a";
+		reg = <0x99600000 0x1000>;
+		interrupts = <7 4>;
+		clock-frequency = <14745600>;
+		reg-shift = <2>;
+		no-loopback-test = <1>;
+	};
+
+};
@@ -8,6 +8,7 @@
  
 #ifndef _ASM_CONFIG_H_
 #define _ASM_CONFIG_H_
+#define CONFIG_LMB
  
 #endif
@@ -14,6 +14,12 @@
  
 DECLARE_GLOBAL_DATA_PTR;
  
+int arch_fixup_fdt(void *blob)
+{
+	return 0;
+}
+
+
 #if defined(CONFIG_SETUP_MEMORY_TAGS) || \
 	defined(CONFIG_CMDLINE_TAG) || \
 	defined(CONFIG_INITRD_TAG) || \
 CONFIG_NDS32=y
 CONFIG_TARGET_ADP_AG101P=y
+CONFIG_DEFAULT_DEVICE_TREE="ag101p"
+CONFIG_FIT=y
 CONFIG_BOOTDELAY=3
 CONFIG_SYS_PROMPT="NDS32 # "
 CONFIG_CMD_MMC=y
@@ -12,5 +14,8 @@
 CONFIG_MMC=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_BAUDRATE=38400
+CONFIG_OF_CONTROL=y
+CONFIG_DM=y
+CONFIG_DM_SERIAL=y
 CONFIG_SYS_NS16550=y
@@ -20,8 +20,6 @@
  
 #define CONFIG_SKIP_LOWLEVEL_INIT
  
-#define CONFIG_SYS_GENERIC_GLOBAL_DATA
-
 /*
  * Definitions related to passing arguments to kernel.
  */
@@ -35,6 +33,10 @@
  
 #ifdef CONFIG_SKIP_LOWLEVEL_INIT
 #define CONFIG_SYS_TEXT_BASE	0x00500000
+#ifdef CONFIG_OF_CONTROL
+#undef CONFIG_OF_SEPARATE
+#define CONFIG_OF_EMBED
+#endif
 #else
 #ifdef CONFIG_MEM_REMAP
 #define CONFIG_SYS_TEXT_BASE	0x80000000
  
@@ -87,7 +89,9 @@
 #define CONFIG_CONS_INDEX		1
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_COM1		CONFIG_FTUART010_02_BASE
+#ifndef CONFIG_DM_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	-4
+#endif
 #define CONFIG_SYS_NS16550_CLK		((18432000 * 20) / 25)	/* AG101P */
  
 /*
...	...	@@ -43,6 +43,7 @@
43	43
44	44	config NDS32
45	45	bool "NDS32 architecture"
	46	+ select SUPPORT_OF_CONTROL
46	47
47	48	config NIOS2
48	49	bool "Nios II architecture"
...	...	@@ -161,9 +161,13 @@
161	161	*/
162	162	call_board_init_f:
163	163	li $sp, CONFIG_SYS_INIT_SP_ADDR
164		- li $r10, GD_SIZE /* get GD size */
165		- sub $sp, $sp, $r10 /* GD start addr */
166		- move $r10, $sp
	164	+ move $r0, $sp
	165	+ bal board_init_f_alloc_reserve
	166	+ move $sp, $r0
	167	+ bal board_init_f_init_reserve
	168	+#ifdef CONFIG_DEBUG_UART
	169	+ bal debug_uart_init
	170	+#endif
167	171	li $r0, 0x00000000
168	172
169	173	#ifdef __PIC__
	1	+#
	2	+# SPDX-License-Identifier: GPL-2.0+
	3	+#
	4	+
	5	+dtb-$(CONFIG_TARGET_ADP_AG101P) += ag101p.dtb
	6	+targets += $(dtb-y)
	7	+
	8	+DTC_FLAGS += -R 4 -p 0x1000
	9	+
	10	+PHONY += dtbs
	11	+dtbs: $(addprefix $(obj)/, $(dtb-y))
	12	+ @:
	13	+
	14	+clean-files := *.dtb
	1	+/dts-v1/;
	2	+/ {
	3	+ compatible = "nds32 ag101p";
	4	+ #address-cells = <1>;
	5	+ #size-cells = <1>;
	6	+ interrupt-parent = <&intc>;
	7	+
	8	+ aliases {
	9	+ uart0 = &serial0;
	10	+ } ;
	11	+
	12	+ chosen {
	13	+ /* bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0x99600000 debug bootmem_debug memblock=debug loglevel=7"; */
	14	+ bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0x99600000 debug loglevel=7";
	15	+ stdout-path = "uart0:38400n8";
	16	+ };
	17	+
	18	+ memory@0 {
	19	+ device_type = "memory";
	20	+ reg = <0x00000000 0x40000000>;
	21	+ };
	22	+
	23	+ cpus {
	24	+ #address-cells = <1>;
	25	+ #size-cells = <0>;
	26	+ cpu@0 {
	27	+ compatible = "andestech,n13";
	28	+ reg = <0>;
	29	+ /* FIXME: to fill correct frqeuency */
	30	+ clock-frequency = <60000000>;
	31	+ };
	32	+ };
	33	+
	34	+ intc: interrupt-controller {
	35	+ compatible = "andestech,atnointc010";
	36	+ #interrupt-cells = <1>;
	37	+ interrupt-controller;
	38	+ };
	39	+
	40	+ serial0: serial@99600000 {
	41	+ compatible = "andestech,uart16550", "ns16550a";
	42	+ reg = <0x99600000 0x1000>;
	43	+ interrupts = <7 4>;
	44	+ clock-frequency = <14745600>;
	45	+ reg-shift = <2>;
	46	+ no-loopback-test = <1>;
	47	+ };
	48	+
	49	+};
...	...	@@ -8,6 +8,7 @@
8	8
9	9	#ifndef _ASM_CONFIG_H_
10	10	#define _ASM_CONFIG_H_
	11	+#define CONFIG_LMB
11	12
12	13	#endif
...	...	@@ -14,6 +14,12 @@
14	14
15	15	DECLARE_GLOBAL_DATA_PTR;
16	16
	17	+int arch_fixup_fdt(void *blob)
	18	+{
	19	+ return 0;
	20	+}
	21	+
	22	+
17	23	#if defined(CONFIG_SETUP_MEMORY_TAGS) \|\| \
18	24	defined(CONFIG_CMDLINE_TAG) \|\| \
19	25	defined(CONFIG_INITRD_TAG) \|\| \
1	1	CONFIG_NDS32=y
2	2	CONFIG_TARGET_ADP_AG101P=y
	3	+CONFIG_DEFAULT_DEVICE_TREE="ag101p"
	4	+CONFIG_FIT=y
3	5	CONFIG_BOOTDELAY=3
4	6	CONFIG_SYS_PROMPT="NDS32 # "
5	7	CONFIG_CMD_MMC=y
...	...	@@ -12,5 +14,8 @@
12	14	CONFIG_MMC=y
13	15	CONFIG_MTD_NOR_FLASH=y
14	16	CONFIG_BAUDRATE=38400
	17	+CONFIG_OF_CONTROL=y
	18	+CONFIG_DM=y
	19	+CONFIG_DM_SERIAL=y
15	20	CONFIG_SYS_NS16550=y
...	...	@@ -20,8 +20,6 @@
20	20
21	21	#define CONFIG_SKIP_LOWLEVEL_INIT
22	22
23		-#define CONFIG_SYS_GENERIC_GLOBAL_DATA
24		-
25	23	/*
26	24	* Definitions related to passing arguments to kernel.
27	25	*/
...	...	@@ -35,6 +33,10 @@
35	33
36	34	#ifdef CONFIG_SKIP_LOWLEVEL_INIT
37	35	#define CONFIG_SYS_TEXT_BASE 0x00500000
	36	+#ifdef CONFIG_OF_CONTROL
	37	+#undef CONFIG_OF_SEPARATE
	38	+#define CONFIG_OF_EMBED
	39	+#endif
38	40	#else
39	41	#ifdef CONFIG_MEM_REMAP
40	42	#define CONFIG_SYS_TEXT_BASE 0x80000000
41	43
...	...	@@ -87,7 +89,9 @@
87	89	#define CONFIG_CONS_INDEX 1
88	90	#define CONFIG_SYS_NS16550_SERIAL
89	91	#define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE
	92	+#ifndef CONFIG_DM_SERIAL
90	93	#define CONFIG_SYS_NS16550_REG_SIZE -4
	94	+#endif
91	95	#define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */
92	96
93	97	/*