Commit 866435866402ad740b09efccf79d19e420f91114
1 parent
a9289e4c1b
Exists in
smarc-m6.0.1_2.1.0-ga
MLK-12658 imx: adjust POR_B setting on i.MX6ULL
Adjust POR_B settings on i.MX6ULL according to design team's suggestion: 2'b00 : always PUP100K 2'b01 : PUP100K when PMIC_ON_REQ || SOC_NOT_FAIL 2'b10 : always disable PUP100K 2'b11 : PDN100K when SOC_FAIL, PUP100K when SOC_NOT_FAIL -- recommended setting Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Showing 1 changed file with 13 additions and 0 deletions Side-by-side Diff
arch/arm/cpu/armv7/mx6/soc.c
... | ... | @@ -489,6 +489,19 @@ |
489 | 489 | } |
490 | 490 | #endif |
491 | 491 | |
492 | +#ifdef CONFIG_MX6ULL | |
493 | + /* | |
494 | + * GPBIT[1:0] is suggested to set to 2'b11: | |
495 | + * 2'b00 : always PUP100K | |
496 | + * 2'b01 : PUP100K when PMIC_ON_REQ or SOC_NOT_FAIL | |
497 | + * 2'b10 : always disable PUP100K | |
498 | + * 2'b11 : PDN100K when SOC_FAIL, PUP100K when SOC_NOT_FAIL | |
499 | + * register offset is different from i.MX6UL, since | |
500 | + * i.MX6UL is fixed by ECO. | |
501 | + */ | |
502 | + writel(readl(SNVS_LP_BASE_ADDR) | 0x3, SNVS_LP_BASE_ADDR); | |
503 | +#endif | |
504 | + | |
492 | 505 | /* Set perclk to source from OSC 24MHz */ |
493 | 506 | #if defined(CONFIG_MX6SL) |
494 | 507 | set_preclk_from_osc(); |