am335x: update README for BCH16

updates documentation with explanation on how to select ECC schemes. Signed-off-by: Pekon Gupta <pekon@ti.com>

am335x: update README for BCH16
updates documentation with explanation on how to select ECC schemes. Signed-off-by: Pekon Gupta <pekon@ti.com>
pekon gupta · Tom Rini
1 parent 46840f66ca
Showing 1 changed file with 42 additions and 0 deletions Side-by-side Diff
doc/README.nand
@@ -249,6 +249,48 @@
 		8-bit BCH code with
 		- ecc calculation using GPMC hardware engine,
 		- error detection using ELM hardware engine.
+	OMAP_ECC_BCH16_CODE_HW
+		16-bit BCH code with
+		- ecc calculation using GPMC hardware engine,
+		- error detection using ELM hardware engine.
+
+	How to select ECC scheme on OMAP and AMxx platforms ?
+	-----------------------------------------------------
+	Though higher ECC schemes have more capability to detect and correct
+	bit-flips, but still selection of ECC scheme is dependent on following
+	- hardware engines present in SoC.
+		Some legacy OMAP SoC do not have ELM h/w engine thus such
+		SoC cannot support BCHx_HW ECC schemes.
+	- size of OOB/Spare region
+		With higher ECC schemes, more OOB/Spare area is required to
+		store ECC. So choice of ECC scheme is limited by NAND oobsize.
+
+	In general following expression can help:
+		NAND_OOBSIZE >= 2 + (NAND_PAGESIZE / 512) * ECC_BYTES
+	where
+		NAND_OOBSIZE	= number of bytes available in
+				OOB/spare area per NAND page.
+		NAND_PAGESIZE	= bytes in main-area of NAND page.
+		ECC_BYTES	= number of ECC bytes generated to
+				protect 512 bytes of data, which is:
+				3 for HAM1_xx ecc schemes
+				7 for BCH4_xx ecc schemes
+				14 for BCH8_xx ecc schemes
+				26 for BCH16_xx ecc schemes
+
+		example to check for BCH16 on 2K page NAND
+		NAND_PAGESIZE = 2048
+		NAND_OOBSIZE = 64
+		2 + (2048 / 512) * 26 = 106 > NAND_OOBSIZE
+		Thus BCH16 cannot be supported on 2K page NAND.
+
+		However, for 4K pagesize NAND
+		NAND_PAGESIZE = 4096
+		NAND_OOBSIZE = 64
+		ECC_BYTES = 26
+		2 + (4096 / 512) * 26 = 210 < NAND_OOBSIZE
+		Thus BCH16 can be supported on 4K page NAND.
+
  
 NOTE:
 =====
...	...	@@ -249,6 +249,48 @@
249	249	8-bit BCH code with
250	250	- ecc calculation using GPMC hardware engine,
251	251	- error detection using ELM hardware engine.
	252	+ OMAP_ECC_BCH16_CODE_HW
	253	+ 16-bit BCH code with
	254	+ - ecc calculation using GPMC hardware engine,
	255	+ - error detection using ELM hardware engine.
	256	+
	257	+ How to select ECC scheme on OMAP and AMxx platforms ?
	258	+ -----------------------------------------------------
	259	+ Though higher ECC schemes have more capability to detect and correct
	260	+ bit-flips, but still selection of ECC scheme is dependent on following
	261	+ - hardware engines present in SoC.
	262	+ Some legacy OMAP SoC do not have ELM h/w engine thus such
	263	+ SoC cannot support BCHx_HW ECC schemes.
	264	+ - size of OOB/Spare region
	265	+ With higher ECC schemes, more OOB/Spare area is required to
	266	+ store ECC. So choice of ECC scheme is limited by NAND oobsize.
	267	+
	268	+ In general following expression can help:
	269	+ NAND_OOBSIZE >= 2 + (NAND_PAGESIZE / 512) * ECC_BYTES
	270	+ where
	271	+ NAND_OOBSIZE = number of bytes available in
	272	+ OOB/spare area per NAND page.
	273	+ NAND_PAGESIZE = bytes in main-area of NAND page.
	274	+ ECC_BYTES = number of ECC bytes generated to
	275	+ protect 512 bytes of data, which is:
	276	+ 3 for HAM1_xx ecc schemes
	277	+ 7 for BCH4_xx ecc schemes
	278	+ 14 for BCH8_xx ecc schemes
	279	+ 26 for BCH16_xx ecc schemes
	280	+
	281	+ example to check for BCH16 on 2K page NAND
	282	+ NAND_PAGESIZE = 2048
	283	+ NAND_OOBSIZE = 64
	284	+ 2 + (2048 / 512) * 26 = 106 > NAND_OOBSIZE
	285	+ Thus BCH16 cannot be supported on 2K page NAND.
	286	+
	287	+ However, for 4K pagesize NAND
	288	+ NAND_PAGESIZE = 4096
	289	+ NAND_OOBSIZE = 64
	290	+ ECC_BYTES = 26
	291	+ 2 + (4096 / 512) * 26 = 210 < NAND_OOBSIZE
	292	+ Thus BCH16 can be supported on 4K page NAND.
	293	+
252	294
253	295	NOTE:
254	296	=====