Eric Lee / smarc-uboot

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Commit 86ac7a9a5d0c8ae9f0e5e6ef2cc189198e498cf4

Authored by Peng Fan
Committed by Stefano Babic
1 parent e3963c0943
Exists in smarc_8mq_lf_v2020.04 and in 11 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

imx: add i.MX8MQ EVK support 

Add i.MX8MQ EVK support. SPL will initialize ddr and load ddr phy
firmware. Then loading FIT image, ATF to OCRAM, U-Boot and DTB to
DRAM.

The boot log with Arm trusted firmware console enabled:
"
U-Boot SPL 2018.11-00142-g9ae14e7274 (Nov 20 2018 - 18:13:16 +0800)
PMIC:  PFUZE100 ID=0x10
Normal Boot
Trying to boot from MMC2
NOTICE:  Configureing TZASC380
NOTICE:  BL31: v1.5(release):p9.0.0_1.0.0-beta-20180928-8-ge09c4b62-dirty
NOTICE:  BL31: Built : 09:28:54, Nov  8 2018
lpddr4 swffc start
NOTICE:  sip svc init

U-Boot 2018.11-00142-g9ae14e7274 (Nov 20 2018 - 18:13:16 +0800)

CPU:   Freescale i.MX8MQ rev2.0 at 1000 MHz
Reset cause: POR
Model: Freescale i.MX8MQ EVK
DRAM:  3 GiB
MMC:   FSL_SDHC: 0, FSL_SDHC: 1
In:    serial
Out:   serial
Err:   serial
Net:
Warning: ethernet@30be0000 using MAC address from ROM
eth0: ethernet@30be0000
Hit any key to stop autoboot:  0
"

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>

Showing 13 changed files with 3671 additions and 0 deletions Side-by-side Diff

arch/arm/dts/Makefile
Diff comments   View file @ 86ac7a9
... ... @@ -465,6 +465,8 @@
465 465  
466 466 dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8qxp-mek.dtb
467 467  
  468 +dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb
  469 +
468 470 dtb-$(CONFIG_RCAR_GEN3) += \
469 471 r8a7795-h3ulcb-u-boot.dtb \
470 472 r8a7795-salvator-x-u-boot.dtb \
arch/arm/dts/fsl-imx8mq-evk.dts
Diff comments   View file @ 86ac7a9
  1 +// SPDX-License-Identifier: GPL-2.0+
  2 +/*
  3 + * Copyright 2018 NXP
  4 + */
  5 +
  6 +/dts-v1/;
  7 +
  8 +/* First 128KB is for PSCI ATF. */
  9 +/memreserve/ 0x40000000 0x00020000;
  10 +
  11 +#include "fsl-imx8mq.dtsi"
  12 +
  13 +/ {
  14 + model = "Freescale i.MX8MQ EVK";
  15 + compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
  16 +
  17 + chosen {
  18 + bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200";
  19 + };
  20 +
  21 + regulators {
  22 + compatible = "simple-bus";
  23 + #address-cells = <1>;
  24 + #size-cells = <0>;
  25 +
  26 + reg_usdhc2_vmmc: usdhc2_vmmc {
  27 + compatible = "regulator-fixed";
  28 + regulator-name = "VSD_3V3";
  29 + regulator-min-microvolt = <3300000>;
  30 + regulator-max-microvolt = <3300000>;
  31 + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
  32 + enable-active-high;
  33 + };
  34 + };
  35 +
  36 + pwmleds {
  37 + compatible = "pwm-leds";
  38 +
  39 + ledpwm2 {
  40 + label = "PWM2";
  41 + pwms = <&pwm2 0 50000>;
  42 + max-brightness = <255>;
  43 + };
  44 + };
  45 +};
  46 +
  47 +&iomuxc {
  48 + pinctrl-names = "default";
  49 +
  50 + imx8mq-evk {
  51 + pinctrl_fec1: fec1grp {
  52 + fsl,pins = <
  53 + MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
  54 + MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
  55 + MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
  56 + MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
  57 + MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
  58 + MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
  59 + MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
  60 + MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
  61 + MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
  62 + MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
  63 + MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
  64 + MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
  65 + MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
  66 + MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
  67 + MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
  68 + >;
  69 + };
  70 +
  71 + pinctrl_i2c1: i2c1grp {
  72 + fsl,pins = <
  73 + MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
  74 + MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
  75 + >;
  76 + };
  77 +
  78 + pinctrl_i2c2: i2c2grp {
  79 + fsl,pins = <
  80 + MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f
  81 + MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f
  82 + >;
  83 + };
  84 +
  85 + pinctrl_pwm2: pwm2grp {
  86 + fsl,pins = <
  87 + MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT 0x16
  88 + >;
  89 + };
  90 +
  91 + pinctrl_qspi: qspigrp {
  92 + fsl,pins = <
  93 + MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
  94 + MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
  95 + MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
  96 + MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
  97 + MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
  98 + MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
  99 +
  100 + >;
  101 + };
  102 +
  103 + pinctrl_usdhc1: usdhc1grp {
  104 + fsl,pins = <
  105 + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
  106 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
  107 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
  108 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
  109 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
  110 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
  111 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
  112 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
  113 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
  114 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
  115 + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
  116 + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
  117 + >;
  118 + };
  119 +
  120 + pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
  121 + fsl,pins = <
  122 + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85
  123 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5
  124 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5
  125 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5
  126 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5
  127 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5
  128 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5
  129 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5
  130 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5
  131 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5
  132 + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85
  133 + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
  134 + >;
  135 + };
  136 +
  137 + pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
  138 + fsl,pins = <
  139 + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87
  140 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7
  141 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7
  142 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7
  143 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7
  144 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7
  145 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7
  146 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7
  147 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7
  148 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7
  149 + MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87
  150 + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
  151 + >;
  152 + };
  153 +
  154 + pinctrl_usdhc2_gpio: usdhc2grpgpio {
  155 + fsl,pins = <
  156 + MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
  157 + MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
  158 + >;
  159 + };
  160 +
  161 + pinctrl_usdhc2: usdhc2grp {
  162 + fsl,pins = <
  163 + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
  164 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
  165 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
  166 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
  167 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
  168 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
  169 + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
  170 + >;
  171 + };
  172 +
  173 + pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
  174 + fsl,pins = <
  175 + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
  176 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
  177 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
  178 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
  179 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
  180 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
  181 + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
  182 + >;
  183 + };
  184 +
  185 + pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
  186 + fsl,pins = <
  187 + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
  188 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
  189 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
  190 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
  191 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
  192 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
  193 + MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
  194 + >;
  195 + };
  196 +
  197 + pinctrl_sai2: sai2grp {
  198 + fsl,pins = <
  199 + MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
  200 + MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
  201 + MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
  202 + MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
  203 + MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6
  204 + >;
  205 + };
  206 +
  207 + pinctrl_wdog: wdoggrp {
  208 + fsl,pins = <
  209 + MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
  210 + >;
  211 + };
  212 + };
  213 +};
  214 +
  215 +&fec1 {
  216 + pinctrl-names = "default";
  217 + pinctrl-0 = <&pinctrl_fec1>;
  218 + phy-mode = "rgmii-id";
  219 + phy-handle = <&ethphy0>;
  220 + fsl,magic-packet;
  221 + status = "okay";
  222 +
  223 + mdio {
  224 + #address-cells = <1>;
  225 + #size-cells = <0>;
  226 +
  227 + ethphy0: ethernet-phy@0 {
  228 + compatible = "ethernet-phy-ieee802.3-c22";
  229 + reg = <0>;
  230 + at803x,led-act-blind-workaround;
  231 + at803x,eee-disabled;
  232 + };
  233 + };
  234 +};
  235 +
  236 +&i2c1 {
  237 + clock-frequency = <100000>;
  238 + pinctrl-names = "default";
  239 + pinctrl-0 = <&pinctrl_i2c1>;
  240 + status = "okay";
  241 +
  242 + pmic: pfuze100@08 {
  243 + compatible = "fsl,pfuze100";
  244 + reg = <0x08>;
  245 +
  246 + regulators {
  247 + sw1a_reg: sw1ab {
  248 + regulator-min-microvolt = <300000>;
  249 + regulator-max-microvolt = <1875000>;
  250 + regulator-always-on;
  251 + };
  252 +
  253 + sw1c_reg: sw1c {
  254 + regulator-min-microvolt = <300000>;
  255 + regulator-max-microvolt = <1875000>;
  256 + regulator-always-on;
  257 + };
  258 +
  259 + sw2_reg: sw2 {
  260 + regulator-min-microvolt = <800000>;
  261 + regulator-max-microvolt = <3300000>;
  262 + regulator-always-on;
  263 + };
  264 +
  265 + sw3a_reg: sw3ab {
  266 + regulator-min-microvolt = <400000>;
  267 + regulator-max-microvolt = <1975000>;
  268 + regulator-always-on;
  269 + };
  270 +
  271 + sw4_reg: sw4 {
  272 + regulator-min-microvolt = <800000>;
  273 + regulator-max-microvolt = <3300000>;
  274 + regulator-always-on;
  275 + };
  276 +
  277 + swbst_reg: swbst {
  278 + regulator-min-microvolt = <5000000>;
  279 + regulator-max-microvolt = <5150000>;
  280 + };
  281 +
  282 + snvs_reg: vsnvs {
  283 + regulator-min-microvolt = <1000000>;
  284 + regulator-max-microvolt = <3000000>;
  285 + regulator-always-on;
  286 + };
  287 +
  288 + vref_reg: vrefddr {
  289 + regulator-always-on;
  290 + };
  291 +
  292 + vgen1_reg: vgen1 {
  293 + regulator-min-microvolt = <800000>;
  294 + regulator-max-microvolt = <1550000>;
  295 + };
  296 +
  297 + vgen2_reg: vgen2 {
  298 + regulator-min-microvolt = <800000>;
  299 + regulator-max-microvolt = <1550000>;
  300 + regulator-always-on;
  301 + };
  302 +
  303 + vgen3_reg: vgen3 {
  304 + regulator-min-microvolt = <1800000>;
  305 + regulator-max-microvolt = <3300000>;
  306 + regulator-always-on;
  307 + };
  308 +
  309 + vgen4_reg: vgen4 {
  310 + regulator-min-microvolt = <1800000>;
  311 + regulator-max-microvolt = <3300000>;
  312 + regulator-always-on;
  313 + };
  314 +
  315 + vgen5_reg: vgen5 {
  316 + regulator-min-microvolt = <1800000>;
  317 + regulator-max-microvolt = <3300000>;
  318 + regulator-always-on;
  319 + };
  320 +
  321 + vgen6_reg: vgen6 {
  322 + regulator-min-microvolt = <1800000>;
  323 + regulator-max-microvolt = <3300000>;
  324 + };
  325 + };
  326 + };
  327 +};
  328 +
  329 +&i2c2 {
  330 + clock-frequency = <100000>;
  331 + pinctrl-names = "default";
  332 + pinctrl-0 = <&pinctrl_i2c2>;
  333 + status = "disabled";
  334 +};
  335 +
  336 +&pwm2 {
  337 + pinctrl-names = "default";
  338 + pinctrl-0 = <&pinctrl_pwm2>;
  339 + status = "okay";
  340 +};
  341 +
  342 +&lcdif {
  343 + status = "okay";
  344 + disp-dev = "mipi_dsi_northwest";
  345 + display = <&display0>;
  346 +
  347 + display0: display@0 {
  348 + bits-per-pixel = <24>;
  349 + bus-width = <24>;
  350 +
  351 + display-timings {
  352 + native-mode = <&timing0>;
  353 + timing0: timing0 {
  354 + clock-frequency = <9200000>;
  355 + hactive = <480>;
  356 + vactive = <272>;
  357 + hfront-porch = <8>;
  358 + hback-porch = <4>;
  359 + hsync-len = <41>;
  360 + vback-porch = <2>;
  361 + vfront-porch = <4>;
  362 + vsync-len = <10>;
  363 +
  364 + hsync-active = <0>;
  365 + vsync-active = <0>;
  366 + de-active = <1>;
  367 + pixelclk-active = <0>;
  368 + };
  369 + };
  370 + };
  371 +};
  372 +
  373 +&qspi {
  374 + pinctrl-names = "default";
  375 + pinctrl-0 = <&pinctrl_qspi>;
  376 + status = "okay";
  377 +
  378 + flash0: n25q256a@0 {
  379 + reg = <0>;
  380 + #address-cells = <1>;
  381 + #size-cells = <1>;
  382 + compatible = "micron,n25q256a";
  383 + spi-max-frequency = <29000000>;
  384 + spi-nor,ddr-quad-read-dummy = <6>;
  385 + };
  386 +};
  387 +
  388 +&usdhc1 {
  389 + pinctrl-names = "default", "state_100mhz", "state_200mhz";
  390 + pinctrl-0 = <&pinctrl_usdhc1>;
  391 + pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
  392 + pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
  393 + bus-width = <8>;
  394 + non-removable;
  395 + status = "okay";
  396 +};
  397 +
  398 +&usdhc2 {
  399 + pinctrl-names = "default", "state_100mhz", "state_200mhz";
  400 + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
  401 + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
  402 + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
  403 + bus-width = <4>;
  404 + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
  405 + vmmc-supply = <&reg_usdhc2_vmmc>;
  406 + status = "okay";
  407 +};
  408 +
  409 +&wdog1 {
  410 + pinctrl-names = "default";
  411 + pinctrl-0 = <&pinctrl_wdog>;
  412 + fsl,ext-reset-output;
  413 + status = "okay";
  414 +};
arch/arm/mach-imx/imx8m/Kconfig
Diff comments   View file @ 86ac7a9
... ... @@ -7,5 +7,18 @@
7 7 config SYS_SOC
8 8 default "imx8m"
9 9  
  10 +choice
  11 + prompt "NXP i.MX8M board select"
  12 + optional
  13 +
  14 +config TARGET_IMX8MQ_EVK
  15 + bool "imx8mq_evk"
  16 + select IMX8M
  17 + select IMX8M_LPDDR4
  18 +
  19 +endchoice
  20 +
  21 +source "board/freescale/imx8mq_evk/Kconfig"
  22 +
10 23 endif
board/freescale/imx8mq_evk/Kconfig
Diff comments   View file @ 86ac7a9
  1 +if TARGET_IMX8MQ_EVK
  2 +
  3 +config SYS_BOARD
  4 + default "imx8mq_evk"
  5 +
  6 +config SYS_VENDOR
  7 + default "freescale"
  8 +
  9 +config SYS_CONFIG_NAME
  10 + default "imx8mq_evk"
  11 +
  12 +endif
board/freescale/imx8mq_evk/MAINTAINERS
Diff comments   View file @ 86ac7a9
  1 +i.MX8MQ EVK BOARD
  2 +M: Peng Fan <peng.fan@nxp.com>
  3 +S: Maintained
  4 +F: board/freescale/imx8mq_evk/
  5 +F: include/configs/imx8mq_evk.h
  6 +F: configs/imx8mq_evk_defconfig
board/freescale/imx8mq_evk/Makefile
Diff comments   View file @ 86ac7a9
  1 +#
  2 +# Copyright 2017 NXP
  3 +#
  4 +# SPDX-License-Identifier: GPL-2.0+
  5 +#
  6 +
  7 +obj-y += imx8mq_evk.o
  8 +
  9 +ifdef CONFIG_SPL_BUILD
  10 +obj-y += spl.o
  11 +obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o lpddr4_timing_b0.o
  12 +endif
board/freescale/imx8mq_evk/README
Diff comments   View file @ 86ac7a9
  1 +U-Boot for the NXP i.MX8MQ EVK board
  2 +
  3 +Quick Start
  4 +====================
  5 +- Build the ARM Trusted firmware binary
  6 +- Get ddr and hdmi fimware
  7 +- Build U-Boot
  8 +- Boot
  9 +
  10 +Get and Build the ARM Trusted firmware
  11 +====================
  12 +Get ATF from: https://source.codeaurora.org/external/imx/imx-atf
  13 +branch: imx_4.14.62_1.0.0_beta
  14 +$ make PLAT=imx8mq bl31
  15 +
  16 +Get the ddr and hdmi firmware
  17 +====================
  18 +Note: srctree is U-Boot source directory
  19 +$ wget https://www.nxp.com/lgfiles/NMG/MAD/YOCTO/firmware-imx-7.9.bin
  20 +$ chmod +x firmware-imx-7.9.bin
  21 +$ cp firmware-imx-7.9/firmware/hdmi/cadence/signed_hdmi_imx8m.bin $(srctree)
  22 +$ cp firmware-imx-7.9/firmware-imx-7.9/firmware/ddr/synopsys/lpddr4*.bin $(srctee)
  23 +
  24 +Build U-Boot
  25 +====================
  26 +$ export ARCH=arm64
  27 +$ export CROSS_COMPILE=aarch64-poky-linux-
  28 +$ make imx8mq_evk_defconfig
  29 +$ make flash.bin
  30 +
  31 +Burn the flash.bin to MicroSD card offset 33KB
  32 +$sudo dd if=flash.bin of=/dev/sd[x] bs=1024 seek=33
  33 +
  34 +Boot
  35 +====================
  36 +Set Boot switch SW801: 1100 and Bmode: 10 to boot from Micro SD.
board/freescale/imx8mq_evk/imx8mq_evk.c
Diff comments   View file @ 86ac7a9
  1 +// SPDX-License-Identifier: GPL-2.0+
  2 +/*
  3 + * Copyright 2018 NXP
  4 + */
  5 +
  6 +#include <common.h>
  7 +#include <malloc.h>
  8 +#include <errno.h>
  9 +#include <asm/io.h>
  10 +#include <miiphy.h>
  11 +#include <netdev.h>
  12 +#include <asm/mach-imx/iomux-v3.h>
  13 +#include <asm-generic/gpio.h>
  14 +#include <fsl_esdhc.h>
  15 +#include <mmc.h>
  16 +#include <asm/arch/imx8mq_pins.h>
  17 +#include <asm/arch/sys_proto.h>
  18 +#include <asm/mach-imx/gpio.h>
  19 +#include <asm/mach-imx/mxc_i2c.h>
  20 +#include <asm/arch/clock.h>
  21 +#include <spl.h>
  22 +#include <power/pmic.h>
  23 +#include <power/pfuze100_pmic.h>
  24 +#include "../common/pfuze.h"
  25 +
  26 +DECLARE_GLOBAL_DATA_PTR;
  27 +
  28 +#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
  29 +
  30 +#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
  31 +
  32 +static iomux_v3_cfg_t const wdog_pads[] = {
  33 + IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
  34 +};
  35 +
  36 +static iomux_v3_cfg_t const uart_pads[] = {
  37 + IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  38 + IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  39 +};
  40 +
  41 +int board_early_init_f(void)
  42 +{
  43 + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
  44 +
  45 + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
  46 + set_wdog_reset(wdog);
  47 +
  48 + imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
  49 +
  50 + return 0;
  51 +}
  52 +
  53 +int dram_init(void)
  54 +{
  55 + /* rom_pointer[1] contains the size of TEE occupies */
  56 + if (rom_pointer[1])
  57 + gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1];
  58 + else
  59 + gd->ram_size = PHYS_SDRAM_SIZE;
  60 +
  61 + return 0;
  62 +}
  63 +
  64 +#ifdef CONFIG_FEC_MXC
  65 +#define FEC_RST_PAD IMX_GPIO_NR(1, 9)
  66 +static iomux_v3_cfg_t const fec1_rst_pads[] = {
  67 + IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL),
  68 +};
  69 +
  70 +static void setup_iomux_fec(void)
  71 +{
  72 + imx_iomux_v3_setup_multiple_pads(fec1_rst_pads,
  73 + ARRAY_SIZE(fec1_rst_pads));
  74 +
  75 + gpio_request(IMX_GPIO_NR(1, 9), "fec1_rst");
  76 + gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
  77 + udelay(500);
  78 + gpio_direction_output(IMX_GPIO_NR(1, 9), 1);
  79 +}
  80 +
  81 +static int setup_fec(void)
  82 +{
  83 + struct iomuxc_gpr_base_regs *gpr =
  84 + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
  85 +
  86 + setup_iomux_fec();
  87 +
  88 + /* Use 125M anatop REF_CLK1 for ENET1, not from external */
  89 + clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0);
  90 + return set_clk_enet(ENET_125MHZ);
  91 +}
  92 +
  93 +int board_phy_config(struct phy_device *phydev)
  94 +{
  95 + /* enable rgmii rxc skew and phy mode select to RGMII copper */
  96 + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
  97 + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
  98 +
  99 + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
  100 + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
  101 +
  102 + if (phydev->drv->config)
  103 + phydev->drv->config(phydev);
  104 + return 0;
  105 +}
  106 +#endif
  107 +
  108 +int board_init(void)
  109 +{
  110 +#ifdef CONFIG_FEC_MXC
  111 + setup_fec();
  112 +#endif
  113 +
  114 + return 0;
  115 +}
  116 +
  117 +int board_mmc_get_env_dev(int devno)
  118 +{
  119 + return devno;
  120 +}
  121 +
  122 +int board_late_init(void)
  123 +{
  124 +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  125 + env_set("board_name", "EVK");
  126 + env_set("board_rev", "iMX8MQ");
  127 +#endif
  128 +
  129 + return 0;
  130 +}
board/freescale/imx8mq_evk/lpddr4_timing.c
Diff comments   View file @ 86ac7a9
Changes suppressed. Click to show
  1 +// SPDX-License-Identifier: GPL-2.0+
  2 +/*
  3 + * Copyright 2018 NXP
  4 + */
  5 +
  6 +#include <linux/kernel.h>
  7 +#include <common.h>
  8 +#include <asm/arch/ddr.h>
  9 +#include <asm/arch/lpddr4_define.h>
  10 +
  11 +#define WR_POST_EXT_3200 /* recommened to define */
  12 +
  13 +struct dram_cfg_param lpddr4_ddrc_cfg[] = {
  14 + /* Start to config, default 3200mbps */
  15 + { DDRC_DBG1(0), 0x00000001 },
  16 + { DDRC_PWRCTL(0), 0x00000001 },
  17 + { DDRC_MSTR(0), 0xa3080020 },
  18 + { DDRC_MSTR2(0), 0x00000000 },
  19 + { DDRC_RFSHTMG(0), 0x006100E0 },
  20 + { DDRC_INIT0(0), 0xC003061B },
  21 + { DDRC_INIT1(0), 0x009D0000 },
  22 + { DDRC_INIT3(0), 0x00D4002D },
  23 +#ifdef WR_POST_EXT_3200
  24 + { DDRC_INIT4(0), 0x00330008 },
  25 +#else
  26 + { DDRC_INIT4(0), 0x00310008 },
  27 +#endif
  28 + { DDRC_INIT6(0), 0x0066004a },
  29 + { DDRC_INIT7(0), 0x0006004a },
  30 +
  31 + { DDRC_DRAMTMG0(0), 0x1A201B22 },
  32 + { DDRC_DRAMTMG1(0), 0x00060633 },
  33 + { DDRC_DRAMTMG3(0), 0x00C0C000 },
  34 + { DDRC_DRAMTMG4(0), 0x0F04080F },
  35 + { DDRC_DRAMTMG5(0), 0x02040C0C },
  36 + { DDRC_DRAMTMG6(0), 0x01010007 },
  37 + { DDRC_DRAMTMG7(0), 0x00000401 },
  38 + { DDRC_DRAMTMG12(0), 0x00020600 },
  39 + { DDRC_DRAMTMG13(0), 0x0C100002 },
  40 + { DDRC_DRAMTMG14(0), 0x000000E6 },
  41 + { DDRC_DRAMTMG17(0), 0x00A00050 },
  42 +
  43 + { DDRC_ZQCTL0(0), 0x03200018 },
  44 + { DDRC_ZQCTL1(0), 0x028061A8 },
  45 + { DDRC_ZQCTL2(0), 0x00000000 },
  46 +
  47 + { DDRC_DFITMG0(0), 0x0497820A },
  48 + { DDRC_DFITMG1(0), 0x00080303 },
  49 + { DDRC_DFIUPD0(0), 0xE0400018 },
  50 + { DDRC_DFIUPD1(0), 0x00DF00E4 },
  51 + { DDRC_DFIUPD2(0), 0x80000000 },
  52 + { DDRC_DFIMISC(0), 0x00000011 },
  53 + { DDRC_DFITMG2(0), 0x0000170A },
  54 +
  55 + { DDRC_DBICTL(0), 0x00000001 },
  56 + { DDRC_DFIPHYMSTR(0), 0x00000001 },
  57 + { DDRC_RANKCTL(0), 0x00000c99 },
  58 + { DDRC_DRAMTMG2(0), 0x070E171a },
  59 +
  60 + /* address mapping */
  61 + { DDRC_ADDRMAP0(0), 0x00000015 },
  62 + { DDRC_ADDRMAP3(0), 0x00000000 },
  63 + { DDRC_ADDRMAP4(0), 0x00001F1F },
  64 + /* bank interleave */
  65 + { DDRC_ADDRMAP1(0), 0x00080808 },
  66 + { DDRC_ADDRMAP5(0), 0x07070707 },
  67 + { DDRC_ADDRMAP6(0), 0x08080707 },
  68 +
  69 + /* performance setting */
  70 + { DDRC_ODTCFG(0), 0x0b060908 },
  71 + { DDRC_ODTMAP(0), 0x00000000 },
  72 + { DDRC_SCHED(0), 0x29511505 },
  73 + { DDRC_SCHED1(0), 0x0000002c },
  74 + { DDRC_PERFHPR1(0), 0x5900575b },
  75 + { DDRC_PERFLPR1(0), 0x00000009 },
  76 + { DDRC_PERFWR1(0), 0x02005574 },
  77 + { DDRC_DBG0(0), 0x00000016 },
  78 + { DDRC_DBG1(0), 0x00000000 },
  79 + { DDRC_DBGCMD(0), 0x00000000 },
  80 + { DDRC_SWCTL(0), 0x00000001 },
  81 + { DDRC_POISONCFG(0), 0x00000011 },
  82 + { DDRC_PCCFG(0), 0x00000111 },
  83 + { DDRC_PCFGR_0(0), 0x000010f3 },
  84 + { DDRC_PCFGW_0(0), 0x000072ff },
  85 + { DDRC_PCTRL_0(0), 0x00000001 },
  86 + { DDRC_PCFGQOS0_0(0), 0x01110d00 },
  87 + { DDRC_PCFGQOS1_0(0), 0x00620790 },
  88 + { DDRC_PCFGWQOS0_0(0), 0x00100001 },
  89 + { DDRC_PCFGWQOS1_0(0), 0x0000041f },
  90 +
  91 + /* Frequency 1: 400mbps */
  92 + { DDRC_FREQ1_DRAMTMG0(0), 0x0d0b010c },
  93 + { DDRC_FREQ1_DRAMTMG1(0), 0x00030410 },
  94 + { DDRC_FREQ1_DRAMTMG2(0), 0x0305090c },
  95 + { DDRC_FREQ1_DRAMTMG3(0), 0x00505006 },
  96 + { DDRC_FREQ1_DRAMTMG4(0), 0x05040305 },
  97 + { DDRC_FREQ1_DRAMTMG5(0), 0x0d0e0504 },
  98 + { DDRC_FREQ1_DRAMTMG6(0), 0x0a060004 },
  99 + { DDRC_FREQ1_DRAMTMG7(0), 0x0000090e },
  100 + { DDRC_FREQ1_DRAMTMG14(0), 0x00000032 },
  101 + { DDRC_FREQ1_DRAMTMG15(0), 0x00000000 },
  102 + { DDRC_FREQ1_DRAMTMG17(0), 0x0036001b },
  103 + { DDRC_FREQ1_DERATEINT(0), 0x7e9fbeb1 },
  104 + { DDRC_FREQ1_DFITMG0(0), 0x03818200 },
  105 + { DDRC_FREQ1_DFITMG2(0), 0x00000000 },
  106 + { DDRC_FREQ1_RFSHTMG(0), 0x000C001c },
  107 + { DDRC_FREQ1_INIT3(0), 0x00840000 },
  108 + { DDRC_FREQ1_INIT4(0), 0x00310008 },
  109 + { DDRC_FREQ1_INIT6(0), 0x0066004a },
  110 + { DDRC_FREQ1_INIT7(0), 0x0006004a },
  111 +
  112 + /* Frequency 2: 100mbps */
  113 + { DDRC_FREQ2_DRAMTMG0(0), 0x0d0b010c },
  114 + { DDRC_FREQ2_DRAMTMG1(0), 0x00030410 },
  115 + { DDRC_FREQ2_DRAMTMG2(0), 0x0305090c },
  116 + { DDRC_FREQ2_DRAMTMG3(0), 0x00505006 },
  117 + { DDRC_FREQ2_DRAMTMG4(0), 0x05040305 },
  118 + { DDRC_FREQ2_DRAMTMG5(0), 0x0d0e0504 },
  119 + { DDRC_FREQ2_DRAMTMG6(0), 0x0a060004 },
  120 + { DDRC_FREQ2_DRAMTMG7(0), 0x0000090e },
  121 + { DDRC_FREQ2_DRAMTMG14(0), 0x00000032 },
  122 + { DDRC_FREQ2_DRAMTMG17(0), 0x0036001b },
  123 + { DDRC_FREQ2_DERATEINT(0), 0x7e9fbeb1 },
  124 + { DDRC_FREQ2_DFITMG0(0), 0x03818200 },
  125 + { DDRC_FREQ2_DFITMG2(0), 0x00000000 },
  126 + { DDRC_FREQ2_RFSHTMG(0), 0x00030007 },
  127 + { DDRC_FREQ2_INIT3(0), 0x00840000 },
  128 + { DDRC_FREQ2_INIT4(0), 0x00310008 },
  129 + { DDRC_FREQ2_INIT6(0), 0x0066004a },
  130 + { DDRC_FREQ2_INIT7(0), 0x0006004a },
  131 +};
  132 +
  133 +/* PHY Initialize Configuration */
  134 +struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
  135 + { 0x20110, 0x02 },
  136 + { 0x20111, 0x03 },
  137 + { 0x20112, 0x04 },
  138 + { 0x20113, 0x05 },
  139 + { 0x20114, 0x00 },
  140 + { 0x20115, 0x01 },
  141 +
  142 + { 0x1005f, 0x1ff },
  143 + { 0x1015f, 0x1ff },
  144 + { 0x1105f, 0x1ff },
  145 + { 0x1115f, 0x1ff },
  146 + { 0x1205f, 0x1ff },
  147 + { 0x1215f, 0x1ff },
  148 + { 0x1305f, 0x1ff },
  149 + { 0x1315f, 0x1ff },
  150 +
  151 + { 0x11005f, 0x1ff },
  152 + { 0x11015f, 0x1ff },
  153 + { 0x11105f, 0x1ff },
  154 + { 0x11115f, 0x1ff },
  155 + { 0x11205f, 0x1ff },
  156 + { 0x11215f, 0x1ff },
  157 + { 0x11305f, 0x1ff },
  158 + { 0x11315f, 0x1ff },
  159 +
  160 + { 0x21005f, 0x1ff },
  161 + { 0x21015f, 0x1ff },
  162 + { 0x21105f, 0x1ff },
  163 + { 0x21115f, 0x1ff },
  164 + { 0x21205f, 0x1ff },
  165 + { 0x21215f, 0x1ff },
  166 + { 0x21305f, 0x1ff },
  167 + { 0x21315f, 0x1ff },
  168 +
  169 + { 0x55, 0x1ff },
  170 + { 0x1055, 0x1ff },
  171 + { 0x2055, 0x1ff },
  172 + { 0x3055, 0x1ff },
  173 + { 0x4055, 0x1ff },
  174 + { 0x5055, 0x1ff },
  175 + { 0x6055, 0x1ff },
  176 + { 0x7055, 0x1ff },
  177 + { 0x8055, 0x1ff },
  178 + { 0x9055, 0x1ff },
  179 +
  180 + { 0x200c5, 0x19 },
  181 + { 0x1200c5, 0x7 },
  182 + { 0x2200c5, 0x7 },
  183 +
  184 + { 0x2002e, 0x2 },
  185 + { 0x12002e, 0x2 },
  186 + { 0x22002e, 0x2 },
  187 +
  188 + { 0x90204, 0x0 },
  189 + { 0x190204, 0x0 },
  190 + { 0x290204, 0x0 },
  191 +
  192 +#ifdef WR_POST_EXT_3200
  193 + { 0x20024, 0xeb },
  194 +#else
  195 + { 0x20024, 0xab },
  196 +#endif
  197 + { 0x2003a, 0x0 },
  198 + { 0x120024, 0xab },
  199 + { 0x2003a, 0x0 },
  200 + { 0x220024, 0xab },
  201 + { 0x2003a, 0x0 },
  202 + { 0x20056, 0x3 },
  203 + { 0x120056, 0xa },
  204 + { 0x220056, 0xa },
  205 + { 0x1004d, 0xe00 },
  206 + { 0x1014d, 0xe00 },
  207 + { 0x1104d, 0xe00 },
  208 + { 0x1114d, 0xe00 },
  209 + { 0x1204d, 0xe00 },
  210 + { 0x1214d, 0xe00 },
  211 + { 0x1304d, 0xe00 },
  212 + { 0x1314d, 0xe00 },
  213 + { 0x11004d, 0xe00 },
  214 + { 0x11014d, 0xe00 },
  215 + { 0x11104d, 0xe00 },
  216 + { 0x11114d, 0xe00 },
  217 + { 0x11204d, 0xe00 },
  218 + { 0x11214d, 0xe00 },
  219 + { 0x11304d, 0xe00 },
  220 + { 0x11314d, 0xe00 },
  221 + { 0x21004d, 0xe00 },
  222 + { 0x21014d, 0xe00 },
  223 + { 0x21104d, 0xe00 },
  224 + { 0x21114d, 0xe00 },
  225 + { 0x21204d, 0xe00 },
  226 + { 0x21214d, 0xe00 },
  227 + { 0x21304d, 0xe00 },
  228 + { 0x21314d, 0xe00 },
  229 +
  230 + { 0x10049, 0xfbe },
  231 + { 0x10149, 0xfbe },
  232 + { 0x11049, 0xfbe },
  233 + { 0x11149, 0xfbe },
  234 + { 0x12049, 0xfbe },
  235 + { 0x12149, 0xfbe },
  236 + { 0x13049, 0xfbe },
  237 + { 0x13149, 0xfbe },
  238 + { 0x110049, 0xfbe },
  239 + { 0x110149, 0xfbe },
  240 + { 0x111049, 0xfbe },
  241 + { 0x111149, 0xfbe },
  242 + { 0x112049, 0xfbe },
  243 + { 0x112149, 0xfbe },
  244 + { 0x113049, 0xfbe },
  245 + { 0x113149, 0xfbe },
  246 + { 0x210049, 0xfbe },
  247 + { 0x210149, 0xfbe },
  248 + { 0x211049, 0xfbe },
  249 + { 0x211149, 0xfbe },
  250 + { 0x212049, 0xfbe },
  251 + { 0x212149, 0xfbe },
  252 + { 0x213049, 0xfbe },
  253 + { 0x213149, 0xfbe },
  254 +
  255 + { 0x43, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
  256 + { 0x1043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
  257 + { 0x2043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
  258 + { 0x3043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
  259 + { 0x4043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
  260 + { 0x5043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
  261 + { 0x6043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
  262 + { 0x7043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
  263 + { 0x8043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
  264 + { 0x9043, ((LPDDR4_PHY_ADDR_RON << 5) | LPDDR4_PHY_ADDR_RON) },
  265 +
  266 + { 0x20018, 0x3 },
  267 + { 0x20075, 0x4 },
  268 + { 0x20050, 0x0 },
  269 + { 0x20008, 0x320 },
  270 + { 0x120008, 0x64 },
  271 + { 0x220008, 0x19 },
  272 + { 0x20088, 0x9 },
  273 + { 0x200b2, 0x104 },
  274 + { 0x10043, 0x5a1 },
  275 + { 0x10143, 0x5a1 },
  276 + { 0x11043, 0x5a1 },
  277 + { 0x11143, 0x5a1 },
  278 + { 0x12043, 0x5a1 },
  279 + { 0x12143, 0x5a1 },
  280 + { 0x13043, 0x5a1 },
  281 + { 0x13143, 0x5a1 },
  282 + { 0x1200b2, 0x104 },
  283 + { 0x110043, 0x5a1 },
  284 + { 0x110143, 0x5a1 },
  285 + { 0x111043, 0x5a1 },
  286 + { 0x111143, 0x5a1 },
  287 + { 0x112043, 0x5a1 },
  288 + { 0x112143, 0x5a1 },
  289 + { 0x113043, 0x5a1 },
  290 + { 0x113143, 0x5a1 },
  291 + { 0x2200b2, 0x104 },
  292 + { 0x210043, 0x5a1 },
  293 + { 0x210143, 0x5a1 },
  294 + { 0x211043, 0x5a1 },
  295 + { 0x211143, 0x5a1 },
  296 + { 0x212043, 0x5a1 },
  297 + { 0x212143, 0x5a1 },
  298 + { 0x213043, 0x5a1 },
  299 + { 0x213143, 0x5a1 },
  300 + { 0x200fa, 0x1 },
  301 + { 0x1200fa, 0x1 },
  302 + { 0x2200fa, 0x1 },
  303 + { 0x20019, 0x1 },
  304 + { 0x120019, 0x1 },
  305 + { 0x220019, 0x1 },
  306 + { 0x200f0, 0x660 },
  307 + { 0x200f1, 0x0 },
  308 + { 0x200f2, 0x4444 },
  309 + { 0x200f3, 0x8888 },
  310 + { 0x200f4, 0x5665 },
  311 + { 0x200f5, 0x0 },
  312 + { 0x200f6, 0x0 },
  313 + { 0x200f7, 0xf000 },
  314 + { 0x20025, 0x0 },
  315 + { 0x2002d, 0x0 },
  316 + { 0x12002d, 0x0 },
  317 + { 0x22002d, 0x0 },
  318 +
  319 + { 0x200c7, 0x80 },
  320 + { 0x1200c7, 0x80 },
  321 + { 0x2200c7, 0x80 },
  322 + { 0x200ca, 0x106 },
  323 + { 0x1200ca, 0x106 },
  324 + { 0x2200ca, 0x106 },
  325 +};
  326 +
  327 +/* P0 message block paremeter for training firmware */
  328 +struct dram_cfg_param lpddr4_fsp0_cfg[] = {
  329 + { 0xd0000, 0x0 },
  330 + { 0x54000, 0x0 },
  331 + { 0x54001, 0x0 },
  332 + { 0x54002, 0x0 },
  333 + { 0x54003, 0xc80 },
  334 + { 0x54004, 0x2 },
  335 + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) }, /* PHY Ron/Rtt */
  336 + { 0x54006, LPDDR4_PHY_VREF_VALUE },
  337 + { 0x54007, 0x0 },
  338 + { 0x54008, 0x131f },
  339 + { 0x54009, LPDDR4_HDT_CTL_3200_1D },
  340 + { 0x5400a, 0x0 },
  341 + { 0x5400b, 0x2 },
  342 + { 0x5400c, 0x0 },
  343 + { 0x5400d, (LPDDR4_CATRAIN_3200_1d << 8) },
  344 + { 0x5400e, 0x0 },
  345 + { 0x5400f, 0x0 },
  346 + { 0x54010, 0x0 },
  347 + { 0x54011, 0x0 },
  348 + { 0x54012, 0x310 },
  349 + { 0x54013, 0x0 },
  350 + { 0x54014, 0x0 },
  351 + { 0x54015, 0x0 },
  352 + { 0x54016, 0x0 },
  353 + { 0x54017, 0x0 },
  354 + { 0x54018, 0x0 },
  355 +
  356 + { 0x54019, 0x2dd4 },
  357 +#ifdef WR_POST_EXT_3200
  358 + { 0x5401a, (((LPDDR4_RON) << 3) | 0x3) },
  359 +#else
  360 + { 0x5401a, (((LPDDR4_RON) << 3) | 0x1) },
  361 +#endif
  362 + { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) |
  363 + (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) },
  364 + { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) },
  365 + { 0x5401d, 0x0 },
  366 + { 0x5401e, LPDDR4_MR22_RANK0 },
  367 + { 0x5401f, 0x2dd4 },
  368 +#ifdef WR_POST_EXT_3200
  369 + { 0x54020, (((LPDDR4_RON) << 3) | 0x3) },
  370 +#else
  371 + { 0x54020, (((LPDDR4_RON) << 3) | 0x1) },
  372 +#endif
  373 + { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) |
  374 + (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) },
  375 + { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) },
  376 + { 0x54023, 0x0 },
  377 + { 0x54024, LPDDR4_MR22_RANK1 },
  378 +
  379 + { 0x54025, 0x0 },
  380 + { 0x54026, 0x0 },
  381 + { 0x54027, 0x0 },
  382 + { 0x54028, 0x0 },
  383 + { 0x54029, 0x0 },
  384 + { 0x5402a, 0x0 },
  385 + { 0x5402b, 0x1000 },
  386 + { 0x5402c, 0x3 },
  387 + { 0x5402d, 0x0 },
  388 + { 0x5402e, 0x0 },
  389 + { 0x5402f, 0x0 },
  390 + { 0x54030, 0x0 },
  391 + { 0x54031, 0x0 },
  392 + { 0x54032, 0xd400 },
  393 + /* MR3/MR2 */
  394 +#ifdef WR_POST_EXT_3200
  395 + { 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d /*0x312d*/ },
  396 +#else
  397 + { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d/*0x312d*/ },
  398 +#endif
  399 + /* MR11/MR4 */
  400 + { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) },
  401 + /* self:0x284d//MR13/MR12 */
  402 + { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA)/*0x084d*/ },
  403 + /* MR16/MR14*/
  404 + { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0/*0x4d*/ },
  405 + { 0x54037, (LPDDR4_MR22_RANK0 << 8)/*0x500*/ },
  406 + /* MR1 */
  407 + { 0x54038, 0xd400 },
  408 + /* MR3/MR2 */
  409 +#ifdef WR_POST_EXT_3200
  410 + { 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d/*0x312d*/ },
  411 +#else
  412 + { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d/*0x312d*/ },
  413 +#endif
  414 + /* MR11/MR4 */
  415 + { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) },
  416 + /* self:0x284d//MR13/MR12 */
  417 + { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA)/*0x084d*/ },
  418 + /* MR16/MR14 */
  419 + { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1/*0x4d*/ },
  420 + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x500*/ },
  421 + /* { 0x5403d, 0x500 } */
  422 + { 0x5403d, (LPDDR4_MR22_RANK1 << 8)/*0x500*/ },
  423 + { 0x5403e, 0x0 },
  424 + { 0x5403f, 0x0 },
  425 + { 0x54040, 0x0 },
  426 + { 0x54041, 0x0 },
  427 + { 0x54042, 0x0 },
  428 + { 0x54043, 0x0 },
  429 + { 0x54044, 0x0 },
  430 + { 0xd0000, 0x1 },
  431 +};
  432 +
  433 +/* P1 message block paremeter for training firmware */
  434 +struct dram_cfg_param lpddr4_fsp1_cfg[] = {
  435 + { 0xd0000, 0x0 },
  436 + { 0x54000, 0x0 },
  437 + { 0x54001, 0x0 },
  438 + { 0x54002, 0x101 },
  439 + { 0x54003, 0x190 },
  440 + { 0x54004, 0x2 },
  441 + /* PHY Ron/Rtt */
  442 + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT)/*0x2828*/ },
  443 + { 0x54006, LPDDR4_PHY_VREF_VALUE },
  444 + { 0x54007, 0x0 },
  445 + { 0x54008, LPDDR4_TRAIN_SEQ_400 },
  446 + { 0x54009, LPDDR4_HDT_CTL_400_1D },
  447 + { 0x5400a, 0x0 },
  448 + { 0x5400b, 0x2 },
  449 + { 0x5400c, 0x0 },
  450 + { 0x5400d, (LPDDR4_CATRAIN_400 << 8) },
  451 + { 0x5400e, 0x0 },
  452 + { 0x5400f, 0x0 },
  453 + { 0x54010, 0x0 },
  454 + { 0x54011, 0x0 },
  455 + { 0x54012, 0x310 },
  456 + { 0x54013, 0x0 },
  457 + { 0x54014, 0x0 },
  458 + { 0x54015, 0x0 },
  459 + { 0x54016, 0x0 },
  460 + { 0x54017, 0x0 },
  461 + { 0x54018, 0x0 },
  462 + { 0x54019, 0x84 },
  463 + /* MR4/MR3 */
  464 + { 0x5401a, (((LPDDR4_RON) << 3) | 0x1)/*0x31*/ },
  465 + /* MR12/MR11 */
  466 + { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) |
  467 + LPDDR4_RTT_DQ)/*0x4d46*/ },
  468 + /* self:0x4d28//MR14/MR13 */
  469 + { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08)/*0x4d08*/ },
  470 + { 0x5401d, 0x0 },
  471 + { 0x5401e, LPDDR4_MR22_RANK0/*0x5*/ },
  472 + { 0x5401f, 0x84 },
  473 + { 0x54020, (((LPDDR4_RON) << 3) | 0x1)/*0x31*/ }, /* MR4/MR3 */
  474 + { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) |
  475 + LPDDR4_RTT_DQ)/*0x4d46*/ },/* MR12/MR11 */
  476 + /* self:0x4d28//MR14/MR13 */
  477 + { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08)/*0x4d08*/ },
  478 + { 0x54023, 0x0 },
  479 + { 0x54024, LPDDR4_MR22_RANK1 },
  480 + { 0x54025, 0x0 },
  481 + { 0x54026, 0x0 },
  482 + { 0x54027, 0x0 },
  483 + { 0x54028, 0x0 },
  484 + { 0x54029, 0x0 },
  485 + { 0x5402a, 0x0 },
  486 + { 0x5402b, 0x1000 },
  487 + { 0x5402c, 0x3 },
  488 + { 0x5402d, 0x0 },
  489 + { 0x5402e, 0x0 },
  490 + { 0x5402f, 0x0 },
  491 + { 0x54030, 0x0 },
  492 + { 0x54031, 0x0 },
  493 + { 0x54032, 0x8400 },
  494 + { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 },
  495 + { 0x54034, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) },
  496 + { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) },
  497 + { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 },
  498 + { 0x54037, (LPDDR4_MR22_RANK0 << 8) },
  499 + { 0x54038, 0x8400 },
  500 + { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 },
  501 + { 0x5403a, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) },
  502 + { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) },
  503 + { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 },
  504 + { 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
  505 + { 0x5403e, 0x0 },
  506 + { 0x5403f, 0x0 },
  507 + { 0x54040, 0x0 },
  508 + { 0x54041, 0x0 },
  509 + { 0x54042, 0x0 },
  510 + { 0x54043, 0x0 },
  511 + { 0x54044, 0x0 },
  512 + { 0xd0000, 0x1 },
  513 +};
  514 +
  515 +/* P2 message block paremeter for training firmware */
  516 +struct dram_cfg_param lpddr4_fsp2_cfg[] = {
  517 + { 0xd0000, 0x0 },
  518 + { 0x54000, 0x0 },
  519 + { 0x54001, 0x0 },
  520 + { 0x54002, 0x102 },
  521 + { 0x54003, 0x64 },
  522 + { 0x54004, 0x2 },
  523 + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },
  524 + { 0x54006, LPDDR4_PHY_VREF_VALUE },
  525 + { 0x54007, 0x0 },
  526 + { 0x54008, LPDDR4_TRAIN_SEQ_100 },
  527 + { 0x54009, LPDDR4_HDT_CTL_100_1D },
  528 + { 0x5400a, 0x0 },
  529 + { 0x5400b, 0x2 },
  530 + { 0x5400c, 0x0 },
  531 + { 0x5400d, (LPDDR4_CATRAIN_100 << 8) },
  532 + { 0x5400e, 0x0 },
  533 + { 0x5400f, 0x0 },
  534 + { 0x54010, 0x0 },
  535 + { 0x54011, 0x0 },
  536 + { 0x54012, 0x310 },
  537 + { 0x54013, 0x0 },
  538 + { 0x54014, 0x0 },
  539 + { 0x54015, 0x0 },
  540 + { 0x54016, 0x0 },
  541 + { 0x54017, 0x0 },
  542 + { 0x54018, 0x0 },
  543 + { 0x54019, 0x84 },
  544 + { 0x5401a, (((LPDDR4_RON) << 3) | 0x1) },
  545 + { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) |
  546 + LPDDR4_RTT_DQ) },
  547 + { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) },
  548 + { 0x5401d, 0x0 },
  549 + { 0x5401e, LPDDR4_MR22_RANK0 },
  550 + { 0x5401f, 0x84 },
  551 + { 0x54020, (((LPDDR4_RON) << 3) | 0x1) },
  552 + { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) | (LPDDR4_RTT_CA << 4) |
  553 + LPDDR4_RTT_DQ) },
  554 + { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) },
  555 + { 0x54023, 0x0 },
  556 + { 0x54024, LPDDR4_MR22_RANK1 },
  557 + { 0x54025, 0x0 },
  558 + { 0x54026, 0x0 },
  559 + { 0x54027, 0x0 },
  560 + { 0x54028, 0x0 },
  561 + { 0x54029, 0x0 },
  562 + { 0x5402a, 0x0 },
  563 + { 0x5402b, 0x1000 },
  564 + { 0x5402c, 0x3 },
  565 + { 0x5402d, 0x0 },
  566 + { 0x5402e, 0x0 },
  567 + { 0x5402f, 0x0 },
  568 + { 0x54030, 0x0 },
  569 + { 0x54031, 0x0 },
  570 + { 0x54032, 0x8400 },
  571 + { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 },
  572 + { 0x54034, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) },
  573 + { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) },
  574 + { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 },
  575 + { 0x54037, (LPDDR4_MR22_RANK0 << 8) },
  576 + { 0x54038, 0x8400 },
  577 + { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x00 },
  578 + { 0x5403a, (((LPDDR4_RTT_CA << 4) | LPDDR4_RTT_DQ) << 8) },
  579 + { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) },
  580 + { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 },
  581 + { 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
  582 + { 0x5403e, 0x0 },
  583 + { 0x5403f, 0x0 },
  584 + { 0x54040, 0x0 },
  585 + { 0x54041, 0x0 },
  586 + { 0x54042, 0x0 },
  587 + { 0x54043, 0x0 },
  588 + { 0x54044, 0x0 },
  589 + { 0xd0000, 0x1 },
  590 +};
  591 +
  592 +/* P0 2D message block paremeter for training firmware */
  593 +struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {
  594 + { 0xd0000, 0x0 },
  595 + { 0x54000, 0x0 },
  596 + { 0x54001, 0x0 },
  597 + { 0x54002, 0x0 },
  598 + { 0x54003, 0xc80 },
  599 + { 0x54004, 0x2 },
  600 + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },
  601 + { 0x54006, LPDDR4_PHY_VREF_VALUE },
  602 + { 0x54007, 0x0 },
  603 + { 0x54008, 0x61 },
  604 + { 0x54009, LPDDR4_HDT_CTL_2D },
  605 + { 0x5400a, 0x0 },
  606 + { 0x5400b, 0x2 },
  607 + { 0x5400c, 0x0 },
  608 + { 0x5400d, (LPDDR4_CATRAIN_3200_2d << 8) },
  609 + { 0x5400e, 0x0 },
  610 + { 0x5400f, (LPDDR4_2D_SHARE << 8) | 0x00 },
  611 + { 0x54010, LPDDR4_2D_WEIGHT },
  612 + { 0x54011, 0x0 },
  613 + { 0x54012, 0x310 },
  614 + { 0x54013, 0x0 },
  615 + { 0x54014, 0x0 },
  616 + { 0x54015, 0x0 },
  617 + { 0x54016, 0x0 },
  618 + { 0x54017, 0x0 },
  619 + { 0x54018, 0x0 },
  620 + { 0x54019, 0x2dd4 },
  621 +#ifdef WR_POST_EXT_3200
  622 + { 0x5401a, (((LPDDR4_RON) << 3) | 0x3) },
  623 +#else
  624 + { 0x5401a, (((LPDDR4_RON) << 3) | 0x1) },
  625 +#endif
  626 + { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) |
  627 + (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) },
  628 + { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) },
  629 + { 0x5401d, 0x0 },
  630 + { 0x5401e, LPDDR4_MR22_RANK0 },
  631 + { 0x5401f, 0x2dd4 },
  632 +#ifdef WR_POST_EXT_3200
  633 + { 0x54020, (((LPDDR4_RON) << 3) | 0x3) },
  634 +#else
  635 + { 0x54020, (((LPDDR4_RON) << 3) | 0x1) },
  636 +#endif
  637 + { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) |
  638 + (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) },
  639 + { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) },
  640 + { 0x54023, 0x0 },
  641 + { 0x54024, LPDDR4_MR22_RANK1 },
  642 + { 0x54025, 0x0 },
  643 + { 0x54026, 0x0 },
  644 + { 0x54027, 0x0 },
  645 + { 0x54028, 0x0 },
  646 + { 0x54029, 0x0 },
  647 + { 0x5402a, 0x0 },
  648 + { 0x5402b, 0x1000 },
  649 + { 0x5402c, 0x3 },
  650 + { 0x5402d, 0x0 },
  651 + { 0x5402e, 0x0 },
  652 + { 0x5402f, 0x0 },
  653 + { 0x54030, 0x0 },
  654 + { 0x54031, 0x0 },
  655 +
  656 + { 0x54032, 0xd400 },
  657 +#ifdef WR_POST_EXT_3200
  658 + { 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d },
  659 +#else
  660 + { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d },
  661 +#endif
  662 + { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) },
  663 + { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) },
  664 + { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 },
  665 + { 0x54037, (LPDDR4_MR22_RANK0 << 8) },
  666 + { 0x54038, 0xd400 },
  667 +#ifdef WR_POST_EXT_3200
  668 + { 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d },
  669 +#else
  670 + { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x2d },
  671 +#endif
  672 + { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) },
  673 + { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) },
  674 + { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 },
  675 + { 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
  676 + { 0x5403e, 0x0 },
  677 + { 0x5403f, 0x0 },
  678 + { 0x54040, 0x0 },
  679 + { 0x54041, 0x0 },
  680 + { 0x54042, 0x0 },
  681 + { 0x54043, 0x0 },
  682 + { 0x54044, 0x0 },
  683 + { 0xd0000, 0x1 },
  684 +};
  685 +
  686 +/* DRAM PHY init engine image */
  687 +struct dram_cfg_param lpddr4_phy_pie[] = {
  688 + { 0xd0000, 0x0 },
  689 + { 0x90000, 0x10 },
  690 + { 0x90001, 0x400 },
  691 + { 0x90002, 0x10e },
  692 + { 0x90003, 0x0 },
  693 + { 0x90004, 0x0 },
  694 + { 0x90005, 0x8 },
  695 + { 0x90029, 0xb },
  696 + { 0x9002a, 0x480 },
  697 + { 0x9002b, 0x109 },
  698 + { 0x9002c, 0x8 },
  699 + { 0x9002d, 0x448 },
  700 + { 0x9002e, 0x139 },
  701 + { 0x9002f, 0x8 },
  702 + { 0x90030, 0x478 },
  703 + { 0x90031, 0x109 },
  704 + { 0x90032, 0x0 },
  705 + { 0x90033, 0xe8 },
  706 + { 0x90034, 0x109 },
  707 + { 0x90035, 0x2 },
  708 + { 0x90036, 0x10 },
  709 + { 0x90037, 0x139 },
  710 + { 0x90038, 0xf },
  711 + { 0x90039, 0x7c0 },
  712 + { 0x9003a, 0x139 },
  713 + { 0x9003b, 0x44 },
  714 + { 0x9003c, 0x630 },
  715 + { 0x9003d, 0x159 },
  716 + { 0x9003e, 0x14f },
  717 + { 0x9003f, 0x630 },
  718 + { 0x90040, 0x159 },
  719 + { 0x90041, 0x47 },
  720 + { 0x90042, 0x630 },
  721 + { 0x90043, 0x149 },
  722 + { 0x90044, 0x4f },
  723 + { 0x90045, 0x630 },
  724 + { 0x90046, 0x179 },
  725 + { 0x90047, 0x8 },
  726 + { 0x90048, 0xe0 },
  727 + { 0x90049, 0x109 },
  728 + { 0x9004a, 0x0 },
  729 + { 0x9004b, 0x7c8 },
  730 + { 0x9004c, 0x109 },
  731 + { 0x9004d, 0x0 },
  732 + { 0x9004e, 0x1 },
  733 + { 0x9004f, 0x8 },
  734 + { 0x90050, 0x0 },
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  841 + { 0x40005, 0x16 },
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  847 + { 0x40046, 0x2001 },
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  851 + { 0x40047, 0x2800 },
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  853 + { 0x40008, 0x716 },
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  856 + { 0x40068, 0x0 },
  857 + { 0x40009, 0x720 },
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  859 + { 0x40049, 0x1400 },
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  861 + { 0x4000a, 0xe08 },
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  866 + { 0x4002b, 0x15 },
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  869 + { 0x4000c, 0x4028 },
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  1224 + { 0x102b4, 0x1 },
  1225 + { 0x103b4, 0x1 },
  1226 + { 0x104b4, 0x1 },
  1227 + { 0x105b4, 0x1 },
  1228 + { 0x106b4, 0x1 },
  1229 + { 0x107b4, 0x1 },
  1230 + { 0x108b4, 0x1 },
  1231 + { 0x11011, 0x1 },
  1232 + { 0x11012, 0x1 },
  1233 + { 0x11013, 0x180 },
  1234 + { 0x11018, 0x1 },
  1235 + { 0x11002, 0x6209 },
  1236 + { 0x110b2, 0x1 },
  1237 + { 0x111b4, 0x1 },
  1238 + { 0x112b4, 0x1 },
  1239 + { 0x113b4, 0x1 },
  1240 + { 0x114b4, 0x1 },
  1241 + { 0x115b4, 0x1 },
  1242 + { 0x116b4, 0x1 },
  1243 + { 0x117b4, 0x1 },
  1244 + { 0x118b4, 0x1 },
  1245 + { 0x12011, 0x1 },
  1246 + { 0x12012, 0x1 },
  1247 + { 0x12013, 0x180 },
  1248 + { 0x12018, 0x1 },
  1249 + { 0x12002, 0x6209 },
  1250 + { 0x120b2, 0x1 },
  1251 + { 0x121b4, 0x1 },
  1252 + { 0x122b4, 0x1 },
  1253 + { 0x123b4, 0x1 },
  1254 + { 0x124b4, 0x1 },
  1255 + { 0x125b4, 0x1 },
  1256 + { 0x126b4, 0x1 },
  1257 + { 0x127b4, 0x1 },
  1258 + { 0x128b4, 0x1 },
  1259 + { 0x13011, 0x1 },
  1260 + { 0x13012, 0x1 },
  1261 + { 0x13013, 0x180 },
  1262 + { 0x13018, 0x1 },
  1263 + { 0x13002, 0x6209 },
  1264 + { 0x130b2, 0x1 },
  1265 + { 0x131b4, 0x1 },
  1266 + { 0x132b4, 0x1 },
  1267 + { 0x133b4, 0x1 },
  1268 + { 0x134b4, 0x1 },
  1269 + { 0x135b4, 0x1 },
  1270 + { 0x136b4, 0x1 },
  1271 + { 0x137b4, 0x1 },
  1272 + { 0x138b4, 0x1 },
  1273 + { 0x2003a, 0x2 },
  1274 + { 0xc0080, 0x2 },
  1275 + { 0xd0000, 0x1 },
  1276 +};
  1277 +
  1278 +struct dram_fsp_msg lpddr4_dram_fsp_msg[] = {
  1279 + {
  1280 + /* P0 3200mts 1D */
  1281 + .drate = 3200,
  1282 + .fw_type = FW_1D_IMAGE,
  1283 + .fsp_cfg = lpddr4_fsp0_cfg,
  1284 + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg),
  1285 + },
  1286 + {
  1287 + /* P1 400mts 1D */
  1288 + .drate = 400,
  1289 + .fw_type = FW_1D_IMAGE,
  1290 + .fsp_cfg = lpddr4_fsp1_cfg,
  1291 + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg),
  1292 + },
  1293 + {
  1294 + /* P1 100mts 1D */
  1295 + .drate = 100,
  1296 + .fw_type = FW_1D_IMAGE,
  1297 + .fsp_cfg = lpddr4_fsp2_cfg,
  1298 + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp2_cfg),
  1299 + },
  1300 + {
  1301 + /* P0 3200mts 2D */
  1302 + .drate = 3200,
  1303 + .fw_type = FW_2D_IMAGE,
  1304 + .fsp_cfg = lpddr4_fsp0_2d_cfg,
  1305 + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg),
  1306 + },
  1307 +};
  1308 +
  1309 +/* lpddr4 timing config params on EVK board */
  1310 +struct dram_timing_info dram_timing = {
  1311 + .ddrc_cfg = lpddr4_ddrc_cfg,
  1312 + .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg),
  1313 + .ddrphy_cfg = lpddr4_ddrphy_cfg,
  1314 + .ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg),
  1315 + .fsp_msg = lpddr4_dram_fsp_msg,
  1316 + .fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg),
  1317 + .ddrphy_pie = lpddr4_phy_pie,
  1318 + .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie),
  1319 + .fsp_table = { 3200, 400, 100, },
  1320 +};
board/freescale/imx8mq_evk/lpddr4_timing_b0.c
Diff comments   View file @ 86ac7a9
Changes suppressed. Click to show
  1 +// SPDX-License-Identifier: GPL-2.0+
  2 +/*
  3 + * Copyright 2018 NXP
  4 + */
  5 +
  6 +#include <linux/kernel.h>
  7 +#include <common.h>
  8 +#include <asm/arch/ddr.h>
  9 +#include <asm/arch/lpddr4_define.h>
  10 +
  11 +#define WR_POST_EXT_3200 /* recommened to define */
  12 +
  13 +static struct dram_cfg_param lpddr4_ddrc_cfg[] = {
  14 + /* Start to config, default 3200mbps */
  15 + /* dis_dq=1, indicates no reads or writes are issued to SDRAM */
  16 + { DDRC_DBG1(0), 0x00000001 },
  17 + /* selfref_en=1, SDRAM enter self-refresh state */
  18 + { DDRC_PWRCTL(0), 0x00000001 },
  19 + { DDRC_MSTR(0), 0xa3080020 },
  20 + { DDRC_MSTR2(0), 0x00000000 },
  21 + { DDRC_RFSHTMG(0), 0x006100E0 },
  22 + { DDRC_INIT0(0), 0xC003061B },
  23 + { DDRC_INIT1(0), 0x009D0000 },
  24 + { DDRC_INIT3(0), 0x00D4002D },
  25 +#ifdef WR_POST_EXT_3200 /* recommened to define */
  26 + { DDRC_INIT4(0), 0x00330008 },
  27 +#else
  28 + { DDRC_INIT4(0), 0x00310008 },
  29 +#endif
  30 + { DDRC_INIT6(0), 0x0066004a },
  31 + { DDRC_INIT7(0), 0x0006004a },
  32 +
  33 + { DDRC_DRAMTMG0(0), 0x1A201B22 },
  34 + { DDRC_DRAMTMG1(0), 0x00060633 },
  35 + { DDRC_DRAMTMG3(0), 0x00C0C000 },
  36 + { DDRC_DRAMTMG4(0), 0x0F04080F },
  37 + { DDRC_DRAMTMG5(0), 0x02040C0C },
  38 + { DDRC_DRAMTMG6(0), 0x01010007 },
  39 + { DDRC_DRAMTMG7(0), 0x00000401 },
  40 + { DDRC_DRAMTMG12(0), 0x00020600 },
  41 + { DDRC_DRAMTMG13(0), 0x0C100002 },
  42 + { DDRC_DRAMTMG14(0), 0x000000E6 },
  43 + { DDRC_DRAMTMG17(0), 0x00A00050 },
  44 +
  45 + { DDRC_ZQCTL0(0), 0x03200018 },
  46 + { DDRC_ZQCTL1(0), 0x028061A8 },
  47 + { DDRC_ZQCTL2(0), 0x00000000 },
  48 +
  49 + { DDRC_DFITMG0(0), 0x0497820A },
  50 + { DDRC_DFITMG1(0), 0x00080303 },
  51 + { DDRC_DFIUPD0(0), 0xE0400018 },
  52 + { DDRC_DFIUPD1(0), 0x00DF00E4 },
  53 + { DDRC_DFIUPD2(0), 0x80000000 },
  54 + { DDRC_DFIMISC(0), 0x00000011 },
  55 + { DDRC_DFITMG2(0), 0x0000170A },
  56 +
  57 + { DDRC_DBICTL(0), 0x00000001 },
  58 + { DDRC_DFIPHYMSTR(0), 0x00000001 },
  59 +
  60 + /* need be refined by ddrphy trained value */
  61 + { DDRC_RANKCTL(0), 0x00000c99 },
  62 + { DDRC_DRAMTMG2(0), 0x070E171a },
  63 +
  64 + /* address mapping */
  65 + /* Address map is from MSB 29: r15, r14, cs, r13-r0, b2-b0, c9-c0 */
  66 + { DDRC_ADDRMAP0(0), 0x00000015 },
  67 + { DDRC_ADDRMAP3(0), 0x00000000 },
  68 + /* addrmap_col_b10 addrmap_col_b11 set to de-activated (5-bit width) */
  69 + { DDRC_ADDRMAP4(0), 0x00001F1F },
  70 + /* bank interleave */
  71 + /* addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 */
  72 + { DDRC_ADDRMAP1(0), 0x00080808 },
  73 + /* addrmap_row_b11 addrmap_row_b10_b2 addrmap_row_b1 addrmap_row_b0 */
  74 + { DDRC_ADDRMAP5(0), 0x07070707 },
  75 + /* addrmap_row_b15 addrmap_row_b14 addrmap_row_b13 addrmap_row_b12 */
  76 + { DDRC_ADDRMAP6(0), 0x08080707 },
  77 +
  78 + /* 667mts frequency setting */
  79 + { DDRC_FREQ1_DERATEEN(0), 0x0000000 },
  80 + { DDRC_FREQ1_DERATEINT(0), 0x0800000 },
  81 + { DDRC_FREQ1_RFSHCTL0(0), 0x0210000 },
  82 + { DDRC_FREQ1_RFSHTMG(0), 0x014001E },
  83 + { DDRC_FREQ1_INIT3(0), 0x0140009 },
  84 + { DDRC_FREQ1_INIT4(0), 0x00310008 },
  85 + { DDRC_FREQ1_INIT6(0), 0x0066004a },
  86 + { DDRC_FREQ1_INIT7(0), 0x0006004a },
  87 + { DDRC_FREQ1_DRAMTMG0(0), 0xB070A07 },
  88 + { DDRC_FREQ1_DRAMTMG1(0), 0x003040A },
  89 + { DDRC_FREQ1_DRAMTMG2(0), 0x305080C },
  90 + { DDRC_FREQ1_DRAMTMG3(0), 0x0505000 },
  91 + { DDRC_FREQ1_DRAMTMG4(0), 0x3040203 },
  92 + { DDRC_FREQ1_DRAMTMG5(0), 0x2030303 },
  93 + { DDRC_FREQ1_DRAMTMG6(0), 0x2020004 },
  94 + { DDRC_FREQ1_DRAMTMG7(0), 0x0000302 },
  95 + { DDRC_FREQ1_DRAMTMG12(0), 0x0020310 },
  96 + { DDRC_FREQ1_DRAMTMG13(0), 0xA100002 },
  97 + { DDRC_FREQ1_DRAMTMG14(0), 0x0000020 },
  98 + { DDRC_FREQ1_DRAMTMG17(0), 0x0220011 },
  99 + { DDRC_FREQ1_ZQCTL0(0), 0x0A70005 },
  100 + { DDRC_FREQ1_DFITMG0(0), 0x3858202 },
  101 + { DDRC_FREQ1_DFITMG1(0), 0x0000404 },
  102 + { DDRC_FREQ1_DFITMG2(0), 0x0000502 },
  103 +
  104 + /* performance setting */
  105 + { DDRC_ODTCFG(0), 0x0b060908 },
  106 + { DDRC_ODTMAP(0), 0x00000000 },
  107 + { DDRC_SCHED(0), 0x29511505 },
  108 + { DDRC_SCHED1(0), 0x0000002c },
  109 + { DDRC_PERFHPR1(0), 0x5900575b },
  110 + /* 150T starve and 0x90 max tran len */
  111 + { DDRC_PERFLPR1(0), 0x90000096 },
  112 + /* 300T starve and 0x10 max tran len */
  113 + { DDRC_PERFWR1(0), 0x1000012c },
  114 + { DDRC_DBG0(0), 0x00000016 },
  115 + { DDRC_DBG1(0), 0x00000000 },
  116 + { DDRC_DBGCMD(0), 0x00000000 },
  117 + { DDRC_SWCTL(0), 0x00000001 },
  118 + { DDRC_POISONCFG(0), 0x00000011 },
  119 + { DDRC_PCCFG(0), 0x00000111 },
  120 + { DDRC_PCFGR_0(0), 0x000010f3 },
  121 + { DDRC_PCFGW_0(0), 0x000072ff },
  122 + { DDRC_PCTRL_0(0), 0x00000001 },
  123 + /* disable Read Qos*/
  124 + { DDRC_PCFGQOS0_0(0), 0x00000e00 },
  125 + { DDRC_PCFGQOS1_0(0), 0x0062ffff },
  126 + /* disable Write Qos*/
  127 + { DDRC_PCFGWQOS0_0(0), 0x00000e00 },
  128 + { DDRC_PCFGWQOS1_0(0), 0x0000ffff },
  129 + { DDRC_FREQ1_DERATEEN(0), 0x00000202 },
  130 + { DDRC_FREQ1_DERATEINT(0), 0xec78f4b5 },
  131 + { DDRC_FREQ1_RFSHCTL0(0), 0x00618040 },
  132 + { DDRC_FREQ1_RFSHTMG(0), 0x00610090 },
  133 +};
  134 +
  135 +/* PHY Initialize Configuration */
  136 +static struct dram_cfg_param lpddr4_ddrphy_cfg[] = {
  137 + { 0x20110, 0x02 }, /* MapCAB0toDFI */
  138 + { 0x20111, 0x03 }, /* MapCAB1toDFI */
  139 + { 0x20112, 0x04 }, /* MapCAB2toDFI */
  140 + { 0x20113, 0x05 }, /* MapCAB3toDFI */
  141 + { 0x20114, 0x00 }, /* MapCAB4toDFI */
  142 + { 0x20115, 0x01 }, /* MapCAB5toDFI */
  143 +
  144 + /* Initialize PHY Configuration */
  145 + { 0x1005f, 0x1ff },
  146 + { 0x1015f, 0x1ff },
  147 + { 0x1105f, 0x1ff },
  148 + { 0x1115f, 0x1ff },
  149 + { 0x1205f, 0x1ff },
  150 + { 0x1215f, 0x1ff },
  151 + { 0x1305f, 0x1ff },
  152 + { 0x1315f, 0x1ff },
  153 +
  154 + { 0x11005f, 0x1ff },
  155 + { 0x11015f, 0x1ff },
  156 + { 0x11105f, 0x1ff },
  157 + { 0x11115f, 0x1ff },
  158 + { 0x11205f, 0x1ff },
  159 + { 0x11215f, 0x1ff },
  160 + { 0x11305f, 0x1ff },
  161 + { 0x11315f, 0x1ff },
  162 +
  163 + { 0x21005f, 0x1ff },
  164 + { 0x21015f, 0x1ff },
  165 + { 0x21105f, 0x1ff },
  166 + { 0x21115f, 0x1ff },
  167 + { 0x21205f, 0x1ff },
  168 + { 0x21215f, 0x1ff },
  169 + { 0x21305f, 0x1ff },
  170 + { 0x21315f, 0x1ff },
  171 +
  172 + { 0x55, 0x1ff },
  173 + { 0x1055, 0x1ff },
  174 + { 0x2055, 0x1ff },
  175 + { 0x3055, 0x1ff },
  176 + { 0x4055, 0x1ff },
  177 + { 0x5055, 0x1ff },
  178 + { 0x6055, 0x1ff },
  179 + { 0x7055, 0x1ff },
  180 + { 0x8055, 0x1ff },
  181 + { 0x9055, 0x1ff },
  182 + { 0x200c5, 0x19 },
  183 + { 0x1200c5, 0x7 },
  184 + { 0x2200c5, 0x7 },
  185 + { 0x2002e, 0x2 },
  186 + { 0x12002e, 0x1 },
  187 + { 0x22002e, 0x2 },
  188 + { 0x90204, 0x0 },
  189 + { 0x190204, 0x0 },
  190 + { 0x290204, 0x0 },
  191 +
  192 + { 0x20024, 0xe3 },
  193 + { 0x2003a, 0x2 },
  194 + { 0x120024, 0xa3 },
  195 + { 0x2003a, 0x2 },
  196 + { 0x220024, 0xa3 },
  197 + { 0x2003a, 0x2 },
  198 +
  199 + { 0x20056, 0x3 },
  200 + { 0x120056, 0xa },
  201 + { 0x220056, 0xa },
  202 +
  203 + { 0x1004d, 0xe00 },
  204 + { 0x1014d, 0xe00 },
  205 + { 0x1104d, 0xe00 },
  206 + { 0x1114d, 0xe00 },
  207 + { 0x1204d, 0xe00 },
  208 + { 0x1214d, 0xe00 },
  209 + { 0x1304d, 0xe00 },
  210 + { 0x1314d, 0xe00 },
  211 + { 0x11004d, 0xe00 },
  212 + { 0x11014d, 0xe00 },
  213 + { 0x11104d, 0xe00 },
  214 + { 0x11114d, 0xe00 },
  215 + { 0x11204d, 0xe00 },
  216 + { 0x11214d, 0xe00 },
  217 + { 0x11304d, 0xe00 },
  218 + { 0x11314d, 0xe00 },
  219 + { 0x21004d, 0xe00 },
  220 + { 0x21014d, 0xe00 },
  221 + { 0x21104d, 0xe00 },
  222 + { 0x21114d, 0xe00 },
  223 + { 0x21204d, 0xe00 },
  224 + { 0x21214d, 0xe00 },
  225 + { 0x21304d, 0xe00 },
  226 + { 0x21314d, 0xe00 },
  227 +
  228 + { 0x10049, 0xfbe },
  229 + { 0x10149, 0xfbe },
  230 + { 0x11049, 0xfbe },
  231 + { 0x11149, 0xfbe },
  232 + { 0x12049, 0xfbe },
  233 + { 0x12149, 0xfbe },
  234 + { 0x13049, 0xfbe },
  235 + { 0x13149, 0xfbe },
  236 +
  237 + { 0x110049, 0xfbe },
  238 + { 0x110149, 0xfbe },
  239 + { 0x111049, 0xfbe },
  240 + { 0x111149, 0xfbe },
  241 + { 0x112049, 0xfbe },
  242 + { 0x112149, 0xfbe },
  243 + { 0x113049, 0xfbe },
  244 + { 0x113149, 0xfbe },
  245 +
  246 + { 0x210049, 0xfbe },
  247 + { 0x210149, 0xfbe },
  248 + { 0x211049, 0xfbe },
  249 + { 0x211149, 0xfbe },
  250 + { 0x212049, 0xfbe },
  251 + { 0x212149, 0xfbe },
  252 + { 0x213049, 0xfbe },
  253 + { 0x213149, 0xfbe },
  254 +
  255 + { 0x43, 0x63 },
  256 + { 0x1043, 0x63 },
  257 + { 0x2043, 0x63 },
  258 + { 0x3043, 0x63 },
  259 + { 0x4043, 0x63 },
  260 + { 0x5043, 0x63 },
  261 + { 0x6043, 0x63 },
  262 + { 0x7043, 0x63 },
  263 + { 0x8043, 0x63 },
  264 + { 0x9043, 0x63 },
  265 +
  266 + { 0x20018, 0x3 },
  267 + { 0x20075, 0x4 },
  268 + { 0x20050, 0x0 },
  269 + { 0x20008, 0x320 },
  270 + { 0x120008, 0xa7 },
  271 + { 0x220008, 0x19 },
  272 + { 0x20088, 0x9 },
  273 + { 0x200b2, 0x104 },
  274 + { 0x10043, 0x5a1 },
  275 + { 0x10143, 0x5a1 },
  276 + { 0x11043, 0x5a1 },
  277 + { 0x11143, 0x5a1 },
  278 + { 0x12043, 0x5a1 },
  279 + { 0x12143, 0x5a1 },
  280 + { 0x13043, 0x5a1 },
  281 + { 0x13143, 0x5a1 },
  282 + { 0x1200b2, 0x104 },
  283 + { 0x110043, 0x5a1 },
  284 + { 0x110143, 0x5a1 },
  285 + { 0x111043, 0x5a1 },
  286 + { 0x111143, 0x5a1 },
  287 + { 0x112043, 0x5a1 },
  288 + { 0x112143, 0x5a1 },
  289 + { 0x113043, 0x5a1 },
  290 + { 0x113143, 0x5a1 },
  291 + { 0x2200b2, 0x104 },
  292 + { 0x210043, 0x5a1 },
  293 + { 0x210143, 0x5a1 },
  294 + { 0x211043, 0x5a1 },
  295 + { 0x211143, 0x5a1 },
  296 + { 0x212043, 0x5a1 },
  297 + { 0x212143, 0x5a1 },
  298 + { 0x213043, 0x5a1 },
  299 + { 0x213143, 0x5a1 },
  300 + { 0x200fa, 0x1 },
  301 + { 0x1200fa, 0x1 },
  302 + { 0x2200fa, 0x1 },
  303 + { 0x20019, 0x1 },
  304 + { 0x120019, 0x1 },
  305 + { 0x220019, 0x1 },
  306 + { 0x200f0, 0x600 },
  307 + { 0x200f1, 0x0 },
  308 + { 0x200f2, 0x4444 },
  309 + { 0x200f3, 0x8888 },
  310 + { 0x200f4, 0x5655 },
  311 + { 0x200f5, 0x0 },
  312 + { 0x200f6, 0x0 },
  313 + { 0x200f7, 0xf000 },
  314 + { 0x20025, 0x0 },
  315 + { 0x2002d, 0x0 },
  316 + { 0x12002d, 0x0 },
  317 + { 0x22002d, 0x0 },
  318 +};
  319 +
  320 +/* P0 message block paremeter for training firmware */
  321 +static struct dram_cfg_param lpddr4_fsp0_cfg[] = {
  322 + { 0xd0000, 0x0 },
  323 + { 0x54000, 0x0 },
  324 + { 0x54001, 0x0 },
  325 + { 0x54002, 0x0 },
  326 + { 0x54003, 0xc80 },
  327 + { 0x54004, 0x2 },
  328 + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },
  329 + { 0x54006, LPDDR4_PHY_VREF_VALUE },
  330 + { 0x54007, 0x0 },
  331 + { 0x54008, 0x131f },
  332 + { 0x54009, LPDDR4_HDT_CTL_3200_1D },
  333 + { 0x5400a, 0x0 },
  334 + { 0x5400b, 0x2 },
  335 + { 0x5400c, 0x0 },
  336 + { 0x5400d, (LPDDR4_CATRAIN_3200_1d << 8) },
  337 + { 0x5400e, 0x0 },
  338 + { 0x5400f, 0x0 },
  339 + { 0x54010, 0x0 },
  340 + { 0x54011, 0x0 },
  341 + { 0x54012, 0x310 },
  342 + { 0x54013, 0x0 },
  343 + { 0x54014, 0x0 },
  344 + { 0x54015, 0x0 },
  345 + { 0x54016, 0x0 },
  346 + { 0x54017, 0x0 },
  347 + { 0x54018, 0x0 },
  348 + { 0x54019, 0x2dd4 },
  349 + { 0x5401a, (((LPDDR4_RON) << 3) | 0x3) },
  350 + { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) |
  351 + (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) },
  352 + { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) },
  353 + { 0x5401d, 0x0 },
  354 + { 0x5401e, LPDDR4_MR22_RANK0 },
  355 + { 0x5401f, 0x2dd4 },
  356 + { 0x54020, (((LPDDR4_RON) << 3) | 0x3) },
  357 + { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) |
  358 + (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) },
  359 + { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) },
  360 + { 0x54023, 0x0 },
  361 + { 0x54024, LPDDR4_MR22_RANK1 },
  362 + { 0x54025, 0x0 },
  363 + { 0x54026, 0x0 },
  364 + { 0x54027, 0x0 },
  365 + { 0x54028, 0x0 },
  366 + { 0x54029, 0x0 },
  367 + { 0x5402a, 0x0 },
  368 + { 0x5402b, 0x1000 },
  369 + { 0x5402c, 0x3 },
  370 + { 0x5402d, 0x0 },
  371 + { 0x5402e, 0x0 },
  372 + { 0x5402f, 0x0 },
  373 + { 0x54030, 0x0 },
  374 + { 0x54031, 0x0 },
  375 + { 0x54032, 0xd400 },
  376 + { 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d },
  377 + { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) },
  378 + { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) },
  379 + { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 },
  380 + { 0x54037, (LPDDR4_MR22_RANK0 << 8) },
  381 + { 0x54038, 0xd400 },
  382 + { 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d },
  383 + { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) },
  384 + { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) },
  385 + { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 },
  386 + { 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
  387 + { 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
  388 + { 0x5403e, 0x0 },
  389 + { 0x5403f, 0x0 },
  390 + { 0x54040, 0x0 },
  391 + { 0x54041, 0x0 },
  392 + { 0x54042, 0x0 },
  393 + { 0x54043, 0x0 },
  394 + { 0x54044, 0x0 },
  395 + { 0xd0000, 0x1 },
  396 +};
  397 +
  398 +/* P1 message block paremeter for training firmware */
  399 +static struct dram_cfg_param lpddr4_fsp1_cfg[] = {
  400 + { 0xd0000, 0x0 },
  401 + { 0x54000, 0x0 },
  402 + { 0x54001, 0x0 },
  403 + { 0x54002, 0x1 },
  404 + { 0x54003, 0x29c },
  405 + { 0x54004, 0x2 },
  406 + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },
  407 + { 0x54006, LPDDR4_PHY_VREF_VALUE },
  408 + { 0x54007, 0x0 },
  409 + { 0x54008, 0x121f },
  410 + { 0x54009, 0xc8 },
  411 + { 0x5400a, 0x0 },
  412 + { 0x5400b, 0x2 },
  413 + { 0x5400c, 0x0 },
  414 + { 0x5400d, 0x0 },
  415 + { 0x5400e, 0x0 },
  416 + { 0x5400f, 0x0 },
  417 + { 0x54010, 0x0 },
  418 + { 0x54011, 0x0 },
  419 + { 0x54012, 0x310 },
  420 + { 0x54013, 0x0 },
  421 + { 0x54014, 0x0 },
  422 + { 0x54015, 0x0 },
  423 + { 0x54016, 0x0 },
  424 + { 0x54017, 0x0 },
  425 + { 0x54018, 0x0 },
  426 + { 0x54019, 0x914 },
  427 + { 0x5401a, (((LPDDR4_RON) << 3) | 0x1) },
  428 + { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) |
  429 + (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) },
  430 + { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) },
  431 + { 0x5401e, 0x6 },
  432 + { 0x5401f, 0x914 },
  433 + { 0x54020, (((LPDDR4_RON) << 3) | 0x1) },
  434 + { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) |
  435 + (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) },
  436 + { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) },
  437 + { 0x54023, 0x0 },
  438 + { 0x54024, LPDDR4_MR22_RANK1 },
  439 + { 0x54025, 0x0 },
  440 + { 0x54026, 0x0 },
  441 + { 0x54027, 0x0 },
  442 + { 0x54028, 0x0 },
  443 + { 0x54029, 0x0 },
  444 + { 0x5402a, 0x0 },
  445 + { 0x5402b, 0x1000 },
  446 + { 0x5402c, 0x3 },
  447 + { 0x5402d, 0x0 },
  448 + { 0x5402e, 0x0 },
  449 + { 0x5402f, 0x0 },
  450 + { 0x54030, 0x0 },
  451 + { 0x54031, 0x0 },
  452 + { 0x54032, 0x1400 },
  453 + { 0x54033, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x09 },
  454 + { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) },
  455 + { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) },
  456 + { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 },
  457 + { 0x54037, 0x600 },
  458 + { 0x54038, 0x1400 },
  459 + { 0x54039, ((((LPDDR4_RON) << 3) | 0x1) << 8) | 0x09 },
  460 + { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) },
  461 + { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) },
  462 + { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 },
  463 + { 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
  464 + { 0x5403e, 0x0 },
  465 + { 0x5403f, 0x0 },
  466 + { 0x54040, 0x0 },
  467 + { 0x54041, 0x0 },
  468 + { 0x54042, 0x0 },
  469 + { 0x54043, 0x0 },
  470 + { 0xd0000, 0x1 },
  471 +
  472 +};
  473 +
  474 +/* P0 2D message block paremeter for training firmware */
  475 +static struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = {
  476 + { 0xd0000, 0x0 },
  477 + { 0x54000, 0x0 },
  478 + { 0x54001, 0x0 },
  479 + { 0x54002, 0x0 },
  480 + { 0x54003, 0xc80 },
  481 + { 0x54004, 0x2 },
  482 + { 0x54005, ((LPDDR4_PHY_RON << 8) | LPDDR4_PHY_RTT) },
  483 + { 0x54006, LPDDR4_PHY_VREF_VALUE },
  484 + { 0x54007, 0x0 },
  485 + { 0x54008, 0x61 },
  486 + { 0x54009, LPDDR4_HDT_CTL_2D },
  487 + { 0x5400a, 0x0 },
  488 + { 0x5400b, 0x2 },
  489 + { 0x5400c, 0x0 },
  490 + { 0x5400d, (LPDDR4_CATRAIN_3200_2d << 8) },
  491 + { 0x5400e, 0x0 },
  492 + { 0x5400f, (LPDDR4_2D_SHARE << 8) | 0x00 },
  493 + { 0x54010, LPDDR4_2D_WEIGHT },
  494 + { 0x54011, 0x0 },
  495 + { 0x54012, 0x310 },
  496 + { 0x54013, 0x0 },
  497 + { 0x54014, 0x0 },
  498 + { 0x54015, 0x0 },
  499 + { 0x54016, 0x0 },
  500 + { 0x54017, 0x0 },
  501 + { 0x54018, 0x0 },
  502 + { 0x54024, 0x5 },
  503 + { 0x54019, 0x2dd4 },
  504 + { 0x5401a, (((LPDDR4_RON) << 3) | 0x3) },
  505 + { 0x5401b, ((LPDDR4_VREF_VALUE_CA << 8) |
  506 + (LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) },
  507 + { 0x5401c, ((LPDDR4_VREF_VALUE_DQ_RANK0 << 8) | 0x08) },
  508 + { 0x5401d, 0x0 },
  509 + { 0x5401e, LPDDR4_MR22_RANK0 },
  510 + { 0x5401f, 0x2dd4 },
  511 + { 0x54020, (((LPDDR4_RON) << 3) | 0x3) },
  512 + { 0x54021, ((LPDDR4_VREF_VALUE_CA << 8) |
  513 + (LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) },
  514 + { 0x54022, ((LPDDR4_VREF_VALUE_DQ_RANK1 << 8) | 0x08) },
  515 + { 0x54023, 0x0 },
  516 + { 0x54024, LPDDR4_MR22_RANK1 },
  517 + { 0x54025, 0x0 },
  518 + { 0x54026, 0x0 },
  519 + { 0x54027, 0x0 },
  520 + { 0x54028, 0x0 },
  521 + { 0x54029, 0x0 },
  522 + { 0x5402a, 0x0 },
  523 + { 0x5402b, 0x1000 },
  524 + { 0x5402c, 0x3 },
  525 + { 0x5402d, 0x0 },
  526 + { 0x5402e, 0x0 },
  527 + { 0x5402f, 0x0 },
  528 + { 0x54030, 0x0 },
  529 + { 0x54031, 0x0 },
  530 + { 0x54032, 0xd400 },
  531 + { 0x54033, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d },
  532 + { 0x54034, (((LPDDR4_RTT_CA_BANK0 << 4) | LPDDR4_RTT_DQ) << 8) },
  533 + { 0x54035, (0x0800 | LPDDR4_VREF_VALUE_CA) },
  534 + { 0x54036, LPDDR4_VREF_VALUE_DQ_RANK0 },
  535 + { 0x54037, (LPDDR4_MR22_RANK0 << 8) },
  536 + { 0x54038, 0xd400 },
  537 + { 0x54039, ((((LPDDR4_RON) << 3) | 0x3) << 8) | 0x2d },
  538 + { 0x5403a, (((LPDDR4_RTT_CA_BANK1 << 4) | LPDDR4_RTT_DQ) << 8) },
  539 + { 0x5403b, (0x0800 | LPDDR4_VREF_VALUE_CA) },
  540 + { 0x5403c, LPDDR4_VREF_VALUE_DQ_RANK1 },
  541 + { 0x5403d, (LPDDR4_MR22_RANK1 << 8) },
  542 + { 0x5403e, 0x0 },
  543 + { 0x5403f, 0x0 },
  544 + { 0x54040, 0x0 },
  545 + { 0x54041, 0x0 },
  546 + { 0x54042, 0x0 },
  547 + { 0x54043, 0x0 },
  548 + { 0x54044, 0x0 },
  549 + { 0xd0000, 0x1 },
  550 +
  551 +};
  552 +
  553 +/* DRAM PHY init engine image */
  554 +static struct dram_cfg_param lpddr4_phy_pie[] = {
  555 + { 0xd0000, 0x0 },
  556 + { 0x90000, 0x10 },
  557 + { 0x90001, 0x400 },
  558 + { 0x90002, 0x10e },
  559 + { 0x90003, 0x0 },
  560 + { 0x90004, 0x0 },
  561 + { 0x90005, 0x8 },
  562 + { 0x90029, 0xb },
  563 + { 0x9002a, 0x480 },
  564 + { 0x9002b, 0x109 },
  565 + { 0x9002c, 0x8 },
  566 + { 0x9002d, 0x448 },
  567 + { 0x9002e, 0x139 },
  568 + { 0x9002f, 0x8 },
  569 + { 0x90030, 0x478 },
  570 + { 0x90031, 0x109 },
  571 + { 0x90032, 0x0 },
  572 + { 0x90033, 0xe8 },
  573 + { 0x90034, 0x109 },
  574 + { 0x90035, 0x2 },
  575 + { 0x90036, 0x10 },
  576 + { 0x90037, 0x139 },
  577 + { 0x90038, 0xb },
  578 + { 0x90039, 0x7c0 },
  579 + { 0x9003a, 0x139 },
  580 + { 0x9003b, 0x44 },
  581 + { 0x9003c, 0x630 },
  582 + { 0x9003d, 0x159 },
  583 + { 0x9003e, 0x14f },
  584 + { 0x9003f, 0x630 },
  585 + { 0x90040, 0x159 },
  586 + { 0x90041, 0x47 },
  587 + { 0x90042, 0x630 },
  588 + { 0x90043, 0x149 },
  589 + { 0x90044, 0x4f },
  590 + { 0x90045, 0x630 },
  591 + { 0x90046, 0x179 },
  592 + { 0x90047, 0x8 },
  593 + { 0x90048, 0xe0 },
  594 + { 0x90049, 0x109 },
  595 + { 0x9004a, 0x0 },
  596 + { 0x9004b, 0x7c8 },
  597 + { 0x9004c, 0x109 },
  598 + { 0x9004d, 0x0 },
  599 + { 0x9004e, 0x1 },
  600 + { 0x9004f, 0x8 },
  601 + { 0x90050, 0x0 },
  602 + { 0x90051, 0x45a },
  603 + { 0x90052, 0x9 },
  604 + { 0x90053, 0x0 },
  605 + { 0x90054, 0x448 },
  606 + { 0x90055, 0x109 },
  607 + { 0x90056, 0x40 },
  608 + { 0x90057, 0x630 },
  609 + { 0x90058, 0x179 },
  610 + { 0x90059, 0x1 },
  611 + { 0x9005a, 0x618 },
  612 + { 0x9005b, 0x109 },
  613 + { 0x9005c, 0x40c0 },
  614 + { 0x9005d, 0x630 },
  615 + { 0x9005e, 0x149 },
  616 + { 0x9005f, 0x8 },
  617 + { 0x90060, 0x4 },
  618 + { 0x90061, 0x48 },
  619 + { 0x90062, 0x4040 },
  620 + { 0x90063, 0x630 },
  621 + { 0x90064, 0x149 },
  622 + { 0x90065, 0x0 },
  623 + { 0x90066, 0x4 },
  624 + { 0x90067, 0x48 },
  625 + { 0x90068, 0x40 },
  626 + { 0x90069, 0x630 },
  627 + { 0x9006a, 0x149 },
  628 + { 0x9006b, 0x10 },
  629 + { 0x9006c, 0x4 },
  630 + { 0x9006d, 0x18 },
  631 + { 0x9006e, 0x0 },
  632 + { 0x9006f, 0x4 },
  633 + { 0x90070, 0x78 },
  634 + { 0x90071, 0x549 },
  635 + { 0x90072, 0x630 },
  636 + { 0x90073, 0x159 },
  637 + { 0x90074, 0xd49 },
  638 + { 0x90075, 0x630 },
  639 + { 0x90076, 0x159 },
  640 + { 0x90077, 0x94a },
  641 + { 0x90078, 0x630 },
  642 + { 0x90079, 0x159 },
  643 + { 0x9007a, 0x441 },
  644 + { 0x9007b, 0x630 },
  645 + { 0x9007c, 0x149 },
  646 + { 0x9007d, 0x42 },
  647 + { 0x9007e, 0x630 },
  648 + { 0x9007f, 0x149 },
  649 + { 0x90080, 0x1 },
  650 + { 0x90081, 0x630 },
  651 + { 0x90082, 0x149 },
  652 + { 0x90083, 0x0 },
  653 + { 0x90084, 0xe0 },
  654 + { 0x90085, 0x109 },
  655 + { 0x90086, 0xa },
  656 + { 0x90087, 0x10 },
  657 + { 0x90088, 0x109 },
  658 + { 0x90089, 0x9 },
  659 + { 0x9008a, 0x3c0 },
  660 + { 0x9008b, 0x149 },
  661 + { 0x9008c, 0x9 },
  662 + { 0x9008d, 0x3c0 },
  663 + { 0x9008e, 0x159 },
  664 + { 0x9008f, 0x18 },
  665 + { 0x90090, 0x10 },
  666 + { 0x90091, 0x109 },
  667 + { 0x90092, 0x0 },
  668 + { 0x90093, 0x3c0 },
  669 + { 0x90094, 0x109 },
  670 + { 0x90095, 0x18 },
  671 + { 0x90096, 0x4 },
  672 + { 0x90097, 0x48 },
  673 + { 0x90098, 0x18 },
  674 + { 0x90099, 0x4 },
  675 + { 0x9009a, 0x58 },
  676 + { 0x9009b, 0xa },
  677 + { 0x9009c, 0x10 },
  678 + { 0x9009d, 0x109 },
  679 + { 0x9009e, 0x2 },
  680 + { 0x9009f, 0x10 },
  681 + { 0x900a0, 0x109 },
  682 + { 0x900a1, 0x5 },
  683 + { 0x900a2, 0x7c0 },
  684 + { 0x900a3, 0x109 },
  685 + { 0x900a4, 0xd },
  686 + { 0x900a5, 0x7c0 },
  687 + { 0x900a6, 0x109 },
  688 + { 0x900a7, 0x4 },
  689 + { 0x900a8, 0x7c0 },
  690 + { 0x900a9, 0x109 },
  691 + { 0x40000, 0x811 },
  692 + { 0x40020, 0x880 },
  693 + { 0x40040, 0x0 },
  694 + { 0x40060, 0x0 },
  695 + { 0x40001, 0x4008 },
  696 + { 0x40021, 0x83 },
  697 + { 0x40041, 0x4f },
  698 + { 0x40061, 0x0 },
  699 + { 0x40002, 0x4040 },
  700 + { 0x40022, 0x83 },
  701 + { 0x40042, 0x51 },
  702 + { 0x40062, 0x0 },
  703 + { 0x40003, 0x811 },
  704 + { 0x40023, 0x880 },
  705 + { 0x40043, 0x0 },
  706 + { 0x40063, 0x0 },
  707 + { 0x40004, 0x720 },
  708 + { 0x40024, 0xf },
  709 + { 0x40044, 0x1740 },
  710 + { 0x40064, 0x0 },
  711 + { 0x40005, 0x16 },
  712 + { 0x40025, 0x83 },
  713 + { 0x40045, 0x4b },
  714 + { 0x40065, 0x0 },
  715 + { 0x40006, 0x716 },
  716 + { 0x40026, 0xf },
  717 + { 0x40046, 0x2001 },
  718 + { 0x40066, 0x0 },
  719 + { 0x40007, 0x716 },
  720 + { 0x40027, 0xf },
  721 + { 0x40047, 0x2800 },
  722 + { 0x40067, 0x0 },
  723 + { 0x40008, 0x716 },
  724 + { 0x40028, 0xf },
  725 + { 0x40048, 0xf00 },
  726 + { 0x40068, 0x0 },
  727 + { 0x40009, 0x720 },
  728 + { 0x40029, 0xf },
  729 + { 0x40049, 0x1400 },
  730 + { 0x40069, 0x0 },
  731 + { 0x4000a, 0xe08 },
  732 + { 0x4002a, 0xc15 },
  733 + { 0x4004a, 0x0 },
  734 + { 0x4006a, 0x0 },
  735 + { 0x4000b, 0x623 },
  736 + { 0x4002b, 0x15 },
  737 + { 0x4004b, 0x0 },
  738 + { 0x4006b, 0x0 },
  739 + { 0x4000c, 0x4028 },
  740 + { 0x4002c, 0x80 },
  741 + { 0x4004c, 0x0 },
  742 + { 0x4006c, 0x0 },
  743 + { 0x4000d, 0xe08 },
  744 + { 0x4002d, 0xc1a },
  745 + { 0x4004d, 0x0 },
  746 + { 0x4006d, 0x0 },
  747 + { 0x4000e, 0x623 },
  748 + { 0x4002e, 0x1a },
  749 + { 0x4004e, 0x0 },
  750 + { 0x4006e, 0x0 },
  751 + { 0x4000f, 0x4040 },
  752 + { 0x4002f, 0x80 },
  753 + { 0x4004f, 0x0 },
  754 + { 0x4006f, 0x0 },
  755 + { 0x40010, 0x2604 },
  756 + { 0x40030, 0x15 },
  757 + { 0x40050, 0x0 },
  758 + { 0x40070, 0x0 },
  759 + { 0x40011, 0x708 },
  760 + { 0x40031, 0x5 },
  761 + { 0x40051, 0x0 },
  762 + { 0x40071, 0x2002 },
  763 + { 0x40012, 0x8 },
  764 + { 0x40032, 0x80 },
  765 + { 0x40052, 0x0 },
  766 + { 0x40072, 0x0 },
  767 + { 0x40013, 0x2604 },
  768 + { 0x40033, 0x1a },
  769 + { 0x40053, 0x0 },
  770 + { 0x40073, 0x0 },
  771 + { 0x40014, 0x708 },
  772 + { 0x40034, 0xa },
  773 + { 0x40054, 0x0 },
  774 + { 0x40074, 0x2002 },
  775 + { 0x40015, 0x4040 },
  776 + { 0x40035, 0x80 },
  777 + { 0x40055, 0x0 },
  778 + { 0x40075, 0x0 },
  779 + { 0x40016, 0x60a },
  780 + { 0x40036, 0x15 },
  781 + { 0x40056, 0x1200 },
  782 + { 0x40076, 0x0 },
  783 + { 0x40017, 0x61a },
  784 + { 0x40037, 0x15 },
  785 + { 0x40057, 0x1300 },
  786 + { 0x40077, 0x0 },
  787 + { 0x40018, 0x60a },
  788 + { 0x40038, 0x1a },
  789 + { 0x40058, 0x1200 },
  790 + { 0x40078, 0x0 },
  791 + { 0x40019, 0x642 },
  792 + { 0x40039, 0x1a },
  793 + { 0x40059, 0x1300 },
  794 + { 0x40079, 0x0 },
  795 + { 0x4001a, 0x4808 },
  796 + { 0x4003a, 0x880 },
  797 + { 0x4005a, 0x0 },
  798 + { 0x4007a, 0x0 },
  799 + { 0x900aa, 0x0 },
  800 + { 0x900ab, 0x790 },
  801 + { 0x900ac, 0x11a },
  802 + { 0x900ad, 0x8 },
  803 + { 0x900ae, 0x7aa },
  804 + { 0x900af, 0x2a },
  805 + { 0x900b0, 0x10 },
  806 + { 0x900b1, 0x7b2 },
  807 + { 0x900b2, 0x2a },
  808 + { 0x900b3, 0x0 },
  809 + { 0x900b4, 0x7c8 },
  810 + { 0x900b5, 0x109 },
  811 + { 0x900b6, 0x10 },
  812 + { 0x900b7, 0x10 },
  813 + { 0x900b8, 0x109 },
  814 + { 0x900b9, 0x10 },
  815 + { 0x900ba, 0x2a8 },
  816 + { 0x900bb, 0x129 },
  817 + { 0x900bc, 0x8 },
  818 + { 0x900bd, 0x370 },
  819 + { 0x900be, 0x129 },
  820 + { 0x900bf, 0xa },
  821 + { 0x900c0, 0x3c8 },
  822 + { 0x900c1, 0x1a9 },
  823 + { 0x900c2, 0xc },
  824 + { 0x900c3, 0x408 },
  825 + { 0x900c4, 0x199 },
  826 + { 0x900c5, 0x14 },
  827 + { 0x900c6, 0x790 },
  828 + { 0x900c7, 0x11a },
  829 + { 0x900c8, 0x8 },
  830 + { 0x900c9, 0x4 },
  831 + { 0x900ca, 0x18 },
  832 + { 0x900cb, 0xe },
  833 + { 0x900cc, 0x408 },
  834 + { 0x900cd, 0x199 },
  835 + { 0x900ce, 0x8 },
  836 + { 0x900cf, 0x8568 },
  837 + { 0x900d0, 0x108 },
  838 + { 0x900d1, 0x18 },
  839 + { 0x900d2, 0x790 },
  840 + { 0x900d3, 0x16a },
  841 + { 0x900d4, 0x8 },
  842 + { 0x900d5, 0x1d8 },
  843 + { 0x900d6, 0x169 },
  844 + { 0x900d7, 0x10 },
  845 + { 0x900d8, 0x8558 },
  846 + { 0x900d9, 0x168 },
  847 + { 0x900da, 0x70 },
  848 + { 0x900db, 0x788 },
  849 + { 0x900dc, 0x16a },
  850 + { 0x900dd, 0x1ff8 },
  851 + { 0x900de, 0x85a8 },
  852 + { 0x900df, 0x1e8 },
  853 + { 0x900e0, 0x50 },
  854 + { 0x900e1, 0x798 },
  855 + { 0x900e2, 0x16a },
  856 + { 0x900e3, 0x60 },
  857 + { 0x900e4, 0x7a0 },
  858 + { 0x900e5, 0x16a },
  859 + { 0x900e6, 0x8 },
  860 + { 0x900e7, 0x8310 },
  861 + { 0x900e8, 0x168 },
  862 + { 0x900e9, 0x8 },
  863 + { 0x900ea, 0xa310 },
  864 + { 0x900eb, 0x168 },
  865 + { 0x900ec, 0xa },
  866 + { 0x900ed, 0x408 },
  867 + { 0x900ee, 0x169 },
  868 + { 0x900ef, 0x6e },
  869 + { 0x900f0, 0x0 },
  870 + { 0x900f1, 0x68 },
  871 + { 0x900f2, 0x0 },
  872 + { 0x900f3, 0x408 },
  873 + { 0x900f4, 0x169 },
  874 + { 0x900f5, 0x0 },
  875 + { 0x900f6, 0x8310 },
  876 + { 0x900f7, 0x168 },
  877 + { 0x900f8, 0x0 },
  878 + { 0x900f9, 0xa310 },
  879 + { 0x900fa, 0x168 },
  880 + { 0x900fb, 0x1ff8 },
  881 + { 0x900fc, 0x85a8 },
  882 + { 0x900fd, 0x1e8 },
  883 + { 0x900fe, 0x68 },
  884 + { 0x900ff, 0x798 },
  885 + { 0x90100, 0x16a },
  886 + { 0x90101, 0x78 },
  887 + { 0x90102, 0x7a0 },
  888 + { 0x90103, 0x16a },
  889 + { 0x90104, 0x68 },
  890 + { 0x90105, 0x790 },
  891 + { 0x90106, 0x16a },
  892 + { 0x90107, 0x8 },
  893 + { 0x90108, 0x8b10 },
  894 + { 0x90109, 0x168 },
  895 + { 0x9010a, 0x8 },
  896 + { 0x9010b, 0xab10 },
  897 + { 0x9010c, 0x168 },
  898 + { 0x9010d, 0xa },
  899 + { 0x9010e, 0x408 },
  900 + { 0x9010f, 0x169 },
  901 + { 0x90110, 0x58 },
  902 + { 0x90111, 0x0 },
  903 + { 0x90112, 0x68 },
  904 + { 0x90113, 0x0 },
  905 + { 0x90114, 0x408 },
  906 + { 0x90115, 0x169 },
  907 + { 0x90116, 0x0 },
  908 + { 0x90117, 0x8b10 },
  909 + { 0x90118, 0x168 },
  910 + { 0x90119, 0x0 },
  911 + { 0x9011a, 0xab10 },
  912 + { 0x9011b, 0x168 },
  913 + { 0x9011c, 0x0 },
  914 + { 0x9011d, 0x1d8 },
  915 + { 0x9011e, 0x169 },
  916 + { 0x9011f, 0x80 },
  917 + { 0x90120, 0x790 },
  918 + { 0x90121, 0x16a },
  919 + { 0x90122, 0x18 },
  920 + { 0x90123, 0x7aa },
  921 + { 0x90124, 0x6a },
  922 + { 0x90125, 0xa },
  923 + { 0x90126, 0x0 },
  924 + { 0x90127, 0x1e9 },
  925 + { 0x90128, 0x8 },
  926 + { 0x90129, 0x8080 },
  927 + { 0x9012a, 0x108 },
  928 + { 0x9012b, 0xf },
  929 + { 0x9012c, 0x408 },
  930 + { 0x9012d, 0x169 },
  931 + { 0x9012e, 0xc },
  932 + { 0x9012f, 0x0 },
  933 + { 0x90130, 0x68 },
  934 + { 0x90131, 0x9 },
  935 + { 0x90132, 0x0 },
  936 + { 0x90133, 0x1a9 },
  937 + { 0x90134, 0x0 },
  938 + { 0x90135, 0x408 },
  939 + { 0x90136, 0x169 },
  940 + { 0x90137, 0x0 },
  941 + { 0x90138, 0x8080 },
  942 + { 0x90139, 0x108 },
  943 + { 0x9013a, 0x8 },
  944 + { 0x9013b, 0x7aa },
  945 + { 0x9013c, 0x6a },
  946 + { 0x9013d, 0x0 },
  947 + { 0x9013e, 0x8568 },
  948 + { 0x9013f, 0x108 },
  949 + { 0x90140, 0xb7 },
  950 + { 0x90141, 0x790 },
  951 + { 0x90142, 0x16a },
  952 + { 0x90143, 0x1f },
  953 + { 0x90144, 0x0 },
  954 + { 0x90145, 0x68 },
  955 + { 0x90146, 0x8 },
  956 + { 0x90147, 0x8558 },
  957 + { 0x90148, 0x168 },
  958 + { 0x90149, 0xf },
  959 + { 0x9014a, 0x408 },
  960 + { 0x9014b, 0x169 },
  961 + { 0x9014c, 0xc },
  962 + { 0x9014d, 0x0 },
  963 + { 0x9014e, 0x68 },
  964 + { 0x9014f, 0x0 },
  965 + { 0x90150, 0x408 },
  966 + { 0x90151, 0x169 },
  967 + { 0x90152, 0x0 },
  968 + { 0x90153, 0x8558 },
  969 + { 0x90154, 0x168 },
  970 + { 0x90155, 0x8 },
  971 + { 0x90156, 0x3c8 },
  972 + { 0x90157, 0x1a9 },
  973 + { 0x90158, 0x3 },
  974 + { 0x90159, 0x370 },
  975 + { 0x9015a, 0x129 },
  976 + { 0x9015b, 0x20 },
  977 + { 0x9015c, 0x2aa },
  978 + { 0x9015d, 0x9 },
  979 + { 0x9015e, 0x0 },
  980 + { 0x9015f, 0x400 },
  981 + { 0x90160, 0x10e },
  982 + { 0x90161, 0x8 },
  983 + { 0x90162, 0xe8 },
  984 + { 0x90163, 0x109 },
  985 + { 0x90164, 0x0 },
  986 + { 0x90165, 0x8140 },
  987 + { 0x90166, 0x10c },
  988 + { 0x90167, 0x10 },
  989 + { 0x90168, 0x8138 },
  990 + { 0x90169, 0x10c },
  991 + { 0x9016a, 0x8 },
  992 + { 0x9016b, 0x7c8 },
  993 + { 0x9016c, 0x101 },
  994 + { 0x9016d, 0x8 },
  995 + { 0x9016e, 0x0 },
  996 + { 0x9016f, 0x8 },
  997 + { 0x90170, 0x8 },
  998 + { 0x90171, 0x448 },
  999 + { 0x90172, 0x109 },
  1000 + { 0x90173, 0xf },
  1001 + { 0x90174, 0x7c0 },
  1002 + { 0x90175, 0x109 },
  1003 + { 0x90176, 0x0 },
  1004 + { 0x90177, 0xe8 },
  1005 + { 0x90178, 0x109 },
  1006 + { 0x90179, 0x47 },
  1007 + { 0x9017a, 0x630 },
  1008 + { 0x9017b, 0x109 },
  1009 + { 0x9017c, 0x8 },
  1010 + { 0x9017d, 0x618 },
  1011 + { 0x9017e, 0x109 },
  1012 + { 0x9017f, 0x8 },
  1013 + { 0x90180, 0xe0 },
  1014 + { 0x90181, 0x109 },
  1015 + { 0x90182, 0x0 },
  1016 + { 0x90183, 0x7c8 },
  1017 + { 0x90184, 0x109 },
  1018 + { 0x90185, 0x8 },
  1019 + { 0x90186, 0x8140 },
  1020 + { 0x90187, 0x10c },
  1021 + { 0x90188, 0x0 },
  1022 + { 0x90189, 0x1 },
  1023 + { 0x9018a, 0x8 },
  1024 + { 0x9018b, 0x8 },
  1025 + { 0x9018c, 0x4 },
  1026 + { 0x9018d, 0x8 },
  1027 + { 0x9018e, 0x8 },
  1028 + { 0x9018f, 0x7c8 },
  1029 + { 0x90190, 0x101 },
  1030 + { 0x90006, 0x0 },
  1031 + { 0x90007, 0x0 },
  1032 + { 0x90008, 0x8 },
  1033 + { 0x90009, 0x0 },
  1034 + { 0x9000a, 0x0 },
  1035 + { 0x9000b, 0x0 },
  1036 + { 0xd00e7, 0x400 },
  1037 + { 0x90017, 0x0 },
  1038 + { 0x9001f, 0x2b },
  1039 + { 0x90026, 0x6c },
  1040 + { 0x400d0, 0x0 },
  1041 + { 0x400d1, 0x101 },
  1042 + { 0x400d2, 0x105 },
  1043 + { 0x400d3, 0x107 },
  1044 + { 0x400d4, 0x10f },
  1045 + { 0x400d5, 0x202 },
  1046 + { 0x400d6, 0x20a },
  1047 + { 0x400d7, 0x20b },
  1048 + { 0x2003a, 0x2 },
  1049 + { 0x2000b, 0x64 },
  1050 + { 0x2000c, 0xc8 },
  1051 + { 0x2000d, 0x7d0 },
  1052 + { 0x2000e, 0x2c },
  1053 + { 0x12000b, 0x14 },
  1054 + { 0x12000c, 0x29 },
  1055 + { 0x12000d, 0x1a1 },
  1056 + { 0x12000e, 0x10 },
  1057 + { 0x22000b, 0x3 },
  1058 + { 0x22000c, 0x6 },
  1059 + { 0x22000d, 0x3e },
  1060 + { 0x22000e, 0x10 },
  1061 + { 0x9000c, 0x0 },
  1062 + { 0x9000d, 0x173 },
  1063 + { 0x9000e, 0x60 },
  1064 + { 0x9000f, 0x6110 },
  1065 + { 0x90010, 0x2152 },
  1066 + { 0x90011, 0xdfbd },
  1067 + { 0x90012, 0x60 },
  1068 + { 0x90013, 0x6152 },
  1069 + { 0x20010, 0x5a },
  1070 + { 0x20011, 0x3 },
  1071 + { 0x40080, 0xe0 },
  1072 + { 0x40081, 0x12 },
  1073 + { 0x40082, 0xe0 },
  1074 + { 0x40083, 0x12 },
  1075 + { 0x40084, 0xe0 },
  1076 + { 0x40085, 0x12 },
  1077 + { 0x140080, 0xe0 },
  1078 + { 0x140081, 0x12 },
  1079 + { 0x140082, 0xe0 },
  1080 + { 0x140083, 0x12 },
  1081 + { 0x140084, 0xe0 },
  1082 + { 0x140085, 0x12 },
  1083 + { 0x240080, 0xe0 },
  1084 + { 0x240081, 0x12 },
  1085 + { 0x240082, 0xe0 },
  1086 + { 0x240083, 0x12 },
  1087 + { 0x240084, 0xe0 },
  1088 + { 0x240085, 0x12 },
  1089 + { 0x400fd, 0xf },
  1090 + { 0x10011, 0x1 },
  1091 + { 0x10012, 0x1 },
  1092 + { 0x10013, 0x180 },
  1093 + { 0x10018, 0x1 },
  1094 + { 0x10002, 0x6209 },
  1095 + { 0x100b2, 0x1 },
  1096 + { 0x101b4, 0x1 },
  1097 + { 0x102b4, 0x1 },
  1098 + { 0x103b4, 0x1 },
  1099 + { 0x104b4, 0x1 },
  1100 + { 0x105b4, 0x1 },
  1101 + { 0x106b4, 0x1 },
  1102 + { 0x107b4, 0x1 },
  1103 + { 0x108b4, 0x1 },
  1104 + { 0x11011, 0x1 },
  1105 + { 0x11012, 0x1 },
  1106 + { 0x11013, 0x180 },
  1107 + { 0x11018, 0x1 },
  1108 + { 0x11002, 0x6209 },
  1109 + { 0x110b2, 0x1 },
  1110 + { 0x111b4, 0x1 },
  1111 + { 0x112b4, 0x1 },
  1112 + { 0x113b4, 0x1 },
  1113 + { 0x114b4, 0x1 },
  1114 + { 0x115b4, 0x1 },
  1115 + { 0x116b4, 0x1 },
  1116 + { 0x117b4, 0x1 },
  1117 + { 0x118b4, 0x1 },
  1118 + { 0x12011, 0x1 },
  1119 + { 0x12012, 0x1 },
  1120 + { 0x12013, 0x180 },
  1121 + { 0x12018, 0x1 },
  1122 + { 0x12002, 0x6209 },
  1123 + { 0x120b2, 0x1 },
  1124 + { 0x121b4, 0x1 },
  1125 + { 0x122b4, 0x1 },
  1126 + { 0x123b4, 0x1 },
  1127 + { 0x124b4, 0x1 },
  1128 + { 0x125b4, 0x1 },
  1129 + { 0x126b4, 0x1 },
  1130 + { 0x127b4, 0x1 },
  1131 + { 0x128b4, 0x1 },
  1132 + { 0x13011, 0x1 },
  1133 + { 0x13012, 0x1 },
  1134 + { 0x13013, 0x180 },
  1135 + { 0x13018, 0x1 },
  1136 + { 0x13002, 0x6209 },
  1137 + { 0x130b2, 0x1 },
  1138 + { 0x131b4, 0x1 },
  1139 + { 0x132b4, 0x1 },
  1140 + { 0x133b4, 0x1 },
  1141 + { 0x134b4, 0x1 },
  1142 + { 0x135b4, 0x1 },
  1143 + { 0x136b4, 0x1 },
  1144 + { 0x137b4, 0x1 },
  1145 + { 0x138b4, 0x1 },
  1146 + { 0x20089, 0x1 },
  1147 + { 0x20088, 0x19 },
  1148 + { 0xc0080, 0x2 },
  1149 + { 0xd0000, 0x1 },
  1150 +};
  1151 +
  1152 +static struct dram_fsp_msg lpddr4_dram_fsp_msg[] = {
  1153 + {
  1154 + /* P0 3200mts 1D */
  1155 + .drate = 3200,
  1156 + .fw_type = FW_1D_IMAGE,
  1157 + .fsp_cfg = lpddr4_fsp0_cfg,
  1158 + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg),
  1159 + },
  1160 + {
  1161 + /* P1 667mts 1D */
  1162 + .drate = 667,
  1163 + .fw_type = FW_1D_IMAGE,
  1164 + .fsp_cfg = lpddr4_fsp1_cfg,
  1165 + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg),
  1166 + },
  1167 + {
  1168 + /* P0 3200mts 2D */
  1169 + .drate = 3200,
  1170 + .fw_type = FW_2D_IMAGE,
  1171 + .fsp_cfg = lpddr4_fsp0_2d_cfg,
  1172 + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg),
  1173 + },
  1174 +};
  1175 +
  1176 +/* lpddr4 timing config params on EVK board */
  1177 +struct dram_timing_info dram_timing_b0 = {
  1178 + .ddrc_cfg = lpddr4_ddrc_cfg,
  1179 + .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg),
  1180 + .ddrphy_cfg = lpddr4_ddrphy_cfg,
  1181 + .ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg),
  1182 + .fsp_msg = lpddr4_dram_fsp_msg,
  1183 + .fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg),
  1184 + .ddrphy_pie = lpddr4_phy_pie,
  1185 + .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie),
  1186 + /*
  1187 + * this table must be initialized if DDRPHY bypass mode is
  1188 + * not used: all fsp drate > 666MTS.
  1189 + */
  1190 + .fsp_table = { 3200, 667, },
  1191 +};
board/freescale/imx8mq_evk/spl.c
Diff comments   View file @ 86ac7a9
  1 +// SPDX-License-Identifier: GPL-2.0+
  2 +/*
  3 + * Copyright 2018 NXP
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#include <common.h>
  9 +#include <asm/io.h>
  10 +#include <errno.h>
  11 +#include <asm/io.h>
  12 +#include <asm/arch/ddr.h>
  13 +#include <asm/arch/imx8mq_pins.h>
  14 +#include <asm/arch/sys_proto.h>
  15 +#include <asm/arch/clock.h>
  16 +#include <asm/mach-imx/iomux-v3.h>
  17 +#include <asm/mach-imx/gpio.h>
  18 +#include <asm/mach-imx/mxc_i2c.h>
  19 +#include <fsl_esdhc.h>
  20 +#include <mmc.h>
  21 +#include <power/pmic.h>
  22 +#include <power/pfuze100_pmic.h>
  23 +#include <spl.h>
  24 +#include "../common/pfuze.h"
  25 +
  26 +DECLARE_GLOBAL_DATA_PTR;
  27 +
  28 +extern struct dram_timing_info dram_timing_b0;
  29 +
  30 +void spl_dram_init(void)
  31 +{
  32 + /* ddr init */
  33 + if ((get_cpu_rev() & 0xfff) == CHIP_REV_2_1)
  34 + ddr_init(&dram_timing);
  35 + else
  36 + ddr_init(&dram_timing_b0);
  37 +}
  38 +
  39 +#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE)
  40 +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  41 +struct i2c_pads_info i2c_pad_info1 = {
  42 + .scl = {
  43 + .i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC,
  44 + .gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC,
  45 + .gp = IMX_GPIO_NR(5, 14),
  46 + },
  47 + .sda = {
  48 + .i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC,
  49 + .gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC,
  50 + .gp = IMX_GPIO_NR(5, 15),
  51 + },
  52 +};
  53 +
  54 +#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12)
  55 +#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10)
  56 +#define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19)
  57 +
  58 +int board_mmc_getcd(struct mmc *mmc)
  59 +{
  60 + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  61 + int ret = 0;
  62 +
  63 + switch (cfg->esdhc_base) {
  64 + case USDHC1_BASE_ADDR:
  65 + ret = 1;
  66 + break;
  67 + case USDHC2_BASE_ADDR:
  68 + ret = !gpio_get_value(USDHC2_CD_GPIO);
  69 + return ret;
  70 + }
  71 +
  72 + return 1;
  73 +}
  74 +
  75 +#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \
  76 + PAD_CTL_FSEL2)
  77 +#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1)
  78 +
  79 +static iomux_v3_cfg_t const usdhc1_pads[] = {
  80 + IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  81 + IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  82 + IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  83 + IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  84 + IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  85 + IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  86 + IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  87 + IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  88 + IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  89 + IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  90 + IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
  91 +};
  92 +
  93 +static iomux_v3_cfg_t const usdhc2_pads[] = {
  94 + IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
  95 + IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
  96 + IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
  97 + IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
  98 + IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */
  99 + IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */
  100 + IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
  101 + IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL),
  102 +};
  103 +
  104 +static struct fsl_esdhc_cfg usdhc_cfg[2] = {
  105 + {USDHC1_BASE_ADDR, 0, 8},
  106 + {USDHC2_BASE_ADDR, 0, 4},
  107 +};
  108 +
  109 +int board_mmc_init(bd_t *bis)
  110 +{
  111 + int i, ret;
  112 + /*
  113 + * According to the board_mmc_init() the following map is done:
  114 + * (U-Boot device node) (Physical Port)
  115 + * mmc0 USDHC1
  116 + * mmc1 USDHC2
  117 + */
  118 + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
  119 + switch (i) {
  120 + case 0:
  121 + init_clk_usdhc(0);
  122 + usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT);
  123 + imx_iomux_v3_setup_multiple_pads(usdhc1_pads,
  124 + ARRAY_SIZE(usdhc1_pads));
  125 + gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset");
  126 + gpio_direction_output(USDHC1_PWR_GPIO, 0);
  127 + udelay(500);
  128 + gpio_direction_output(USDHC1_PWR_GPIO, 1);
  129 + break;
  130 + case 1:
  131 + init_clk_usdhc(1);
  132 + usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT);
  133 + imx_iomux_v3_setup_multiple_pads(usdhc2_pads,
  134 + ARRAY_SIZE(usdhc2_pads));
  135 + gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset");
  136 + gpio_direction_output(USDHC2_PWR_GPIO, 0);
  137 + udelay(500);
  138 + gpio_direction_output(USDHC2_PWR_GPIO, 1);
  139 + break;
  140 + default:
  141 + printf("Warning: you configured more USDHC controllers(%d) than supported by the board\n", i + 1);
  142 + return -EINVAL;
  143 + }
  144 +
  145 + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
  146 + if (ret)
  147 + return ret;
  148 + }
  149 +
  150 + return 0;
  151 +}
  152 +
  153 +#ifdef CONFIG_POWER
  154 +#define I2C_PMIC 0
  155 +int power_init_board(void)
  156 +{
  157 + struct pmic *p;
  158 + int ret;
  159 + unsigned int reg;
  160 +
  161 + ret = power_pfuze100_init(I2C_PMIC);
  162 + if (ret)
  163 + return -ENODEV;
  164 +
  165 + p = pmic_get("PFUZE100");
  166 + ret = pmic_probe(p);
  167 + if (ret)
  168 + return -ENODEV;
  169 +
  170 + pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
  171 + printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
  172 +
  173 + pmic_reg_read(p, PFUZE100_SW3AVOL, &reg);
  174 + if ((reg & 0x3f) != 0x18) {
  175 + reg &= ~0x3f;
  176 + reg |= 0x18;
  177 + pmic_reg_write(p, PFUZE100_SW3AVOL, reg);
  178 + }
  179 +
  180 + ret = pfuze_mode_init(p, APS_PFM);
  181 + if (ret < 0)
  182 + return ret;
  183 +
  184 + /* set SW3A standby mode to off */
  185 + pmic_reg_read(p, PFUZE100_SW3AMODE, &reg);
  186 + reg &= ~0xf;
  187 + reg |= APS_OFF;
  188 + pmic_reg_write(p, PFUZE100_SW3AMODE, reg);
  189 +
  190 + return 0;
  191 +}
  192 +#endif
  193 +
  194 +void spl_board_init(void)
  195 +{
  196 + puts("Normal Boot\n");
  197 +}
  198 +
  199 +#ifdef CONFIG_SPL_LOAD_FIT
  200 +int board_fit_config_name_match(const char *name)
  201 +{
  202 + /* Just empty function now - can't decide what to choose */
  203 + debug("%s: %s\n", __func__, name);
  204 +
  205 + return 0;
  206 +}
  207 +#endif
  208 +
  209 +void board_init_f(ulong dummy)
  210 +{
  211 + int ret;
  212 +
  213 + /* Clear global data */
  214 + memset((void *)gd, 0, sizeof(gd_t));
  215 +
  216 + arch_cpu_init();
  217 +
  218 + init_uart_clk(0);
  219 +
  220 + board_early_init_f();
  221 +
  222 + timer_init();
  223 +
  224 + preloader_console_init();
  225 +
  226 + /* Clear the BSS. */
  227 + memset(__bss_start, 0, __bss_end - __bss_start);
  228 +
  229 + ret = spl_init();
  230 + if (ret) {
  231 + debug("spl_init() failed: %d\n", ret);
  232 + hang();
  233 + }
  234 +
  235 + enable_tzc380();
  236 +
  237 + /* Adjust pmic voltage to 1.0V for 800M */
  238 + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
  239 +
  240 + power_init_board();
  241 +
  242 + /* DDR initialization */
  243 + spl_dram_init();
  244 +
  245 + board_init_r(NULL, 0);
  246 +}
configs/imx8mq_evk_defconfig
Diff comments   View file @ 86ac7a9
  1 +CONFIG_ARM=y
  2 +CONFIG_ARCH_IMX8M=y
  3 +CONFIG_SYS_TEXT_BASE=0x40200000
  4 +CONFIG_SYS_MALLOC_F_LEN=0x2000
  5 +CONFIG_SPL_SERIAL_SUPPORT=y
  6 +CONFIG_TARGET_IMX8MQ_EVK=y
  7 +CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000
  8 +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mq-evk"
  9 +CONFIG_OF_LIST="fsl-imx8mq-evk"
  10 +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage.cfg"
  11 +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
  12 +CONFIG_FIT=y
  13 +CONFIG_SPL_LOAD_FIT=y
  14 +#CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/spl_sd.cfg"
  15 +CONFIG_SPL=y
  16 +CONFIG_SPL_BOARD_INIT=y
  17 +CONFIG_HUSH_PARSER=y
  18 +CONFIG_CMD_GPIO=y
  19 +CONFIG_CMD_I2C=y
  20 +CONFIG_CMD_CACHE=y
  21 +CONFIG_CMD_REGULATOR=y
  22 +CONFIG_OF_CONTROL=y
  23 +CONFIG_DM_GPIO=y
  24 +CONFIG_DM_I2C=y
  25 +CONFIG_DM_MMC=y
  26 +CONFIG_DM_ETH=y
  27 +CONFIG_PINCTRL=y
  28 +CONFIG_PINCTRL_IMX8M=y
  29 +CONFIG_SYS_I2C_MXC=y
  30 +CONFIG_DM_PMIC_PFUZE100=y
  31 +CONFIG_DM_REGULATOR=y
  32 +CONFIG_DM_REGULATOR_PFUZE100=y
  33 +CONFIG_DM_REGULATOR_FIXED=y
  34 +CONFIG_DM_REGULATOR_GPIO=y
  35 +CONFIG_DM_THERMAL=y
  36 +CONFIG_FS_FAT=y
  37 +CONFIG_FIT_EXTERNAL_OFFSET=0x3000
include/configs/imx8mq_evk.h
Diff comments   View file @ 86ac7a9
  1 +/* SPDX-License-Identifier: GPL-2.0+ */
  2 +/*
  3 + * Copyright 2018 NXP
  4 + */
  5 +
  6 +#ifndef __IMX8M_EVK_H
  7 +#define __IMX8M_EVK_H
  8 +
  9 +#include <linux/sizes.h>
  10 +#include <asm/arch/imx-regs.h>
  11 +
  12 +#ifdef CONFIG_SECURE_BOOT
  13 +#define CONFIG_CSF_SIZE 0x2000 /* 8K region */
  14 +#endif
  15 +
  16 +#define CONFIG_SPL_TEXT_BASE 0x7E1000
  17 +#define CONFIG_SPL_MAX_SIZE (124 * 1024)
  18 +#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
  19 +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
  20 +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300
  21 +#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
  22 +
  23 +#ifdef CONFIG_SPL_BUILD
  24 +/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
  25 +#define CONFIG_SPL_WATCHDOG_SUPPORT
  26 +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
  27 +#define CONFIG_SPL_POWER_SUPPORT
  28 +#define CONFIG_SPL_I2C_SUPPORT
  29 +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
  30 +#define CONFIG_SPL_STACK 0x187FF0
  31 +#define CONFIG_SPL_LIBCOMMON_SUPPORT
  32 +#define CONFIG_SPL_LIBGENERIC_SUPPORT
  33 +#define CONFIG_SPL_GPIO_SUPPORT
  34 +#define CONFIG_SPL_MMC_SUPPORT
  35 +#define CONFIG_SPL_BSS_START_ADDR 0x00180000
  36 +#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */
  37 +#define CONFIG_SYS_SPL_MALLOC_START 0x42200000
  38 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */
  39 +#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000
  40 +#define CONFIG_SYS_ICACHE_OFF
  41 +#define CONFIG_SYS_DCACHE_OFF
  42 +
  43 +/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */
  44 +#define CONFIG_MALLOC_F_ADDR 0x182000
  45 +/* For RAW image gives a error info not panic */
  46 +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE
  47 +
  48 +#undef CONFIG_DM_MMC
  49 +#undef CONFIG_DM_PMIC
  50 +#undef CONFIG_DM_PMIC_PFUZE100
  51 +
  52 +#define CONFIG_SYS_I2C
  53 +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
  54 +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
  55 +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
  56 +
  57 +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  58 +
  59 +#define CONFIG_POWER
  60 +#define CONFIG_POWER_I2C
  61 +#define CONFIG_POWER_PFUZE100
  62 +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
  63 +#endif
  64 +
  65 +#define CONFIG_REMAKE_ELF
  66 +
  67 +#define CONFIG_BOARD_EARLY_INIT_F
  68 +#define CONFIG_BOARD_LATE_INIT
  69 +
  70 +#undef CONFIG_CMD_EXPORTENV
  71 +#undef CONFIG_CMD_IMPORTENV
  72 +#undef CONFIG_CMD_IMLS
  73 +
  74 +#undef CONFIG_CMD_CRC32
  75 +#undef CONFIG_BOOTM_NETBSD
  76 +
  77 +/* ENET Config */
  78 +/* ENET1 */
  79 +#if defined(CONFIG_CMD_NET)
  80 +#define CONFIG_CMD_PING
  81 +#define CONFIG_CMD_DHCP
  82 +#define CONFIG_CMD_MII
  83 +#define CONFIG_MII
  84 +#define CONFIG_ETHPRIME "FEC"
  85 +
  86 +#define CONFIG_FEC_MXC
  87 +#define CONFIG_FEC_XCV_TYPE RGMII
  88 +#define CONFIG_FEC_MXC_PHYADDR 0
  89 +#define FEC_QUIRK_ENET_MAC
  90 +
  91 +#define CONFIG_PHY_GIGE
  92 +#define IMX_FEC_BASE 0x30BE0000
  93 +
  94 +#define CONFIG_PHYLIB
  95 +#define CONFIG_PHY_ATHEROS
  96 +#endif
  97 +
  98 +#define CONFIG_MFG_ENV_SETTINGS \
  99 + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \
  100 + "rdinit=/linuxrc " \
  101 + "g_mass_storage.stall=0 g_mass_storage.removable=1 " \
  102 + "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
  103 + "g_mass_storage.iSerialNumber=\"\" "\
  104 + "clk_ignore_unused "\
  105 + "\0" \
  106 + "initrd_addr=0x43800000\0" \
  107 + "initrd_high=0xffffffff\0" \
  108 + "bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
  109 +/* Initial environment variables */
  110 +#define CONFIG_EXTRA_ENV_SETTINGS \
  111 + CONFIG_MFG_ENV_SETTINGS \
  112 + "script=boot.scr\0" \
  113 + "image=Image\0" \
  114 + "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200\0" \
  115 + "fdt_addr=0x43000000\0" \
  116 + "fdt_high=0xffffffffffffffff\0" \
  117 + "boot_fdt=try\0" \
  118 + "fdt_file=fsl-imx8mq-evk.dtb\0" \
  119 + "initrd_addr=0x43800000\0" \
  120 + "initrd_high=0xffffffffffffffff\0" \
  121 + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
  122 + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
  123 + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
  124 + "mmcautodetect=yes\0" \
  125 + "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
  126 + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
  127 + "bootscript=echo Running bootscript from mmc ...; " \
  128 + "source\0" \
  129 + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
  130 + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
  131 + "mmcboot=echo Booting from mmc ...; " \
  132 + "run mmcargs; " \
  133 + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
  134 + "if run loadfdt; then " \
  135 + "booti ${loadaddr} - ${fdt_addr}; " \
  136 + "else " \
  137 + "echo WARN: Cannot load the DT; " \
  138 + "fi; " \
  139 + "else " \
  140 + "echo wait for boot; " \
  141 + "fi;\0" \
  142 + "netargs=setenv bootargs console=${console} " \
  143 + "root=/dev/nfs " \
  144 + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
  145 + "netboot=echo Booting from net ...; " \
  146 + "run netargs; " \
  147 + "if test ${ip_dyn} = yes; then " \
  148 + "setenv get_cmd dhcp; " \
  149 + "else " \
  150 + "setenv get_cmd tftp; " \
  151 + "fi; " \
  152 + "${get_cmd} ${loadaddr} ${image}; " \
  153 + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
  154 + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
  155 + "booti ${loadaddr} - ${fdt_addr}; " \
  156 + "else " \
  157 + "echo WARN: Cannot load the DT; " \
  158 + "fi; " \
  159 + "else " \
  160 + "booti; " \
  161 + "fi;\0"
  162 +
  163 +#define CONFIG_BOOTCOMMAND \
  164 + "mmc dev ${mmcdev}; if mmc rescan; then " \
  165 + "if run loadbootscript; then " \
  166 + "run bootscript; " \
  167 + "else " \
  168 + "if run loadimage; then " \
  169 + "run mmcboot; " \
  170 + "else run netboot; " \
  171 + "fi; " \
  172 + "fi; " \
  173 + "else booti ${loadaddr} - ${fdt_addr}; fi"
  174 +
  175 +/* Link Definitions */
  176 +#define CONFIG_LOADADDR 0x40480000
  177 +
  178 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
  179 +
  180 +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
  181 +#define CONFIG_SYS_INIT_RAM_SIZE 0x80000
  182 +#define CONFIG_SYS_INIT_SP_OFFSET \
  183 + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  184 +#define CONFIG_SYS_INIT_SP_ADDR \
  185 + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  186 +
  187 +#define CONFIG_ENV_OVERWRITE
  188 +#define CONFIG_ENV_OFFSET (64 * SZ_64K)
  189 +#define CONFIG_ENV_SIZE 0x1000
  190 +#define CONFIG_ENV_IS_IN_MMC
  191 +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
  192 +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
  193 +
  194 +/* Size of malloc() pool */
  195 +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2 * 1024)) * 1024)
  196 +
  197 +#define CONFIG_SYS_SDRAM_BASE 0x40000000
  198 +#define PHYS_SDRAM 0x40000000
  199 +#define PHYS_SDRAM_SIZE 0xC0000000 /* 3GB DDR */
  200 +
  201 +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
  202 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
  203 + (PHYS_SDRAM_SIZE >> 1))
  204 +
  205 +#define CONFIG_BAUDRATE 115200
  206 +
  207 +#define CONFIG_MXC_UART
  208 +#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR
  209 +
  210 +/* Monitor Command Prompt */
  211 +#undef CONFIG_SYS_PROMPT
  212 +#define CONFIG_SYS_PROMPT "u-boot=> "
  213 +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  214 +#define CONFIG_SYS_CBSIZE 1024
  215 +#define CONFIG_SYS_MAXARGS 64
  216 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  217 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
  218 + sizeof(CONFIG_SYS_PROMPT) + 16)
  219 +
  220 +#define CONFIG_IMX_BOOTAUX
  221 +
  222 +#define CONFIG_CMD_MMC
  223 +#define CONFIG_FSL_ESDHC
  224 +#define CONFIG_FSL_USDHC
  225 +
  226 +#define CONFIG_SYS_FSL_USDHC_NUM 2
  227 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0
  228 +
  229 +#define CONFIG_DOS_PARTITION
  230 +#define CONFIG_CMD_EXT2
  231 +#define CONFIG_CMD_EXT4
  232 +#define CONFIG_CMD_EXT4_WRITE
  233 +#define CONFIG_CMD_FAT
  234 +
  235 +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
  236 +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
  237 +
  238 +#define CONFIG_MXC_GPIO
  239 +
  240 +#define CONFIG_MXC_OCOTP
  241 +#define CONFIG_CMD_FUSE
  242 +
  243 +/* I2C Configs */
  244 +#define CONFIG_SYS_I2C_SPEED 100000
  245 +
  246 +#define CONFIG_OF_SYSTEM_SETUP
  247 +
  248 +#ifndef CONFIG_SPL_BUILD
  249 +#define CONFIG_DM_PMIC
  250 +#endif
  251 +
  252 +#endif