Eric Lee / smarc-uboot

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Commit 873e3ef90ba98c764af6e05251354332205b9d3a

Authored by Tom Warren
1 parent 3cee35f841
Exists in v2017.01-smarct4x and in 30 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

T210: Add support for 64-bit T210-based P2571 board 

Based on Venice2, incorporates Stephen Warren's
latest P2571 pinmux table.

With Thierry Reding's 64-bit build fixes, this
will build and and boot in 64-bit on my P2571
(when used with a 32-bit AVP loader).

Signed-off-by: Tom Warren <twarren@nvidia.com>

Showing 11 changed files with 617 additions and 0 deletions Side-by-side Diff

arch/arm/mach-tegra/tegra210/Kconfig
Diff comments   View file @ 873e3ef
... ... @@ -3,10 +3,17 @@
3 3 choice
4 4 prompt "Tegra210 board select"
5 5  
  6 +config TARGET_P2571
  7 + bool "NVIDIA Tegra210 P2571 base board"
  8 + help
  9 + P2571 is a P2530 married to a P1963 I/O board
  10 +
6 11 endchoice
7 12  
8 13 config SYS_SOC
9 14 default "tegra210"
  15 +
  16 +source "board/nvidia/p2571/Kconfig"
10 17  
11 18 endif
board/nvidia/p2571/Kconfig
Diff comments   View file @ 873e3ef
  1 +if TARGET_P2571
  2 +
  3 +config SYS_BOARD
  4 + default "p2571"
  5 +
  6 +config SYS_VENDOR
  7 + default "nvidia"
  8 +
  9 +config SYS_CONFIG_NAME
  10 + default "p2571"
  11 +
  12 +endif
board/nvidia/p2571/MAINTAINERS
Diff comments   View file @ 873e3ef
  1 +P2571 BOARD
  2 +M: Tom Warren <twarren@nvidia.com>
  3 +S: Maintained
  4 +F: board/nvidia/p2571/
  5 +F: include/configs/p2571.h
  6 +F: configs/p2571_defconfig
board/nvidia/p2571/Makefile
Diff comments   View file @ 873e3ef
  1 +#
  2 +# (C) Copyright 2013-2015
  3 +# NVIDIA Corporation <www.nvidia.com>
  4 +#
  5 +# SPDX-License-Identifier: GPL-2.0+
  6 +#
  7 +
  8 +obj-y += max77620_init.o
  9 +obj-y += p2571.o
board/nvidia/p2571/max77620_init.c
Diff comments   View file @ 873e3ef
  1 +/*
  2 + * (C) Copyright 2013-2015
  3 + * NVIDIA Corporation <www.nvidia.com>
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#include <common.h>
  9 +#include <asm/io.h>
  10 +#include <asm/arch-tegra/tegra_i2c.h>
  11 +#include "max77620_init.h"
  12 +
  13 +/* MAX77620-PMIC-specific early init code - get CPU rails up, etc */
  14 +
  15 +void tegra_i2c_ll_write_addr(uint addr, uint config)
  16 +{
  17 + struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
  18 +
  19 + writel(addr, &reg->cmd_addr0);
  20 + writel(config, &reg->cnfg);
  21 +}
  22 +
  23 +void tegra_i2c_ll_write_data(uint data, uint config)
  24 +{
  25 + struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
  26 +
  27 + writel(data, &reg->cmd_data1);
  28 + writel(config, &reg->cnfg);
  29 +}
  30 +
  31 +void pmic_enable_cpu_vdd(void)
  32 +{
  33 + uint reg;
  34 + debug("%s entry\n", __func__);
  35 +
  36 + /* Setup/Enable GPIO5 - VDD_CPU_REG_EN */
  37 + debug("%s: Setting GPIO5 to enable CPU regulator\n", __func__);
  38 + /* B3=1=logic high,B2=dontcare,B1=0=output,B0=1=push-pull */
  39 + reg = 0x0900 | MAX77620_GPIO5_REG;
  40 + tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2);
  41 + tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES);
  42 + udelay(10 * 1000);
  43 +
  44 + /* Setup/Enable GPIO1 - VDD_HDMI_5V0_BST_EN */
  45 + debug("%s: Setting GPIO1 to enable HDMI\n", __func__);
  46 + reg = 0x0900 | MAX77620_GPIO1_REG;
  47 + tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2);
  48 + tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES);
  49 + udelay(10 * 1000);
  50 +
  51 + /* GPIO 0,1,5,6,7 = GPIO, 2,3,4 = alt mode */
  52 + reg = 0x1C00 | MAX77620_AME_GPIO;
  53 + tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2);
  54 + tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES);
  55 + udelay(10 * 1000);
  56 +
  57 + /* Disable SD1 Remote Sense, Set SD1 for LPDDR4 to 1.125v */
  58 + debug("%s: Set SD1 for LPDDR4, disable SD1RS, voltage to 1.125v\n",
  59 + __func__);
  60 + /* bit1=0, SD1 remote sense disabled */
  61 + reg = 0x0400 | MAX77620_CNFG2SD_REG;
  62 + tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2);
  63 + tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES);
  64 + udelay(10 * 1000);
  65 +
  66 + /* SD1 output = 1.125V */
  67 + reg = 0x2A00 | MAX77620_SD1_REG;
  68 + tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2);
  69 + tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES);
  70 + udelay(10 * 1000);
  71 +
  72 + debug("%s: Set LDO2 for VDDIO_SDMMC_AP power to 3.3V\n", __func__);
  73 + /* 0xF2 for 3.3v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
  74 + reg = 0xF200 | MAX77620_CNFG1_L2_REG;
  75 + tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2);
  76 + tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES);
  77 + udelay(10 * 1000);
  78 +
  79 + debug("%s: Set LDO1 for USB3 phy power to 1.05V??\n", __func__);
  80 + /* 0xCA for 105v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
  81 + reg = 0xCA00 | MAX77620_CNFG1_L1_REG;
  82 + tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2);
  83 + tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES);
  84 + udelay(10 * 1000);
  85 +}
board/nvidia/p2571/max77620_init.h
Diff comments   View file @ 873e3ef
  1 +/*
  2 + * (C) Copyright 2013-2015
  3 + * NVIDIA Corporation <www.nvidia.com>
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#ifndef _MAX77620_INIT_H_
  9 +#define _MAX77620_INIT_H_
  10 +
  11 +/* MAX77620-PMIC-specific early init regs */
  12 +
  13 +#define MAX77620_I2C_ADDR 0x78 /* or 0x3C 7-bit */
  14 +
  15 +#define MAX77620_SD0_REG 0x16
  16 +#define MAX77620_SD1_REG 0x17
  17 +#define MAX77620_SD2_REG 0x18
  18 +#define MAX77620_SD3_REG 0x19
  19 +#define MAX77620_CNFG2SD_REG 0x22
  20 +
  21 +#define MAX77620_CNFG1_L0_REG 0x23
  22 +#define MAX77620_CNFG2_L0_REG 0x24
  23 +#define MAX77620_CNFG1_L1_REG 0x25
  24 +#define MAX77620_CNFG2_L1_REG 0x26
  25 +#define MAX77620_CNFG1_L2_REG 0x27
  26 +#define MAX77620_CNFG2_L2_REG 0x28
  27 +#define MAX77620_CNFG1_L3_REG 0x29
  28 +#define MAX77620_CNFG2_L3_REG 0x2A
  29 +#define MAX77620_CNFG1_L4_REG 0x2B
  30 +#define MAX77620_CNFG2_L4_REG 0x2C
  31 +#define MAX77620_CNFG1_L5_REG 0x2D
  32 +#define MAX77620_CNFG2_L5_REG 0x2E
  33 +#define MAX77620_CNFG1_L6_REG 0x2F
  34 +#define MAX77620_CNFG2_L6_REG 0x30
  35 +#define MAX77620_CNFG1_L7_REG 0x31
  36 +#define MAX77620_CNFG2_L7_REG 0x32
  37 +#define MAX77620_CNFG1_L8_REG 0x33
  38 +#define MAX77620_CNFG2_L8_REG 0x34
  39 +#define MAX77620_CNFG3_LDO_REG 0x35
  40 +
  41 +#define MAX77620_GPIO0_REG 0x36
  42 +#define MAX77620_GPIO1_REG 0x37
  43 +#define MAX77620_GPIO2_REG 0x38
  44 +#define MAX77620_GPIO3_REG 0x39
  45 +#define MAX77620_GPIO4_REG 0x3A
  46 +#define MAX77620_GPIO5_REG 0x3B
  47 +#define MAX77620_GPIO6_REG 0x3C
  48 +#define MAX77620_GPIO7_REG 0x3D
  49 +#define MAX77620_GPIO_PUE_GPIO 0x3E
  50 +#define MAX77620_GPIO_PDE_GPIO 0x3F
  51 +
  52 +#define MAX77620_AME_GPIO 0x40
  53 +#define MAX77620_REG_ONOFF_CFG1 0x41
  54 +#define MAX77620_REG_ONOFF_CFG2 0x42
  55 +
  56 +#define MAX77620_CID0_REG 0x58
  57 +#define MAX77620_CID1_REG 0x59
  58 +#define MAX77620_CID2_REG 0x5A
  59 +#define MAX77620_CID3_REG 0x5B
  60 +#define MAX77620_CID4_REG 0x5C
  61 +#define MAX77620_CID5_REG 0x5D
  62 +
  63 +#define I2C_SEND_2_BYTES 0x0A02
  64 +
  65 +void pmic_enable_cpu_vdd(void);
  66 +
  67 +#endif /* _MAX77620_INIT_H_ */
board/nvidia/p2571/p2571.c
Diff comments   View file @ 873e3ef
  1 +/*
  2 + * (C) Copyright 2013-2015
  3 + * NVIDIA Corporation <www.nvidia.com>
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#include <common.h>
  9 +#include <asm/arch/gpio.h>
  10 +#include <asm/arch/pinmux.h>
  11 +#include "pinmux-config-p2571.h"
  12 +
  13 +/*
  14 + * Routine: pinmux_init
  15 + * Description: Do individual peripheral pinmux configs
  16 + */
  17 +void pinmux_init(void)
  18 +{
  19 + pinmux_clear_tristate_input_clamping();
  20 +
  21 + gpio_config_table(p2571_gpio_inits,
  22 + ARRAY_SIZE(p2571_gpio_inits));
  23 +
  24 + pinmux_config_pingrp_table(p2571_pingrps,
  25 + ARRAY_SIZE(p2571_pingrps));
  26 +
  27 + pinmux_config_drvgrp_table(p2571_drvgrps,
  28 + ARRAY_SIZE(p2571_drvgrps));
  29 +}
board/nvidia/p2571/pinmux-config-p2571.h
Diff comments   View file @ 873e3ef
  1 +/*
  2 + * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#ifndef _PINMUX_CONFIG_P2571_H_
  8 +#define _PINMUX_CONFIG_P2571_H_
  9 +
  10 +#define GPIO_INIT(_gpio, _init) \
  11 + { \
  12 + .gpio = GPIO_P##_gpio, \
  13 + .init = TEGRA_GPIO_INIT_##_init, \
  14 + }
  15 +
  16 +static const struct tegra_gpio_config p2571_gpio_inits[] = {
  17 + /* gpio, init_val */
  18 + GPIO_INIT(A0, IN),
  19 + GPIO_INIT(A5, IN),
  20 + GPIO_INIT(D4, IN),
  21 + GPIO_INIT(E4, OUT0),
  22 + GPIO_INIT(G0, IN),
  23 + GPIO_INIT(H0, OUT0),
  24 + GPIO_INIT(H2, IN),
  25 + GPIO_INIT(H3, OUT0),
  26 + GPIO_INIT(H4, OUT0),
  27 + GPIO_INIT(H5, IN),
  28 + GPIO_INIT(I0, OUT0),
  29 + GPIO_INIT(I1, IN),
  30 + GPIO_INIT(V1, OUT0),
  31 + GPIO_INIT(V6, OUT1),
  32 + GPIO_INIT(X4, IN),
  33 + GPIO_INIT(X6, IN),
  34 + GPIO_INIT(X7, IN),
  35 + GPIO_INIT(Y1, IN),
  36 + GPIO_INIT(Z0, IN),
  37 + GPIO_INIT(Z4, OUT0),
  38 + GPIO_INIT(BB2, OUT0),
  39 + GPIO_INIT(CC1, IN),
  40 + GPIO_INIT(CC3, IN),
  41 +};
  42 +
  43 +#define PINCFG(_pingrp, _mux, _pull, _tri, _io, _od, _e_io_hv) \
  44 + { \
  45 + .pingrp = PMUX_PINGRP_##_pingrp, \
  46 + .func = PMUX_FUNC_##_mux, \
  47 + .pull = PMUX_PULL_##_pull, \
  48 + .tristate = PMUX_TRI_##_tri, \
  49 + .io = PMUX_PIN_##_io, \
  50 + .od = PMUX_PIN_OD_##_od, \
  51 + .e_io_hv = PMUX_PIN_E_IO_HV_##_e_io_hv, \
  52 + .lock = PMUX_PIN_LOCK_DEFAULT, \
  53 + }
  54 +
  55 +static const struct pmux_pingrp_config p2571_pingrps[] = {
  56 + /* pingrp, mux, pull, tri, e_input, od, e_io_hv */
  57 + PINCFG(PEX_L0_RST_N_PA0, DEFAULT, UP, NORMAL, INPUT, DISABLE, NORMAL),
  58 + PINCFG(PEX_L0_CLKREQ_N_PA1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL),
  59 + PINCFG(PEX_WAKE_N_PA2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL),
  60 + PINCFG(PEX_L1_RST_N_PA3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL),
  61 + PINCFG(PEX_L1_CLKREQ_N_PA4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL),
  62 + PINCFG(SATA_LED_ACTIVE_PA5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
  63 + PINCFG(PA6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  64 + PINCFG(DAP1_FS_PB0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  65 + PINCFG(DAP1_DIN_PB1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  66 + PINCFG(DAP1_DOUT_PB2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  67 + PINCFG(DAP1_SCLK_PB3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  68 + PINCFG(SPI2_MOSI_PB4, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  69 + PINCFG(SPI2_MISO_PB5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  70 + PINCFG(SPI2_SCK_PB6, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  71 + PINCFG(SPI2_CS0_PB7, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  72 + PINCFG(SPI1_MOSI_PC0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  73 + PINCFG(SPI1_MISO_PC1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  74 + PINCFG(SPI1_SCK_PC2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  75 + PINCFG(SPI1_CS0_PC3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  76 + PINCFG(SPI1_CS1_PC4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  77 + PINCFG(SPI4_SCK_PC5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  78 + PINCFG(SPI4_CS0_PC6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  79 + PINCFG(SPI4_MOSI_PC7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  80 + PINCFG(SPI4_MISO_PD0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  81 + PINCFG(UART3_TX_PD1, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  82 + PINCFG(UART3_RX_PD2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  83 + PINCFG(UART3_RTS_PD3, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  84 + PINCFG(UART3_CTS_PD4, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
  85 + PINCFG(DMIC1_CLK_PE0, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
  86 + PINCFG(DMIC1_DAT_PE1, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
  87 + PINCFG(DMIC2_CLK_PE2, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
  88 + PINCFG(DMIC2_DAT_PE3, I2S3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
  89 + PINCFG(DMIC3_CLK_PE4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
  90 + PINCFG(DMIC3_DAT_PE5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  91 + PINCFG(PE6, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  92 + PINCFG(PE7, PWM3, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
  93 + PINCFG(GEN3_I2C_SCL_PF0, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
  94 + PINCFG(GEN3_I2C_SDA_PF1, I2C3, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
  95 + PINCFG(UART2_TX_PG0, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
  96 + PINCFG(UART2_RX_PG1, UARTB, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  97 + PINCFG(UART2_RTS_PG2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  98 + PINCFG(UART2_CTS_PG3, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  99 + PINCFG(WIFI_EN_PH0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
  100 + PINCFG(WIFI_RST_PH1, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  101 + PINCFG(WIFI_WAKE_AP_PH2, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
  102 + PINCFG(AP_WAKE_BT_PH3, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
  103 + PINCFG(BT_RST_PH4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
  104 + PINCFG(BT_WAKE_AP_PH5, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
  105 + PINCFG(PH6, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  106 + PINCFG(AP_WAKE_NFC_PH7, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  107 + PINCFG(NFC_EN_PI0, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
  108 + PINCFG(NFC_INT_PI1, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
  109 + PINCFG(GPS_EN_PI2, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  110 + PINCFG(GPS_RST_PI3, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  111 + PINCFG(UART4_TX_PI4, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
  112 + PINCFG(UART4_RX_PI5, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
  113 + PINCFG(UART4_RTS_PI6, UARTD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
  114 + PINCFG(UART4_CTS_PI7, UARTD, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
  115 + PINCFG(GEN1_I2C_SDA_PJ0, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
  116 + PINCFG(GEN1_I2C_SCL_PJ1, I2C1, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
  117 + PINCFG(GEN2_I2C_SCL_PJ2, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
  118 + PINCFG(GEN2_I2C_SDA_PJ3, I2C2, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
  119 + PINCFG(DAP4_FS_PJ4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  120 + PINCFG(DAP4_DIN_PJ5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  121 + PINCFG(DAP4_DOUT_PJ6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  122 + PINCFG(DAP4_SCLK_PJ7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  123 + PINCFG(PK0, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  124 + PINCFG(PK1, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  125 + PINCFG(PK2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  126 + PINCFG(PK3, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  127 + PINCFG(PK4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  128 + PINCFG(PK5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  129 + PINCFG(PK6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  130 + PINCFG(PK7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  131 + PINCFG(PL0, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  132 + PINCFG(PL1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  133 + PINCFG(SDMMC1_CLK_PM0, SDMMC1, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
  134 + PINCFG(SDMMC1_CMD_PM1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
  135 + PINCFG(SDMMC1_DAT3_PM2, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
  136 + PINCFG(SDMMC1_DAT2_PM3, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
  137 + PINCFG(SDMMC1_DAT1_PM4, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
  138 + PINCFG(SDMMC1_DAT0_PM5, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
  139 + PINCFG(SDMMC3_CLK_PP0, SDMMC3, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
  140 + PINCFG(SDMMC3_CMD_PP1, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
  141 + PINCFG(SDMMC3_DAT3_PP2, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
  142 + PINCFG(SDMMC3_DAT2_PP3, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
  143 + PINCFG(SDMMC3_DAT1_PP4, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
  144 + PINCFG(SDMMC3_DAT0_PP5, SDMMC3, UP, NORMAL, INPUT, DISABLE, DEFAULT),
  145 + PINCFG(CAM1_MCLK_PS0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  146 + PINCFG(CAM2_MCLK_PS1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  147 + PINCFG(CAM_I2C_SCL_PS2, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
  148 + PINCFG(CAM_I2C_SDA_PS3, I2CVI, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
  149 + PINCFG(CAM_RST_PS4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  150 + PINCFG(CAM_AF_EN_PS5, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  151 + PINCFG(CAM_FLASH_EN_PS6, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  152 + PINCFG(CAM1_PWDN_PS7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  153 + PINCFG(CAM2_PWDN_PT0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  154 + PINCFG(CAM1_STROBE_PT1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  155 + PINCFG(UART1_TX_PU0, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
  156 + PINCFG(UART1_RX_PU1, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT),
  157 + PINCFG(UART1_RTS_PU2, UARTA, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
  158 + PINCFG(UART1_CTS_PU3, UARTA, UP, NORMAL, INPUT, DISABLE, DEFAULT),
  159 + PINCFG(LCD_BL_PWM_PV0, PWM0, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
  160 + PINCFG(LCD_BL_EN_PV1, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
  161 + PINCFG(LCD_RST_PV2, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  162 + PINCFG(LCD_GPIO1_PV3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  163 + PINCFG(LCD_GPIO2_PV4, PWM1, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
  164 + PINCFG(AP_READY_PV5, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  165 + PINCFG(TOUCH_RST_PV6, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
  166 + PINCFG(TOUCH_CLK_PV7, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  167 + PINCFG(MODEM_WAKE_AP_PX0, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  168 + PINCFG(TOUCH_INT_PX1, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  169 + PINCFG(MOTION_INT_PX2, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  170 + PINCFG(ALS_PROX_INT_PX3, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  171 + PINCFG(TEMP_ALERT_PX4, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
  172 + PINCFG(BUTTON_POWER_ON_PX5, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  173 + PINCFG(BUTTON_VOL_UP_PX6, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
  174 + PINCFG(BUTTON_VOL_DOWN_PX7, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
  175 + PINCFG(BUTTON_SLIDE_SW_PY0, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  176 + PINCFG(BUTTON_HOME_PY1, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
  177 + PINCFG(LCD_TE_PY2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  178 + PINCFG(PWR_I2C_SCL_PY3, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
  179 + PINCFG(PWR_I2C_SDA_PY4, I2CPMU, NORMAL, NORMAL, INPUT, DISABLE, NORMAL),
  180 + PINCFG(CLK_32K_OUT_PY5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
  181 + PINCFG(PZ0, DEFAULT, UP, NORMAL, INPUT, DISABLE, DEFAULT),
  182 + PINCFG(PZ1, SDMMC1, UP, NORMAL, INPUT, DISABLE, DEFAULT),
  183 + PINCFG(PZ2, RSVD2, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  184 + PINCFG(PZ3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  185 + PINCFG(PZ4, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
  186 + PINCFG(PZ5, SOC, UP, NORMAL, INPUT, DISABLE, DEFAULT),
  187 + PINCFG(DAP2_FS_PAA0, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
  188 + PINCFG(DAP2_SCLK_PAA1, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
  189 + PINCFG(DAP2_DIN_PAA2, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
  190 + PINCFG(DAP2_DOUT_PAA3, I2S2, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
  191 + PINCFG(AUD_MCLK_PBB0, AUD, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
  192 + PINCFG(DVFS_PWM_PBB1, CLDVFS, NORMAL, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  193 + PINCFG(DVFS_CLK_PBB2, DEFAULT, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
  194 + PINCFG(GPIO_X1_AUD_PBB3, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  195 + PINCFG(GPIO_X3_AUD_PBB4, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  196 + PINCFG(HDMI_CEC_PCC0, CEC, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
  197 + PINCFG(HDMI_INT_DP_HPD_PCC1, DEFAULT, DOWN, NORMAL, INPUT, DISABLE, NORMAL),
  198 + PINCFG(SPDIF_OUT_PCC2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  199 + PINCFG(SPDIF_IN_PCC3, DEFAULT, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
  200 + PINCFG(USB_VBUS_EN0_PCC4, USB, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
  201 + PINCFG(USB_VBUS_EN1_PCC5, USB, NORMAL, NORMAL, INPUT, DISABLE, HIGH),
  202 + PINCFG(DP_HPD0_PCC6, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  203 + PINCFG(PCC7, RSVD0, DOWN, TRISTATE, OUTPUT, DISABLE, NORMAL),
  204 + PINCFG(SPI2_CS1_PDD0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  205 + PINCFG(QSPI_SCK_PEE0, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  206 + PINCFG(QSPI_CS_N_PEE1, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  207 + PINCFG(QSPI_IO0_PEE2, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  208 + PINCFG(QSPI_IO1_PEE3, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  209 + PINCFG(QSPI_IO2_PEE4, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  210 + PINCFG(QSPI_IO3_PEE5, RSVD1, DOWN, TRISTATE, OUTPUT, DISABLE, DEFAULT),
  211 + PINCFG(CORE_PWR_REQ, CORE, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
  212 + PINCFG(CPU_PWR_REQ, CPU, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
  213 + PINCFG(PWR_INT_N, PMI, UP, NORMAL, INPUT, DISABLE, DEFAULT),
  214 + PINCFG(CLK_32K_IN, CLK, NORMAL, NORMAL, INPUT, DISABLE, DEFAULT),
  215 + PINCFG(JTAG_RTCK, JTAG, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
  216 + PINCFG(CLK_REQ, SYS, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
  217 + PINCFG(SHUTDOWN, SHUTDOWN, NORMAL, NORMAL, OUTPUT, DISABLE, DEFAULT),
  218 +};
  219 +
  220 +#define DRVCFG(_drvgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
  221 + { \
  222 + .drvgrp = PMUX_DRVGRP_##_drvgrp, \
  223 + .slwf = _slwf, \
  224 + .slwr = _slwr, \
  225 + .drvup = _drvup, \
  226 + .drvdn = _drvdn, \
  227 + .lpmd = PMUX_LPMD_##_lpmd, \
  228 + .schmt = PMUX_SCHMT_##_schmt, \
  229 + .hsm = PMUX_HSM_##_hsm, \
  230 + }
  231 +
  232 +static const struct pmux_drvgrp_config p2571_drvgrps[] = {
  233 +};
  234 +
  235 +#endif /* PINMUX_CONFIG_P2571_H */
configs/p2571_defconfig
Diff comments   View file @ 873e3ef
  1 +CONFIG_ARM=y
  2 +CONFIG_TEGRA=y
  3 +CONFIG_TEGRA210=y
  4 +CONFIG_TARGET_P2571=y
  5 +CONFIG_DEFAULT_DEVICE_TREE="tegra210-p2571"
  6 +# CONFIG_CMD_IMI is not set
  7 +# CONFIG_CMD_IMLS is not set
  8 +# CONFIG_CMD_FLASH is not set
  9 +# CONFIG_CMD_FPGA is not set
  10 +# CONFIG_CMD_SETEXPR is not set
  11 +# CONFIG_CMD_NFS is not set
  12 +CONFIG_SPL_DM=y
  13 +CONFIG_SPI_FLASH=y
  14 +CONFIG_USB=y
  15 +CONFIG_DM_USB=y
  16 +CONFIG_USE_PRIVATE_LIBGCC=y
include/configs/p2571.h
Diff comments   View file @ 873e3ef
  1 +/*
  2 + * (C) Copyright 2013-2015
  3 + * NVIDIA Corporation <www.nvidia.com>
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#ifndef _P2571_H
  9 +#define _P2571_H
  10 +
  11 +#include <linux/sizes.h>
  12 +
  13 +/* enable PMIC */
  14 +#define CONFIG_MAX77620_POWER
  15 +
  16 +#include "tegra210-common.h"
  17 +
  18 +/* High-level configuration options */
  19 +#define V_PROMPT "Tegra210 (P2571) # "
  20 +#define CONFIG_TEGRA_BOARD_STRING "NVIDIA P2571"
  21 +
  22 +/* Board-specific serial config */
  23 +#define CONFIG_SERIAL_MULTI
  24 +#define CONFIG_TEGRA_ENABLE_UARTA
  25 +#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
  26 +
  27 +/* I2C */
  28 +#define CONFIG_SYS_I2C_TEGRA
  29 +#define CONFIG_CMD_I2C
  30 +
  31 +/* SD/MMC */
  32 +#define CONFIG_MMC
  33 +#define CONFIG_GENERIC_MMC
  34 +#define CONFIG_TEGRA_MMC
  35 +#define CONFIG_CMD_MMC
  36 +
  37 +/* Environment in eMMC, at the end of 2nd "boot sector" */
  38 +#define CONFIG_ENV_IS_IN_MMC
  39 +#define CONFIG_SYS_MMC_ENV_DEV 0
  40 +#define CONFIG_SYS_MMC_ENV_PART 2
  41 +#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE)
  42 +
  43 +/* SPI */
  44 +#define CONFIG_TEGRA114_SPI /* Compatible w/ Tegra114 SPI */
  45 +#define CONFIG_TEGRA114_SPI_CTRLS 6
  46 +#define CONFIG_SPI_FLASH_WINBOND
  47 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
  48 +#define CONFIG_SF_DEFAULT_SPEED 24000000
  49 +#define CONFIG_CMD_SPI
  50 +#define CONFIG_CMD_SF
  51 +#define CONFIG_SPI_FLASH_SIZE (4 << 20)
  52 +
  53 +/* USB2.0 Host support */
  54 +#define CONFIG_USB_EHCI
  55 +#define CONFIG_USB_EHCI_TEGRA
  56 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  57 +#define CONFIG_USB_STORAGE
  58 +#define CONFIG_CMD_USB
  59 +
  60 +/* USB networking support */
  61 +#define CONFIG_USB_HOST_ETHER
  62 +#define CONFIG_USB_ETHER_ASIX
  63 +
  64 +/* General networking support */
  65 +#define CONFIG_CMD_DHCP
  66 +
  67 +/*
  68 + * TODO(twarren@nvidia.com) - add tegra-common-usb-gadget.h back
  69 + * breaks 64-bit build in ci_udc.c
  70 + */
  71 +#include "tegra-common-post.h"
  72 +
  73 +#define COUNTER_FREQUENCY 38400000
  74 +
  75 +#endif /* _P2571_H */
include/configs/tegra210-common.h
Diff comments   View file @ 873e3ef
  1 +/*
  2 + * (C) Copyright 2013-2015
  3 + * NVIDIA Corporation <www.nvidia.com>
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#ifndef _TEGRA210_COMMON_H_
  9 +#define _TEGRA210_COMMON_H_
  10 +
  11 +#include "tegra-common.h"
  12 +
  13 +/* Cortex-A57 uses a cache line size of 64 bytes */
  14 +#define CONFIG_SYS_CACHELINE_SIZE 64
  15 +
  16 +/*
  17 + * NS16550 Configuration
  18 + */
  19 +#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
  20 +
  21 +/*
  22 + * Miscellaneous configurable options
  23 + */
  24 +#define CONFIG_STACKBASE 0x82800000 /* 40MB */
  25 +
  26 +/*-----------------------------------------------------------------------
  27 + * Physical Memory Map
  28 + */
  29 +#define CONFIG_SYS_TEXT_BASE 0x8010E000
  30 +
  31 +/* Generic Interrupt Controller */
  32 +#define CONFIG_GICV2
  33 +
  34 +/*
  35 + * Memory layout for where various images get loaded by boot scripts:
  36 + *
  37 + * scriptaddr can be pretty much anywhere that doesn't conflict with something
  38 + * else. Put it above BOOTMAPSZ to eliminate conflicts.
  39 + *
  40 + * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
  41 + * something else. Put it above BOOTMAPSZ to eliminate conflicts.
  42 + *
  43 + * kernel_addr_r must be within the first 128M of RAM in order for the
  44 + * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
  45 + * decompress itself to 0x8000 after the start of RAM, kernel_addr_r
  46 + * should not overlap that area, or the kernel will have to copy itself
  47 + * somewhere else before decompression. Similarly, the address of any other
  48 + * data passed to the kernel shouldn't overlap the start of RAM. Pushing
  49 + * this up to 16M allows for a sizable kernel to be decompressed below the
  50 + * compressed load address.
  51 + *
  52 + * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
  53 + * the compressed kernel to be up to 16M too.
  54 + *
  55 + * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
  56 + * for the FDT/DTB to be up to 1M, which is hopefully plenty.
  57 + */
  58 +#define CONFIG_LOADADDR 0x81000000
  59 +#define MEM_LAYOUT_ENV_SETTINGS \
  60 + "scriptaddr=0x90000000\0" \
  61 + "pxefile_addr_r=0x90100000\0" \
  62 + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
  63 + "fdt_addr_r=0x82000000\0" \
  64 + "ramdisk_addr_r=0x82100000\0"
  65 +
  66 +/* Defines for SPL */
  67 +#define CONFIG_SPL_TEXT_BASE 0x80108000
  68 +#define CONFIG_SYS_SPL_MALLOC_START 0x80090000
  69 +#define CONFIG_SPL_STACK 0x800ffffc
  70 +
  71 +/* For USB EHCI controller */
  72 +#define CONFIG_EHCI_IS_TDI
  73 +#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
  74 +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
  75 +
  76 +#endif /* _TEGRA210_COMMON_H_ */