- PPC405EP support added.

- CONFIG_UART1_CONSOLE added (see README).

- PPC405EP support added.
- CONFIG_UART1_CONSOLE added (see README).
stroese
1 parent b867d705b6
Showing 1 changed file with 103 additions and 66 deletions Side-by-side Diff
cpu/ppc4xx/serial.c
@@ -266,7 +266,7 @@
  
  
 /*****************************************************************************/
-#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440)
+#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || defined(CONFIG_405EP)
  
 #if defined(CONFIG_440)
 #define UART0_BASE  CFG_PERIPHERAL_BASE + 0x00000200
  
  
  
@@ -274,15 +274,36 @@
 #define CR0_MASK        0x3fff0000
 #define CR0_EXTCLK_ENA  0x00600000
 #define CR0_UDIV_POS    16
-#else
-#define UART_BASE_PTR   0xF800FFFC;	/* pointer to uart base */
+#elif defined(CONFIG_405EP)
 #define UART0_BASE      0xef600300
 #define UART1_BASE      0xef600400
+#define UCR0_MASK       0x0000007f
+#define UCR1_MASK       0x00007f00
+#define UCR0_UDIV_POS   0
+#define UCR1_UDIV_POS   8
+#define UDIV_MAX        127
+#else /* CONFIG_405GP || CONFIG_405CR */
+#define UART0_BASE      0xef600300
+#define UART1_BASE      0xef600400
 #define CR0_MASK        0x00001fff
 #define CR0_EXTCLK_ENA  0x000000c0
 #define CR0_UDIV_POS    1
+#define UDIV_MAX        32
 #endif
  
+/* using serial port 0 or 1 as U-Boot console ? */
+#if defined(CONFIG_UART1_CONSOLE)
+#define ACTING_UART0_BASE	UART1_BASE
+#define ACTING_UART1_BASE	UART0_BASE
+#else
+#define ACTING_UART0_BASE	UART0_BASE
+#define ACTING_UART1_BASE	UART1_BASE
+#endif
+
+#if defined(CONFIG_405EP) && defined(CFG_EXT_SERIAL_CLOCK)
+#error "External serial clock not supported on IBM PPC405EP!"
+#endif
+
 #define UART_RBR    0x00
 #define UART_THR    0x00
 #define UART_IER    0x01
@@ -299,7 +320,7 @@
 /*-----------------------------------------------------------------------------+
   | Line Status Register.
   +-----------------------------------------------------------------------------*/
-/*#define asyncLSRport1           UART0_BASE+0x05 */
+/*#define asyncLSRport1           ACTING_UART0_BASE+0x05 */
 #define asyncLSRDataReady1            0x01
 #define asyncLSROverrunError1         0x02
 #define asyncLSRParityError1          0x04
@@ -312,8 +333,8 @@
 /*-----------------------------------------------------------------------------+
   | Miscellanies defines.
   +-----------------------------------------------------------------------------*/
-/*#define asyncTxBufferport1      UART0_BASE+0x00 */
-/*#define asyncRxBufferport1      UART0_BASE+0x00 */
+/*#define asyncTxBufferport1      ACTING_UART0_BASE+0x00 */
+/*#define asyncRxBufferport1      ACTING_UART0_BASE+0x00 */
  
  
 #if CONFIG_SERIAL_SOFTWARE_FIFO
@@ -412,16 +433,16 @@
 	reg |= (udiv - 1) << CR0_UDIV_POS;	/* set the UART divisor */
 	mtdcr (cntrl0, reg);
  
-	out8 (UART0_BASE + UART_LCR, 0x80);	/* set DLAB bit */
-	out8 (UART0_BASE + UART_DLL, bdiv);	/* set baudrate divisor */
-	out8 (UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
-	out8 (UART0_BASE + UART_LCR, 0x03);	/* clear DLAB; set 8 bits, no parity */
-	out8 (UART0_BASE + UART_FCR, 0x00);	/* disable FIFO */
-	out8 (UART0_BASE + UART_MCR, 0x00);	/* no modem control DTR RTS */
-	val = in8 (UART0_BASE + UART_LSR);	/* clear line status */
-	val = in8 (UART0_BASE + UART_RBR);	/* read receive buffer */
-	out8 (UART0_BASE + UART_SCR, 0x00);	/* set scratchpad */
-	out8 (UART0_BASE + UART_IER, 0x00);	/* set interrupt enable reg */
+	out8 (ACTING_UART0_BASE + UART_LCR, 0x80);	/* set DLAB bit */
+	out8 (ACTING_UART0_BASE + UART_DLL, bdiv);	/* set baudrate divisor */
+	out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
+	out8 (ACTING_UART0_BASE + UART_LCR, 0x03);	/* clear DLAB; set 8 bits, no parity */
+	out8 (ACTING_UART0_BASE + UART_FCR, 0x00);	/* disable FIFO */
+	out8 (ACTING_UART0_BASE + UART_MCR, 0x00);	/* no modem control DTR RTS */
+	val = in8 (ACTING_UART0_BASE + UART_LSR);	/* clear line status */
+	val = in8 (ACTING_UART0_BASE + UART_RBR);	/* read receive buffer */
+	out8 (ACTING_UART0_BASE + UART_SCR, 0x00);	/* set scratchpad */
+	out8 (ACTING_UART0_BASE + UART_IER, 0x00);	/* set interrupt enable reg */
  
 	return (0);
 }
@@ -439,6 +460,17 @@
 	unsigned short bdiv;
 	volatile char val;
  
+#ifdef CONFIG_405EP
+	reg = mfdcr(cpc0_ucr) & ~(UCR0_MASK | UCR1_MASK);
+	clk = gd->cpu_clk;
+	tmp = CFG_BASE_BAUD * 16;
+	udiv = (clk + tmp / 2) / tmp;
+	if (udiv > UDIV_MAX)                    /* max. n bits for udiv */
+		udiv = UDIV_MAX;
+	reg |= (udiv) << UCR0_UDIV_POS;	        /* set the UART divisor */
+	reg |= (udiv) << UCR1_UDIV_POS;	        /* set the UART divisor */
+	mtdcr (cpc0_ucr, reg);
+#else /* CONFIG_405EP */
 	reg = mfdcr(cntrl0) & ~CR0_MASK;
 #ifdef CFG_EXT_SERIAL_CLOCK
 	clk = CFG_EXT_SERIAL_CLOCK;
  
  
  
@@ -451,27 +483,27 @@
 #else
 	tmp = CFG_BASE_BAUD * 16;
 	udiv = (clk + tmp / 2) / tmp;
-	if (udiv > 32)                          /* max. 5 bits for udiv */
-		udiv = 32;
+	if (udiv > UDIV_MAX)                    /* max. n bits for udiv */
+		udiv = UDIV_MAX;
 #endif
 #endif
-
 	reg |= (udiv - 1) << CR0_UDIV_POS;	/* set the UART divisor */
 	mtdcr (cntrl0, reg);
+#endif /* CONFIG_405EP */
  
 	tmp = gd->baudrate * udiv * 16;
 	bdiv = (clk + tmp / 2) / tmp;
  
-	out8 (UART0_BASE + UART_LCR, 0x80);	/* set DLAB bit */
-	out8 (UART0_BASE + UART_DLL, bdiv);	/* set baudrate divisor */
-	out8 (UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
-	out8 (UART0_BASE + UART_LCR, 0x03);	/* clear DLAB; set 8 bits, no parity */
-	out8 (UART0_BASE + UART_FCR, 0x00);	/* disable FIFO */
-	out8 (UART0_BASE + UART_MCR, 0x00);	/* no modem control DTR RTS */
-	val = in8 (UART0_BASE + UART_LSR);	/* clear line status */
-	val = in8 (UART0_BASE + UART_RBR);	/* read receive buffer */
-	out8 (UART0_BASE + UART_SCR, 0x00);	/* set scratchpad */
-	out8 (UART0_BASE + UART_IER, 0x00);	/* set interrupt enable reg */
+	out8 (ACTING_UART0_BASE + UART_LCR, 0x80);	/* set DLAB bit */
+	out8 (ACTING_UART0_BASE + UART_DLL, bdiv);	/* set baudrate divisor */
+	out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
+	out8 (ACTING_UART0_BASE + UART_LCR, 0x03);	/* clear DLAB; set 8 bits, no parity */
+	out8 (ACTING_UART0_BASE + UART_FCR, 0x00);	/* disable FIFO */
+	out8 (ACTING_UART0_BASE + UART_MCR, 0x00);	/* no modem control DTR RTS */
+	val = in8 (ACTING_UART0_BASE + UART_LSR);	/* clear line status */
+	val = in8 (ACTING_UART0_BASE + UART_RBR);	/* read receive buffer */
+	out8 (ACTING_UART0_BASE + UART_SCR, 0x00);	/* set scratchpad */
+	out8 (ACTING_UART0_BASE + UART_IER, 0x00);	/* set interrupt enable reg */
  
 	return (0);
 }
  
  
@@ -492,14 +524,19 @@
 #else
 	clk = gd->cpu_clk;
 #endif
+
+#ifdef CONFIG_405EP
+	udiv = ((mfdcr (cpc0_ucr) & UCR0_MASK) >> UCR0_UDIV_POS);
+#else
 	udiv = ((mfdcr (cntrl0) & 0x3e) >> 1) + 1;
+#endif /* CONFIG_405EP */
 	tmp = gd->baudrate * udiv * 16;
 	bdiv = (clk + tmp / 2) / tmp;
  
-	out8 (UART0_BASE + UART_LCR, 0x80);	/* set DLAB bit */
-	out8 (UART0_BASE + UART_DLL, bdiv);	/* set baudrate divisor */
-	out8 (UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
-	out8 (UART0_BASE + UART_LCR, 0x03);	/* clear DLAB; set 8 bits, no parity */
+	out8 (ACTING_UART0_BASE + UART_LCR, 0x80);	/* set DLAB bit */
+	out8 (ACTING_UART0_BASE + UART_DLL, bdiv);	/* set baudrate divisor */
+	out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
+	out8 (ACTING_UART0_BASE + UART_LCR, 0x03);	/* clear DLAB; set 8 bits, no parity */
 }
  
  
  
@@ -512,11 +549,11 @@
  
 	/* check THRE bit, wait for transmiter available */
 	for (i = 1; i < 3500; i++) {
-		if ((in8 (UART0_BASE + UART_LSR) & 0x20) == 0x20)
+		if ((in8 (ACTING_UART0_BASE + UART_LSR) & 0x20) == 0x20)
 			break;
 		udelay (100);
 	}
-	out8 (UART0_BASE + UART_THR, c);	/* put character out */
+	out8 (ACTING_UART0_BASE + UART_THR, c);	/* put character out */
 }
  
  
@@ -536,7 +573,7 @@
 #if defined(CONFIG_HW_WATCHDOG)
 		WATCHDOG_RESET ();	/* Reset HW Watchdog, if needed */
 #endif	/* CONFIG_HW_WATCHDOG */
-		status = in8 (UART0_BASE + UART_LSR);
+		status = in8 (ACTING_UART0_BASE + UART_LSR);
 		if ((status & asyncLSRDataReady1) != 0x0) {
 			break;
 		}
  
@@ -544,14 +581,14 @@
 				asyncLSROverrunError1 |
 				asyncLSRParityError1  |
 				asyncLSRBreakInterrupt1 )) != 0) {
-			out8 (UART0_BASE + UART_LSR,
+			out8 (ACTING_UART0_BASE + UART_LSR,
 			      asyncLSRFramingError1 |
 			      asyncLSROverrunError1 |
 			      asyncLSRParityError1  |
 			      asyncLSRBreakInterrupt1);
 		}
 	}
-	return (0x000000ff & (int) in8 (UART0_BASE));
+	return (0x000000ff & (int) in8 (ACTING_UART0_BASE));
 }
  
  
@@ -559,7 +596,7 @@
 {
 	unsigned char status;
  
-	status = in8 (UART0_BASE + UART_LSR);
+	status = in8 (ACTING_UART0_BASE + UART_LSR);
 	if ((status & asyncLSRDataReady1) != 0x0) {
 		return (1);
 	}
@@ -567,7 +604,7 @@
 			asyncLSROverrunError1 |
 			asyncLSRParityError1  |
 			asyncLSRBreakInterrupt1 )) != 0) {
-		out8 (UART0_BASE + UART_LSR,
+		out8 (ACTING_UART0_BASE + UART_LSR,
 		      asyncLSRFramingError1 |
 		      asyncLSROverrunError1 |
 		      asyncLSRParityError1  |
@@ -601,8 +638,8 @@
 			rx_put = 0;
 		if (space < CONFIG_SERIAL_SOFTWARE_FIFO / 4) {
 			/* Stop flow by setting RTS inactive */
-			out8 (UART0_BASE + UART_MCR,
-			      in8 (UART0_BASE + UART_MCR) & (0xFF ^ 0x02));
+			out8 (ACTING_UART0_BASE + UART_MCR,
+			      in8 (ACTING_UART0_BASE + UART_MCR) & (0xFF ^ 0x02));
 		}
 	}
 	buf_info.rx_put = rx_put;
@@ -615,7 +652,7 @@
 	buf_info.rx_put = 0;
 	buf_info.rx_get = 0;
  
-	if (in8 (UART0_BASE + UART_MSR) & 0x10) {
+	if (in8 (ACTING_UART0_BASE + UART_MSR) & 0x10) {
 		serial_puts ("Check CTS signal present on serial port: OK.\n");
 	} else {
 		serial_puts ("WARNING: CTS signal not present on serial port.\n");
  
  
  
  
  
@@ -626,24 +663,24 @@
 			      (void *) &buf_info /*void *arg */ );
  
 	/* Enable "RX Data Available" Interrupt on UART */
-	/* out8(UART0_BASE + UART_IER, in8(UART0_BASE + UART_IER) |0x01); */
-	out8 (UART0_BASE + UART_IER, 0x01);
+	/* out8(ACTING_UART0_BASE + UART_IER, in8(ACTING_UART0_BASE + UART_IER) |0x01); */
+	out8 (ACTING_UART0_BASE + UART_IER, 0x01);
 	/* Set DTR active */
-	out8 (UART0_BASE + UART_MCR, in8 (UART0_BASE + UART_MCR) | 0x01);
+	out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x01);
 	/* Start flow by setting RTS active */
-	out8 (UART0_BASE + UART_MCR, in8 (UART0_BASE + UART_MCR) | 0x02);
+	out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x02);
 	/* Setup UART FIFO: RX trigger level: 4 byte, Enable FIFO */
-	out8 (UART0_BASE + UART_FCR, (1 << 6) | 1);
+	out8 (ACTING_UART0_BASE + UART_FCR, (1 << 6) | 1);
 }
  
 void serial_buffered_putc (const char c)
 {
 	/* Wait for CTS */
 #if defined(CONFIG_HW_WATCHDOG)
-	while (!(in8 (UART0_BASE + UART_MSR) & 0x10))
+	while (!(in8 (ACTING_UART0_BASE + UART_MSR) & 0x10))
 		WATCHDOG_RESET ();
 #else
-	while (!(in8 (UART0_BASE + UART_MSR) & 0x10));
+	while (!(in8 (ACTING_UART0_BASE + UART_MSR) & 0x10));
 #endif
 	serial_putc (c);
 }
@@ -679,7 +716,7 @@
 	}
 	if (space > CONFIG_SERIAL_SOFTWARE_FIFO / 2) {
 		/* Start flow by setting RTS active */
-		out8 (UART0_BASE + UART_MCR, in8 (UART0_BASE + UART_MCR) | 0x02);
+		out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) | 0x02);
 	}
  
 	return c;
@@ -716,16 +753,16 @@
 	/*
 	 * Init onboard 16550 UART
 	 */
-	out8 (UART1_BASE + UART_LCR, 0x80);	/* set DLAB bit */
-	out8 (UART1_BASE + UART_DLL, (br_reg & 0x00ff));	/* set divisor for 9600 baud */
-	out8 (UART1_BASE + UART_DLM, ((br_reg & 0xff00) >> 8));	/* set divisor for 9600 baud */
-	out8 (UART1_BASE + UART_LCR, 0x03);	/* line control 8 bits no parity */
-	out8 (UART1_BASE + UART_FCR, 0x00);	/* disable FIFO */
-	out8 (UART1_BASE + UART_MCR, 0x00);	/* no modem control DTR RTS */
-	val = in8 (UART1_BASE + UART_LSR);	/* clear line status */
-	val = in8 (UART1_BASE + UART_RBR);	/* read receive buffer */
-	out8 (UART1_BASE + UART_SCR, 0x00);	/* set scratchpad */
-	out8 (UART1_BASE + UART_IER, 0x00);	/* set interrupt enable reg */
+	out8 (ACTING_UART1_BASE + UART_LCR, 0x80);	/* set DLAB bit */
+	out8 (ACTING_UART1_BASE + UART_DLL, (br_reg & 0x00ff));	/* set divisor for 9600 baud */
+	out8 (ACTING_UART1_BASE + UART_DLM, ((br_reg & 0xff00) >> 8));	/* set divisor for 9600 baud */
+	out8 (ACTING_UART1_BASE + UART_LCR, 0x03);	/* line control 8 bits no parity */
+	out8 (ACTING_UART1_BASE + UART_FCR, 0x00);	/* disable FIFO */
+	out8 (ACTING_UART1_BASE + UART_MCR, 0x00);	/* no modem control DTR RTS */
+	val = in8 (ACTING_UART1_BASE + UART_LSR);	/* clear line status */
+	val = in8 (ACTING_UART1_BASE + UART_RBR);	/* read receive buffer */
+	out8 (ACTING_UART1_BASE + UART_SCR, 0x00);	/* set scratchpad */
+	out8 (ACTING_UART1_BASE + UART_IER, 0x00);	/* set interrupt enable reg */
 }
  
  
  
@@ -734,10 +771,10 @@
 	if (c == '\n')
 		serial_putc ('\r');
  
-	out8 (UART1_BASE + UART_THR, c);	/* put character out */
+	out8 (ACTING_UART1_BASE + UART_THR, c);	/* put character out */
  
 	/* check THRE bit, wait for transfer done */
-	while ((in8 (UART1_BASE + UART_LSR) & 0x20) != 0x20);
+	while ((in8 (ACTING_UART1_BASE + UART_LSR) & 0x20) != 0x20);
 }
  
  
@@ -754,7 +791,7 @@
 	unsigned char status = 0;
  
 	while (1) {
-		status = in8 (UART1_BASE + UART_LSR);
+		status = in8 (ACTING_UART1_BASE + UART_LSR);
 		if ((status & asyncLSRDataReady1) != 0x0) {
 			break;
 		}
  
@@ -762,14 +799,14 @@
 				asyncLSROverrunError1 |
 				asyncLSRParityError1  |
 				asyncLSRBreakInterrupt1 )) != 0) {
-			out8 (UART1_BASE + UART_LSR,
+			out8 (ACTING_UART1_BASE + UART_LSR,
 			      asyncLSRFramingError1 |
 			      asyncLSROverrunError1 |
 			      asyncLSRParityError1  |
 			      asyncLSRBreakInterrupt1);
 		}
 	}
-	return (0x000000ff & (int) in8 (UART1_BASE));
+	return (0x000000ff & (int) in8 (ACTING_UART1_BASE));
 }
...	...	@@ -266,7 +266,7 @@
266	266
267	267
268	268	/*****************************************************************************/
269		-#if defined(CONFIG_405GP) \|\| defined(CONFIG_405CR) \|\| defined(CONFIG_440)
	269	+#if defined(CONFIG_405GP) \|\| defined(CONFIG_405CR) \|\| defined(CONFIG_440) \|\| defined(CONFIG_405EP)
270	270
271	271	#if defined(CONFIG_440)
272	272	#define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000200
273	273
274	274
275	275
...	...	@@ -274,15 +274,36 @@
274	274	#define CR0_MASK 0x3fff0000
275	275	#define CR0_EXTCLK_ENA 0x00600000
276	276	#define CR0_UDIV_POS 16
277		-#else
278		-#define UART_BASE_PTR 0xF800FFFC; /* pointer to uart base */
	277	+#elif defined(CONFIG_405EP)
279	278	#define UART0_BASE 0xef600300
280	279	#define UART1_BASE 0xef600400
	280	+#define UCR0_MASK 0x0000007f
	281	+#define UCR1_MASK 0x00007f00
	282	+#define UCR0_UDIV_POS 0
	283	+#define UCR1_UDIV_POS 8
	284	+#define UDIV_MAX 127
	285	+#else /* CONFIG_405GP \|\| CONFIG_405CR */
	286	+#define UART0_BASE 0xef600300
	287	+#define UART1_BASE 0xef600400
281	288	#define CR0_MASK 0x00001fff
282	289	#define CR0_EXTCLK_ENA 0x000000c0
283	290	#define CR0_UDIV_POS 1
	291	+#define UDIV_MAX 32
284	292	#endif
285	293
	294	+/* using serial port 0 or 1 as U-Boot console ? */
	295	+#if defined(CONFIG_UART1_CONSOLE)
	296	+#define ACTING_UART0_BASE UART1_BASE
	297	+#define ACTING_UART1_BASE UART0_BASE
	298	+#else
	299	+#define ACTING_UART0_BASE UART0_BASE
	300	+#define ACTING_UART1_BASE UART1_BASE
	301	+#endif
	302	+
	303	+#if defined(CONFIG_405EP) && defined(CFG_EXT_SERIAL_CLOCK)
	304	+#error "External serial clock not supported on IBM PPC405EP!"
	305	+#endif
	306	+
286	307	#define UART_RBR 0x00
287	308	#define UART_THR 0x00
288	309	#define UART_IER 0x01
...	...	@@ -299,7 +320,7 @@
299	320	/*-----------------------------------------------------------------------------+
300	321	\| Line Status Register.
301	322	+-----------------------------------------------------------------------------*/
302		-/#define asyncLSRport1 UART0_BASE+0x05 /
	323	+/#define asyncLSRport1 ACTING_UART0_BASE+0x05 /
303	324	#define asyncLSRDataReady1 0x01
304	325	#define asyncLSROverrunError1 0x02
305	326	#define asyncLSRParityError1 0x04
...	...	@@ -312,8 +333,8 @@
312	333	/*-----------------------------------------------------------------------------+
313	334	\| Miscellanies defines.
314	335	+-----------------------------------------------------------------------------*/
315		-/#define asyncTxBufferport1 UART0_BASE+0x00 /
316		-/#define asyncRxBufferport1 UART0_BASE+0x00 /
	336	+/#define asyncTxBufferport1 ACTING_UART0_BASE+0x00 /
	337	+/#define asyncRxBufferport1 ACTING_UART0_BASE+0x00 /
317	338
318	339
319	340	#if CONFIG_SERIAL_SOFTWARE_FIFO
...	...	@@ -412,16 +433,16 @@
412	433	reg \|= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
413	434	mtdcr (cntrl0, reg);
414	435
415		- out8 (UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */
416		- out8 (UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */
417		- out8 (UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
418		- out8 (UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
419		- out8 (UART0_BASE + UART_FCR, 0x00); /* disable FIFO */
420		- out8 (UART0_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
421		- val = in8 (UART0_BASE + UART_LSR); /* clear line status */
422		- val = in8 (UART0_BASE + UART_RBR); /* read receive buffer */
423		- out8 (UART0_BASE + UART_SCR, 0x00); /* set scratchpad */
424		- out8 (UART0_BASE + UART_IER, 0x00); /* set interrupt enable reg */
	436	+ out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */
	437	+ out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */
	438	+ out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
	439	+ out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
	440	+ out8 (ACTING_UART0_BASE + UART_FCR, 0x00); /* disable FIFO */
	441	+ out8 (ACTING_UART0_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
	442	+ val = in8 (ACTING_UART0_BASE + UART_LSR); /* clear line status */
	443	+ val = in8 (ACTING_UART0_BASE + UART_RBR); /* read receive buffer */
	444	+ out8 (ACTING_UART0_BASE + UART_SCR, 0x00); /* set scratchpad */
	445	+ out8 (ACTING_UART0_BASE + UART_IER, 0x00); /* set interrupt enable reg */
425	446
426	447	return (0);
427	448	}
...	...	@@ -439,6 +460,17 @@
439	460	unsigned short bdiv;
440	461	volatile char val;
441	462
	463	+#ifdef CONFIG_405EP
	464	+ reg = mfdcr(cpc0_ucr) & ~(UCR0_MASK \| UCR1_MASK);
	465	+ clk = gd->cpu_clk;
	466	+ tmp = CFG_BASE_BAUD * 16;
	467	+ udiv = (clk + tmp / 2) / tmp;
	468	+ if (udiv > UDIV_MAX) /* max. n bits for udiv */
	469	+ udiv = UDIV_MAX;
	470	+ reg \|= (udiv) << UCR0_UDIV_POS; /* set the UART divisor */
	471	+ reg \|= (udiv) << UCR1_UDIV_POS; /* set the UART divisor */
	472	+ mtdcr (cpc0_ucr, reg);
	473	+#else /* CONFIG_405EP */
442	474	reg = mfdcr(cntrl0) & ~CR0_MASK;
443	475	#ifdef CFG_EXT_SERIAL_CLOCK
444	476	clk = CFG_EXT_SERIAL_CLOCK;
445	477
446	478
447	479
...	...	@@ -451,27 +483,27 @@
451	483	#else
452	484	tmp = CFG_BASE_BAUD * 16;
453	485	udiv = (clk + tmp / 2) / tmp;
454		- if (udiv > 32) /* max. 5 bits for udiv */
455		- udiv = 32;
	486	+ if (udiv > UDIV_MAX) /* max. n bits for udiv */
	487	+ udiv = UDIV_MAX;
456	488	#endif
457	489	#endif
458		-
459	490	reg \|= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
460	491	mtdcr (cntrl0, reg);
	492	+#endif /* CONFIG_405EP */
461	493
462	494	tmp = gd->baudrate * udiv * 16;
463	495	bdiv = (clk + tmp / 2) / tmp;
464	496
465		- out8 (UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */
466		- out8 (UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */
467		- out8 (UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
468		- out8 (UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
469		- out8 (UART0_BASE + UART_FCR, 0x00); /* disable FIFO */
470		- out8 (UART0_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
471		- val = in8 (UART0_BASE + UART_LSR); /* clear line status */
472		- val = in8 (UART0_BASE + UART_RBR); /* read receive buffer */
473		- out8 (UART0_BASE + UART_SCR, 0x00); /* set scratchpad */
474		- out8 (UART0_BASE + UART_IER, 0x00); /* set interrupt enable reg */
	497	+ out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */
	498	+ out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */
	499	+ out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
	500	+ out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
	501	+ out8 (ACTING_UART0_BASE + UART_FCR, 0x00); /* disable FIFO */
	502	+ out8 (ACTING_UART0_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
	503	+ val = in8 (ACTING_UART0_BASE + UART_LSR); /* clear line status */
	504	+ val = in8 (ACTING_UART0_BASE + UART_RBR); /* read receive buffer */
	505	+ out8 (ACTING_UART0_BASE + UART_SCR, 0x00); /* set scratchpad */
	506	+ out8 (ACTING_UART0_BASE + UART_IER, 0x00); /* set interrupt enable reg */
475	507
476	508	return (0);
477	509	}
478	510
479	511
...	...	@@ -492,14 +524,19 @@
492	524	#else
493	525	clk = gd->cpu_clk;
494	526	#endif
	527	+
	528	+#ifdef CONFIG_405EP
	529	+ udiv = ((mfdcr (cpc0_ucr) & UCR0_MASK) >> UCR0_UDIV_POS);
	530	+#else
495	531	udiv = ((mfdcr (cntrl0) & 0x3e) >> 1) + 1;
	532	+#endif /* CONFIG_405EP */
496	533	tmp = gd->baudrate * udiv * 16;
497	534	bdiv = (clk + tmp / 2) / tmp;
498	535
499		- out8 (UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */
500		- out8 (UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */
501		- out8 (UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
502		- out8 (UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
	536	+ out8 (ACTING_UART0_BASE + UART_LCR, 0x80); /* set DLAB bit */
	537	+ out8 (ACTING_UART0_BASE + UART_DLL, bdiv); /* set baudrate divisor */
	538	+ out8 (ACTING_UART0_BASE + UART_DLM, bdiv >> 8);/* set baudrate divisor */
	539	+ out8 (ACTING_UART0_BASE + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */
503	540	}
504	541
505	542
506	543
...	...	@@ -512,11 +549,11 @@
512	549
513	550	/* check THRE bit, wait for transmiter available */
514	551	for (i = 1; i < 3500; i++) {
515		- if ((in8 (UART0_BASE + UART_LSR) & 0x20) == 0x20)
	552	+ if ((in8 (ACTING_UART0_BASE + UART_LSR) & 0x20) == 0x20)
516	553	break;
517	554	udelay (100);
518	555	}
519		- out8 (UART0_BASE + UART_THR, c); /* put character out */
	556	+ out8 (ACTING_UART0_BASE + UART_THR, c); /* put character out */
520	557	}
521	558
522	559
...	...	@@ -536,7 +573,7 @@
536	573	#if defined(CONFIG_HW_WATCHDOG)
537	574	WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */
538	575	#endif /* CONFIG_HW_WATCHDOG */
539		- status = in8 (UART0_BASE + UART_LSR);
	576	+ status = in8 (ACTING_UART0_BASE + UART_LSR);
540	577	if ((status & asyncLSRDataReady1) != 0x0) {
541	578	break;
542	579	}
543	580
...	...	@@ -544,14 +581,14 @@
544	581	asyncLSROverrunError1 \|
545	582	asyncLSRParityError1 \|
546	583	asyncLSRBreakInterrupt1 )) != 0) {
547		- out8 (UART0_BASE + UART_LSR,
	584	+ out8 (ACTING_UART0_BASE + UART_LSR,
548	585	asyncLSRFramingError1 \|
549	586	asyncLSROverrunError1 \|
550	587	asyncLSRParityError1 \|
551	588	asyncLSRBreakInterrupt1);
552	589	}
553	590	}
554		- return (0x000000ff & (int) in8 (UART0_BASE));
	591	+ return (0x000000ff & (int) in8 (ACTING_UART0_BASE));
555	592	}
556	593
557	594
...	...	@@ -559,7 +596,7 @@
559	596	{
560	597	unsigned char status;
561	598
562		- status = in8 (UART0_BASE + UART_LSR);
	599	+ status = in8 (ACTING_UART0_BASE + UART_LSR);
563	600	if ((status & asyncLSRDataReady1) != 0x0) {
564	601	return (1);
565	602	}
...	...	@@ -567,7 +604,7 @@
567	604	asyncLSROverrunError1 \|
568	605	asyncLSRParityError1 \|
569	606	asyncLSRBreakInterrupt1 )) != 0) {
570		- out8 (UART0_BASE + UART_LSR,
	607	+ out8 (ACTING_UART0_BASE + UART_LSR,
571	608	asyncLSRFramingError1 \|
572	609	asyncLSROverrunError1 \|
573	610	asyncLSRParityError1 \|
...	...	@@ -601,8 +638,8 @@
601	638	rx_put = 0;
602	639	if (space < CONFIG_SERIAL_SOFTWARE_FIFO / 4) {
603	640	/* Stop flow by setting RTS inactive */
604		- out8 (UART0_BASE + UART_MCR,
605		- in8 (UART0_BASE + UART_MCR) & (0xFF ^ 0x02));
	641	+ out8 (ACTING_UART0_BASE + UART_MCR,
	642	+ in8 (ACTING_UART0_BASE + UART_MCR) & (0xFF ^ 0x02));
606	643	}
607	644	}
608	645	buf_info.rx_put = rx_put;
...	...	@@ -615,7 +652,7 @@
615	652	buf_info.rx_put = 0;
616	653	buf_info.rx_get = 0;
617	654
618		- if (in8 (UART0_BASE + UART_MSR) & 0x10) {
	655	+ if (in8 (ACTING_UART0_BASE + UART_MSR) & 0x10) {
619	656	serial_puts ("Check CTS signal present on serial port: OK.\n");
620	657	} else {
621	658	serial_puts ("WARNING: CTS signal not present on serial port.\n");
622	659
623	660
624	661
625	662
626	663
...	...	@@ -626,24 +663,24 @@
626	663	(void ) &buf_info /void arg / );
627	664
628	665	/* Enable "RX Data Available" Interrupt on UART */
629		- /* out8(UART0_BASE + UART_IER, in8(UART0_BASE + UART_IER) \|0x01); */
630		- out8 (UART0_BASE + UART_IER, 0x01);
	666	+ /* out8(ACTING_UART0_BASE + UART_IER, in8(ACTING_UART0_BASE + UART_IER) \|0x01); */
	667	+ out8 (ACTING_UART0_BASE + UART_IER, 0x01);
631	668	/* Set DTR active */
632		- out8 (UART0_BASE + UART_MCR, in8 (UART0_BASE + UART_MCR) \| 0x01);
	669	+ out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) \| 0x01);
633	670	/* Start flow by setting RTS active */
634		- out8 (UART0_BASE + UART_MCR, in8 (UART0_BASE + UART_MCR) \| 0x02);
	671	+ out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) \| 0x02);
635	672	/* Setup UART FIFO: RX trigger level: 4 byte, Enable FIFO */
636		- out8 (UART0_BASE + UART_FCR, (1 << 6) \| 1);
	673	+ out8 (ACTING_UART0_BASE + UART_FCR, (1 << 6) \| 1);
637	674	}
638	675
639	676	void serial_buffered_putc (const char c)
640	677	{
641	678	/* Wait for CTS */
642	679	#if defined(CONFIG_HW_WATCHDOG)
643		- while (!(in8 (UART0_BASE + UART_MSR) & 0x10))
	680	+ while (!(in8 (ACTING_UART0_BASE + UART_MSR) & 0x10))
644	681	WATCHDOG_RESET ();
645	682	#else
646		- while (!(in8 (UART0_BASE + UART_MSR) & 0x10));
	683	+ while (!(in8 (ACTING_UART0_BASE + UART_MSR) & 0x10));
647	684	#endif
648	685	serial_putc (c);
649	686	}
...	...	@@ -679,7 +716,7 @@
679	716	}
680	717	if (space > CONFIG_SERIAL_SOFTWARE_FIFO / 2) {
681	718	/* Start flow by setting RTS active */
682		- out8 (UART0_BASE + UART_MCR, in8 (UART0_BASE + UART_MCR) \| 0x02);
	719	+ out8 (ACTING_UART0_BASE + UART_MCR, in8 (ACTING_UART0_BASE + UART_MCR) \| 0x02);
683	720	}
684	721
685	722	return c;
...	...	@@ -716,16 +753,16 @@
716	753	/*
717	754	* Init onboard 16550 UART
718	755	*/
719		- out8 (UART1_BASE + UART_LCR, 0x80); /* set DLAB bit */
720		- out8 (UART1_BASE + UART_DLL, (br_reg & 0x00ff)); /* set divisor for 9600 baud */
721		- out8 (UART1_BASE + UART_DLM, ((br_reg & 0xff00) >> 8)); /* set divisor for 9600 baud */
722		- out8 (UART1_BASE + UART_LCR, 0x03); /* line control 8 bits no parity */
723		- out8 (UART1_BASE + UART_FCR, 0x00); /* disable FIFO */
724		- out8 (UART1_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
725		- val = in8 (UART1_BASE + UART_LSR); /* clear line status */
726		- val = in8 (UART1_BASE + UART_RBR); /* read receive buffer */
727		- out8 (UART1_BASE + UART_SCR, 0x00); /* set scratchpad */
728		- out8 (UART1_BASE + UART_IER, 0x00); /* set interrupt enable reg */
	756	+ out8 (ACTING_UART1_BASE + UART_LCR, 0x80); /* set DLAB bit */
	757	+ out8 (ACTING_UART1_BASE + UART_DLL, (br_reg & 0x00ff)); /* set divisor for 9600 baud */
	758	+ out8 (ACTING_UART1_BASE + UART_DLM, ((br_reg & 0xff00) >> 8)); /* set divisor for 9600 baud */
	759	+ out8 (ACTING_UART1_BASE + UART_LCR, 0x03); /* line control 8 bits no parity */
	760	+ out8 (ACTING_UART1_BASE + UART_FCR, 0x00); /* disable FIFO */
	761	+ out8 (ACTING_UART1_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */
	762	+ val = in8 (ACTING_UART1_BASE + UART_LSR); /* clear line status */
	763	+ val = in8 (ACTING_UART1_BASE + UART_RBR); /* read receive buffer */
	764	+ out8 (ACTING_UART1_BASE + UART_SCR, 0x00); /* set scratchpad */
	765	+ out8 (ACTING_UART1_BASE + UART_IER, 0x00); /* set interrupt enable reg */
729	766	}
730	767
731	768
732	769
...	...	@@ -734,10 +771,10 @@
734	771	if (c == '\n')
735	772	serial_putc ('\r');
736	773
737		- out8 (UART1_BASE + UART_THR, c); /* put character out */
	774	+ out8 (ACTING_UART1_BASE + UART_THR, c); /* put character out */
738	775
739	776	/* check THRE bit, wait for transfer done */
740		- while ((in8 (UART1_BASE + UART_LSR) & 0x20) != 0x20);
	777	+ while ((in8 (ACTING_UART1_BASE + UART_LSR) & 0x20) != 0x20);
741	778	}
742	779
743	780
...	...	@@ -754,7 +791,7 @@
754	791	unsigned char status = 0;
755	792
756	793	while (1) {
757		- status = in8 (UART1_BASE + UART_LSR);
	794	+ status = in8 (ACTING_UART1_BASE + UART_LSR);
758	795	if ((status & asyncLSRDataReady1) != 0x0) {
759	796	break;
760	797	}
761	798
...	...	@@ -762,14 +799,14 @@
762	799	asyncLSROverrunError1 \|
763	800	asyncLSRParityError1 \|
764	801	asyncLSRBreakInterrupt1 )) != 0) {
765		- out8 (UART1_BASE + UART_LSR,
	802	+ out8 (ACTING_UART1_BASE + UART_LSR,
766	803	asyncLSRFramingError1 \|
767	804	asyncLSROverrunError1 \|
768	805	asyncLSRParityError1 \|
769	806	asyncLSRBreakInterrupt1);
770	807	}
771	808	}
772		- return (0x000000ff & (int) in8 (UART1_BASE));
	809	+ return (0x000000ff & (int) in8 (ACTING_UART1_BASE));
773	810	}
774	811
775	812