Eric Lee / smarc-uboot

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Commit 8782122052481f60638c2191a5512a644bb57abb

Authored by Jianchao Wang
Committed by Joe Hershberger
1 parent c40e65eb16
Exists in smarc_8mq_lf_v2020.04 and in 11 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, emb_lf_v2023.04, emb_lf_v2024.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

Add support for the NXP LS1021A-TSN board 

The LS1021A-TSN is a development board built by VVDN/Argonboards in
partnership with NXP.

It features the LS1021A SoC and the first-generation SJA1105T Ethernet
switch for prototyping implementations of a subset of IEEE 802.1 TSN
standards.

Supported boot media: microSD card (via SPL), QSPI flash.

Rev. A of the board uses a Spansion S25FL512S_256K serial flash, which
is 64 MB in size and has an erase sector size of 256KB (therefore,
flashing the RCW would erase part of U-Boot).

Rev. B and C of the board use a Spansion S25FL256S1 serial flash, which
is only 32 MB in size but has an erase sector size of 64KB (therefore
the RCW image can be flashed without erasing U-Boot).

To avoid the problems above, the U-Boot base address has been selected
at 0x100000 (the start of the 5th 256KB erase sector), which works for
all board revisions. Actually 0x40000 would have been enough, but
0x100000 is common for all Layerscape devices.

eTSEC3 is connecting directly to SJA1105 via an RGMII fixed-link, but
SJA1105 is currently not supported by uboot. Therefore, eTSEC3 is
disabled.

Signed-off-by: Xiaoliang Yang <xiaoliang.yang_1@nxp.com>
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Signed-off-by: Jianchao Wang <jianchao.wang@nxp.com>
Signed-off-by: Changming Huang <jerry.huang@nxp.com>
Signed-off-by: Vladimir Oltean <olteanv@gmail.com>

[Vladimir] Code taken from https://github.com/openil/u-boot (which
itself is mostly copied from ls1021a-iot) and adapted with the following
changes:

- Add a008850 errata workaround
- Converted eTSEC, MMC to DM to avoid all build warnings
- Plugged in distro boot feature, including support for extlinux.conf
- Added defconfig for QSPI boot
- Added the board/freescale/ls1021atsn/README.rst for initial setup
- Increased CONFIG_SYS_MONITOR_LEN so that the SPL malloc pool does not
  get overwritten during copying of the u-boot.bin payload from MMC to
  DDR.
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

Showing 13 changed files with 921 additions and 1 deletions Side-by-side Diff

... ... @@ -1352,6 +1352,19 @@
1352 1352 select SUPPORT_SPL
1353 1353 imply SCSI
1354 1354  
  1355 +config TARGET_LS1021ATSN
  1356 + bool "Support ls1021atsn"
  1357 + select ARCH_LS1021A
  1358 + select ARCH_SUPPORT_PSCI
  1359 + select BOARD_EARLY_INIT_F
  1360 + select BOARD_LATE_INIT
  1361 + select CPU_V7A
  1362 + select CPU_V7_HAS_NONSEC
  1363 + select CPU_V7_HAS_VIRT
  1364 + select LS1_DEEP_SLEEP
  1365 + select SUPPORT_SPL
  1366 + imply SCSI
  1367 +
1355 1368 config TARGET_LS1021AIOT
1356 1369 bool "Support ls1021aiot"
1357 1370 select ARCH_LS1021A
... ... @@ -1745,6 +1758,7 @@
1745 1758 source "board/freescale/ls1021aqds/Kconfig"
1746 1759 source "board/freescale/ls1043aqds/Kconfig"
1747 1760 source "board/freescale/ls1021atwr/Kconfig"
  1761 +source "board/freescale/ls1021atsn/Kconfig"
1748 1762 source "board/freescale/ls1021aiot/Kconfig"
1749 1763 source "board/freescale/ls1046aqds/Kconfig"
1750 1764 source "board/freescale/ls1043ardb/Kconfig"
arch/arm/dts/Makefile
Diff comments   View file @ 8782122
... ... @@ -328,7 +328,7 @@
328 328 dtb-$(CONFIG_ARCH_LS1021A) += ls1021a-qds-duart.dtb \
329 329 ls1021a-qds-lpuart.dtb \
330 330 ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb \
331   - ls1021a-iot-duart.dtb
  331 + ls1021a-iot-duart.dtb ls1021a-tsn.dtb
332 332 dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
333 333 fsl-ls2080a-rdb.dtb \
334 334 fsl-ls2081a-rdb.dtb \
arch/arm/dts/ls1021a-tsn.dts
Diff comments   View file @ 8782122
  1 +// SPDX-License-Identifier: GPL-2.0
  2 +/* Copyright 2016-2018 NXP Semiconductors
  3 + * Copyright 2019 Vladimir Oltean <olteanv@gmail.com>
  4 + */
  5 +
  6 +/dts-v1/;
  7 +#include "ls1021a.dtsi"
  8 +
  9 +/ {
  10 + model = "NXP LS1021A-TSN Board";
  11 +
  12 + aliases {
  13 + enet0-sgmii-phy = &sgmii_phy2;
  14 + enet1-sgmii-phy = &sgmii_phy1;
  15 + spi0 = &qspi;
  16 + spi1 = &dspi1;
  17 + };
  18 +};
  19 +
  20 +&enet0 {
  21 + tbi-handle = <&tbi0>;
  22 + phy-handle = <&sgmii_phy2>;
  23 + phy-mode = "sgmii";
  24 + status = "okay";
  25 +};
  26 +
  27 +&enet1 {
  28 + tbi-handle = <&tbi1>;
  29 + phy-handle = <&sgmii_phy1>;
  30 + phy-mode = "sgmii";
  31 + status = "okay";
  32 +};
  33 +
  34 +&i2c0 {
  35 + status = "okay";
  36 +};
  37 +
  38 +&mdio0 {
  39 + /* AR8031 */
  40 + sgmii_phy1: ethernet-phy@1 {
  41 + reg = <0x1>;
  42 + };
  43 +
  44 + /* AR8031 */
  45 + sgmii_phy2: ethernet-phy@2 {
  46 + reg = <0x2>;
  47 + };
  48 +
  49 + /* SGMII PCS for enet0 */
  50 + tbi0: tbi-phy@1f {
  51 + reg = <0x1f>;
  52 + device_type = "tbi-phy";
  53 + };
  54 +};
  55 +
  56 +&mdio1 {
  57 + /* SGMII PCS for enet1 */
  58 + tbi1: tbi-phy@1f {
  59 + reg = <0x1f>;
  60 + device_type = "tbi-phy";
  61 + };
  62 +};
  63 +
  64 +&qspi {
  65 + bus-num = <0>;
  66 + status = "okay";
  67 +
  68 + flash@0 {
  69 + compatible = "spi-flash";
  70 + spi-max-frequency = <20000000>;
  71 + reg = <0>;
  72 + };
  73 +};
  74 +
  75 +&uart0 {
  76 + status = "okay";
  77 +};
board/freescale/ls1021atsn/Kconfig
Diff comments   View file @ 8782122
  1 +# SPDX-License-Identifier: GPL-2.0
  2 +if TARGET_LS1021ATSN
  3 +
  4 +config SYS_BOARD
  5 + default "ls1021atsn"
  6 +
  7 +config SYS_VENDOR
  8 + default "freescale"
  9 +
  10 +config SYS_SOC
  11 + default "ls102xa"
  12 +
  13 +config SYS_CONFIG_NAME
  14 + default "ls1021atsn"
  15 +
  16 +source "board/freescale/common/Kconfig"
  17 +
  18 +endif
board/freescale/ls1021atsn/MAINTAINERS
Diff comments   View file @ 8782122
  1 +NXP LS1021A-TSN Board
  2 +M: Vladimir Oltean <olteanv@gmail.com>
  3 +S: Maintained
  4 +F: arch/arm/dts/ls1021a-tsn.dts
  5 +F: board/freescale/ls1021atsn/
  6 +F: include/configs/ls1021atsn.h
  7 +F: configs/ls1021atsn_qspi_defconfig
  8 +F: configs/ls1021atsn_sdcard_defconfig
board/freescale/ls1021atsn/Makefile
Diff comments   View file @ 8782122
  1 +# SPDX-License-Identifier: GPL-2.0
  2 +obj-y += ls1021atsn.o
  3 +obj-$(CONFIG_ARMV7_PSCI) += ../ls1021atwr/psci.o
board/freescale/ls1021atsn/README.rst
Diff comments   View file @ 8782122
  1 +.. SPDX-License-Identifier: GPL-2.0
  2 +
  3 +LS1021A-TSN Board Overview
  4 +==========================
  5 +
  6 + - 1GB DDR3 at 800 MHz
  7 + - Spansion/Cypress 64 MB (Rev. A) / 32 MB (Rev. B and C) QSPI NOR flash
  8 + - Ethernet
  9 + - 2 SGMII 10/100/1G Ethernet ports (Atheros AR8031)
  10 + - One SJA1105T switch with 4 Ethernet ports (Broadcom BCM5464R)
  11 + - One internal RGMII port connected to the switch
  12 + - SDHC
  13 + - microSDHC/SDXC connector
  14 + - Other I/O
  15 + - One Serial port
  16 + - Arduino and expansion headers
  17 + - mPCIE slot
  18 + - SATA port
  19 + - USB3.0 port
  20 +
  21 +LS1021A Memory map
  22 +==================
  23 +
  24 +The addresses in brackets are physical addresses.
  25 +
  26 +============== ============== ============================== =======
  27 +Start Address End Address Description Size
  28 +============== ============== ============================== =======
  29 +0x00_0000_0000 0x00_000F_FFFF Secure Boot ROM 1MB
  30 +0x00_0100_0000 0x00_0FFF_FFFF CCSRBAR 240MB
  31 +0x00_1000_0000 0x00_1000_FFFF OCRAM0 64KB
  32 +0x00_1001_0000 0x00_1001_FFFF OCRAM1 64KB
  33 +0x00_2000_0000 0x00_20FF_FFFF DCSR 16MB
  34 +0x00_4000_0000 0x00_5FFF_FFFF QSPI 512MB
  35 +0x00_6000_0000 0x00_67FF_FFFF IFC - NOR Flash 128MB
  36 +0x00_8000_0000 0x00_FFFF_FFFF DRAM1 2GB
  37 +============== ============== ============================== =======
  38 +
  39 +Compiling and flashing
  40 +======================
  41 +
  42 +The LS1021A-TSN board comes along with a microSD card with OpenIL U-Boot that
  43 +can be used to update its internal QSPI flash (which is empty out of the
  44 +factory).
  45 +
  46 +To compile and flash an SD card image::
  47 +
  48 + make ls1021atsn_sdcard_defconfig && make -j 8 && sudo cp u-boot-with-spl-pbl.bin /srv/tftpboot/
  49 + => tftp 0x82000000 u-boot-with-spl-pbl.bin && mmc rescan && mmc erase 8 0x1100 && mmc write 0x82000000 8 0x1100
  50 +
  51 +For the QSPI flash, first obtain the Reset Configuration Word binary for
  52 +bootimg from the QSPI flash from the rcw project
  53 +(https://source.codeaurora.org/external/qoriq/qoriq-components/rcw)::
  54 +
  55 + make -j 8 && sudo cp ls1021atsn/SSR_PNS_30/rcw_1200_qspiboot.bin.swapped /srv/tftpboot/
  56 +
  57 +The above RCW binary takes care of swapping the QSPI AMBA memory, so that the
  58 +U-Boot binary does not need to be swapped when flashing it.
  59 +
  60 +To compile and flash a U-Boot image for QSPI::
  61 +
  62 + make ls1021atsn_qspi_defconfig && make -j 8 && sudo cp u-boot.bin /srv/tftpboot/
  63 +
  64 +Then optionally create a custom uboot-env.txt file (although the default
  65 +environment already supports distro boot) and convert it to binary format::
  66 +
  67 + mkenvimage -s 2M -o /srv/tftpboot/uboot-env.bin uboot-env.txt
  68 +
  69 +To program the QSPI flash with the images::
  70 +
  71 + => tftp 0x82000000 rcw_1200_qspiboot.bin.swapped && sf probe && sf erase 0x0 +${filesize} && sf write 0x82000000 0x0 ${filesize}
  72 + => tftp 0x82000000 u-boot.bin && sf probe && sf erase 0x100000 +${filesize} && sf write 0x82000000 0x100000 ${filesize}
  73 + => tftp 0x82000000 uboot-env.bin && sf probe && sf erase 0x400000 +${filesize} && sf write 0x82000000 0x400000 ${filesize}
  74 +
  75 +The boards contain an AT24 I2C EEPROM that is supposed to hold the MAC
  76 +addresses of the Ethernet interfaces, however the EEPROM comes blank out of
  77 +the factory, and the MAC addresses are printed on a label on the bottom of
  78 +the boards.
  79 +
  80 +To write the MAC addresses to the EEPROM, the following needs to be done once::
  81 +
  82 + => mac id
  83 + => mac 0 00:1F:7B:xx:xx:xx
  84 + => mac 1 00:1F:7B:xx:xx:xx
  85 + => mac 2 00:1F:7B:xx:xx:xx
  86 + => mac save
  87 +
  88 +The switch ports do not have their own MAC address - they inherit it from the
  89 +master enet2 port.
  90 +
  91 +Known issues and limitations
  92 +============================
  93 +
  94 +- The 4 SJA1105 switch ports are not functional in U-Boot for now.
  95 +- Since the IFC pins are multiplexed with QSPI on LS1021A, currently there is
  96 + no way to talk to the CPLD for e.g. running the "qixis_reset" command, or
  97 + turning the fan on, etc.
board/freescale/ls1021atsn/ls1021atsn.c
Diff comments   View file @ 8782122
  1 +// SPDX-License-Identifier: GPL-2.0
  2 +/* Copyright 2016-2019 NXP Semiconductors
  3 + */
  4 +#include <common.h>
  5 +#include <asm/arch-ls102xa/ls102xa_soc.h>
  6 +#include <asm/arch/ls102xa_devdis.h>
  7 +#include <asm/arch/immap_ls102xa.h>
  8 +#include <asm/arch/ls102xa_soc.h>
  9 +#include <asm/arch/fsl_serdes.h>
  10 +#include "../common/sleep.h"
  11 +#include <fsl_validate.h>
  12 +#include <fsl_immap.h>
  13 +#include <fsl_csu.h>
  14 +#include <netdev.h>
  15 +#include <spl.h>
  16 +#ifdef CONFIG_U_QE
  17 +#include <fsl_qe.h>
  18 +#endif
  19 +
  20 +DECLARE_GLOBAL_DATA_PTR;
  21 +
  22 +static void ddrmc_init(void)
  23 +{
  24 +#if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
  25 + struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
  26 + u32 temp_sdram_cfg, tmp;
  27 +
  28 + out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
  29 +
  30 + out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
  31 + out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
  32 +
  33 + out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
  34 + out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
  35 + out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
  36 + out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
  37 + out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
  38 + out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
  39 +
  40 +#ifdef CONFIG_DEEP_SLEEP
  41 + if (is_warm_boot()) {
  42 + out_be32(&ddr->sdram_cfg_2,
  43 + DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT);
  44 + out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
  45 + out_be32(&ddr->init_ext_addr, (1 << 31));
  46 +
  47 + /* DRAM VRef will not be trained */
  48 + out_be32(&ddr->ddr_cdr2,
  49 + DDR_DDR_CDR2 & ~DDR_CDR2_VREF_TRAIN_EN);
  50 + } else
  51 +#endif
  52 + {
  53 + out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
  54 + out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
  55 + }
  56 +
  57 + out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
  58 + out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
  59 +
  60 + out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
  61 +
  62 + out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
  63 +
  64 + out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
  65 + out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
  66 +
  67 + out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
  68 +
  69 + out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
  70 + out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
  71 +
  72 + out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
  73 +
  74 + /* DDR erratum A-009942 */
  75 + tmp = in_be32(&ddr->debug[28]);
  76 + out_be32(&ddr->debug[28], tmp | 0x0070006f);
  77 +
  78 + udelay(1);
  79 +
  80 +#ifdef CONFIG_DEEP_SLEEP
  81 + if (is_warm_boot()) {
  82 + /* enter self-refresh */
  83 + temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
  84 + temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
  85 + out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
  86 +
  87 + temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN | SDRAM_CFG_BI);
  88 + } else
  89 +#endif
  90 + temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);
  91 +
  92 + out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
  93 +
  94 +#ifdef CONFIG_DEEP_SLEEP
  95 + if (is_warm_boot()) {
  96 + /* exit self-refresh */
  97 + temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
  98 + temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
  99 + out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
  100 + }
  101 +#endif
  102 +#endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */
  103 +}
  104 +
  105 +int dram_init(void)
  106 +{
  107 + ddrmc_init();
  108 +
  109 + erratum_a008850_post();
  110 +
  111 + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  112 +
  113 +#if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
  114 + fsl_dp_resume();
  115 +#endif
  116 +
  117 + return 0;
  118 +}
  119 +
  120 +int board_eth_init(bd_t *bis)
  121 +{
  122 + return pci_eth_init(bis);
  123 +}
  124 +
  125 +int board_early_init_f(void)
  126 +{
  127 + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
  128 +
  129 +#ifdef CONFIG_TSEC_ENET
  130 + /*
  131 + * Clear BD & FR bits for big endian BD's and frame data (aka set
  132 + * correct eTSEC endianness). This is crucial in ensuring that it does
  133 + * not report Data Parity Errors in its RX/TX FIFOs when attempting to
  134 + * send traffic.
  135 + */
  136 + clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
  137 + /* EC3_GTX_CLK125 (of enet2) used for all RGMII interfaces */
  138 + out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
  139 +#endif
  140 +
  141 + arch_soc_init();
  142 +
  143 +#if defined(CONFIG_DEEP_SLEEP)
  144 + if (is_warm_boot()) {
  145 + timer_init();
  146 + dram_init();
  147 + }
  148 +#endif
  149 +
  150 + return 0;
  151 +}
  152 +
  153 +#ifdef CONFIG_SPL_BUILD
  154 +void board_init_f(ulong dummy)
  155 +{
  156 + void (*second_uboot)(void);
  157 +
  158 + /* Clear the BSS */
  159 + memset(__bss_start, 0, __bss_end - __bss_start);
  160 +
  161 + get_clocks();
  162 +
  163 +#if defined(CONFIG_DEEP_SLEEP)
  164 + if (is_warm_boot())
  165 + fsl_dp_disable_console();
  166 +#endif
  167 +
  168 + preloader_console_init();
  169 +
  170 + dram_init();
  171 +
  172 + /* Allow OCRAM access permission as R/W */
  173 +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
  174 + enable_layerscape_ns_access();
  175 + enable_layerscape_ns_access();
  176 +#endif
  177 +
  178 + /*
  179 + * if it is woken up from deep sleep, then jump to second
  180 + * stage U-Boot and continue executing without recopying
  181 + * it from SD since it has already been reserved in memory
  182 + * in last boot.
  183 + */
  184 + if (is_warm_boot()) {
  185 + second_uboot = (void (*)(void))CONFIG_SYS_TEXT_BASE;
  186 + second_uboot();
  187 + }
  188 +
  189 + board_init_r(NULL, 0);
  190 +}
  191 +#endif
  192 +
  193 +int board_init(void)
  194 +{
  195 +#ifndef CONFIG_SYS_FSL_NO_SERDES
  196 + fsl_serdes_init();
  197 +#endif
  198 + ls102xa_smmu_stream_id_init();
  199 +
  200 +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
  201 + enable_layerscape_ns_access();
  202 +#endif
  203 +
  204 +#ifdef CONFIG_U_QE
  205 + u_qe_init();
  206 +#endif
  207 +
  208 + return 0;
  209 +}
  210 +
  211 +#if defined(CONFIG_SPL_BUILD)
  212 +void spl_board_init(void)
  213 +{
  214 + ls102xa_smmu_stream_id_init();
  215 +}
  216 +#endif
  217 +
  218 +#ifdef CONFIG_BOARD_LATE_INIT
  219 +int board_late_init(void)
  220 +{
  221 +#ifdef CONFIG_CHAIN_OF_TRUST
  222 + fsl_setenv_chain_of_trust();
  223 +#endif
  224 +
  225 + return 0;
  226 +}
  227 +#endif
  228 +
  229 +#if defined(CONFIG_MISC_INIT_R)
  230 +int misc_init_r(void)
  231 +{
  232 +#ifdef CONFIG_FSL_DEVICE_DISABLE
  233 + device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
  234 +#endif
  235 +
  236 +#ifdef CONFIG_FSL_CAAM
  237 + return sec_init();
  238 +#endif
  239 +}
  240 +#endif
  241 +
  242 +#if defined(CONFIG_DEEP_SLEEP)
  243 +void board_sleep_prepare(void)
  244 +{
  245 +#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
  246 + enable_layerscape_ns_access();
  247 +#endif
  248 +}
  249 +#endif
  250 +
  251 +int ft_board_setup(void *blob, bd_t *bd)
  252 +{
  253 + ft_cpu_setup(blob, bd);
  254 +
  255 +#ifdef CONFIG_PCI
  256 + ft_pci_setup(blob, bd);
  257 +#endif
  258 +
  259 + return 0;
  260 +}
board/freescale/ls1021atsn/ls102xa_pbi.cfg
Diff comments   View file @ 8782122
  1 +# PBI commands
  2 +
  3 +09570200 ffffffff
  4 +09570158 00000300
  5 +8940007c 21f47300
  6 +
  7 +# Configure Scratch register
  8 +09ee0200 10000000
  9 +# Configure alternate space
  10 +09570158 00001000
  11 +# Flush PBL data
  12 +096100c0 000FFFFF
  13 +
  14 +09ea085c 00502880
  15 +09ea0560 80800000
board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg
Diff comments   View file @ 8782122
  1 +# PBL preamble and RCW header
  2 +aa55aa55 01ee0100
  3 +
  4 +# Disable IFC, enable QSPI and DSPI
  5 +0608000c 00000000 00000000 00000000
  6 +30000000 08007900 40105a00 21046000
  7 +00000000 00000000 00000000 10002000
  8 +20124801 8804b340 00000000 00000000
configs/ls1021atsn_qspi_defconfig
Diff comments   View file @ 8782122
  1 +CONFIG_ARM=y
  2 +CONFIG_TARGET_LS1021ATSN=y
  3 +CONFIG_SYS_TEXT_BASE=0x40100000
  4 +CONFIG_DEFAULT_DEVICE_TREE="ls1021a-tsn"
  5 +CONFIG_BOARD_EARLY_INIT_F=y
  6 +CONFIG_MISC_INIT_R=y
  7 +CONFIG_SYS_EXTRA_OPTIONS="QSPI_BOOT"
  8 +CONFIG_QSPI_BOOT=y
  9 +CONFIG_BOOTDELAY=3
  10 +CONFIG_HUSH_PARSER=y
  11 +CONFIG_CMD_GREPENV=y
  12 +CONFIG_CMD_MEMINFO=y
  13 +CONFIG_CMD_GPT=y
  14 +CONFIG_CMD_FAT=y
  15 +CONFIG_FSL_ESDHC=y
  16 +CONFIG_CMD_SF=y
  17 +CONFIG_OF_CONTROL=y
  18 +CONFIG_OF_BOARD_SETUP=y
  19 +CONFIG_OF_STDOUT_VIA_ALIAS=y
  20 +CONFIG_ENV_IS_IN_SPI_FLASH=y
  21 +CONFIG_DM=y
  22 +CONFIG_FSL_CAAM=y
  23 +CONFIG_SPI=y
  24 +CONFIG_SPI_FLASH=y
  25 +CONFIG_SPI_FLASH_ATMEL=y
  26 +CONFIG_SPI_FLASH_STMICRO=y
  27 +CONFIG_SPI_FLASH_BAR=y
  28 +CONFIG_SPI_FLASH_SPANSION=y
  29 +CONFIG_NETDEVICES=y
  30 +CONFIG_DM_ETH=y
  31 +CONFIG_TSEC_ENET=y
  32 +CONFIG_MII=y
  33 +CONFIG_SYS_NS16550=y
  34 +CONFIG_DM_SPI=y
  35 +CONFIG_DM_SPI_FLASH=y
  36 +CONFIG_SPI_FLASH_DATAFLASH=y
  37 +CONFIG_FSL_DSPI=y
  38 +CONFIG_FSL_QSPI=y
  39 +CONFIG_PCI=y
  40 +CONFIG_CMD_PCI=y
  41 +CONFIG_DM_PCI=y
  42 +CONFIG_DM_PCI_COMPAT=y
  43 +CONFIG_CMD_MMC=y
  44 +CONFIG_DM_MMC=y
  45 +CONFIG_FSL_SPI_ALIGNED_TXFIFO=y
  46 +CONFIG_USB=y
  47 +CONFIG_DM_USB=y
  48 +CONFIG_CMD_USB=y
  49 +CONFIG_USB_XHCI_HCD=y
  50 +CONFIG_USB_XHCI_FSL=y
  51 +CONFIG_USB_XHCI_DWC3=y
  52 +CONFIG_HAS_FSL_XHCI_USB=y
  53 +CONFIG_USB_STORAGE=y
  54 +CONFIG_CMD_EXT2=y
  55 +CONFIG_PCIE_LAYERSCAPE=y
  56 +CONFIG_PHYLIB=y
  57 +CONFIG_PHY_GIGE=y
  58 +CONFIG_PHY_ATHEROS=y
  59 +CONFIG_PHY_BROADCOM=y
  60 +CONFIG_PHY_FIXED=y
  61 +CONFIG_CMD_PING=y
  62 +CONFIG_CMD_DHCP=y
  63 +CONFIG_CMD_MII=y
  64 +CONFIG_CMDLINE_TAG=y
  65 +CONFIG_CMDLINE_EDITING=y
  66 +CONFIG_AUTO_COMPLETE=y
  67 +CONFIG_NR_DRAM_BANKS=1
  68 +CONFIG_CMD_BOOTZ=y
  69 +CONFIG_SYS_LONGHELP=y
  70 +CONFIG_FIT=y
  71 +CONFIG_CMD_DM=y
  72 +CONFIG_AHCI=y
  73 +CONFIG_CMD_I2C=y
  74 +CONFIG_BLK=y
  75 +CONFIG_CMD_PART=y
  76 +CONFIG_CMD_FS_GENERIC=y
  77 +CONFIG_CMD_FS_UUID=y
  78 +CONFIG_SILENT_CONSOLE=y
  79 +CONFIG_DISTRO_DEFAULTS=y
configs/ls1021atsn_sdcard_defconfig
Diff comments   View file @ 8782122
  1 +CONFIG_ARM=y
  2 +CONFIG_TARGET_LS1021ATSN=y
  3 +CONFIG_SPL_TEXT_BASE=0x10000000
  4 +CONFIG_SYS_TEXT_BASE=0x82000000
  5 +CONFIG_DEFAULT_DEVICE_TREE="ls1021a-tsn"
  6 +CONFIG_BOARD_EARLY_INIT_F=y
  7 +CONFIG_MISC_INIT_R=y
  8 +CONFIG_SPL=y
  9 +CONFIG_SPL_FRAMEWORK=y
  10 +CONFIG_SPL_LIBGENERIC_SUPPORT=y
  11 +CONFIG_SPL_WATCHDOG_SUPPORT=y
  12 +CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
  13 +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT,SD_BOOT_QSPI"
  14 +CONFIG_SD_BOOT=y
  15 +CONFIG_BOOTDELAY=3
  16 +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
  17 +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xe8
  18 +CONFIG_HUSH_PARSER=y
  19 +CONFIG_CMD_GREPENV=y
  20 +CONFIG_CMD_MEMINFO=y
  21 +CONFIG_CMD_GPT=y
  22 +CONFIG_CMD_FAT=y
  23 +CONFIG_CMD_MMC=y
  24 +CONFIG_FSL_ESDHC=y
  25 +CONFIG_CMD_SF=y
  26 +CONFIG_OF_CONTROL=y
  27 +CONFIG_OF_BOARD_SETUP=y
  28 +CONFIG_OF_STDOUT_VIA_ALIAS=y
  29 +CONFIG_ENV_IS_IN_MMC=y
  30 +CONFIG_DM=y
  31 +CONFIG_FSL_CAAM=y
  32 +CONFIG_SPI=y
  33 +CONFIG_SPI_FLASH=y
  34 +CONFIG_SPI_FLASH_ATMEL=y
  35 +CONFIG_SPI_FLASH_STMICRO=y
  36 +CONFIG_SPI_FLASH_BAR=y
  37 +CONFIG_SPI_FLASH_SPANSION=y
  38 +CONFIG_NETDEVICES=y
  39 +CONFIG_DM_ETH=y
  40 +CONFIG_TSEC_ENET=y
  41 +CONFIG_MII=y
  42 +CONFIG_SYS_NS16550=y
  43 +CONFIG_DM_SPI=y
  44 +CONFIG_DM_SPI_FLASH=y
  45 +CONFIG_SPI_FLASH_DATAFLASH=y
  46 +CONFIG_FSL_DSPI=y
  47 +CONFIG_FSL_QSPI=y
  48 +CONFIG_PCI=y
  49 +CONFIG_CMD_PCI=y
  50 +CONFIG_DM_PCI=y
  51 +CONFIG_DM_PCI_COMPAT=y
  52 +CONFIG_USB=y
  53 +CONFIG_DM_USB=y
  54 +CONFIG_CMD_USB=y
  55 +CONFIG_USB_XHCI_HCD=y
  56 +CONFIG_USB_XHCI_FSL=y
  57 +CONFIG_USB_XHCI_DWC3=y
  58 +CONFIG_HAS_FSL_XHCI_USB=y
  59 +CONFIG_USB_STORAGE=y
  60 +CONFIG_CMD_EXT2=y
  61 +CONFIG_PCIE_LAYERSCAPE=y
  62 +CONFIG_PHYLIB=y
  63 +CONFIG_PHY_GIGE=y
  64 +CONFIG_PHY_ATHEROS=y
  65 +CONFIG_PHY_BROADCOM=y
  66 +CONFIG_PHY_FIXED=y
  67 +CONFIG_CMD_PING=y
  68 +CONFIG_CMD_DHCP=y
  69 +CONFIG_CMD_MII=y
  70 +CONFIG_CMDLINE_TAG=y
  71 +CONFIG_CMDLINE_EDITING=y
  72 +CONFIG_AUTO_COMPLETE=y
  73 +CONFIG_NR_DRAM_BANKS=1
  74 +CONFIG_CMD_BOOTZ=y
  75 +CONFIG_SYS_LONGHELP=y
  76 +CONFIG_FIT=y
  77 +CONFIG_SPL_MMC_SUPPORT=y
  78 +CONFIG_SPL_SERIAL_SUPPORT=y
  79 +CONFIG_SPL_I2C_SUPPORT=y
  80 +CONFIG_SPL_ENV_SUPPORT=y
  81 +CONFIG_SPL_LIBCOMMON_SUPPORT=y
  82 +CONFIG_CMD_DM=y
  83 +CONFIG_AHCI=y
  84 +CONFIG_CMD_I2C=y
  85 +CONFIG_BLK=y
  86 +CONFIG_DM_MMC=y
  87 +CONFIG_CMD_PART=y
  88 +CONFIG_CMD_FS_GENERIC=y
  89 +CONFIG_CMD_FS_UUID=y
  90 +CONFIG_SILENT_CONSOLE=y
  91 +CONFIG_DISTRO_DEFAULTS=y
include/configs/ls1021atsn.h
Diff comments   View file @ 8782122
  1 +/* SPDX-License-Identifier: GPL-2.0
  2 + * Copyright 2016-2018 NXP Semiconductors
  3 + * Copyright 2019 Vladimir Oltean <olteanv@gmail.com>
  4 + */
  5 +
  6 +#ifndef __CONFIG_H
  7 +#define __CONFIG_H
  8 +
  9 +#define CONFIG_ARMV7_SECURE_BASE OCRAM_BASE_S_ADDR
  10 +
  11 +#define CONFIG_SYS_FSL_CLK
  12 +
  13 +#define CONFIG_DEEP_SLEEP
  14 +
  15 +/* Size of malloc() pool */
  16 +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
  17 +
  18 +#define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
  19 +#define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
  20 +
  21 +/* XHCI Support - enabled by default */
  22 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  23 +
  24 +#define CONFIG_SYS_CLK_FREQ 100000000
  25 +#define CONFIG_DDR_CLK_FREQ 100000000
  26 +
  27 +#define DDR_SDRAM_CFG 0x470c0008
  28 +#define DDR_CS0_BNDS 0x008000bf
  29 +#define DDR_CS0_CONFIG 0x80014302
  30 +#define DDR_TIMING_CFG_0 0x50550004
  31 +#define DDR_TIMING_CFG_1 0xbcb38c56
  32 +#define DDR_TIMING_CFG_2 0x0040d120
  33 +#define DDR_TIMING_CFG_3 0x010e1000
  34 +#define DDR_TIMING_CFG_4 0x00000001
  35 +#define DDR_TIMING_CFG_5 0x03401400
  36 +#define DDR_SDRAM_CFG_2 0x00401010
  37 +#define DDR_SDRAM_MODE 0x00061c60
  38 +#define DDR_SDRAM_MODE_2 0x00180000
  39 +#define DDR_SDRAM_INTERVAL 0x18600618
  40 +#define DDR_DDR_WRLVL_CNTL 0x8655f605
  41 +#define DDR_DDR_WRLVL_CNTL_2 0x05060607
  42 +#define DDR_DDR_WRLVL_CNTL_3 0x05050505
  43 +#define DDR_DDR_CDR1 0x80040000
  44 +#define DDR_DDR_CDR2 0x00000001
  45 +#define DDR_SDRAM_CLK_CNTL 0x02000000
  46 +#define DDR_DDR_ZQ_CNTL 0x89080600
  47 +#define DDR_CS0_CONFIG_2 0
  48 +#define DDR_SDRAM_CFG_MEM_EN 0x80000000
  49 +#define SDRAM_CFG2_D_INIT 0x00000010
  50 +#define DDR_CDR2_VREF_TRAIN_EN 0x00000080
  51 +#define SDRAM_CFG2_FRC_SR 0x80000000
  52 +#define SDRAM_CFG_BI 0x00000001
  53 +
  54 +#ifdef CONFIG_RAMBOOT_PBL
  55 +#define CONFIG_SYS_FSL_PBL_PBI \
  56 + "board/freescale/ls1021atsn/ls102xa_pbi.cfg"
  57 +#endif
  58 +
  59 +#ifdef CONFIG_SD_BOOT
  60 +#define CONFIG_SYS_FSL_PBL_RCW \
  61 + "board/freescale/ls1021atsn/ls102xa_rcw_sd.cfg"
  62 +
  63 +#ifdef CONFIG_SECURE_BOOT
  64 +#define CONFIG_U_BOOT_HDR_SIZE (16 << 10)
  65 +#endif /* ifdef CONFIG_SECURE_BOOT */
  66 +
  67 +#define CONFIG_SPL_MAX_SIZE 0x1a000
  68 +#define CONFIG_SPL_STACK 0x1001d000
  69 +#define CONFIG_SPL_PAD_TO 0x1c000
  70 +
  71 +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
  72 + CONFIG_SYS_MONITOR_LEN)
  73 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
  74 +#define CONFIG_SPL_BSS_START_ADDR 0x80100000
  75 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
  76 +
  77 +#ifdef CONFIG_U_BOOT_HDR_SIZE
  78 +/*
  79 + * HDR would be appended at end of image and copied to DDR along
  80 + * with U-Boot image. Here u-boot max. size is 512K. So if binary
  81 + * size increases then increase this size in case of secure boot as
  82 + * it uses raw U-Boot image instead of FIT image.
  83 + */
  84 +#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
  85 +#else
  86 +#define CONFIG_SYS_MONITOR_LEN 0x100000
  87 +#endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
  88 +#endif
  89 +
  90 +#define CONFIG_NR_DRAM_BANKS 1
  91 +#define PHYS_SDRAM 0x80000000
  92 +#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
  93 +
  94 +#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
  95 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  96 +
  97 +#define CONFIG_CHIP_SELECTS_PER_CTRL 4
  98 +
  99 +/* Serial Port */
  100 +#define CONFIG_CONS_INDEX 1
  101 +#define CONFIG_SYS_NS16550_SERIAL
  102 +#ifndef CONFIG_DM_SERIAL
  103 +#define CONFIG_SYS_NS16550_REG_SIZE 1
  104 +#endif
  105 +#define CONFIG_SYS_NS16550_CLK get_serial_clock()
  106 +
  107 +#define CONFIG_BAUDRATE 115200
  108 +
  109 +/* I2C */
  110 +#define CONFIG_SYS_I2C
  111 +#define CONFIG_SYS_I2C_MXC
  112 +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
  113 +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
  114 +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
  115 +
  116 +/* EEPROM */
  117 +#define CONFIG_ID_EEPROM
  118 +#define CONFIG_SYS_I2C_EEPROM_NXID
  119 +#define CONFIG_SYS_EEPROM_BUS_NUM 0
  120 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x51
  121 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
  122 +
  123 +/* QSPI */
  124 +#define FSL_QSPI_FLASH_SIZE (1 << 24)
  125 +#define FSL_QSPI_FLASH_NUM 2
  126 +
  127 +/* PCIe */
  128 +#define CONFIG_PCIE1 /* PCIE controller 1 */
  129 +#define CONFIG_PCIE2 /* PCIE controller 2 */
  130 +#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
  131 +#ifdef CONFIG_PCI
  132 +#define CONFIG_PCI_SCAN_SHOW
  133 +#endif
  134 +
  135 +#define CONFIG_LAYERSCAPE_NS_ACCESS
  136 +#define COUNTER_FREQUENCY 12500000
  137 +
  138 +#define CONFIG_HWCONFIG
  139 +#define HWCONFIG_BUFFER_SIZE 256
  140 +
  141 +#define CONFIG_FSL_DEVICE_DISABLE
  142 +
  143 +#define BOOT_TARGET_DEVICES(func) \
  144 + func(MMC, mmc, 0) \
  145 + func(USB, usb, 0) \
  146 + func(DHCP, dhcp, na)
  147 +#include <config_distro_bootcmd.h>
  148 +
  149 +#define CONFIG_EXTRA_ENV_SETTINGS \
  150 + "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
  151 + "initrd_high=0xffffffff\0" \
  152 + "fdt_high=0xffffffff\0" \
  153 + "fdt_addr=0x64f00000\0" \
  154 + "kernel_addr=0x61000000\0" \
  155 + "kernelheader_addr=0x60800000\0" \
  156 + "scriptaddr=0x80000000\0" \
  157 + "scripthdraddr=0x80080000\0" \
  158 + "fdtheader_addr_r=0x80100000\0" \
  159 + "kernelheader_addr_r=0x80200000\0" \
  160 + "kernel_addr_r=0x80008000\0" \
  161 + "kernelheader_size=0x40000\0" \
  162 + "fdt_addr_r=0x8f000000\0" \
  163 + "ramdisk_addr_r=0xa0000000\0" \
  164 + "load_addr=0x80008000\0" \
  165 + "kernel_size=0x2800000\0" \
  166 + "kernel_addr_sd=0x8000\0" \
  167 + "kernel_size_sd=0x14000\0" \
  168 + "kernelhdr_addr_sd=0x4000\0" \
  169 + "kernelhdr_size_sd=0x10\0" \
  170 + BOOTENV \
  171 + "boot_scripts=ls1021atsn_boot.scr\0" \
  172 + "boot_script_hdr=hdr_ls1021atsn_bs.out\0" \
  173 + "scan_dev_for_boot_part=" \
  174 + "part list ${devtype} ${devnum} devplist; " \
  175 + "env exists devplist || setenv devplist 1; " \
  176 + "for distro_bootpart in ${devplist}; do " \
  177 + "if fstype ${devtype} " \
  178 + "${devnum}:${distro_bootpart} " \
  179 + "bootfstype; then " \
  180 + "run scan_dev_for_boot; " \
  181 + "fi; " \
  182 + "done\0" \
  183 + "scan_dev_for_boot=" \
  184 + "echo Scanning ${devtype} " \
  185 + "${devnum}:${distro_bootpart}...; " \
  186 + "for prefix in ${boot_prefixes}; do " \
  187 + "run scan_dev_for_scripts; " \
  188 + "run scan_dev_for_extlinux; " \
  189 + "done;" \
  190 + "\0" \
  191 + "boot_a_script=" \
  192 + "load ${devtype} ${devnum}:${distro_bootpart} " \
  193 + "${scriptaddr} ${prefix}${script}; " \
  194 + "env exists secureboot && load ${devtype} " \
  195 + "${devnum}:${distro_bootpart} " \
  196 + "${scripthdraddr} ${prefix}${boot_script_hdr} " \
  197 + "&& esbc_validate ${scripthdraddr};" \
  198 + "source ${scriptaddr}\0" \
  199 + "qspi_bootcmd=echo Trying load from qspi..;" \
  200 + "sf probe && sf read $load_addr " \
  201 + "$kernel_addr $kernel_size; env exists secureboot " \
  202 + "&& sf read $kernelheader_addr_r $kernelheader_addr " \
  203 + "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
  204 + "bootm $load_addr#$board\0" \
  205 + "sd_bootcmd=echo Trying load from SD ..;" \
  206 + "mmcinfo && mmc read $load_addr " \
  207 + "$kernel_addr_sd $kernel_size_sd && " \
  208 + "env exists secureboot && mmc read $kernelheader_addr_r " \
  209 + "$kernelhdr_addr_sd $kernelhdr_size_sd " \
  210 + " && esbc_validate ${kernelheader_addr_r};" \
  211 + "bootm $load_addr#$board\0"
  212 +
  213 +/* Miscellaneous configurable options */
  214 +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  215 +#define CONFIG_SYS_PBSIZE \
  216 + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  217 +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  218 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  219 +
  220 +#define CONFIG_SYS_LOAD_ADDR 0x82000000
  221 +
  222 +#define CONFIG_LS102XA_STREAM_ID
  223 +
  224 +#define CONFIG_SYS_INIT_SP_OFFSET \
  225 + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  226 +#define CONFIG_SYS_INIT_SP_ADDR \
  227 + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
  228 +
  229 +#ifdef CONFIG_SPL_BUILD
  230 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  231 +#else
  232 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  233 +#endif
  234 +
  235 +/* Environment */
  236 +#define CONFIG_ENV_OVERWRITE
  237 +
  238 +#if defined(CONFIG_SD_BOOT)
  239 +#define CONFIG_ENV_OFFSET 0x300000
  240 +#define CONFIG_SYS_MMC_ENV_DEV 0
  241 +#define CONFIG_ENV_SIZE 0x20000
  242 +#elif defined(CONFIG_QSPI_BOOT)
  243 +#define CONFIG_ENV_SIZE 0x2000
  244 +#define CONFIG_ENV_OFFSET 0x300000
  245 +#define CONFIG_ENV_SECT_SIZE 0x40000
  246 +#endif
  247 +
  248 +#define CONFIG_SYS_BOOTM_LEN 0x8000000 /* 128 MB */
  249 +
  250 +#endif