Eric Lee / smarc-uboot

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Commit 87e29878caba758ed3e09e9912ac8eb6dfc55f39

Authored by Andy Fleming
Committed by York Sun
1 parent c79e1c1ce9
Exists in v2017.01-smarct4x and in 30 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

mpc85xx: Add support for the Varisys Cyrus board 

This board runs a P5020 or P5040 chip, and utilizes
an EEPROM with similar formatting to the Freescale P5020DS.

Large amounts of this code were developed by
Adrian Cox <adrian at humboldt dot co dot uk>

Signed-off-by: Andy Fleming <afleming@gmail.com>
Reviewed-by: York Sun <yorksun@freescale.com>

Showing 21 changed files with 1810 additions and 0 deletions Side-by-side Diff

arch/powerpc/cpu/mpc85xx/Kconfig
Diff comments   View file @ 87e2987
... ... @@ -149,6 +149,9 @@
149 149 config TARGET_UCP1020
150 150 bool "Support uCP1020"
151 151  
  152 +config TARGET_CYRUS
  153 + bool "Support Varisys Cyrus"
  154 +
152 155 endchoice
153 156  
154 157 source "board/freescale/b4860qds/Kconfig"
... ... @@ -185,6 +188,7 @@
185 188 source "board/keymile/kmp204x/Kconfig"
186 189 source "board/sbc8548/Kconfig"
187 190 source "board/socrates/Kconfig"
  191 +source "board/varisys/cyrus/Kconfig"
188 192 source "board/xes/xpedite520x/Kconfig"
189 193 source "board/xes/xpedite537x/Kconfig"
190 194 source "board/xes/xpedite550x/Kconfig"
board/varisys/common/Makefile
Diff comments   View file @ 87e2987
  1 +#
  2 +# (C) Copyright 2006
  3 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 +#
  5 +# SPDX-License-Identifier: GPL-2.0+
  6 +#
  7 +
  8 +MINIMAL=
  9 +
  10 +ifdef CONFIG_SPL_BUILD
  11 +ifdef CONFIG_SPL_INIT_MINIMAL
  12 +MINIMAL=y
  13 +endif
  14 +endif
  15 +
  16 +ifdef MINIMAL
  17 +# necessary to create built-in.o
  18 +obj- := __dummy__.o
  19 +else
  20 +ifndef CONFIG_SPL_BUILD
  21 +obj-$(CONFIG_ID_EEPROM) += sys_eeprom.o
  22 +endif
  23 +endif
board/varisys/common/eeprom.h
Diff comments   View file @ 87e2987
  1 +/* EEPROM init functions for Cyrus */
  2 +
  3 +
  4 +void init_eeprom(int bus_num, int addr, int addr_len);
  5 +void mac_read_from_fixed_id(void);
  6 +int mac_read_from_eeprom_common(void);
board/varisys/common/sys_eeprom.c
Diff comments   View file @ 87e2987
  1 +/*
  2 + * Based on board/freescale/common/sys_eeprom.c
  3 + * Copyright 2006, 2008-2009, 2011 Freescale Semiconductor
  4 + *
  5 + * This defines the API for storing board information in the
  6 + * eeprom. It has been adapted from an earlier version of the
  7 + * Freescale API, but has a number of key differences. Because
  8 + * the two APIs are independent and may diverge further, the
  9 + * Varisys version of the API is implemented separately here.
  10 + *
  11 + * SPDX-License-Identifier: GPL-2.0+
  12 + */
  13 +
  14 +#include <common.h>
  15 +#include <command.h>
  16 +#include <i2c.h>
  17 +#include <linux/ctype.h>
  18 +
  19 +#include "eeprom.h"
  20 +
  21 +#ifdef CONFIG_SYS_I2C_EEPROM_NXID_MAC
  22 +#define MAX_NUM_PORTS CONFIG_SYS_I2C_EEPROM_NXID_MAC
  23 +#else
  24 +#define MAX_NUM_PORTS 8
  25 +#endif
  26 +#define NXID_VERSION 0
  27 +
  28 +/**
  29 + * static eeprom: EEPROM layout for NXID formats
  30 + *
  31 + * See Freescale application note AN3638 for details.
  32 + */
  33 +static struct __attribute__ ((__packed__)) eeprom {
  34 + u8 id[4]; /* 0x00 - 0x03 EEPROM Tag 'NXID' */
  35 + u8 sn[12]; /* 0x04 - 0x0F Serial Number */
  36 + u8 errata[5]; /* 0x10 - 0x14 Errata Level */
  37 + u8 date[6]; /* 0x15 - 0x1a Build Date */
  38 + u8 res_0; /* 0x1b Reserved */
  39 + u32 version; /* 0x1c - 0x1f NXID Version */
  40 + u8 tempcal[8]; /* 0x20 - 0x27 Temperature Calibration Factors */
  41 + u8 tempcalsys[2]; /* 0x28 - 0x29 System Temperature Calibration Factors */
  42 + u8 tempcalflags; /* 0x2a Temperature Calibration Flags */
  43 + u8 res_1[21]; /* 0x2b - 0x3f Reserved */
  44 + u8 mac_count; /* 0x40 Number of MAC addresses */
  45 + u8 mac_flag; /* 0x41 MAC table flags */
  46 + u8 mac[MAX_NUM_PORTS][6]; /* 0x42 - x MAC addresses */
  47 + u32 crc; /* x+1 CRC32 checksum */
  48 +} e;
  49 +
  50 +/* Set to 1 if we've read EEPROM into memory */
  51 +static int has_been_read;
  52 +
  53 +/* Is this a valid NXID EEPROM? */
  54 +#define is_valid ((e.id[0] == 'N') || (e.id[1] == 'X') || \
  55 + (e.id[2] == 'I') || (e.id[3] == 'D'))
  56 +
  57 +/** Fixed ID field in EEPROM */
  58 +static unsigned char uid[16];
  59 +
  60 +static int eeprom_bus_num = -1;
  61 +static int eeprom_addr;
  62 +static int eeprom_addr_len;
  63 +
  64 +/**
  65 + * This must be called before any eeprom access.
  66 + */
  67 +void init_eeprom(int bus_num, int addr, int addr_len)
  68 +{
  69 + eeprom_bus_num = bus_num;
  70 + eeprom_addr = addr;
  71 + eeprom_addr_len = addr_len;
  72 +}
  73 +
  74 +/**
  75 + * show_eeprom - display the contents of the EEPROM
  76 + */
  77 +void show_eeprom(void)
  78 +{
  79 + int i;
  80 + unsigned int crc;
  81 +
  82 + /* EEPROM tag ID, either CCID or NXID */
  83 + printf("ID: %c%c%c%c v%u\n", e.id[0], e.id[1], e.id[2], e.id[3],
  84 + be32_to_cpu(e.version));
  85 +
  86 + /* Serial number */
  87 + printf("SN: %s\n", e.sn);
  88 +
  89 + printf("UID: ");
  90 + for (i = 0; i < 16; i++)
  91 + printf("%02x", uid[i]);
  92 + printf("\n");
  93 +
  94 + /* Errata level. */
  95 + printf("Errata: %s\n", e.errata);
  96 +
  97 + /* Build date, BCD date values, as YYMMDDhhmmss */
  98 + printf("Build date: 20%02x/%02x/%02x %02x:%02x:%02x %s\n",
  99 + e.date[0], e.date[1], e.date[2],
  100 + e.date[3] & 0x7F, e.date[4], e.date[5],
  101 + e.date[3] & 0x80 ? "PM" : "");
  102 +
  103 + /* Show MAC addresses */
  104 + for (i = 0; i < min(e.mac_count, (u8)MAX_NUM_PORTS); i++) {
  105 + u8 *p = e.mac[i];
  106 +
  107 + printf("Eth%u: %02x:%02x:%02x:%02x:%02x:%02x\n", i,
  108 + p[0], p[1], p[2], p[3], p[4], p[5]);
  109 + }
  110 +
  111 + crc = crc32(0, (void *)&e, sizeof(e) - 4);
  112 +
  113 + if (crc == be32_to_cpu(e.crc))
  114 + printf("CRC: %08x\n", be32_to_cpu(e.crc));
  115 + else
  116 + printf("CRC: %08x (should be %08x)\n",
  117 + be32_to_cpu(e.crc), crc);
  118 +
  119 +#ifdef DEBUG
  120 + printf("EEPROM dump: (0x%x bytes)\n", sizeof(e));
  121 + for (i = 0; i < sizeof(e); i++) {
  122 + if ((i % 16) == 0)
  123 + printf("%02X: ", i);
  124 + printf("%02X ", ((u8 *)&e)[i]);
  125 + if (((i % 16) == 15) || (i == sizeof(e) - 1))
  126 + printf("\n");
  127 + }
  128 +#endif
  129 +}
  130 +
  131 +/**
  132 + * read_eeprom - read the EEPROM into memory
  133 + */
  134 +int read_eeprom(void)
  135 +{
  136 + int ret;
  137 + unsigned int bus;
  138 +
  139 + if (eeprom_bus_num < 0) {
  140 + printf("EEPROM not configured\n");
  141 + return -1;
  142 + }
  143 +
  144 + if (has_been_read)
  145 + return 0;
  146 +
  147 + bus = i2c_get_bus_num();
  148 + i2c_set_bus_num(eeprom_bus_num);
  149 +
  150 + ret = i2c_read(eeprom_addr, 0, eeprom_addr_len,
  151 + (void *)&e, sizeof(e));
  152 +
  153 +
  154 + /* Fixed address of ID field */
  155 + i2c_read(0x5f, 0x80, 1, uid, 16);
  156 +
  157 + i2c_set_bus_num(bus);
  158 +
  159 +#ifdef DEBUG
  160 + show_eeprom();
  161 +#endif
  162 +
  163 + has_been_read = (ret == 0) ? 1 : 0;
  164 +
  165 + return ret;
  166 +}
  167 +
  168 +/**
  169 + * update_crc - update the CRC
  170 + *
  171 + * This function should be called after each update to the EEPROM structure,
  172 + * to make sure the CRC is always correct.
  173 + */
  174 +static void update_crc(void)
  175 +{
  176 + u32 crc, crc_offset = offsetof(struct eeprom, crc);
  177 +
  178 + crc = crc32(0, (void *)&e, crc_offset);
  179 + e.crc = cpu_to_be32(crc);
  180 +}
  181 +
  182 +/**
  183 + * prog_eeprom - write the EEPROM from memory
  184 + */
  185 +static int prog_eeprom(void)
  186 +{
  187 + int ret = 0;
  188 + int i;
  189 + void *p;
  190 + unsigned int bus;
  191 +
  192 + if (eeprom_bus_num < 0) {
  193 + printf("EEPROM not configured\n");
  194 + return -1;
  195 + }
  196 +
  197 + /* Set the reserved values to 0xFF */
  198 + e.res_0 = 0xFF;
  199 + memset(e.res_1, 0xFF, sizeof(e.res_1));
  200 + update_crc();
  201 +
  202 + bus = i2c_get_bus_num();
  203 + i2c_set_bus_num(eeprom_bus_num);
  204 +
  205 + /*
  206 + * The AT24C02 datasheet says that data can only be written in page
  207 + * mode, which means 8 bytes at a time, and it takes up to 5ms to
  208 + * complete a given write.
  209 + */
  210 + for (i = 0, p = &e; i < sizeof(e); i += 8, p += 8) {
  211 + ret = i2c_write(eeprom_addr, i, eeprom_addr_len,
  212 + p, min((int)(sizeof(e) - i), 8));
  213 + if (ret)
  214 + break;
  215 + udelay(5000); /* 5ms write cycle timing */
  216 + }
  217 +
  218 + if (!ret) {
  219 + /* Verify the write by reading back the EEPROM and comparing */
  220 + struct eeprom e2;
  221 +
  222 + ret = i2c_read(eeprom_addr, 0,
  223 + eeprom_addr_len, (void *)&e2, sizeof(e2));
  224 + if (!ret && memcmp(&e, &e2, sizeof(e)))
  225 + ret = -1;
  226 + }
  227 +
  228 + i2c_set_bus_num(bus);
  229 +
  230 + if (ret) {
  231 + printf("Programming failed.\n");
  232 + has_been_read = 0;
  233 + return -1;
  234 + }
  235 +
  236 + printf("Programming passed.\n");
  237 + return 0;
  238 +}
  239 +
  240 +/**
  241 + * h2i - converts hex character into a number
  242 + *
  243 + * This function takes a hexadecimal character (e.g. '7' or 'C') and returns
  244 + * the integer equivalent.
  245 + */
  246 +static inline u8 h2i(char p)
  247 +{
  248 + if ((p >= '0') && (p <= '9'))
  249 + return p - '0';
  250 +
  251 + if ((p >= 'A') && (p <= 'F'))
  252 + return (p - 'A') + 10;
  253 +
  254 + if ((p >= 'a') && (p <= 'f'))
  255 + return (p - 'a') + 10;
  256 +
  257 + return 0;
  258 +}
  259 +
  260 +/**
  261 + * set_date - stores the build date into the EEPROM
  262 + *
  263 + * This function takes a pointer to a string in the format "YYMMDDhhmmss"
  264 + * (2-digit year, 2-digit month, etc), converts it to a 6-byte BCD string,
  265 + * and stores it in the build date field of the EEPROM local copy.
  266 + */
  267 +static void set_date(const char *string)
  268 +{
  269 + unsigned int i;
  270 +
  271 + if (strlen(string) != 12) {
  272 + printf("Usage: mac date YYMMDDhhmmss\n");
  273 + return;
  274 + }
  275 +
  276 + for (i = 0; i < 6; i++)
  277 + e.date[i] = h2i(string[2 * i]) << 4 | h2i(string[2 * i + 1]);
  278 +
  279 + update_crc();
  280 +}
  281 +
  282 +/**
  283 + * set_mac_address - stores a MAC address into the EEPROM
  284 + *
  285 + * This function takes a pointer to MAC address string
  286 + * (i.e."XX:XX:XX:XX:XX:XX", where "XX" is a two-digit hex number) and
  287 + * stores it in one of the MAC address fields of the EEPROM local copy.
  288 + */
  289 +static void set_mac_address(unsigned int index, const char *string)
  290 +{
  291 + char *p = (char *)string;
  292 + unsigned int i;
  293 +
  294 + if ((index >= MAX_NUM_PORTS) || !string) {
  295 + printf("Usage: mac <n> XX:XX:XX:XX:XX:XX\n");
  296 + return;
  297 + }
  298 +
  299 + for (i = 0; *p && (i < 6); i++) {
  300 + e.mac[index][i] = simple_strtoul(p, &p, 16);
  301 + if (*p == ':')
  302 + p++;
  303 + }
  304 +
  305 + update_crc();
  306 +}
  307 +
  308 +int do_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  309 +{
  310 + char cmd;
  311 +
  312 + if (argc == 1) {
  313 + show_eeprom();
  314 + return 0;
  315 + }
  316 +
  317 + cmd = argv[1][0];
  318 +
  319 + if (cmd == 'r') {
  320 + read_eeprom();
  321 + return 0;
  322 + }
  323 +
  324 + if (cmd == 'i') {
  325 + memcpy(e.id, "NXID", sizeof(e.id));
  326 + e.version = NXID_VERSION;
  327 + update_crc();
  328 + return 0;
  329 + }
  330 +
  331 + if (!is_valid) {
  332 + printf("Please read the EEPROM ('r') and/or set the ID ('i') first.\n");
  333 + return 0;
  334 + }
  335 +
  336 + if (argc == 2) {
  337 + switch (cmd) {
  338 + case 's': /* save */
  339 + prog_eeprom();
  340 + break;
  341 + default:
  342 + return cmd_usage(cmdtp);
  343 + }
  344 +
  345 + return 0;
  346 + }
  347 +
  348 + /* We know we have at least one parameter */
  349 +
  350 + switch (cmd) {
  351 + case 'n': /* serial number */
  352 + memset(e.sn, 0, sizeof(e.sn));
  353 + strncpy((char *)e.sn, argv[2], sizeof(e.sn) - 1);
  354 + update_crc();
  355 + break;
  356 + case 'e': /* errata */
  357 + memset(e.errata, 0, 5);
  358 + strncpy((char *)e.errata, argv[2], 4);
  359 + update_crc();
  360 + break;
  361 + case 'd': /* date BCD format YYMMDDhhmmss */
  362 + set_date(argv[2]);
  363 + break;
  364 + case 'p': /* MAC table size */
  365 + e.mac_count = simple_strtoul(argv[2], NULL, 16);
  366 + update_crc();
  367 + break;
  368 + case '0' ... '9': /* "mac 0" through "mac 22" */
  369 + set_mac_address(simple_strtoul(argv[1], NULL, 10), argv[2]);
  370 + break;
  371 + case 'h': /* help */
  372 + default:
  373 + return cmd_usage(cmdtp);
  374 + }
  375 +
  376 + return 0;
  377 +}
  378 +
  379 +int mac_read_from_generic_eeprom(const char *envvar, int chip,
  380 + int address, int mac_bus)
  381 +{
  382 + int ret;
  383 + unsigned int bus;
  384 + unsigned char mac[6];
  385 + char ethaddr[18];
  386 +
  387 + bus = i2c_get_bus_num();
  388 + i2c_set_bus_num(mac_bus);
  389 +
  390 + ret = i2c_read(chip, address, 1, mac, 6);
  391 +
  392 + i2c_set_bus_num(bus);
  393 +
  394 + if (!ret) {
  395 + sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X",
  396 + mac[0],
  397 + mac[1],
  398 + mac[2],
  399 + mac[3],
  400 + mac[4],
  401 + mac[5]);
  402 +
  403 + printf("MAC: %s\n", ethaddr);
  404 + setenv(envvar, ethaddr);
  405 + }
  406 +
  407 + return ret;
  408 +}
  409 +
  410 +void mac_read_from_fixed_id(void)
  411 +{
  412 +#ifdef CONFIG_SYS_I2C_MAC1_CHIP_ADDR
  413 + mac_read_from_generic_eeprom("ethaddr", CONFIG_SYS_I2C_MAC1_CHIP_ADDR,
  414 + CONFIG_SYS_I2C_MAC1_DATA_ADDR, CONFIG_SYS_I2C_MAC1_BUS);
  415 +#endif
  416 +#ifdef CONFIG_SYS_I2C_MAC2_CHIP_ADDR
  417 + mac_read_from_generic_eeprom("eth1addr", CONFIG_SYS_I2C_MAC2_CHIP_ADDR,
  418 + CONFIG_SYS_I2C_MAC2_DATA_ADDR, CONFIG_SYS_I2C_MAC2_BUS);
  419 +#endif
  420 +}
  421 +
  422 +/**
  423 + * mac_read_from_eeprom - read the MAC addresses from EEPROM
  424 + *
  425 + * This function reads the MAC addresses from EEPROM and sets the
  426 + * appropriate environment variables for each one read.
  427 + *
  428 + * The environment variables are only set if they haven't been set already.
  429 + * This ensures that any user-saved variables are never overwritten.
  430 + *
  431 + * This function must be called after relocation.
  432 + *
  433 + * For NXID v1 EEPROMs, we support loading and up-converting the older NXID v0
  434 + * format. In a v0 EEPROM, there are only eight MAC addresses and the CRC is
  435 + * located at a different offset.
  436 + */
  437 +int mac_read_from_eeprom_common(void)
  438 +{
  439 + unsigned int i;
  440 + u32 crc, crc_offset = offsetof(struct eeprom, crc);
  441 + u32 *crcp; /* Pointer to the CRC in the data read from the EEPROM */
  442 +
  443 + puts("EEPROM: ");
  444 +
  445 + if (read_eeprom()) {
  446 + printf("Read failed.\n");
  447 + return 0;
  448 + }
  449 +
  450 + if (!is_valid) {
  451 + printf("Invalid ID (%02x %02x %02x %02x)\n",
  452 + e.id[0], e.id[1], e.id[2], e.id[3]);
  453 + return 0;
  454 + }
  455 +
  456 + crc = crc32(0, (void *)&e, crc_offset);
  457 + crcp = (void *)&e + crc_offset;
  458 + if (crc != be32_to_cpu(*crcp)) {
  459 + printf("CRC mismatch (%08x != %08x)\n", crc,
  460 + be32_to_cpu(e.crc));
  461 + return 0;
  462 + }
  463 +
  464 + /*
  465 + * MAC address #9 in v1 occupies the same position as the CRC in v0.
  466 + * Erase it so that it's not mistaken for a MAC address. We'll
  467 + * update the CRC later.
  468 + */
  469 + if (e.version == 0)
  470 + memset(e.mac[8], 0xff, 6);
  471 +
  472 + for (i = 0; i < min(e.mac_count, (u8)MAX_NUM_PORTS); i++) {
  473 + if (memcmp(&e.mac[i], "\0\0\0\0\0\0", 6) &&
  474 + memcmp(&e.mac[i], "\xFF\xFF\xFF\xFF\xFF\xFF", 6)) {
  475 + char ethaddr[18];
  476 + char enetvar[9];
  477 +
  478 + sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X",
  479 + e.mac[i][0],
  480 + e.mac[i][1],
  481 + e.mac[i][2],
  482 + e.mac[i][3],
  483 + e.mac[i][4],
  484 + e.mac[i][5]);
  485 + sprintf(enetvar, i ? "eth%daddr" : "ethaddr", i);
  486 + /* Only initialize environment variables that are blank
  487 + * (i.e. have not yet been set)
  488 + */
  489 + if (!getenv(enetvar))
  490 + setenv(enetvar, ethaddr);
  491 + }
  492 + }
  493 +
  494 + printf("%c%c%c%c v%u\n", e.id[0], e.id[1], e.id[2], e.id[3],
  495 + be32_to_cpu(e.version));
  496 +
  497 + return 0;
  498 +}
board/varisys/cyrus/Kconfig
Diff comments   View file @ 87e2987
  1 +if TARGET_CYRUS
  2 +
  3 +config SYS_BOARD
  4 + default "cyrus"
  5 +
  6 +config SYS_VENDOR
  7 + default "varisys"
  8 +
  9 +config SYS_CONFIG_NAME
  10 + default "cyrus"
  11 +
  12 +endif
board/varisys/cyrus/MAINTAINERS
Diff comments   View file @ 87e2987
  1 +Cyrus BOARD
  2 +M: Andy Fleming <afleming@gmail.com>
  3 +S: Maintained
  4 +F: board/varisys/cyrus/
  5 +F: include/configs/cyrus.h
  6 +F: configs/Cyrus_P5020_defconfig
  7 +F: configs/Cyrus_P5040_defconfig
board/varisys/cyrus/Makefile
Diff comments   View file @ 87e2987
  1 +#
  2 +
  3 +obj-y += $(BOARD).o
  4 +obj-y += ddr.o
  5 +obj-y += law.o
  6 +obj-y += tlb.o
  7 +obj-y += eth.o
  8 +obj-$(CONFIG_PCI) += pci.o
board/varisys/cyrus/README
Diff comments   View file @ 87e2987
  1 +Rebuilding u-boot for Cyrus
  2 +
  3 +The Cyrus defconfigs are Cyrus_P5020_defconfig and Cyrus_P5040_defconfig.
  4 +
  5 +They currently disable size optimization in order to avoid a relocation
  6 +bug in some versions of GCC. As the output size is a constant, the size
  7 +optimization is not currently important.
  8 +
  9 +Cyrus boots off a microSD card in a slot on the motherboard. This requires
  10 +that the u-boot is built for the Pre-Boot Loader on the P5020/P5040.
  11 +In order to reflash u-boot, you must download u-boot.pbl, then write it
  12 +onto the card. To do that from u-boot:
  13 +
  14 +> tftp 1000000 u-boot.pbl
  15 +> mmc write 1000000 8 672
  16 +
  17 +If you want to do this via a card reader in linux:
  18 +
  19 +> dd if=u-boot.pbl of=/dev/sdX bs=512 oseek=8
board/varisys/cyrus/cyrus.c
Diff comments   View file @ 87e2987
  1 +/*
  2 + * Based on corenet_ds.c
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <common.h>
  8 +#include <command.h>
  9 +#include <netdev.h>
  10 +#include <linux/compiler.h>
  11 +#include <asm/mmu.h>
  12 +#include <asm/processor.h>
  13 +#include <asm/cache.h>
  14 +#include <asm/immap_85xx.h>
  15 +#include <asm/fsl_law.h>
  16 +#include <asm/fsl_serdes.h>
  17 +#include <asm/fsl_portals.h>
  18 +#include <asm/fsl_liodn.h>
  19 +#include <fm_eth.h>
  20 +#include <pci.h>
  21 +
  22 +#include "cyrus.h"
  23 +#include "../common/eeprom.h"
  24 +
  25 +DECLARE_GLOBAL_DATA_PTR;
  26 +
  27 +#define GPIO_OPENDRAIN 0x30000000
  28 +#define GPIO_DIR 0x3c000004
  29 +#define GPIO_INITIAL 0x30000000
  30 +#define GPIO_VGA_SWITCH 0x00001000
  31 +
  32 +int checkboard(void)
  33 +{
  34 + printf("Board: CYRUS\n");
  35 +
  36 + return 0;
  37 +}
  38 +
  39 +int board_early_init_f(void)
  40 +{
  41 + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  42 + ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
  43 +
  44 + /*
  45 + * Only use DDR1_MCK0/3 and DDR2_MCK0/3
  46 + * disable DDR1_MCK1/2/4/5 and DDR2_MCK1/2/4/5 to reduce
  47 + * the noise introduced by these unterminated and unused clock pairs.
  48 + */
  49 + setbits_be32(&gur->ddrclkdr, 0x001B001B);
  50 +
  51 + /* Set GPIO reset lines to open-drain, tristate */
  52 + setbits_be32(&pgpio->gpdat, GPIO_INITIAL);
  53 + setbits_be32(&pgpio->gpodr, GPIO_OPENDRAIN);
  54 +
  55 + /* Set GPIO Direction */
  56 + setbits_be32(&pgpio->gpdir, GPIO_DIR);
  57 +
  58 + return 0;
  59 +}
  60 +
  61 +int board_early_init_r(void)
  62 +{
  63 + fsl_lbc_t *lbc = LBC_BASE_ADDR;
  64 +
  65 + out_be32(&lbc->lbcr, 0);
  66 + /* 1 clock LALE cycle */
  67 + out_be32(&lbc->lcrr, 0x80000000 | CONFIG_SYS_LBC_LCRR);
  68 +
  69 + set_liodns();
  70 +
  71 +#ifdef CONFIG_SYS_DPAA_QBMAN
  72 + setup_portals();
  73 +#endif
  74 + print_lbc_regs();
  75 + return 0;
  76 +}
  77 +
  78 +int misc_init_r(void)
  79 +{
  80 + return 0;
  81 +}
  82 +
  83 +int ft_board_setup(void *blob, bd_t *bd)
  84 +{
  85 + phys_addr_t base;
  86 + phys_size_t size;
  87 +
  88 + ft_cpu_setup(blob, bd);
  89 +
  90 + base = getenv_bootm_low();
  91 + size = getenv_bootm_size();
  92 +
  93 + fdt_fixup_memory(blob, (u64)base, (u64)size);
  94 +
  95 +#ifdef CONFIG_PCI
  96 + pci_of_setup(blob, bd);
  97 +#endif
  98 +
  99 + fdt_fixup_liodn(blob);
  100 + fdt_fixup_dr_usb(blob, bd);
  101 +
  102 +#ifdef CONFIG_SYS_DPAA_FMAN
  103 + fdt_fixup_fman_ethernet(blob);
  104 +#endif
  105 +
  106 + return 0;
  107 +}
  108 +
  109 +int mac_read_from_eeprom(void)
  110 +{
  111 + init_eeprom(CONFIG_SYS_EEPROM_BUS_NUM,
  112 + CONFIG_SYS_I2C_EEPROM_ADDR,
  113 + CONFIG_SYS_I2C_EEPROM_ADDR_LEN);
  114 +
  115 + return mac_read_from_eeprom_common();
  116 +}
board/varisys/cyrus/cyrus.h
Diff comments   View file @ 87e2987
  1 +/*
  2 + * SPDX-License-Identifier: GPL-2.0+
  3 + */
  4 +
  5 +#ifndef __CYRUS_H
  6 +#define __CYRUS_H
  7 +
  8 +void fdt_fixup_board_enet(void *blob);
  9 +void pci_of_setup(void *blob, bd_t *bd);
  10 +
  11 +#endif
board/varisys/cyrus/ddr.c
Diff comments   View file @ 87e2987
  1 +/*
  2 + * Based on corenet_ds ddr code
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <common.h>
  8 +#include <i2c.h>
  9 +#include <hwconfig.h>
  10 +#include <asm/mmu.h>
  11 +#include <fsl_ddr_sdram.h>
  12 +#include <fsl_ddr_dimm_params.h>
  13 +#include <asm/fsl_law.h>
  14 +
  15 +DECLARE_GLOBAL_DATA_PTR;
  16 +
  17 +
  18 +struct board_specific_parameters {
  19 + u32 n_ranks;
  20 + u32 datarate_mhz_high;
  21 + u32 clk_adjust;
  22 + u32 wrlvl_start;
  23 + u32 cpo;
  24 + u32 write_data_delay;
  25 + u32 force_2t;
  26 +};
  27 +
  28 +/*
  29 + * This table contains all valid speeds we want to override with board
  30 + * specific parameters. datarate_mhz_high values need to be in ascending order
  31 + * for each n_ranks group.
  32 + */
  33 +static const struct board_specific_parameters udimm0[] = {
  34 + /*
  35 + * memory controller 0
  36 + * num| hi| clk| wrlvl | cpo |wrdata|2T
  37 + * ranks| mhz|adjst| start | |delay |
  38 + */
  39 + {4, 850, 4, 6, 0xff, 2, 0},
  40 + {4, 950, 5, 7, 0xff, 2, 0},
  41 + {4, 1050, 5, 8, 0xff, 2, 0},
  42 + {4, 1250, 5, 10, 0xff, 2, 0},
  43 + {4, 1350, 5, 11, 0xff, 2, 0},
  44 + {4, 1666, 5, 12, 0xff, 2, 0},
  45 + {2, 850, 5, 6, 0xff, 2, 0},
  46 + {2, 1050, 5, 7, 0xff, 2, 0},
  47 + {2, 1250, 4, 6, 0xff, 2, 0},
  48 + {2, 1350, 5, 7, 0xff, 2, 0},
  49 + {2, 1666, 5, 8, 0xff, 2, 0},
  50 + {1, 1250, 4, 6, 0xff, 2, 0},
  51 + {1, 1335, 4, 7, 0xff, 2, 0},
  52 + {1, 1666, 4, 8, 0xff, 2, 0},
  53 + {}
  54 +};
  55 +
  56 +/*
  57 + * The two slots have slightly different timing. The center values are good
  58 + * for both slots. We use identical speed tables for them. In future use, if
  59 + * DIMMs have fewer center values that require two separated tables, copy the
  60 + * udimm0 table to udimm1 and make changes to clk_adjust and wrlvl_start.
  61 + */
  62 +static const struct board_specific_parameters *udimms[] = {
  63 + udimm0,
  64 + udimm0,
  65 +};
  66 +
  67 +static const struct board_specific_parameters rdimm0[] = {
  68 + /*
  69 + * memory controller 0
  70 + * num| hi| clk| wrlvl | cpo |wrdata|2T
  71 + * ranks| mhz|adjst| start | |delay |
  72 + */
  73 + {4, 850, 4, 6, 0xff, 2, 0},
  74 + {4, 950, 5, 7, 0xff, 2, 0},
  75 + {4, 1050, 5, 8, 0xff, 2, 0},
  76 + {4, 1250, 5, 10, 0xff, 2, 0},
  77 + {4, 1350, 5, 11, 0xff, 2, 0},
  78 + {4, 1666, 5, 12, 0xff, 2, 0},
  79 + {2, 850, 4, 6, 0xff, 2, 0},
  80 + {2, 1050, 4, 7, 0xff, 2, 0},
  81 + {2, 1666, 4, 8, 0xff, 2, 0},
  82 + {1, 850, 4, 5, 0xff, 2, 0},
  83 + {1, 950, 4, 7, 0xff, 2, 0},
  84 + {1, 1666, 4, 8, 0xff, 2, 0},
  85 + {}
  86 +};
  87 +
  88 +/*
  89 + * The two slots have slightly different timing. See comments above.
  90 + */
  91 +static const struct board_specific_parameters *rdimms[] = {
  92 + rdimm0,
  93 + rdimm0,
  94 +};
  95 +
  96 +void fsl_ddr_board_options(memctl_options_t *popts,
  97 + dimm_params_t *pdimm,
  98 + unsigned int ctrl_num)
  99 +{
  100 + const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  101 + ulong ddr_freq;
  102 +
  103 + if (ctrl_num > 1) {
  104 + printf("Wrong parameter for controller number %d", ctrl_num);
  105 + return;
  106 + }
  107 + if (!pdimm->n_ranks)
  108 + return;
  109 +
  110 + if (popts->registered_dimm_en)
  111 + pbsp = rdimms[ctrl_num];
  112 + else
  113 + pbsp = udimms[ctrl_num];
  114 +
  115 +
  116 + /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
  117 + * freqency and n_banks specified in board_specific_parameters table.
  118 + */
  119 + ddr_freq = get_ddr_freq(0) / 1000000;
  120 + while (pbsp->datarate_mhz_high) {
  121 + if (pbsp->n_ranks == pdimm->n_ranks) {
  122 + if (ddr_freq <= pbsp->datarate_mhz_high) {
  123 + popts->cpo_override = pbsp->cpo;
  124 + popts->write_data_delay =
  125 + pbsp->write_data_delay;
  126 + popts->clk_adjust = pbsp->clk_adjust;
  127 + popts->wrlvl_start = pbsp->wrlvl_start;
  128 + popts->twot_en = pbsp->force_2t;
  129 + goto found;
  130 + }
  131 + pbsp_highest = pbsp;
  132 + }
  133 + pbsp++;
  134 + }
  135 +
  136 + if (pbsp_highest) {
  137 + printf("Error: board specific timing not found for data rate %lu MT/s!\nTrying to use the highest speed (%u) parameters\n",
  138 + ddr_freq, pbsp_highest->datarate_mhz_high);
  139 + popts->cpo_override = pbsp_highest->cpo;
  140 + popts->write_data_delay = pbsp_highest->write_data_delay;
  141 + popts->clk_adjust = pbsp_highest->clk_adjust;
  142 + popts->wrlvl_start = pbsp_highest->wrlvl_start;
  143 + popts->twot_en = pbsp_highest->force_2t;
  144 + } else {
  145 + panic("DIMM is not supported by this board");
  146 + }
  147 +found:
  148 + /*
  149 + * Factors to consider for half-strength driver enable:
  150 + * - number of DIMMs installed
  151 + */
  152 + popts->half_strength_driver_enable = 0;
  153 + /*
  154 + * Write leveling override
  155 + */
  156 + popts->wrlvl_override = 1;
  157 + popts->wrlvl_sample = 0xf;
  158 +
  159 + /*
  160 + * Rtt and Rtt_WR override
  161 + */
  162 + popts->rtt_override = 0;
  163 +
  164 + /* Enable ZQ calibration */
  165 + popts->zq_en = 1;
  166 +
  167 + /* DHC_EN =1, ODT = 60 Ohm */
  168 + popts->ddr_cdr1 = DDR_CDR1_DHC_EN;
  169 +}
  170 +
  171 +phys_size_t initdram(int board_type)
  172 +{
  173 + phys_size_t dram_size;
  174 +
  175 + puts("Initializing....");
  176 +
  177 + if (!fsl_use_spd())
  178 + panic("Cyrus only supports using SPD for DRAM\n");
  179 +
  180 + puts("using SPD\n");
  181 + dram_size = fsl_ddr_sdram();
  182 +
  183 + dram_size = setup_ddr_tlbs(dram_size / 0x100000);
  184 + dram_size *= 0x100000;
  185 +
  186 + debug(" DDR: ");
  187 + return dram_size;
  188 +}
board/varisys/cyrus/eth.c
Diff comments   View file @ 87e2987
  1 +/*
  2 + * Author Adrian Cox
  3 + * Based somewhat on board/freescale/corenet_ds/eth_hydra.c
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#include <common.h>
  9 +#include <netdev.h>
  10 +#include <asm/fsl_serdes.h>
  11 +#include <fm_eth.h>
  12 +#include <fsl_mdio.h>
  13 +#include <malloc.h>
  14 +#include <fdt_support.h>
  15 +#include <fsl_dtsec.h>
  16 +
  17 +#ifdef CONFIG_FMAN_ENET
  18 +
  19 +#define FIRST_PORT_ADDR 3
  20 +#define SECOND_PORT_ADDR 7
  21 +
  22 +#ifdef CONFIG_PPC_P5040
  23 +#define FIRST_PORT FM1_DTSEC5
  24 +#define SECOND_PORT FM2_DTSEC5
  25 +#else
  26 +#define FIRST_PORT FM1_DTSEC4
  27 +#define SECOND_PORT FM1_DTSEC5
  28 +#endif
  29 +
  30 +#define IS_VALID_PORT(p) ((p) == FIRST_PORT || (p) == SECOND_PORT)
  31 +
  32 +static void cyrus_phy_tuning(int phy)
  33 +{
  34 + /*
  35 + * Enable RGMII delay on Tx and Rx for CPU port
  36 + */
  37 + printf("Tuning PHY @ %d\n", phy);
  38 +
  39 + /* sets address 0x104 or reg 260 for writing */
  40 + miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xb, 0x8104);
  41 + /* Sets RXC/TXC to +0.96ns and TX_CTL/RX_CTL to -0.84ns */
  42 + miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xc, 0xf0f0);
  43 + /* sets address 0x105 or reg 261 for writing */
  44 + miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xb, 0x8105);
  45 + /* writes to address 0x105 , RXD[3..0] to -0. */
  46 + miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xc, 0x0000);
  47 + /* sets address 0x106 or reg 261 for writing */
  48 + miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xb, 0x8106);
  49 + /* writes to address 0x106 , TXD[3..0] to -0.84ns */
  50 + miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xc, 0x0000);
  51 + /* force re-negotiation */
  52 + miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0x0, 0x1340);
  53 +}
  54 +#endif
  55 +
  56 +int board_eth_init(bd_t *bis)
  57 +{
  58 +#ifdef CONFIG_FMAN_ENET
  59 + struct fsl_pq_mdio_info dtsec_mdio_info;
  60 + unsigned int i;
  61 +
  62 + printf("Initializing Fman\n");
  63 +
  64 +
  65 + /* Register the real 1G MDIO bus */
  66 + dtsec_mdio_info.regs =
  67 + (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
  68 + dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
  69 +
  70 + fsl_pq_mdio_init(bis, &dtsec_mdio_info);
  71 +
  72 +
  73 + fm_info_set_phy_address(FIRST_PORT, FIRST_PORT_ADDR);
  74 + fm_info_set_mdio(FIRST_PORT,
  75 + miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
  76 + fm_info_set_phy_address(SECOND_PORT, SECOND_PORT_ADDR);
  77 + fm_info_set_mdio(SECOND_PORT,
  78 + miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
  79 +
  80 + /* Never disable DTSEC1 - it controls MDIO */
  81 + for (i = FM1_DTSEC2; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
  82 + if (!IS_VALID_PORT(i))
  83 + fm_disable_port(i);
  84 + }
  85 +
  86 +#ifdef CONFIG_PPC_P5040
  87 + for (i = FM2_DTSEC2; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) {
  88 + if (!IS_VALID_PORT(i))
  89 + fm_disable_port(i);
  90 + }
  91 +#endif
  92 +
  93 + cpu_eth_init(bis);
  94 +
  95 + cyrus_phy_tuning(FIRST_PORT_ADDR);
  96 + cyrus_phy_tuning(SECOND_PORT_ADDR);
  97 +#endif
  98 +
  99 + return pci_eth_init(bis);
  100 +}
board/varisys/cyrus/law.c
Diff comments   View file @ 87e2987
  1 +/*
  2 + * Author: Adrian Cox
  3 + * Based on corenet_ds law files.
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#include <common.h>
  9 +#include <asm/fsl_law.h>
  10 +#include <asm/mmu.h>
  11 +
  12 +struct law_entry law_table[] = {
  13 + SET_LAW(CONFIG_SYS_LBC0_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC),
  14 + SET_LAW(CONFIG_SYS_LBC1_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
  15 +#ifdef CONFIG_SYS_BMAN_MEM_PHYS
  16 + SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_BMAN),
  17 +#endif
  18 +#ifdef CONFIG_SYS_QMAN_MEM_PHYS
  19 + SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_2M, LAW_TRGT_IF_QMAN),
  20 +#endif
  21 +#ifdef CONFIG_SYS_DCSRBAR_PHYS
  22 + /* Limit DCSR to 32M to access NPC Trace Buffer */
  23 + SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
  24 +#endif
  25 +};
  26 +
  27 +int num_law_entries = ARRAY_SIZE(law_table);
board/varisys/cyrus/pbi.cfg
Diff comments   View file @ 87e2987
  1 +#
  2 +# Copyright 2012 Freescale Semiconductor, Inc.
  3 +#
  4 +# Refer docs/README.pblimage for more details about how-to configure
  5 +# and create PBL boot image
  6 +#
  7 +# SPDX-License-Identifier: GPL-2.0+
  8 +#
  9 +
  10 +#PBI commands
  11 +#Initialize CPC1 as 1MB SRAM
  12 +09010000 00200400
  13 +09138000 00000000
  14 +091380c0 00000100
  15 +09010100 00000000
  16 +09010104 fff0000b
  17 +09010f00 08000000
  18 +09010000 80000000
  19 +#Configure LAW for CPC1
  20 +09000d00 00000000
  21 +09000d04 fff00000
  22 +09000d08 81000013
  23 +09000010 00000000
  24 +09000014 ff000000
  25 +09000018 81000000
  26 +#Initialize eSPI controller, default configuration is slow for eSPI to
  27 +#load data, this configuration comes from u-boot eSPI driver.
  28 +09110000 80000403
  29 +09110020 2d170008
  30 +09110024 00100008
  31 +09110028 00100008
  32 +0911002c 00100008
  33 +#Flush PBL data
  34 +09138000 00000000
  35 +091380c0 00000000
board/varisys/cyrus/pci.c
Diff comments   View file @ 87e2987
  1 +/*
  2 + * Copyright 2007-2011 Freescale Semiconductor, Inc.
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#include <common.h>
  8 +#include <command.h>
  9 +#include <pci.h>
  10 +#include <asm/fsl_pci.h>
  11 +#include <libfdt.h>
  12 +#include <fdt_support.h>
  13 +#include <asm/fsl_serdes.h>
  14 +
  15 +void pci_init_board(void)
  16 +{
  17 + fsl_pcie_init_board(0);
  18 +}
  19 +
  20 +void pci_of_setup(void *blob, bd_t *bd)
  21 +{
  22 + FT_FSL_PCI_SETUP;
  23 +}
board/varisys/cyrus/rcw_p5020_v2.cfg
Diff comments   View file @ 87e2987
  1 +#
  2 +# Default RCW for Cyrus P5020
  3 +#
  4 +
  5 +#PBL preamble and RCW header
  6 +aa55aa55 010e0100
  7 +#64 bytes RCW data
  8 +0c540000 00000000 1e1e0000 00000000
  9 +44808c00 ff002000 68000000 45000000
  10 +00000000 00000000 00000000 0003000f
  11 +a0000000 00000000 00000000 00000000
board/varisys/cyrus/rcw_p5040.cfg
Diff comments   View file @ 87e2987
  1 +#
  2 +# Default RCW for Cyrus P5040
  3 +#
  4 +
  5 +#PBL preamble and RCW header
  6 +aa55aa55 010e0100
  7 +#64 bytes RCW data
  8 +90e00000 00000000 acac9800 00440000
  9 +44808c00 ff29a000 68000000 61000000
  10 +00000000 00000000 00000000 0003000f
  11 +a0000000 00000000 00000000 00000000
board/varisys/cyrus/tlb.c
Diff comments   View file @ 87e2987
  1 +/*
  2 + * Author: Adrian Cox
  3 + * Based on corenet_ds tlb code
  4 + *
  5 + * SPDX-License-Identifier: GPL-2.0+
  6 + */
  7 +
  8 +#include <common.h>
  9 +#include <asm/mmu.h>
  10 +
  11 +struct fsl_e_tlb_entry tlb_table[] = {
  12 + /* TLB 0 - for temp stack in cache */
  13 + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
  14 + CONFIG_SYS_INIT_RAM_ADDR_PHYS,
  15 + MAS3_SW|MAS3_SR, 0,
  16 + 0, 0, BOOKE_PAGESZ_4K, 0),
  17 + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  18 + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
  19 + MAS3_SW|MAS3_SR, 0,
  20 + 0, 0, BOOKE_PAGESZ_4K, 0),
  21 + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  22 + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
  23 + MAS3_SW|MAS3_SR, 0,
  24 + 0, 0, BOOKE_PAGESZ_4K, 0),
  25 + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  26 + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
  27 + MAS3_SW|MAS3_SR, 0,
  28 + 0, 0, BOOKE_PAGESZ_4K, 0),
  29 +
  30 + /* TLB 1 */
  31 + /* *I*** - Covers boot page */
  32 +#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
  33 + /*
  34 + * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
  35 + * SRAM is at 0xfff00000, it covered the 0xfffff000.
  36 + */
  37 + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
  38 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  39 + 0, 0, BOOKE_PAGESZ_1M, 1),
  40 +#else
  41 + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
  42 + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  43 + 0, 0, BOOKE_PAGESZ_4K, 1),
  44 +#endif
  45 +
  46 + /* *I*G* - CCSRBAR */
  47 + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
  48 + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  49 + 0, 1, BOOKE_PAGESZ_16M, 1),
  50 +
  51 + /* Local Bus */
  52 + SET_TLB_ENTRY(1, CONFIG_SYS_LBC0_BASE, CONFIG_SYS_LBC0_BASE_PHYS,
  53 + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  54 + 0, 2, BOOKE_PAGESZ_64K, 1),
  55 + SET_TLB_ENTRY(1, CONFIG_SYS_LBC1_BASE, CONFIG_SYS_LBC1_BASE_PHYS,
  56 + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  57 + 0, 3, BOOKE_PAGESZ_4K, 1),
  58 +
  59 + /* *I*G* - PCI */
  60 + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
  61 + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  62 + 0, 4, BOOKE_PAGESZ_1G, 1),
  63 +
  64 + /* *I*G* - PCI */
  65 + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000,
  66 + CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
  67 + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  68 + 0, 5, BOOKE_PAGESZ_256M, 1),
  69 +
  70 + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000,
  71 + CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
  72 + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  73 + 0, 6, BOOKE_PAGESZ_256M, 1),
  74 +
  75 + /* *I*G* - PCI I/O */
  76 + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
  77 + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  78 + 0, 7, BOOKE_PAGESZ_256K, 1),
  79 +
  80 + /* Bman/Qman */
  81 +#ifdef CONFIG_SYS_BMAN_MEM_PHYS
  82 + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
  83 + MAS3_SW|MAS3_SR, 0,
  84 + 0, 9, BOOKE_PAGESZ_1M, 1),
  85 + SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000,
  86 + CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000,
  87 + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  88 + 0, 10, BOOKE_PAGESZ_1M, 1),
  89 +#endif
  90 +#ifdef CONFIG_SYS_QMAN_MEM_PHYS
  91 + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
  92 + MAS3_SW|MAS3_SR, 0,
  93 + 0, 11, BOOKE_PAGESZ_1M, 1),
  94 + SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000,
  95 + CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000,
  96 + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  97 + 0, 12, BOOKE_PAGESZ_1M, 1),
  98 +#endif
  99 +#ifdef CONFIG_SYS_DCSRBAR_PHYS
  100 + SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
  101 + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  102 + 0, 13, BOOKE_PAGESZ_4M, 1),
  103 +#endif
  104 +};
  105 +
  106 +int num_tlb_entries = ARRAY_SIZE(tlb_table);
configs/Cyrus_P5020_defconfig
Diff comments   View file @ 87e2987
  1 +CONFIG_PPC=y
  2 +CONFIG_MPC85xx=y
  3 +CONFIG_TARGET_CYRUS=y
  4 +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SYS_TEXT_BASE=0xFFF40000,PPC_P5020"
  5 +# CONFIG_CMD_IMLS is not set
  6 +# CONFIG_CMD_FLASH is not set
  7 +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
  8 +CONFIG_NETDEVICES=y
  9 +CONFIG_E1000=y
configs/Cyrus_P5040_defconfig
Diff comments   View file @ 87e2987
  1 +CONFIG_PPC=y
  2 +CONFIG_MPC85xx=y
  3 +CONFIG_TARGET_CYRUS=y
  4 +CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SYS_TEXT_BASE=0xFFF40000,PPC_P5040"
  5 +# CONFIG_CMD_IMLS is not set
  6 +# CONFIG_CMD_FLASH is not set
  7 +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
  8 +CONFIG_NETDEVICES=y
  9 +CONFIG_E1000=y
include/configs/cyrus.h
Diff comments   View file @ 87e2987
  1 +/*
  2 + * Based on corenet_ds.h
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#ifndef __CONFIG_H
  8 +#define __CONFIG_H
  9 +
  10 +#define CONFIG_DISPLAY_BOARDINFO
  11 +
  12 +#define CONFIG_CYRUS
  13 +
  14 +#define CONFIG_PHYS_64BIT
  15 +
  16 +#if !defined(CONFIG_PPC_P5020) && !defined(CONFIG_PPC_P5040)
  17 +#error Must call Cyrus CONFIG with a specific CPU enabled.
  18 +#endif
  19 +
  20 +
  21 +#define CONFIG_MMC
  22 +#define CONFIG_SDCARD
  23 +#define CONFIG_FSL_SATA_V2
  24 +#define CONFIG_PCIE3
  25 +#define CONFIG_PCIE4
  26 +#ifdef CONFIG_PPC_P5020
  27 +#define CONFIG_SYS_FSL_RAID_ENGINE
  28 +#define CONFIG_SYS_DPAA_RMAN
  29 +#endif
  30 +#define CONFIG_SYS_DPAA_PME
  31 +
  32 +/*
  33 + * Corenet DS style board configuration file
  34 + */
  35 +#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
  36 +#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  37 +#define CONFIG_SYS_FSL_PBL_PBI board/varisys/cyrus/pbi.cfg
  38 +#if defined(CONFIG_PPC_P5020)
  39 +#define CONFIG_SYS_CLK_FREQ 133000000
  40 +#define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5020_v2.cfg
  41 +#elif defined(CONFIG_PPC_P5040)
  42 +#define CONFIG_SYS_CLK_FREQ 100000000
  43 +#define CONFIG_SYS_FSL_PBL_RCW board/varisys/cyrus/rcw_p5040.cfg
  44 +#endif
  45 +
  46 +
  47 +/* High Level Configuration Options */
  48 +#define CONFIG_BOOKE
  49 +#define CONFIG_E500 /* BOOKE e500 family */
  50 +#define CONFIG_E500MC /* BOOKE e500mc family */
  51 +#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
  52 +#define CONFIG_MP /* support multiple processors */
  53 +
  54 +
  55 +#define CONFIG_SYS_MMC_MAX_DEVICE 1
  56 +
  57 +#ifndef CONFIG_SYS_TEXT_BASE
  58 +#define CONFIG_SYS_TEXT_BASE 0xeff40000
  59 +#endif
  60 +
  61 +#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
  62 +#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
  63 +#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
  64 +#define CONFIG_PCI /* Enable PCI/PCIE */
  65 +#define CONFIG_PCIE1 /* PCIE controler 1 */
  66 +#define CONFIG_PCIE2 /* PCIE controler 2 */
  67 +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  68 +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  69 +
  70 +#define CONFIG_FSL_LAW /* Use common FSL init code */
  71 +
  72 +#define CONFIG_ENV_OVERWRITE
  73 +
  74 +#define CONFIG_SYS_NO_FLASH
  75 +
  76 +#if defined(CONFIG_SDCARD)
  77 +#define CONFIG_SYS_EXTRA_ENV_RELOC
  78 +#define CONFIG_ENV_IS_IN_MMC
  79 +#define CONFIG_FSL_FIXED_MMC_LOCATION
  80 +#define CONFIG_SYS_MMC_ENV_DEV 0
  81 +#define CONFIG_ENV_SIZE 0x2000
  82 +#define CONFIG_ENV_OFFSET (512 * 1658)
  83 +#endif
  84 +
  85 +/*
  86 + * These can be toggled for performance analysis, otherwise use default.
  87 + */
  88 +#define CONFIG_SYS_CACHE_STASHING
  89 +#define CONFIG_BACKSIDE_L2_CACHE
  90 +#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
  91 +#define CONFIG_BTB /* toggle branch predition */
  92 +#define CONFIG_DDR_ECC
  93 +#ifdef CONFIG_DDR_ECC
  94 +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
  95 +#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
  96 +#endif
  97 +
  98 +#define CONFIG_ENABLE_36BIT_PHYS
  99 +
  100 +#ifdef CONFIG_PHYS_64BIT
  101 +#define CONFIG_ADDR_MAP
  102 +#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
  103 +#endif
  104 +
  105 +/* test POST memory test */
  106 +#undef CONFIG_POST
  107 +#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
  108 +#define CONFIG_SYS_MEMTEST_END 0x00400000
  109 +#define CONFIG_SYS_ALT_MEMTEST
  110 +#define CONFIG_PANIC_HANG /* do not reset board on panic */
  111 +
  112 +/*
  113 + * Config the L3 Cache as L3 SRAM
  114 + */
  115 +#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
  116 +#ifdef CONFIG_PHYS_64BIT
  117 +#define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE)
  118 +#else
  119 +#define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR
  120 +#endif
  121 +#define CONFIG_SYS_L3_SIZE (1024 << 10)
  122 +#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
  123 +
  124 +#ifdef CONFIG_PHYS_64BIT
  125 +#define CONFIG_SYS_DCSRBAR 0xf0000000
  126 +#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
  127 +#endif
  128 +
  129 +/*
  130 + * DDR Setup
  131 + */
  132 +#define CONFIG_VERY_BIG_RAM
  133 +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  134 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  135 +
  136 +#define CONFIG_DIMM_SLOTS_PER_CTLR 1
  137 +#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
  138 +
  139 +#define CONFIG_DDR_SPD
  140 +#define CONFIG_SYS_FSL_DDR3
  141 +
  142 +#define CONFIG_SYS_SPD_BUS_NUM 1
  143 +#define SPD_EEPROM_ADDRESS1 0x51
  144 +#define SPD_EEPROM_ADDRESS2 0x52
  145 +#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
  146 +
  147 +/*
  148 + * Local Bus Definitions
  149 + */
  150 +
  151 +#define CONFIG_SYS_LBC0_BASE 0xe0000000 /* Start of LBC Registers */
  152 +#ifdef CONFIG_PHYS_64BIT
  153 +#define CONFIG_SYS_LBC0_BASE_PHYS 0xfe0000000ull
  154 +#else
  155 +#define CONFIG_SYS_LBC0_BASE_PHYS CONFIG_SYS_LBC0_BASE
  156 +#endif
  157 +
  158 +#define CONFIG_SYS_LBC1_BASE 0xe1000000 /* Start of LBC Registers */
  159 +#ifdef CONFIG_PHYS_64BIT
  160 +#define CONFIG_SYS_LBC1_BASE_PHYS 0xfe1000000ull
  161 +#else
  162 +#define CONFIG_SYS_LBC1_BASE_PHYS CONFIG_SYS_LBC1_BASE
  163 +#endif
  164 +
  165 +/* Set the local bus clock 1/16 of platform clock */
  166 +#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_16 | LCRR_EADC_1)
  167 +
  168 +#define CONFIG_SYS_BR0_PRELIM \
  169 +(BR_PHYS_ADDR(CONFIG_SYS_LBC0_BASE_PHYS) | BR_PS_16 | BR_V)
  170 +#define CONFIG_SYS_BR1_PRELIM \
  171 +(BR_PHYS_ADDR(CONFIG_SYS_LBC1_BASE_PHYS) | BR_PS_16 | BR_V)
  172 +
  173 +#define CONFIG_SYS_OR0_PRELIM 0xfff00010
  174 +#define CONFIG_SYS_OR1_PRELIM 0xfff00010
  175 +
  176 +
  177 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  178 +
  179 +#if defined(CONFIG_RAMBOOT_PBL)
  180 +#define CONFIG_SYS_RAMBOOT
  181 +#endif
  182 +
  183 +#define CONFIG_BOARD_EARLY_INIT_F
  184 +#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
  185 +#define CONFIG_MISC_INIT_R
  186 +
  187 +#define CONFIG_HWCONFIG
  188 +
  189 +/* define to use L1 as initial stack */
  190 +#define CONFIG_L1_INIT_RAM
  191 +#define CONFIG_SYS_INIT_RAM_LOCK
  192 +#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
  193 +#ifdef CONFIG_PHYS_64BIT
  194 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
  195 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
  196 +/* The assembler doesn't like typecast */
  197 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
  198 + ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
  199 + CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
  200 +#else
  201 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */
  202 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
  203 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
  204 +#endif
  205 +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
  206 +
  207 +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  208 +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  209 +
  210 +#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
  211 +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
  212 +
  213 +/* Serial Port - controlled on board with jumper J8
  214 + * open - index 2
  215 + * shorted - index 1
  216 + */
  217 +#define CONFIG_CONS_INDEX 1
  218 +#define CONFIG_SYS_NS16550
  219 +#define CONFIG_SYS_NS16550_SERIAL
  220 +#define CONFIG_SYS_NS16550_REG_SIZE 1
  221 +#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
  222 +
  223 +#define CONFIG_SYS_BAUDRATE_TABLE \
  224 +{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  225 +
  226 +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
  227 +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
  228 +#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
  229 +#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
  230 +
  231 +/* Use the HUSH parser */
  232 +#define CONFIG_SYS_HUSH_PARSER
  233 +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  234 +
  235 +/* pass open firmware flat tree */
  236 +#define CONFIG_OF_LIBFDT
  237 +#define CONFIG_OF_BOARD_SETUP
  238 +
  239 +/* new uImage format support */
  240 +#define CONFIG_FIT
  241 +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
  242 +
  243 +/* I2C */
  244 +#define CONFIG_SYS_I2C
  245 +#define CONFIG_SYS_I2C_FSL
  246 +#define CONFIG_I2C_MULTI_BUS
  247 +#define CONFIG_I2C_CMD_TREE
  248 +#define CONFIG_SYS_FSL_I2C_SPEED 400000 /* I2C speed and slave address */
  249 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  250 +#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
  251 +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 /* I2C speed and slave address */
  252 +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  253 +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
  254 +#define CONFIG_SYS_FSL_I2C3_SPEED 400000 /* I2C speed and slave address */
  255 +#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
  256 +#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
  257 +#define CONFIG_SYS_FSL_I2C4_SPEED 400000 /* I2C speed and slave address */
  258 +#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
  259 +#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
  260 +
  261 +#define CONFIG_ID_EEPROM
  262 +#define CONFIG_SYS_I2C_EEPROM_NXID
  263 +#define CONFIG_SYS_EEPROM_BUS_NUM 0
  264 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  265 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  266 +
  267 +#define CONFIG_SYS_I2C_GENERIC_MAC
  268 +#define CONFIG_SYS_I2C_MAC1_BUS 3
  269 +#define CONFIG_SYS_I2C_MAC1_CHIP_ADDR 0x57
  270 +#define CONFIG_SYS_I2C_MAC1_DATA_ADDR 0xf2
  271 +#define CONFIG_SYS_I2C_MAC2_BUS 0
  272 +#define CONFIG_SYS_I2C_MAC2_CHIP_ADDR 0x50
  273 +#define CONFIG_SYS_I2C_MAC2_DATA_ADDR 0xfa
  274 +
  275 +#define CONFIG_CMD_DATE 1
  276 +#define CONFIG_RTC_MCP79411 1
  277 +#define CONFIG_SYS_RTC_BUS_NUM 3
  278 +#define CONFIG_SYS_I2C_RTC_ADDR 0x6f
  279 +
  280 +/*
  281 + * eSPI - Enhanced SPI
  282 + */
  283 +#define CONFIG_FSL_ESPI
  284 +
  285 +/*
  286 + * General PCI
  287 + * Memory space is mapped 1-1, but I/O space must start from 0.
  288 + */
  289 +
  290 +/* controller 1, direct to uli, tgtid 3, Base address 20000 */
  291 +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  292 +#ifdef CONFIG_PHYS_64BIT
  293 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
  294 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
  295 +#else
  296 +#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
  297 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
  298 +#endif
  299 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  300 +#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
  301 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  302 +#ifdef CONFIG_PHYS_64BIT
  303 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
  304 +#else
  305 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000
  306 +#endif
  307 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  308 +
  309 +/* controller 2, Slot 2, tgtid 2, Base address 201000 */
  310 +#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
  311 +#ifdef CONFIG_PHYS_64BIT
  312 +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
  313 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
  314 +#else
  315 +#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
  316 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
  317 +#endif
  318 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
  319 +#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
  320 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  321 +#ifdef CONFIG_PHYS_64BIT
  322 +#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
  323 +#else
  324 +#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000
  325 +#endif
  326 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
  327 +
  328 +/* controller 3, Slot 1, tgtid 1, Base address 202000 */
  329 +#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
  330 +#ifdef CONFIG_PHYS_64BIT
  331 +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
  332 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
  333 +#else
  334 +#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000
  335 +#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000
  336 +#endif
  337 +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
  338 +#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
  339 +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
  340 +#ifdef CONFIG_PHYS_64BIT
  341 +#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
  342 +#else
  343 +#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000
  344 +#endif
  345 +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
  346 +
  347 +/* controller 4, Base address 203000 */
  348 +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
  349 +#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
  350 +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
  351 +#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
  352 +#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
  353 +#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
  354 +
  355 +/* Qman/Bman */
  356 +#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
  357 +#define CONFIG_SYS_BMAN_NUM_PORTALS 10
  358 +#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
  359 +#ifdef CONFIG_PHYS_64BIT
  360 +#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
  361 +#else
  362 +#define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE
  363 +#endif
  364 +#define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000
  365 +#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
  366 +#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
  367 +#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
  368 +#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  369 +#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
  370 + CONFIG_SYS_BMAN_CENA_SIZE)
  371 +#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
  372 +#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
  373 +#define CONFIG_SYS_QMAN_NUM_PORTALS 10
  374 +#define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000
  375 +#ifdef CONFIG_PHYS_64BIT
  376 +#define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull
  377 +#else
  378 +#define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE
  379 +#endif
  380 +#define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000
  381 +#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
  382 +#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
  383 +#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
  384 +#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  385 +#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
  386 + CONFIG_SYS_QMAN_CENA_SIZE)
  387 +#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
  388 +#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
  389 +
  390 +#define CONFIG_SYS_DPAA_FMAN
  391 +/* Default address of microcode for the Linux Fman driver */
  392 +/*
  393 + * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
  394 + * about 825KB (1650 blocks), Env is stored after the image, and the env size is
  395 + * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
  396 + */
  397 +#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
  398 +#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
  399 +
  400 +#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
  401 +#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
  402 +
  403 +#ifdef CONFIG_SYS_DPAA_FMAN
  404 +#define CONFIG_FMAN_ENET
  405 +#define CONFIG_PHY_MICREL
  406 +#define CONFIG_PHY_MICREL_KSZ9021
  407 +#endif
  408 +
  409 +#ifdef CONFIG_PCI
  410 +#define CONFIG_PCI_INDIRECT_BRIDGE
  411 +#define CONFIG_PCI_PNP /* do pci plug-and-play */
  412 +#define CONFIG_NET_MULTI
  413 +
  414 +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  415 +#define CONFIG_DOS_PARTITION
  416 +#endif /* CONFIG_PCI */
  417 +
  418 +/* SATA */
  419 +#ifdef CONFIG_FSL_SATA_V2
  420 +#define CONFIG_LIBATA
  421 +#define CONFIG_FSL_SATA
  422 +
  423 +#define CONFIG_SYS_SATA_MAX_DEVICE 2
  424 +#define CONFIG_SATA1
  425 +#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
  426 +#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
  427 +#define CONFIG_SATA2
  428 +#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
  429 +#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
  430 +
  431 +#define CONFIG_LBA48
  432 +#define CONFIG_CMD_SATA
  433 +#define CONFIG_DOS_PARTITION
  434 +#define CONFIG_CMD_EXT2
  435 +#endif
  436 +
  437 +#ifdef CONFIG_FMAN_ENET
  438 +#define CONFIG_SYS_TBIPA_VALUE 8
  439 +#define CONFIG_MII /* MII PHY management */
  440 +#define CONFIG_ETHPRIME "FM1@DTSEC4"
  441 +#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
  442 +#endif
  443 +
  444 +/*
  445 + * Environment
  446 + */
  447 +#define CONFIG_LOADS_ECHO /* echo on for serial download */
  448 +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  449 +
  450 +/*
  451 + * Command line configuration.
  452 + */
  453 +#define CONFIG_CMD_DHCP
  454 +#define CONFIG_CMD_ERRATA
  455 +#define CONFIG_CMD_GREPENV
  456 +#define CONFIG_CMD_IRQ
  457 +#define CONFIG_CMD_I2C
  458 +#define CONFIG_CMD_MII
  459 +#define CONFIG_CMD_PING
  460 +#define CONFIG_CMD_REGINFO
  461 +
  462 +#ifdef CONFIG_PCI
  463 +#define CONFIG_CMD_PCI
  464 +#endif
  465 +
  466 +/*
  467 + * USB
  468 + */
  469 +#define CONFIG_HAS_FSL_DR_USB
  470 +#define CONFIG_HAS_FSL_MPH_USB
  471 +
  472 +#if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
  473 +#define CONFIG_CMD_USB
  474 +#define CONFIG_USB_STORAGE
  475 +#define CONFIG_USB_EHCI
  476 +#define CONFIG_USB_EHCI_FSL
  477 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  478 +#define CONFIG_CMD_EXT2
  479 +#define CONFIG_EHCI_IS_TDI
  480 +#define CONFIG_USB_KEYBOARD
  481 +#define CONFIG_SYS_USB_EVENT_POLL
  482 + /* _VIA_CONTROL_EP */
  483 +#define CONFIG_CONSOLE_MUX
  484 +#define CONFIG_SYS_CONSOLE_IS_IN_ENV
  485 +#endif
  486 +
  487 +#ifdef CONFIG_MMC
  488 +#define CONFIG_FSL_ESDHC
  489 +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  490 +#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
  491 +#define CONFIG_CMD_MMC
  492 +#define CONFIG_GENERIC_MMC
  493 +#define CONFIG_CMD_EXT2
  494 +#define CONFIG_CMD_FAT
  495 +#define CONFIG_DOS_PARTITION
  496 +#endif
  497 +
  498 +/*
  499 + * Miscellaneous configurable options
  500 + */
  501 +#define CONFIG_SYS_LONGHELP /* undef to save memory */
  502 +#define CONFIG_CMDLINE_EDITING /* Command-line editing */
  503 +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
  504 +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  505 +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  506 +#ifdef CONFIG_CMD_KGDB
  507 +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  508 +#else
  509 +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  510 +#endif
  511 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  512 +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  513 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  514 +
  515 +/*
  516 + * For booting Linux, the board info and command line data
  517 + * have to be in the first 64 MB of memory, since this is
  518 + * the maximum mapped by the Linux kernel during initialization.
  519 + */
  520 +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
  521 +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  522 +
  523 +#ifdef CONFIG_CMD_KGDB
  524 +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  525 +#endif
  526 +
  527 +/*
  528 + * Environment Configuration
  529 + */
  530 +#define CONFIG_ROOTPATH "/opt/nfsroot"
  531 +#define CONFIG_BOOTFILE "uImage"
  532 +#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
  533 +
  534 +/* default location for tftp and bootm */
  535 +#define CONFIG_LOADADDR 1000000
  536 +
  537 +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
  538 +
  539 +#define CONFIG_BAUDRATE 115200
  540 +
  541 +#define __USB_PHY_TYPE utmi
  542 +
  543 +#define CONFIG_EXTRA_ENV_SETTINGS \
  544 +"hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
  545 +"bank_intlv=cs0_cs1;" \
  546 +"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) ";"\
  547 +"usb2:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
  548 +"netdev=eth0\0" \
  549 +"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
  550 +"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
  551 +"consoledev=ttyS0\0" \
  552 +"ramdiskaddr=2000000\0" \
  553 +"fdtaddr=c00000\0" \
  554 +"bdev=sda3\0"
  555 +
  556 +#define CONFIG_HDBOOT \
  557 +"setenv bootargs root=/dev/$bdev rw " \
  558 +"console=$consoledev,$baudrate $othbootargs;" \
  559 +"tftp $loadaddr $bootfile;" \
  560 +"tftp $fdtaddr $fdtfile;" \
  561 +"bootm $loadaddr - $fdtaddr"
  562 +
  563 +#define CONFIG_NFSBOOTCOMMAND \
  564 +"setenv bootargs root=/dev/nfs rw " \
  565 +"nfsroot=$serverip:$rootpath " \
  566 +"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  567 +"console=$consoledev,$baudrate $othbootargs;" \
  568 +"tftp $loadaddr $bootfile;" \
  569 +"tftp $fdtaddr $fdtfile;" \
  570 +"bootm $loadaddr - $fdtaddr"
  571 +
  572 +#define CONFIG_RAMBOOTCOMMAND \
  573 +"setenv bootargs root=/dev/ram rw " \
  574 +"console=$consoledev,$baudrate $othbootargs;" \
  575 +"tftp $ramdiskaddr $ramdiskfile;" \
  576 +"tftp $loadaddr $bootfile;" \
  577 +"tftp $fdtaddr $fdtfile;" \
  578 +"bootm $loadaddr $ramdiskaddr $fdtaddr"
  579 +
  580 +#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
  581 +
  582 +#include <asm/fsl_secure_boot.h>
  583 +
  584 +#ifdef CONFIG_SECURE_BOOT
  585 +#endif
  586 +
  587 +#endif /* __CONFIG_H */