Commit 88d2b1abea95db33d4238dbaed0694b1a36565bb
Committed by
Joe Hershberger
Joe Hershberger
1 parent
d9a9174fa5
Exists in
smarc_8mq_lf_v2020.04
and in
11 other branches
doc: bindings: Add binding for register driven MDIO muxes
This binding documents two properties that describe the registers used to perform MUX selection. Signed-off-by: Alex Marginean <alexm.osslist@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Showing 1 changed file with 82 additions and 0 deletions Side-by-side Diff
doc/device-tree-bindings/net/mdio-mux-reg.txt
| 1 | +Device tree structures used by register based MDIO muxes is described here. | |
| 2 | +This binding is based on reg-mux.txt binding in Linux and is currently used by | |
| 3 | +mdio-mux-i2creg driver in U-Boot. | |
| 4 | + | |
| 5 | +Required properties: | |
| 6 | +#mux-control-cells = <1> indicates how many registers are used for mux | |
| 7 | + selection. mux-reg-mask property described below must | |
| 8 | + include this number of pairs. | |
| 9 | +mux-reg-masks = <reg mask> describes pairs of register offset and register mask. | |
| 10 | + Register bits enabled in mask are set to the selection | |
| 11 | + value defined in reg property of child MDIOs to control | |
| 12 | + selection. | |
| 13 | +Properties described in mdio-mux.txt also apply. | |
| 14 | + | |
| 15 | +Example structure, used on Freescale LS1028A QDS board: | |
| 16 | + | |
| 17 | +&i2c0 { | |
| 18 | + status = "okay"; | |
| 19 | + u-boot,dm-pre-reloc; | |
| 20 | + | |
| 21 | + fpga@66 { | |
| 22 | + #address-cells = <1>; | |
| 23 | + #size-cells = <0>; | |
| 24 | + compatible = "simple-mfd"; | |
| 25 | + reg = <0x66>; | |
| 26 | + | |
| 27 | + mux-mdio@54 { | |
| 28 | + #address-cells = <1>; | |
| 29 | + #size-cells = <0>; | |
| 30 | + compatible = "mdio-mux-i2creg"; | |
| 31 | + reg = <0x54>; | |
| 32 | + #mux-control-cells = <1>; | |
| 33 | + mux-reg-masks = <0x54 0xf0>; | |
| 34 | + mdio-parent-bus = <&mdio0>; | |
| 35 | + | |
| 36 | + /* on-board MDIO with a single RGMII PHY */ | |
| 37 | + mdio@00 { | |
| 38 | + #address-cells = <1>; | |
| 39 | + #size-cells = <0>; | |
| 40 | + reg = <0x00>; | |
| 41 | + | |
| 42 | + /* on-board 1G RGMII PHY */ | |
| 43 | + qds_phy0: phy@5 { | |
| 44 | + reg = <5>; | |
| 45 | + }; | |
| 46 | + }; | |
| 47 | + /* card slot 1 */ | |
| 48 | + mdio@40 { | |
| 49 | + #address-cells = <1>; | |
| 50 | + #size-cells = <0>; | |
| 51 | + reg = <0x40>; | |
| 52 | + /* VSC8234 1G SGMII card */ | |
| 53 | + sgmii_port0: phy@1c { | |
| 54 | + reg = <0x1c>; | |
| 55 | + }; | |
| 56 | + }; | |
| 57 | + /* card slot 2 */ | |
| 58 | + mdio@50 { | |
| 59 | + #address-cells = <1>; | |
| 60 | + #size-cells = <0>; | |
| 61 | + reg = <0x50>; | |
| 62 | + }; | |
| 63 | + /* card slot 3 */ | |
| 64 | + mdio@60 { | |
| 65 | + #address-cells = <1>; | |
| 66 | + #size-cells = <0>; | |
| 67 | + reg = <0x60>; | |
| 68 | + }; | |
| 69 | + /* card slot 4 */ | |
| 70 | + mdio@70 { | |
| 71 | + #address-cells = <1>; | |
| 72 | + #size-cells = <0>; | |
| 73 | + reg = <0x70>; | |
| 74 | + }; | |
| 75 | + }; | |
| 76 | + }; | |
| 77 | +}; | |
| 78 | + | |
| 79 | +/* Parent MDIO, defined in SoC .dtsi file, just enabled here */ | |
| 80 | +&mdio0 { | |
| 81 | + status = "okay"; | |
| 82 | +}; |