Commit 88d577ed2b12e436c2e11d7663520b76de2898e1
1 parent
3e50573a70
Exists in
smarc_8mm-imx_v2019.04_4.19.35_1.1.0
and in
1 other branch
MLK-22080 imx8mn_evk: add SPL and u-boot build for nominal mode
Add imx8mn_ddr4_evk_nom_defconfig to generate SPL and u-boot to force SOC to nominal mode. So the VDD_SOC will be 0.85V and ARM will be fixed to 0.85V with DVFS disabled in kernel. Signed-off-by: Ye Li <ye.li@nxp.com> Acked-by: Anson Huang <Anson.Huang@nxp.com> (cherry picked from commit 0dca81742f51141ce0fb2117cbc1e99b84945009)
Showing 4 changed files with 129 additions and 0 deletions Side-by-side Diff
arch/arm/mach-imx/imx8m/soc.c
... | ... | @@ -711,6 +711,39 @@ |
711 | 711 | disable_cpu_nodes(blob, 2); |
712 | 712 | else if (is_imx8mms() || is_imx8mmsl()) |
713 | 713 | disable_cpu_nodes(blob, 3); |
714 | + | |
715 | +#elif defined(CONFIG_IMX8MN) | |
716 | + | |
717 | +#ifdef CONFIG_IMX8MN_FORCE_NOM_SOC | |
718 | + /* Disable the DVFS by removing 1.4Ghz and 1.5Ghz operating-points*/ | |
719 | + int rc; | |
720 | + int nodeoff; | |
721 | + static const char * const nodes_path = "/cpus/cpu@0"; | |
722 | + u32 val[] = {1200000, 850000}; | |
723 | + | |
724 | + nodeoff = fdt_path_offset(blob, nodes_path); | |
725 | + if (nodeoff < 0) { | |
726 | + printf("Unable to find node %s, err=%s\n", | |
727 | + nodes_path, fdt_strerror(nodeoff)); | |
728 | + return nodeoff; | |
729 | + } | |
730 | + | |
731 | + printf("Found %s node\n", nodes_path); | |
732 | + | |
733 | + val[0] = cpu_to_fdt32(val[0]); | |
734 | + val[1] = cpu_to_fdt32(val[1]); | |
735 | + rc = fdt_setprop(blob, nodeoff, "operating-points", &val, 2 * sizeof(u32)); | |
736 | + if (rc) { | |
737 | + printf("Unable to update operating-points for node %s, err=%s\n", | |
738 | + nodes_path, fdt_strerror(rc)); | |
739 | + return rc; | |
740 | + } | |
741 | + | |
742 | + printf("Update %s:%s\n", nodes_path, | |
743 | + "operating-points"); | |
744 | + | |
745 | +#endif /* CONFIG_IMX8MN_FORCE_NOM_SOC */ | |
746 | + | |
714 | 747 | #endif |
715 | 748 | |
716 | 749 | return ft_add_optee_node(blob, bd); |
board/freescale/imx8mn_evk/Kconfig
board/freescale/imx8mn_evk/spl.c
... | ... | @@ -162,8 +162,16 @@ |
162 | 162 | /* unlock the PMIC regs */ |
163 | 163 | pmic_reg_write(p, BD71837_REGLOCK, 0x1); |
164 | 164 | |
165 | +#ifdef CONFIG_IMX8MN_FORCE_NOM_SOC | |
166 | + /* increase VDD_ARM to typical value 0.85v for 1.2Ghz */ | |
167 | + pmic_reg_write(p, BD71837_BUCK2_VOLT_RUN, 0xf); | |
168 | + | |
169 | + /* increase VDD_SOC/VDD_DRAM to typical value 0.85v for nominal mode */ | |
170 | + pmic_reg_write(p, BD71837_BUCK1_VOLT_RUN, 0xf); | |
171 | +#else | |
165 | 172 | /* increase VDD_SOC/VDD_DRAM to typical value 0.95v for 3Ghz DDRs */ |
166 | 173 | pmic_reg_write(p, BD71837_BUCK1_VOLT_RUN, 0x19); |
174 | +#endif | |
167 | 175 | |
168 | 176 | #ifdef CONFIG_IMX8M_DDR4 |
169 | 177 | /* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */ |
configs/imx8mn_ddr4_evk_nom_defconfig
1 | +CONFIG_ARM=y | |
2 | +CONFIG_ARCH_IMX8M=y | |
3 | +CONFIG_SYS_TEXT_BASE=0x40200000 | |
4 | +CONFIG_SYS_MALLOC_F_LEN=0x2000 | |
5 | +CONFIG_USB_TCPC=y | |
6 | +CONFIG_TARGET_IMX8MN_EVK=y | |
7 | +CONFIG_ARCH_MISC_INIT=y | |
8 | +CONFIG_SPL=y | |
9 | +CONFIG_FIT=y | |
10 | +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 | |
11 | +CONFIG_SPL_LOAD_FIT=y | |
12 | +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" | |
13 | +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage.cfg,SPL_TEXT_BASE=0x912000" | |
14 | +CONFIG_SPL_BOARD_INIT=y | |
15 | +CONFIG_SPL_SERIAL_SUPPORT=y | |
16 | +CONFIG_NR_DRAM_BANKS=1 | |
17 | +CONFIG_HUSH_PARSER=y | |
18 | +CONFIG_OF_LIBFDT=y | |
19 | +CONFIG_FS_FAT=y | |
20 | +CONFIG_CMD_EXT2=y | |
21 | +CONFIG_CMD_EXT4=y | |
22 | +CONFIG_CMD_EXT4_WRITE=y | |
23 | +CONFIG_CMD_FAT=y | |
24 | +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8mn-ddr4-evk" | |
25 | +CONFIG_DEFAULT_FDT_FILE="fsl-imx8mn-ddr4-evk.dtb" | |
26 | +CONFIG_ENV_IS_IN_MMC=y | |
27 | +CONFIG_CMD_SF=y | |
28 | +CONFIG_CMD_I2C=y | |
29 | +CONFIG_CMD_GPIO=y | |
30 | +CONFIG_CMD_CACHE=y | |
31 | +CONFIG_CMD_REGULATOR=y | |
32 | +CONFIG_CMD_MEMTEST=y | |
33 | +CONFIG_OF_CONTROL=y | |
34 | +CONFIG_FASTBOOT=y | |
35 | +CONFIG_USB_FUNCTION_FASTBOOT=y | |
36 | +CONFIG_CMD_FASTBOOT=y | |
37 | +CONFIG_ANDROID_BOOT_IMAGE=y | |
38 | +CONFIG_FASTBOOT_UUU_SUPPORT=y | |
39 | +CONFIG_FASTBOOT_BUF_ADDR=0x42800000 | |
40 | +CONFIG_FASTBOOT_BUF_SIZE=0x40000000 | |
41 | +CONFIG_FASTBOOT_FLASH=y | |
42 | + | |
43 | +CONFIG_DM_GPIO=y | |
44 | +CONFIG_DM_I2C=y | |
45 | +CONFIG_SYS_I2C_MXC=y | |
46 | +CONFIG_DM_MMC=y | |
47 | +# CONFIG_DM_PMIC=y | |
48 | +CONFIG_EFI_PARTITION=y | |
49 | +CONFIG_DM_SPI_FLASH=y | |
50 | +CONFIG_DM_SPI=y | |
51 | +CONFIG_FSL_FSPI=y | |
52 | +CONFIG_SPI=y | |
53 | +CONFIG_SPI_FLASH=y | |
54 | +CONFIG_SPI_FLASH_BAR=y | |
55 | +CONFIG_SPI_FLASH_STMICRO=y | |
56 | +CONFIG_SF_DEFAULT_BUS=0 | |
57 | +CONFIG_SF_DEFAULT_CS=0 | |
58 | +CONFIG_SF_DEFAULT_SPEED=40000000 | |
59 | +CONFIG_SF_DEFAULT_MODE=0 | |
60 | + | |
61 | +CONFIG_DM_ETH=y | |
62 | +CONFIG_PINCTRL=y | |
63 | +CONFIG_PINCTRL_IMX8M=y | |
64 | +CONFIG_DM_REGULATOR=y | |
65 | +CONFIG_DM_REGULATOR_FIXED=y | |
66 | +CONFIG_DM_REGULATOR_GPIO=y | |
67 | +CONFIG_NXP_TMU=y | |
68 | +CONFIG_DM_THERMAL=y | |
69 | +CONFIG_USB=y | |
70 | +CONFIG_USB_GADGET=y | |
71 | +CONFIG_DM_USB=y | |
72 | +CONFIG_USB_EHCI_HCD=y | |
73 | + | |
74 | +CONFIG_USB_GADGET_MANUFACTURER="FSL" | |
75 | +CONFIG_USB_GADGET_VENDOR_NUM=0x0525 | |
76 | +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5 | |
77 | + | |
78 | +CONFIG_VIDEO=y | |
79 | +CONFIG_IMX_SEC_MIPI_DSI=y | |
80 | + | |
81 | +CONFIG_SPL_IMX_ROMAPI_SUPPORT=y | |
82 | +CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 | |
83 | + | |
84 | +CONFIG_IMX8MN_FORCE_NOM_SOC=y |