add block write function to spartan3 slave serial load

Using seperate function calls for each bit-bang of slave serial load can be painfully slow. This patch adds the possibility to supply a block write function that loads the complete block of data in one call (like it can already be done with Altera FPGAs). On an MCF5373L (240 MHz) loading an XC3S4000 this reduces the load time from around 15 seconds to around 3 seconds Signed-off-by: Wolfgang Wegner <w.wegner at astro-kom.de>

add block write function to spartan3 slave serial load
Using seperate function calls for each bit-bang of slave serial load can be painfully slow. This patch adds the possibility to supply a block write function that loads the complete block of data in one call (like it can already be done with Altera FPGAs). On an MCF5373L (240 MHz) loading an XC3S4000 this reduces the load time from around 15 seconds to around 3 seconds Signed-off-by: Wolfgang Wegner <w.wegner at astro-kom.de>
Wolfgang Wegner · TsiChung Liew
1 parent 9d79e5758c
Showing 3 changed files with 31 additions and 25 deletions Side-by-side Diff
drivers/fpga/spartan3.c
include/spartan3.h
include/xilinx.h
@@ -385,34 +385,38 @@
 		} while ((*fn->init) (cookie));
  
 		/* Load the data */
-		while (bytecount < bsize) {
+		if(*fn->bwr)
+			(*fn->bwr) (data, bsize, TRUE, cookie);
+		else {
+			while (bytecount < bsize) {
  
-			/* Xilinx detects an error if INIT goes low (active)
-			   while DONE is low (inactive) */
-			if ((*fn->done) (cookie) == 0 && (*fn->init) (cookie)) {
-				puts ("** CRC error during FPGA load.\n");
-				return (FPGA_FAIL);
-			}
-			val = data [bytecount ++];
-			i = 8;
-			do {
-				/* Deassert the clock */
-				(*fn->clk) (FALSE, TRUE, cookie);
-				CONFIG_FPGA_DELAY ();
-				/* Write data */
-				(*fn->wr) ((val & 0x80), TRUE, cookie);
-				CONFIG_FPGA_DELAY ();
-				/* Assert the clock */
-				(*fn->clk) (TRUE, TRUE, cookie);
-				CONFIG_FPGA_DELAY ();
-				val <<= 1;
-				i --;
-			} while (i > 0);
+				/* Xilinx detects an error if INIT goes low (active)
+				   while DONE is low (inactive) */
+				if ((*fn->done) (cookie) == 0 && (*fn->init) (cookie)) {
+					puts ("** CRC error during FPGA load.\n");
+					return (FPGA_FAIL);
+				}
+				val = data [bytecount ++];
+				i = 8;
+				do {
+					/* Deassert the clock */
+					(*fn->clk) (FALSE, TRUE, cookie);
+					CONFIG_FPGA_DELAY ();
+					/* Write data */
+					(*fn->wr) ((val & 0x80), TRUE, cookie);
+					CONFIG_FPGA_DELAY ();
+					/* Assert the clock */
+					(*fn->clk) (TRUE, TRUE, cookie);
+					CONFIG_FPGA_DELAY ();
+					val <<= 1;
+					i --;
+				} while (i > 0);
  
 #ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
-			if (bytecount % (bsize / 40) == 0)
-				putc ('.');		/* let them know we are alive */
+				if (bytecount % (bsize / 40) == 0)
+					putc ('.');		/* let them know we are alive */
 #endif
+			}
 		}
  
 		CONFIG_FPGA_DELAY ();
@@ -57,6 +57,7 @@
 	Xilinx_done_fn	done;
 	Xilinx_wr_fn	wr;
 	Xilinx_post_fn	post;
+	Xilinx_bwr_fn	bwr; /* block write function */
 } Xilinx_Spartan3_Slave_Serial_fns;
  
 /* Device Image Sizes
@@ -100,6 +100,7 @@
 typedef int (*Xilinx_abort_fn)( int cookie );
 typedef int (*Xilinx_pre_fn)( int cookie );
 typedef int (*Xilinx_post_fn)( int cookie );
+typedef int (*Xilinx_bwr_fn)( void *buf, size_t len, int flush, int cookie );
  
 #endif  /* _XILINX_H_ */
...	...	@@ -385,34 +385,38 @@
385	385	} while ((*fn->init) (cookie));
386	386
387	387	/* Load the data */
388		- while (bytecount < bsize) {
	388	+ if(*fn->bwr)
	389	+ (*fn->bwr) (data, bsize, TRUE, cookie);
	390	+ else {
	391	+ while (bytecount < bsize) {
389	392
390		- /* Xilinx detects an error if INIT goes low (active)
391		- while DONE is low (inactive) */
392		- if ((fn->done) (cookie) == 0 && (fn->init) (cookie)) {
393		- puts ("** CRC error during FPGA load.\n");
394		- return (FPGA_FAIL);
395		- }
396		- val = data [bytecount ++];
397		- i = 8;
398		- do {
399		- /* Deassert the clock */
400		- (*fn->clk) (FALSE, TRUE, cookie);
401		- CONFIG_FPGA_DELAY ();
402		- /* Write data */
403		- (*fn->wr) ((val & 0x80), TRUE, cookie);
404		- CONFIG_FPGA_DELAY ();
405		- /* Assert the clock */
406		- (*fn->clk) (TRUE, TRUE, cookie);
407		- CONFIG_FPGA_DELAY ();
408		- val <<= 1;
409		- i --;
410		- } while (i > 0);
	393	+ /* Xilinx detects an error if INIT goes low (active)
	394	+ while DONE is low (inactive) */
	395	+ if ((fn->done) (cookie) == 0 && (fn->init) (cookie)) {
	396	+ puts ("** CRC error during FPGA load.\n");
	397	+ return (FPGA_FAIL);
	398	+ }
	399	+ val = data [bytecount ++];
	400	+ i = 8;
	401	+ do {
	402	+ /* Deassert the clock */
	403	+ (*fn->clk) (FALSE, TRUE, cookie);
	404	+ CONFIG_FPGA_DELAY ();
	405	+ /* Write data */
	406	+ (*fn->wr) ((val & 0x80), TRUE, cookie);
	407	+ CONFIG_FPGA_DELAY ();
	408	+ /* Assert the clock */
	409	+ (*fn->clk) (TRUE, TRUE, cookie);
	410	+ CONFIG_FPGA_DELAY ();
	411	+ val <<= 1;
	412	+ i --;
	413	+ } while (i > 0);
411	414
412	415	#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
413		- if (bytecount % (bsize / 40) == 0)
414		- putc ('.'); /* let them know we are alive */
	416	+ if (bytecount % (bsize / 40) == 0)
	417	+ putc ('.'); /* let them know we are alive */
415	418	#endif
	419	+ }
416	420	}
417	421
418	422	CONFIG_FPGA_DELAY ();
...	...	@@ -57,6 +57,7 @@
57	57	Xilinx_done_fn done;
58	58	Xilinx_wr_fn wr;
59	59	Xilinx_post_fn post;
	60	+ Xilinx_bwr_fn bwr; /* block write function */
60	61	} Xilinx_Spartan3_Slave_Serial_fns;
61	62
62	63	/* Device Image Sizes
...	...	@@ -100,6 +100,7 @@
100	100	typedef int (*Xilinx_abort_fn)( int cookie );
101	101	typedef int (*Xilinx_pre_fn)( int cookie );
102	102	typedef int (*Xilinx_post_fn)( int cookie );
	103	+typedef int (Xilinx_bwr_fn)( void buf, size_t len, int flush, int cookie );
103	104
104	105	#endif /* _XILINX_H_ */