Eric Lee / smarc-uboot

Download as
Browse Code ยป

Commit 8946034a311f80ca913f99f5c5691983d8b619c6

Authored by Simon Glass
1 parent 184b1b7175
Exists in v2017.01-smarct4x and in 40 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

tegra: dts: Bring in GPIO bindings from linux 

These files are taken from Linux 3.14.

Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Stephen Warren <swarren@nvidia.com>

Showing 8 changed files with 155 additions and 28 deletions Side-by-side Diff

arch/arm/dts/tegra114.dtsi
Diff comments   View file @ 8946034
  1 +#include <dt-bindings/gpio/tegra-gpio.h>
  2 +#include <dt-bindings/interrupt-controller/arm-gic.h>
  3 +
1 4 #include "skeleton.dtsi"
2 5  
3 6 / {
4 7  
... ... @@ -46,17 +49,17 @@
46 49 0 143 0x04>;
47 50 };
48 51  
49   - gpio: gpio {
  52 + gpio: gpio@6000d000 {
50 53 compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
51 54 reg = <0x6000d000 0x1000>;
52   - interrupts = <0 32 0x04
53   - 0 33 0x04
54   - 0 34 0x04
55   - 0 35 0x04
56   - 0 55 0x04
57   - 0 87 0x04
58   - 0 89 0x04
59   - 0 125 0x04>;
  55 + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
  56 + <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
  57 + <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
  58 + <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
  59 + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
  60 + <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
  61 + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
  62 + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
60 63 #gpio-cells = <2>;
61 64 gpio-controller;
62 65 #interrupt-cells = <2>;
arch/arm/dts/tegra124.dtsi
Diff comments   View file @ 8946034
  1 +#include <dt-bindings/gpio/tegra-gpio.h>
  2 +#include <dt-bindings/interrupt-controller/arm-gic.h>
  3 +
1 4 #include "skeleton.dtsi"
2 5  
3 6 / {
... ... @@ -49,14 +52,14 @@
49 52 gpio: gpio@6000d000 {
50 53 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
51 54 reg = <0x6000d000 0x1000>;
52   - interrupts = <0 32 0x04
53   - 0 33 0x04
54   - 0 34 0x04
55   - 0 35 0x04
56   - 0 55 0x04
57   - 0 87 0x04
58   - 0 89 0x04
59   - 0 125 0x04>;
  55 + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
  56 + <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
  57 + <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
  58 + <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
  59 + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
  60 + <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
  61 + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
  62 + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
60 63 #gpio-cells = <2>;
61 64 gpio-controller;
62 65 #interrupt-cells = <2>;
arch/arm/dts/tegra20.dtsi
Diff comments   View file @ 8946034
  1 +#include <dt-bindings/gpio/tegra-gpio.h>
  2 +#include <dt-bindings/interrupt-controller/arm-gic.h>
  3 +
1 4 #include "skeleton.dtsi"
2 5  
3 6 / {
4 7  
... ... @@ -139,10 +142,18 @@
139 142  
140 143 gpio: gpio@6000d000 {
141 144 compatible = "nvidia,tegra20-gpio";
142   - reg = < 0x6000d000 0x1000 >;
143   - interrupts = < 64 65 66 67 87 119 121 >;
  145 + reg = <0x6000d000 0x1000>;
  146 + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
  147 + <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
  148 + <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
  149 + <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
  150 + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
  151 + <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
  152 + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
144 153 #gpio-cells = <2>;
145 154 gpio-controller;
  155 + #interrupt-cells = <2>;
  156 + interrupt-controller;
146 157 };
147 158  
148 159 pinmux: pinmux@70000000 {
arch/arm/dts/tegra30.dtsi
Diff comments   View file @ 8946034
  1 +#include <dt-bindings/gpio/tegra-gpio.h>
  2 +#include <dt-bindings/interrupt-controller/arm-gic.h>
  3 +
1 4 #include "skeleton.dtsi"
2 5  
3 6 / {
4 7  
... ... @@ -47,17 +50,17 @@
47 50 clocks = <&tegra_car 34>;
48 51 };
49 52  
50   - gpio: gpio {
  53 + gpio: gpio@6000d000 {
51 54 compatible = "nvidia,tegra30-gpio";
52 55 reg = <0x6000d000 0x1000>;
53   - interrupts = <0 32 0x04
54   - 0 33 0x04
55   - 0 34 0x04
56   - 0 35 0x04
57   - 0 55 0x04
58   - 0 87 0x04
59   - 0 89 0x04
60   - 0 125 0x04>;
  56 + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
  57 + <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
  58 + <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
  59 + <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
  60 + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
  61 + <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
  62 + <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
  63 + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
61 64 #gpio-cells = <2>;
62 65 gpio-controller;
63 66 #interrupt-cells = <2>;
include/dt-bindings/gpio/gpio.h
Diff comments   View file @ 8946034
  1 +/*
  2 + * This header provides constants for most GPIO bindings.
  3 + *
  4 + * Most GPIO bindings include a flags cell as part of the GPIO specifier.
  5 + * In most cases, the format of the flags cell uses the standard values
  6 + * defined in this header.
  7 + */
  8 +
  9 +#ifndef _DT_BINDINGS_GPIO_GPIO_H
  10 +#define _DT_BINDINGS_GPIO_GPIO_H
  11 +
  12 +#define GPIO_ACTIVE_HIGH 0
  13 +#define GPIO_ACTIVE_LOW 1
  14 +
  15 +#endif
include/dt-bindings/gpio/tegra-gpio.h
Diff comments   View file @ 8946034
  1 +/*
  2 + * This header provides constants for binding nvidia,tegra*-gpio.
  3 + *
  4 + * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below
  5 + * provide names for this.
  6 + *
  7 + * The second cell contains standard flag values specified in gpio.h.
  8 + */
  9 +
  10 +#ifndef _DT_BINDINGS_GPIO_TEGRA_GPIO_H
  11 +#define _DT_BINDINGS_GPIO_TEGRA_GPIO_H
  12 +
  13 +#include <dt-bindings/gpio/gpio.h>
  14 +
  15 +#define TEGRA_GPIO_BANK_ID_A 0
  16 +#define TEGRA_GPIO_BANK_ID_B 1
  17 +#define TEGRA_GPIO_BANK_ID_C 2
  18 +#define TEGRA_GPIO_BANK_ID_D 3
  19 +#define TEGRA_GPIO_BANK_ID_E 4
  20 +#define TEGRA_GPIO_BANK_ID_F 5
  21 +#define TEGRA_GPIO_BANK_ID_G 6
  22 +#define TEGRA_GPIO_BANK_ID_H 7
  23 +#define TEGRA_GPIO_BANK_ID_I 8
  24 +#define TEGRA_GPIO_BANK_ID_J 9
  25 +#define TEGRA_GPIO_BANK_ID_K 10
  26 +#define TEGRA_GPIO_BANK_ID_L 11
  27 +#define TEGRA_GPIO_BANK_ID_M 12
  28 +#define TEGRA_GPIO_BANK_ID_N 13
  29 +#define TEGRA_GPIO_BANK_ID_O 14
  30 +#define TEGRA_GPIO_BANK_ID_P 15
  31 +#define TEGRA_GPIO_BANK_ID_Q 16
  32 +#define TEGRA_GPIO_BANK_ID_R 17
  33 +#define TEGRA_GPIO_BANK_ID_S 18
  34 +#define TEGRA_GPIO_BANK_ID_T 19
  35 +#define TEGRA_GPIO_BANK_ID_U 20
  36 +#define TEGRA_GPIO_BANK_ID_V 21
  37 +#define TEGRA_GPIO_BANK_ID_W 22
  38 +#define TEGRA_GPIO_BANK_ID_X 23
  39 +#define TEGRA_GPIO_BANK_ID_Y 24
  40 +#define TEGRA_GPIO_BANK_ID_Z 25
  41 +#define TEGRA_GPIO_BANK_ID_AA 26
  42 +#define TEGRA_GPIO_BANK_ID_BB 27
  43 +#define TEGRA_GPIO_BANK_ID_CC 28
  44 +#define TEGRA_GPIO_BANK_ID_DD 29
  45 +#define TEGRA_GPIO_BANK_ID_EE 30
  46 +#define TEGRA_GPIO_BANK_ID_FF 31
  47 +
  48 +#define TEGRA_GPIO(bank, offset) \
  49 + ((TEGRA_GPIO_BANK_ID_##bank * 8) + offset)
  50 +
  51 +#endif
include/dt-bindings/interrupt-controller/arm-gic.h
Diff comments   View file @ 8946034
  1 +/*
  2 + * This header provides constants for the ARM GIC.
  3 + */
  4 +
  5 +#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H
  6 +#define _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H
  7 +
  8 +#include <dt-bindings/interrupt-controller/irq.h>
  9 +
  10 +/* interrupt specific cell 0 */
  11 +
  12 +#define GIC_SPI 0
  13 +#define GIC_PPI 1
  14 +
  15 +/*
  16 + * Interrupt specifier cell 2.
  17 + * The flaggs in irq.h are valid, plus those below.
  18 + */
  19 +#define GIC_CPU_MASK_RAW(x) ((x) << 8)
  20 +#define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1)
  21 +
  22 +#endif
include/dt-bindings/interrupt-controller/irq.h
Diff comments   View file @ 8946034
  1 +/*
  2 + * This header provides constants for most IRQ bindings.
  3 + *
  4 + * Most IRQ bindings include a flags cell as part of the IRQ specifier.
  5 + * In most cases, the format of the flags cell uses the standard values
  6 + * defined in this header.
  7 + */
  8 +
  9 +#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H
  10 +#define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H
  11 +
  12 +#define IRQ_TYPE_NONE 0
  13 +#define IRQ_TYPE_EDGE_RISING 1
  14 +#define IRQ_TYPE_EDGE_FALLING 2
  15 +#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)
  16 +#define IRQ_TYPE_LEVEL_HIGH 4
  17 +#define IRQ_TYPE_LEVEL_LOW 8
  18 +
  19 +#endif