Eric Lee / smarc-uboot

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Commit 89a168f776cbc15a2ff1f25a0f4e54f9bbaffdec

Authored by Priyanka Jain
Committed by York Sun
1 parent d1418c15c8
Exists in smarc_8mq_lf_v2020.04 and in 17 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

armv8: ls2080ardb: Add QSPI-boot support 

QSPI-boot is supported on LS2088ARDB RevF board with LS2088A SoC.
LS2088ARDB RevF Board has limitation that QIXIS can not be accessed.
CONFIG_FSL_QIXIS is not enabled.

Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

Showing 9 changed files with 195 additions and 11 deletions Side-by-side Diff

arch/arm/cpu/armv8/fsl-layerscape/Kconfig
Diff comments   View file @ 89a168f
... ... @@ -163,6 +163,7 @@
163 163 config SYS_LS_PPA_FW_ADDR
164 164 hex "Address of PPA firmware loading from"
165 165 depends on FSL_LS_PPA
  166 + default 0x20400000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A
166 167 default 0x40500000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT
167 168 default 0x580a00000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
168 169 default 0x60500000 if SYS_LS_PPA_FW_IN_XIP
arch/arm/dts/Makefile
Diff comments   View file @ 89a168f
... ... @@ -174,7 +174,8 @@
174 174 ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb \
175 175 ls1021a-iot-duart.dtb
176 176 dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
177   - fsl-ls2080a-rdb.dtb
  177 + fsl-ls2080a-rdb.dtb \
  178 + fsl-ls2088a-rdb-qspi.dtb
178 179 dtb-$(CONFIG_FSL_LSCH2) += fsl-ls1043a-qds-duart.dtb \
179 180 fsl-ls1043a-qds-lpuart.dtb \
180 181 fsl-ls1043a-rdb.dtb \
arch/arm/dts/fsl-ls2088a-rdb-qspi.dts
Diff comments   View file @ 89a168f
  1 +/*
  2 + * NXP ls2080a RDB board device tree source for QSPI-boot
  3 + *
  4 + * Author: Priyanka Jain <priyanka.jain@nxp.com>
  5 + *
  6 + * Copyright 2017 NXP
  7 + *
  8 + * SPDX-License-Identifier: GPL-2.0+
  9 + */
  10 +
  11 +/dts-v1/;
  12 +
  13 +#include "fsl-ls2080a.dtsi"
  14 +
  15 +/ {
  16 + model = "Freescale Layerscape 2080a RDB Board";
  17 + compatible = "fsl,ls2080a-rdb", "fsl,ls2080a";
  18 +
  19 + aliases {
  20 + spi0 = &qspi;
  21 + spi1 = &dspi;
  22 + };
  23 +};
  24 +
  25 +&dspi {
  26 + bus-num = <0>;
  27 + status = "okay";
  28 +
  29 + dflash0: n25q512a {
  30 + #address-cells = <1>;
  31 + #size-cells = <1>;
  32 + compatible = "spi-flash";
  33 + spi-max-frequency = <3000000>;
  34 + spi-cpol;
  35 + spi-cpha;
  36 + reg = <0>;
  37 + };
  38 +};
  39 +
  40 +&qspi {
  41 + bus-num = <0>;
  42 + status = "okay";
  43 +
  44 + qflash0: s25fs512s@0 {
  45 + #address-cells = <1>;
  46 + #size-cells = <1>;
  47 + compatible = "spi-flash";
  48 + spi-max-frequency = <50000000>;
  49 + reg = <0>;
  50 + };
  51 +
  52 + qflash1: s25fs512s@1 {
  53 + #address-cells = <1>;
  54 + #size-cells = <1>;
  55 + compatible = "spi-flash";
  56 + spi-max-frequency = <50000000>;
  57 + reg = <1>;
  58 + };
  59 +};
board/freescale/ls2080ardb/MAINTAINERS
Diff comments   View file @ 89a168f
... ... @@ -7,6 +7,11 @@
7 7 F: configs/ls2080ardb_defconfig
8 8 F: configs/ls2080ardb_nand_defconfig
9 9  
  10 +LS2088A_QSPI-boot BOARD
  11 +M: Priyanka Jain <priyanka.jain@nxp.com>
  12 +S: Maintained
  13 +F: configs/ls2088ardb_qspi_defconfig
  14 +
10 15 LS2080A_SECURE_BOOT BOARD
11 16 M: Saksham Jain <saksham.jain@nxp.freescale.com>
12 17 S: Maintained
board/freescale/ls2080ardb/README
Diff comments   View file @ 89a168f
... ... @@ -43,6 +43,7 @@
43 43 0x00_0000_0000 .. 0x00_000F_FFFF Boot Rom
44 44 0x00_0100_0000 .. 0x00_0FFF_FFFF CCSR
45 45 0x00_1800_0000 .. 0x00_181F_FFFF OCRAM
  46 +0x00_2000_0000 .. 0x00_2FFF_FFFF QSPI region #1
46 47 0x00_3000_0000 .. 0x00_3FFF_FFFF IFC region #1
47 48 0x00_8000_0000 .. 0x00_FFFF_FFFF DDR region #1
48 49 0x05_1000_0000 .. 0x05_FFFF_FFFF IFC region #2
... ... @@ -68,6 +69,31 @@
68 69 ---------------
69 70 a) NOR boot
70 71 b) NAND boot
  72 +c) QSPI boot
  73 +
  74 +cfg_rcw_src switches needs to be changed for booting from different option.
  75 +Refer to board documentation for correct switch setting.
  76 +
  77 +QSPI boot details
  78 +===================
  79 +Supported only for
  80 + LS2088ARDB RevF board with LS2088A SoC.
  81 +
  82 +Images needs to be copied to QSPI flash
  83 +as per memory map given below.
  84 +
  85 +Memory map for QSPI flash
  86 +-------------------------
  87 +Image Flash Offset
  88 +RCW+PBI 0x00000000
  89 +Boot firmware (U-Boot) 0x00100000
  90 +Boot firmware Environment 0x00300000
  91 +PPA firmware 0x00400000
  92 +Cortina PHY firmware 0x00980000
  93 +DPAA2 MC 0x00A00000
  94 +DPAA2 DPL 0x00D00000
  95 +DPAA2 DPC 0x00E00000
  96 +Kernel.itb 0x01000000
71 97  
72 98 Booting Linux flavors which do not support 48-bit VA (< Linux 3.18)
73 99 -------------------------------------------------------------------
configs/ls2088ardb_qspi_defconfig
Diff comments   View file @ 89a168f
  1 +CONFIG_ARM=y
  2 +CONFIG_TARGET_LS2080ARDB=y
  3 +CONFIG_FSL_LS_PPA=y
  4 +CONFIG_QSPI_AHB_INIT=y
  5 +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls2088a-rdb-qspi"
  6 +# CONFIG_SYS_MALLOC_F is not set
  7 +CONFIG_FIT_VERBOSE=y
  8 +CONFIG_OF_BOARD_SETUP=y
  9 +CONFIG_OF_STDOUT_VIA_ALIAS=y
  10 +CONFIG_QSPI_BOOT=y
  11 +CONFIG_BOOTDELAY=10
  12 +CONFIG_CMD_GREPENV=y
  13 +# CONFIG_CMD_IMLS is not set
  14 +CONFIG_CMD_GPT=y
  15 +CONFIG_CMD_MMC=y
  16 +CONFIG_CMD_SF=y
  17 +CONFIG_CMD_I2C=y
  18 +CONFIG_CMD_DHCP=y
  19 +CONFIG_CMD_MII=y
  20 +CONFIG_CMD_PING=y
  21 +CONFIG_CMD_CACHE=y
  22 +CONFIG_CMD_EXT2=y
  23 +CONFIG_CMD_FAT=y
  24 +CONFIG_OF_CONTROL=y
  25 +CONFIG_NET_RANDOM_ETHADDR=y
  26 +CONFIG_DM=y
  27 +CONFIG_FSL_CAAM=y
  28 +CONFIG_DM_SPI_FLASH=y
  29 +CONFIG_NETDEVICES=y
  30 +CONFIG_E1000=y
  31 +CONFIG_PCI=y
  32 +CONFIG_DM_PCI=y
  33 +CONFIG_DM_PCI_COMPAT=y
  34 +CONFIG_PCIE_LAYERSCAPE=y
  35 +CONFIG_SYS_NS16550=y
  36 +CONFIG_DM_SPI=y
  37 +CONFIG_FSL_QSPI=y
  38 +CONFIG_FSL_DSPI=y
  39 +CONFIG_CMD_USB=y
  40 +# CONFIG_CMD_SETEXPR is not set
  41 +CONFIG_USB=y
  42 +CONFIG_DM_USB=y
  43 +CONFIG_USB_XHCI_HCD=y
  44 +CONFIG_USB_XHCI_DWC3=y
  45 +CONFIG_USB_STORAGE=y
  46 +CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
include/configs/ls2080a_common.h
Diff comments   View file @ 89a168f
1 1 /*
  2 + * Copyright 2017 NXP
2 3 * Copyright (C) 2014 Freescale Semiconductor
3 4 *
4 5 * SPDX-License-Identifier: GPL-2.0+
... ... @@ -28,6 +29,12 @@
28 29 #else
29 30 #define CONFIG_SYS_TEXT_BASE 0x30100000
30 31 #endif
  32 +#else
  33 +#define CONFIG_SYS_TEXT_BASE 0x20100000
  34 +#define CONFIG_ENV_IS_IN_SPI_FLASH
  35 +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
  36 +#define CONFIG_ENV_OFFSET 0x300000 /* 3MB */
  37 +#define CONFIG_ENV_SECT_SIZE 0x10000
31 38 #endif
32 39  
33 40 #define CONFIG_SUPPORT_RAW_INITRD
include/configs/ls2080aqds.h
Diff comments   View file @ 89a168f
1 1 /*
  2 + * Copyright 2017 NXP
2 3 * Copyright 2015 Freescale Semiconductor
3 4 *
4 5 * SPDX-License-Identifier: GPL-2.0+
... ... @@ -262,13 +263,7 @@
262 263 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
263 264 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
264 265  
265   -#if defined(CONFIG_QSPI_BOOT)
266   -#define CONFIG_SYS_TEXT_BASE 0x20010000
267   -#define CONFIG_ENV_IS_IN_SPI_FLASH
268   -#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
269   -#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
270   -#define CONFIG_ENV_SECT_SIZE 0x10000
271   -#else
  266 +#ifndef CONFIG_QSPI_BOOT
272 267 #define CONFIG_ENV_IS_IN_FLASH
273 268 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x200000)
274 269 #define CONFIG_ENV_SECT_SIZE 0x20000
include/configs/ls2080ardb.h
Diff comments   View file @ 89a168f
1 1 /*
  2 + * Copyright 2017 NXP
2 3 * Copyright 2015 Freescale Semiconductor
3 4 *
4 5 * SPDX-License-Identifier: GPL-2.0+
... ... @@ -12,6 +13,11 @@
12 13 #undef CONFIG_CONS_INDEX
13 14 #define CONFIG_CONS_INDEX 2
14 15  
  16 +#ifdef CONFIG_FSL_QSPI
  17 +#define CONFIG_SYS_I2C_EARLY_INIT
  18 +#define CONFIG_DISPLAY_BOARDINFO_LATE
  19 +#endif
  20 +
15 21 #define I2C_MUX_CH_VOL_MONITOR 0xa
16 22 #define I2C_VOL_MONITOR_ADDR 0x38
17 23 #define CONFIG_VOL_MONITOR_IR36021_READ
... ... @@ -69,6 +75,7 @@
69 75 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
70 76 CONFIG_SYS_SCSI_MAX_LUN)
71 77  
  78 +#ifndef CONFIG_FSL_QSPI
72 79 /* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */
73 80  
74 81 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
... ... @@ -157,7 +164,6 @@
157 164 #define CONFIG_CMD_NAND
158 165  
159 166 #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
160   -
161 167 #define CONFIG_FSL_QIXIS /* use common QIXIS code */
162 168 #define QIXIS_LBMAP_SWITCH 0x06
163 169 #define QIXIS_LBMAP_MASK 0x0f
... ... @@ -250,7 +256,7 @@
250 256 /* Debug Server firmware */
251 257 #define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
252 258 #define CONFIG_SYS_DEBUG_SERVER_FW_ADDR 0x580D00000ULL
253   -
  259 +#endif
254 260 #define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
255 261  
256 262 /*
257 263  
258 264  
... ... @@ -263,10 +269,17 @@
263 269 #define I2C_MUX_CH_DEFAULT 0x8
264 270  
265 271 /* SPI */
266   -#ifdef CONFIG_FSL_DSPI
  272 +#if defined(CONFIG_FSL_QSPI) || defined(CONFIG_FSL_DSPI)
267 273 #define CONFIG_SPI_FLASH
  274 +#ifdef CONFIG_FSL_QSPI
268 275 #define CONFIG_SPI_FLASH_STMICRO
269 276 #endif
  277 +#ifdef CONFIG_FSL_QSPI
  278 +#define CONFIG_SPI_FLASH_SPANSION
  279 +#define FSL_QSPI_FLASH_SIZE SZ_64M /* 64MB */
  280 +#define FSL_QSPI_FLASH_NUM 2
  281 +#endif
  282 +#endif
270 283  
271 284 /*
272 285 * RTC configuration
... ... @@ -345,6 +358,7 @@
345 358 " 0x580800000 \0" \
346 359 BOOTENV
347 360 #else
  361 +#ifdef CONFIG_QSPI_BOOT
348 362 #define CONFIG_EXTRA_ENV_SETTINGS \
349 363 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
350 364 "scriptaddr=0x80800000\0" \
... ... @@ -354,6 +368,24 @@
354 368 "ramdisk_addr_r=0x89000000\0" \
355 369 "loadaddr=0x80100000\0" \
356 370 "kernel_addr=0x100000\0" \
  371 + "ramdisk_size=0x2000000\0" \
  372 + "fdt_high=0xa0000000\0" \
  373 + "initrd_high=0xffffffffffffffff\0" \
  374 + "kernel_start=0x21000000\0" \
  375 + "mcmemsize=0x40000000\0" \
  376 + "mcinitcmd=fsl_mc start mc 0x20a00000" \
  377 + " 0x20e00000 \0" \
  378 + BOOTENV
  379 +#else
  380 +#define CONFIG_EXTRA_ENV_SETTINGS \
  381 + "hwconfig=fsl_ddr:bank_intlv=auto\0" \
  382 + "scriptaddr=0x80800000\0" \
  383 + "kernel_addr_r=0x81000000\0" \
  384 + "pxefile_addr_r=0x81000000\0" \
  385 + "fdt_addr_r=0x88000000\0" \
  386 + "ramdisk_addr_r=0x89000000\0" \
  387 + "loadaddr=0x80100000\0" \
  388 + "kernel_addr=0x100000\0" \
357 389 "ramdisk_addr=0x800000\0" \
358 390 "ramdisk_size=0x2000000\0" \
359 391 "fdt_high=0xa0000000\0" \
... ... @@ -367,6 +399,7 @@
367 399 " 0x580800000 \0" \
368 400 BOOTENV
369 401 #endif
  402 +#endif
370 403  
371 404  
372 405 #undef CONFIG_BOOTARGS
373 406  
... ... @@ -376,11 +409,18 @@
376 409 " hugepagesz=2m hugepages=256"
377 410  
378 411 #undef CONFIG_BOOTCOMMAND
  412 +#ifdef CONFIG_QSPI_BOOT
  413 +/* Try to boot an on-QSPI kernel first, then do normal distro boot */
  414 +#define CONFIG_BOOTCOMMAND "run mcinitcmd && fsl_mc lazyapply dpl 0x20d00000" \
  415 + " && bootm $kernel_start" \
  416 + " || run distro_bootcmd"
  417 +#else
379 418 /* Try to boot an on-NOR kernel first, then do normal distro boot */
380 419 #define CONFIG_BOOTCOMMAND "run mcinitcmd && fsl_mc lazyapply dpl 0x580700000" \
381 420 " && cp.b $kernel_start $kernel_load $kernel_size" \
382 421 " && bootm $kernel_load" \
383 422 " || run distro_bootcmd"
  423 +#endif
384 424  
385 425 /* MAC/PHY configuration */
386 426 #ifdef CONFIG_FSL_MC_ENET
387 427  
... ... @@ -389,7 +429,11 @@
389 429 #define CONFIG_PHY_CORTINA
390 430 #define CONFIG_PHYLIB
391 431 #define CONFIG_SYS_CORTINA_FW_IN_NOR
  432 +#ifdef CONFIG_QSPI_BOOT
  433 +#define CONFIG_CORTINA_FW_ADDR 0x20980000
  434 +#else
392 435 #define CONFIG_CORTINA_FW_ADDR 0x581000000
  436 +#endif
393 437 #define CONFIG_CORTINA_FW_LENGTH 0x40000
394 438  
395 439 #define CORTINA_PHY_ADDR1 0x10