Eric Lee / smarc-uboot

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Commit 89c00f009ca8107d80834513877bc4ddd0ab2f5b

Authored by Eugeniu Rosca
Committed by Marek Vasut
1 parent 70f3b164a6
Exists in smarc_8mq_lf_v2020.04 and in 9 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

ARM: dts: rmobile: Synchronize Gen3 DTs with Linux 5.2 

Backport and squash below Linux 5.2 commits for R-Car Gen3:

Commit id       * Summary line
6fffb98645e67b5   arm64: dts: renesas: r8a77990: ebisu: Add GPIO expander
b068ed6efe6244d   arm64: dts: renesas: r8a77990: Fix SPDX license identifier style
96c25882252704d ! arm64: dts: renesas: r8a7796: remove unneeded sound #address/size-cells
71ac75dffdae2f8   arm64: dts: renesas: r8a77990: ebisu: Enable LVDS1 encoder
9a0ff5c727b60a3   arm64: dts: renesas: r8a77995: draak: Enable LVDS1 encoder
9130c15829846fa   arm64: dts: renesas: ebisu: Fix adv7482 hexadecimal register address
191f7dcd1f5ea1f   arm64: dts: renesas: r8a77965: add SSIU support for sound
a8f6110e64422d5   arm64: dts: renesas: ebisu: Enable VIN5
4162aa9db3d4469   arm64: dts: renesas: r8a77995: draak: Enable CAN0, CAN1
af965ba3248edde   arm64: dts: renesas: r8a77990: Remove invalid compatible value for CSI40
1f4c123a98098cc   arm64: dts: renesas: r8a77990-ebisu: Add BD9571 PMIC
474706117c2baa6   arm64: dts: renesas: ebisu: Add PMIC DDR0 Backup Power config
e2fa79de7ecbef4   arm64: dts: renesas: Update Ebisu and Draak bootargs
de8e8daaf7190ef   arm64: dts: renesas: salvator-common: Sort node label
05f1d882d28b871   arm64: dts: renesas: r8a77995: draak: Fix EthernetAVB phy mode to rgmii
7a516e49d975311   arm64: dts: renesas: use extended audio dmac register
e3414b8c45afa5c   arm64: dts: renesas: salvator-common: Add GPIO keys support
720066d17c973fd   arm64: dts: renesas: r8a7795: Add CMT device nodes
99cb95103e2d058   arm64: dts: renesas: r8a77965: Add CMT device nodes
28a5c61b5136d58   arm64: dts: renesas: r8a77990: Add CMT device nodes
32d622f3290b2a1   arm64: dts: renesas: r8a77965: Remove reg-names of display node

(*) Patch id mismatch between Linux and U-Boot commit.
[!] Dropped changes in arch/arm64/boot/dts/renesas/r8a7796-salvator-xs.dts,
    since the file doesn't exist in the U-Boot tree.

Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>

Showing 8 changed files with 595 additions and 47 deletions Side-by-side Diff

arch/arm/dts/r8a7795.dtsi
Diff comments   View file @ 89c00f0
... ... @@ -462,6 +462,76 @@
462 462 reg = <0 0xe6060000 0 0x50c>;
463 463 };
464 464  
  465 + cmt0: timer@e60f0000 {
  466 + compatible = "renesas,r8a7795-cmt0",
  467 + "renesas,rcar-gen3-cmt0";
  468 + reg = <0 0xe60f0000 0 0x1004>;
  469 + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
  470 + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
  471 + clocks = <&cpg CPG_MOD 303>;
  472 + clock-names = "fck";
  473 + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
  474 + resets = <&cpg 303>;
  475 + status = "disabled";
  476 + };
  477 +
  478 + cmt1: timer@e6130000 {
  479 + compatible = "renesas,r8a7795-cmt1",
  480 + "renesas,rcar-gen3-cmt1";
  481 + reg = <0 0xe6130000 0 0x1004>;
  482 + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
  483 + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
  484 + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
  485 + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
  486 + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
  487 + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
  488 + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
  489 + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
  490 + clocks = <&cpg CPG_MOD 302>;
  491 + clock-names = "fck";
  492 + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
  493 + resets = <&cpg 302>;
  494 + status = "disabled";
  495 + };
  496 +
  497 + cmt2: timer@e6140000 {
  498 + compatible = "renesas,r8a7795-cmt1",
  499 + "renesas,rcar-gen3-cmt1";
  500 + reg = <0 0xe6140000 0 0x1004>;
  501 + interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
  502 + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
  503 + <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
  504 + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
  505 + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
  506 + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
  507 + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
  508 + <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
  509 + clocks = <&cpg CPG_MOD 301>;
  510 + clock-names = "fck";
  511 + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
  512 + resets = <&cpg 301>;
  513 + status = "disabled";
  514 + };
  515 +
  516 + cmt3: timer@e6148000 {
  517 + compatible = "renesas,r8a7795-cmt1",
  518 + "renesas,rcar-gen3-cmt1";
  519 + reg = <0 0xe6148000 0 0x1004>;
  520 + interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
  521 + <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
  522 + <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
  523 + <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
  524 + <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
  525 + <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
  526 + <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
  527 + <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
  528 + clocks = <&cpg CPG_MOD 300>;
  529 + clock-names = "fck";
  530 + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
  531 + resets = <&cpg 300>;
  532 + status = "disabled";
  533 + };
  534 +
465 535 cpg: clock-controller@e6150000 {
466 536 compatible = "renesas,r8a7795-cpg-mssr";
467 537 reg = <0 0xe6150000 0 0x1000>;
... ... @@ -1836,7 +1906,7 @@
1836 1906 <0 0xec5a0000 0 0x100>, /* ADG */
1837 1907 <0 0xec540000 0 0x1000>, /* SSIU */
1838 1908 <0 0xec541000 0 0x280>, /* SSI */
1839   - <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
  1909 + <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1840 1910 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1841 1911  
1842 1912 clocks = <&cpg CPG_MOD 1005>,
arch/arm/dts/r8a7796-salvator-x.dts
Diff comments   View file @ 89c00f0
... ... @@ -68,6 +68,7 @@
68 68 ports {
69 69 /* rsnd_port0 is on salvator-common */
70 70 rsnd_port1: port@1 {
  71 + reg = <1>;
71 72 rsnd_endpoint1: endpoint {
72 73 remote-endpoint = <&dw_hdmi0_snd_in>;
73 74  
arch/arm/dts/r8a7796.dtsi
Diff comments   View file @ 89c00f0
... ... @@ -1775,7 +1775,7 @@
1775 1775 <0 0xec5a0000 0 0x100>, /* ADG */
1776 1776 <0 0xec540000 0 0x1000>, /* SSIU */
1777 1777 <0 0xec541000 0 0x280>, /* SSI */
1778   - <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
  1778 + <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1779 1779 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1780 1780  
1781 1781 clocks = <&cpg CPG_MOD 1005>,
... ... @@ -2160,17 +2160,6 @@
2160 2160 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
2161 2161 dmas = <&audma0 0x13>, <&audma1 0x14>;
2162 2162 dma-names = "rx", "tx";
2163   - };
2164   - };
2165   -
2166   - ports {
2167   - #address-cells = <1>;
2168   - #size-cells = <0>;
2169   - port@0 {
2170   - reg = <0>;
2171   - };
2172   - port@1 {
2173   - reg = <1>;
2174 2163 };
2175 2164 };
2176 2165 };
arch/arm/dts/r8a77965.dtsi
Diff comments   View file @ 89c00f0
... ... @@ -317,6 +317,76 @@
317 317 reg = <0 0xe6060000 0 0x50c>;
318 318 };
319 319  
  320 + cmt0: timer@e60f0000 {
  321 + compatible = "renesas,r8a77965-cmt0",
  322 + "renesas,rcar-gen3-cmt0";
  323 + reg = <0 0xe60f0000 0 0x1004>;
  324 + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
  325 + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
  326 + clocks = <&cpg CPG_MOD 303>;
  327 + clock-names = "fck";
  328 + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
  329 + resets = <&cpg 303>;
  330 + status = "disabled";
  331 + };
  332 +
  333 + cmt1: timer@e6130000 {
  334 + compatible = "renesas,r8a77965-cmt1",
  335 + "renesas,rcar-gen3-cmt1";
  336 + reg = <0 0xe6130000 0 0x1004>;
  337 + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
  338 + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
  339 + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
  340 + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
  341 + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
  342 + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
  343 + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
  344 + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
  345 + clocks = <&cpg CPG_MOD 302>;
  346 + clock-names = "fck";
  347 + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
  348 + resets = <&cpg 302>;
  349 + status = "disabled";
  350 + };
  351 +
  352 + cmt2: timer@e6140000 {
  353 + compatible = "renesas,r8a77965-cmt1",
  354 + "renesas,rcar-gen3-cmt1";
  355 + reg = <0 0xe6140000 0 0x1004>;
  356 + interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
  357 + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
  358 + <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
  359 + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
  360 + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
  361 + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
  362 + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
  363 + <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
  364 + clocks = <&cpg CPG_MOD 301>;
  365 + clock-names = "fck";
  366 + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
  367 + resets = <&cpg 301>;
  368 + status = "disabled";
  369 + };
  370 +
  371 + cmt3: timer@e6148000 {
  372 + compatible = "renesas,r8a77965-cmt1",
  373 + "renesas,rcar-gen3-cmt1";
  374 + reg = <0 0xe6148000 0 0x1004>;
  375 + interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
  376 + <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
  377 + <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
  378 + <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
  379 + <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
  380 + <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
  381 + <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
  382 + <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
  383 + clocks = <&cpg CPG_MOD 300>;
  384 + clock-names = "fck";
  385 + power-domains = <&sysc R8A77965_PD_ALWAYS_ON>;
  386 + resets = <&cpg 300>;
  387 + status = "disabled";
  388 + };
  389 +
320 390 cpg: clock-controller@e6150000 {
321 391 compatible = "renesas,r8a77965-cpg-mssr";
322 392 reg = <0 0xe6150000 0 0x1000>;
... ... @@ -1461,7 +1531,7 @@
1461 1531 <0 0xec5a0000 0 0x100>, /* ADG */
1462 1532 <0 0xec540000 0 0x1000>, /* SSIU */
1463 1533 <0 0xec541000 0 0x280>, /* SSI */
1464   - <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
  1534 + <0 0xec760000 0 0x200>; /* Audio DMAC peri peri*/
1465 1535 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
1466 1536  
1467 1537 clocks = <&cpg CPG_MOD 1005>,
1468 1538  
1469 1539  
1470 1540  
1471 1541  
1472 1542  
1473 1543  
1474 1544  
1475 1545  
1476 1546  
1477 1547  
... ... @@ -1585,56 +1655,267 @@
1585 1655 };
1586 1656 };
1587 1657  
  1658 + rcar_sound,ssiu {
  1659 + ssiu00: ssiu-0 {
  1660 + dmas = <&audma0 0x15>, <&audma1 0x16>;
  1661 + dma-names = "rx", "tx";
  1662 + };
  1663 + ssiu01: ssiu-1 {
  1664 + dmas = <&audma0 0x35>, <&audma1 0x36>;
  1665 + dma-names = "rx", "tx";
  1666 + };
  1667 + ssiu02: ssiu-2 {
  1668 + dmas = <&audma0 0x37>, <&audma1 0x38>;
  1669 + dma-names = "rx", "tx";
  1670 + };
  1671 + ssiu03: ssiu-3 {
  1672 + dmas = <&audma0 0x47>, <&audma1 0x48>;
  1673 + dma-names = "rx", "tx";
  1674 + };
  1675 + ssiu04: ssiu-4 {
  1676 + dmas = <&audma0 0x3F>, <&audma1 0x40>;
  1677 + dma-names = "rx", "tx";
  1678 + };
  1679 + ssiu05: ssiu-5 {
  1680 + dmas = <&audma0 0x43>, <&audma1 0x44>;
  1681 + dma-names = "rx", "tx";
  1682 + };
  1683 + ssiu06: ssiu-6 {
  1684 + dmas = <&audma0 0x4F>, <&audma1 0x50>;
  1685 + dma-names = "rx", "tx";
  1686 + };
  1687 + ssiu07: ssiu-7 {
  1688 + dmas = <&audma0 0x53>, <&audma1 0x54>;
  1689 + dma-names = "rx", "tx";
  1690 + };
  1691 + ssiu10: ssiu-8 {
  1692 + dmas = <&audma0 0x49>, <&audma1 0x4a>;
  1693 + dma-names = "rx", "tx";
  1694 + };
  1695 + ssiu11: ssiu-9 {
  1696 + dmas = <&audma0 0x4B>, <&audma1 0x4C>;
  1697 + dma-names = "rx", "tx";
  1698 + };
  1699 + ssiu12: ssiu-10 {
  1700 + dmas = <&audma0 0x57>, <&audma1 0x58>;
  1701 + dma-names = "rx", "tx";
  1702 + };
  1703 + ssiu13: ssiu-11 {
  1704 + dmas = <&audma0 0x59>, <&audma1 0x5A>;
  1705 + dma-names = "rx", "tx";
  1706 + };
  1707 + ssiu14: ssiu-12 {
  1708 + dmas = <&audma0 0x5F>, <&audma1 0x60>;
  1709 + dma-names = "rx", "tx";
  1710 + };
  1711 + ssiu15: ssiu-13 {
  1712 + dmas = <&audma0 0xC3>, <&audma1 0xC4>;
  1713 + dma-names = "rx", "tx";
  1714 + };
  1715 + ssiu16: ssiu-14 {
  1716 + dmas = <&audma0 0xC7>, <&audma1 0xC8>;
  1717 + dma-names = "rx", "tx";
  1718 + };
  1719 + ssiu17: ssiu-15 {
  1720 + dmas = <&audma0 0xCB>, <&audma1 0xCC>;
  1721 + dma-names = "rx", "tx";
  1722 + };
  1723 + ssiu20: ssiu-16 {
  1724 + dmas = <&audma0 0x63>, <&audma1 0x64>;
  1725 + dma-names = "rx", "tx";
  1726 + };
  1727 + ssiu21: ssiu-17 {
  1728 + dmas = <&audma0 0x67>, <&audma1 0x68>;
  1729 + dma-names = "rx", "tx";
  1730 + };
  1731 + ssiu22: ssiu-18 {
  1732 + dmas = <&audma0 0x6B>, <&audma1 0x6C>;
  1733 + dma-names = "rx", "tx";
  1734 + };
  1735 + ssiu23: ssiu-19 {
  1736 + dmas = <&audma0 0x6D>, <&audma1 0x6E>;
  1737 + dma-names = "rx", "tx";
  1738 + };
  1739 + ssiu24: ssiu-20 {
  1740 + dmas = <&audma0 0xCF>, <&audma1 0xCE>;
  1741 + dma-names = "rx", "tx";
  1742 + };
  1743 + ssiu25: ssiu-21 {
  1744 + dmas = <&audma0 0xEB>, <&audma1 0xEC>;
  1745 + dma-names = "rx", "tx";
  1746 + };
  1747 + ssiu26: ssiu-22 {
  1748 + dmas = <&audma0 0xED>, <&audma1 0xEE>;
  1749 + dma-names = "rx", "tx";
  1750 + };
  1751 + ssiu27: ssiu-23 {
  1752 + dmas = <&audma0 0xEF>, <&audma1 0xF0>;
  1753 + dma-names = "rx", "tx";
  1754 + };
  1755 + ssiu30: ssiu-24 {
  1756 + dmas = <&audma0 0x6f>, <&audma1 0x70>;
  1757 + dma-names = "rx", "tx";
  1758 + };
  1759 + ssiu31: ssiu-25 {
  1760 + dmas = <&audma0 0x21>, <&audma1 0x22>;
  1761 + dma-names = "rx", "tx";
  1762 + };
  1763 + ssiu32: ssiu-26 {
  1764 + dmas = <&audma0 0x23>, <&audma1 0x24>;
  1765 + dma-names = "rx", "tx";
  1766 + };
  1767 + ssiu33: ssiu-27 {
  1768 + dmas = <&audma0 0x25>, <&audma1 0x26>;
  1769 + dma-names = "rx", "tx";
  1770 + };
  1771 + ssiu34: ssiu-28 {
  1772 + dmas = <&audma0 0x27>, <&audma1 0x28>;
  1773 + dma-names = "rx", "tx";
  1774 + };
  1775 + ssiu35: ssiu-29 {
  1776 + dmas = <&audma0 0x29>, <&audma1 0x2A>;
  1777 + dma-names = "rx", "tx";
  1778 + };
  1779 + ssiu36: ssiu-30 {
  1780 + dmas = <&audma0 0x2B>, <&audma1 0x2C>;
  1781 + dma-names = "rx", "tx";
  1782 + };
  1783 + ssiu37: ssiu-31 {
  1784 + dmas = <&audma0 0x2D>, <&audma1 0x2E>;
  1785 + dma-names = "rx", "tx";
  1786 + };
  1787 + ssiu40: ssiu-32 {
  1788 + dmas = <&audma0 0x71>, <&audma1 0x72>;
  1789 + dma-names = "rx", "tx";
  1790 + };
  1791 + ssiu41: ssiu-33 {
  1792 + dmas = <&audma0 0x17>, <&audma1 0x18>;
  1793 + dma-names = "rx", "tx";
  1794 + };
  1795 + ssiu42: ssiu-34 {
  1796 + dmas = <&audma0 0x19>, <&audma1 0x1A>;
  1797 + dma-names = "rx", "tx";
  1798 + };
  1799 + ssiu43: ssiu-35 {
  1800 + dmas = <&audma0 0x1B>, <&audma1 0x1C>;
  1801 + dma-names = "rx", "tx";
  1802 + };
  1803 + ssiu44: ssiu-36 {
  1804 + dmas = <&audma0 0x1D>, <&audma1 0x1E>;
  1805 + dma-names = "rx", "tx";
  1806 + };
  1807 + ssiu45: ssiu-37 {
  1808 + dmas = <&audma0 0x1F>, <&audma1 0x20>;
  1809 + dma-names = "rx", "tx";
  1810 + };
  1811 + ssiu46: ssiu-38 {
  1812 + dmas = <&audma0 0x31>, <&audma1 0x32>;
  1813 + dma-names = "rx", "tx";
  1814 + };
  1815 + ssiu47: ssiu-39 {
  1816 + dmas = <&audma0 0x33>, <&audma1 0x34>;
  1817 + dma-names = "rx", "tx";
  1818 + };
  1819 + ssiu50: ssiu-40 {
  1820 + dmas = <&audma0 0x73>, <&audma1 0x74>;
  1821 + dma-names = "rx", "tx";
  1822 + };
  1823 + ssiu60: ssiu-41 {
  1824 + dmas = <&audma0 0x75>, <&audma1 0x76>;
  1825 + dma-names = "rx", "tx";
  1826 + };
  1827 + ssiu70: ssiu-42 {
  1828 + dmas = <&audma0 0x79>, <&audma1 0x7a>;
  1829 + dma-names = "rx", "tx";
  1830 + };
  1831 + ssiu80: ssiu-43 {
  1832 + dmas = <&audma0 0x7b>, <&audma1 0x7c>;
  1833 + dma-names = "rx", "tx";
  1834 + };
  1835 + ssiu90: ssiu-44 {
  1836 + dmas = <&audma0 0x7d>, <&audma1 0x7e>;
  1837 + dma-names = "rx", "tx";
  1838 + };
  1839 + ssiu91: ssiu-45 {
  1840 + dmas = <&audma0 0x7F>, <&audma1 0x80>;
  1841 + dma-names = "rx", "tx";
  1842 + };
  1843 + ssiu92: ssiu-46 {
  1844 + dmas = <&audma0 0x81>, <&audma1 0x82>;
  1845 + dma-names = "rx", "tx";
  1846 + };
  1847 + ssiu93: ssiu-47 {
  1848 + dmas = <&audma0 0x83>, <&audma1 0x84>;
  1849 + dma-names = "rx", "tx";
  1850 + };
  1851 + ssiu94: ssiu-48 {
  1852 + dmas = <&audma0 0xA3>, <&audma1 0xA4>;
  1853 + dma-names = "rx", "tx";
  1854 + };
  1855 + ssiu95: ssiu-49 {
  1856 + dmas = <&audma0 0xA5>, <&audma1 0xA6>;
  1857 + dma-names = "rx", "tx";
  1858 + };
  1859 + ssiu96: ssiu-50 {
  1860 + dmas = <&audma0 0xA7>, <&audma1 0xA8>;
  1861 + dma-names = "rx", "tx";
  1862 + };
  1863 + ssiu97: ssiu-51 {
  1864 + dmas = <&audma0 0xA9>, <&audma1 0xAA>;
  1865 + dma-names = "rx", "tx";
  1866 + };
  1867 + };
  1868 +
1588 1869 rcar_sound,ssi {
1589 1870 ssi0: ssi-0 {
1590 1871 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
1591   - dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
1592   - dma-names = "rx", "tx", "rxu", "txu";
  1872 + dmas = <&audma0 0x01>, <&audma1 0x02>;
  1873 + dma-names = "rx", "tx";
1593 1874 };
1594 1875 ssi1: ssi-1 {
1595 1876 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
1596   - dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
1597   - dma-names = "rx", "tx", "rxu", "txu";
  1877 + dmas = <&audma0 0x03>, <&audma1 0x04>;
  1878 + dma-names = "rx", "tx";
1598 1879 };
1599 1880 ssi2: ssi-2 {
1600 1881 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
1601   - dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
1602   - dma-names = "rx", "tx", "rxu", "txu";
  1882 + dmas = <&audma0 0x05>, <&audma1 0x06>;
  1883 + dma-names = "rx", "tx";
1603 1884 };
1604 1885 ssi3: ssi-3 {
1605 1886 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
1606   - dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
1607   - dma-names = "rx", "tx", "rxu", "txu";
  1887 + dmas = <&audma0 0x07>, <&audma1 0x08>;
  1888 + dma-names = "rx", "tx";
1608 1889 };
1609 1890 ssi4: ssi-4 {
1610 1891 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
1611   - dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
1612   - dma-names = "rx", "tx", "rxu", "txu";
  1892 + dmas = <&audma0 0x09>, <&audma1 0x0a>;
  1893 + dma-names = "rx", "tx";
1613 1894 };
1614 1895 ssi5: ssi-5 {
1615 1896 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
1616   - dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
1617   - dma-names = "rx", "tx", "rxu", "txu";
  1897 + dmas = <&audma0 0x0b>, <&audma1 0x0c>;
  1898 + dma-names = "rx", "tx";
1618 1899 };
1619 1900 ssi6: ssi-6 {
1620 1901 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
1621   - dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
1622   - dma-names = "rx", "tx", "rxu", "txu";
  1902 + dmas = <&audma0 0x0d>, <&audma1 0x0e>;
  1903 + dma-names = "rx", "tx";
1623 1904 };
1624 1905 ssi7: ssi-7 {
1625 1906 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
1626   - dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
1627   - dma-names = "rx", "tx", "rxu", "txu";
  1907 + dmas = <&audma0 0x0f>, <&audma1 0x10>;
  1908 + dma-names = "rx", "tx";
1628 1909 };
1629 1910 ssi8: ssi-8 {
1630 1911 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
1631   - dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
1632   - dma-names = "rx", "tx", "rxu", "txu";
  1912 + dmas = <&audma0 0x11>, <&audma1 0x12>;
  1913 + dma-names = "rx", "tx";
1633 1914 };
1634 1915 ssi9: ssi-9 {
1635 1916 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
1636   - dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
1637   - dma-names = "rx", "tx", "rxu", "txu";
  1917 + dmas = <&audma0 0x13>, <&audma1 0x14>;
  1918 + dma-names = "rx", "tx";
1638 1919 };
1639 1920 };
1640 1921 };
... ... @@ -2166,7 +2447,6 @@
2166 2447 du: display@feb00000 {
2167 2448 compatible = "renesas,du-r8a77965";
2168 2449 reg = <0 0xfeb00000 0 0x80000>;
2169   - reg-names = "du";
2170 2450 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
2171 2451 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
2172 2452 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
arch/arm/dts/r8a77990-ebisu.dts
Diff comments   View file @ 89c00f0
1   -/* SPDX-License-Identifier: GPL-2.0 */
  1 +// SPDX-License-Identifier: GPL-2.0
2 2 /*
3 3 * Device Tree Source for the ebisu board
4 4 *
... ... @@ -19,7 +19,7 @@
19 19 };
20 20  
21 21 chosen {
22   - bootargs = "ignore_loglevel";
  22 + bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
23 23 stdout-path = "serial0:115200n8";
24 24 };
25 25  
... ... @@ -337,6 +337,15 @@
337 337 &i2c0 {
338 338 status = "okay";
339 339  
  340 + io_expander: gpio@20 {
  341 + compatible = "onnn,pca9654";
  342 + reg = <0x20>;
  343 + gpio-controller;
  344 + #gpio-cells = <2>;
  345 + interrupt-parent = <&gpio2>;
  346 + interrupts = <22 IRQ_TYPE_LEVEL_LOW>;
  347 + };
  348 +
340 349 hdmi-encoder@39 {
341 350 compatible = "adi,adv7511w";
342 351 reg = <0x39>;
... ... @@ -398,7 +407,7 @@
398 407 };
399 408  
400 409 port@a {
401   - reg = <0xa>;
  410 + reg = <10>;
402 411  
403 412 adv7482_txa: endpoint {
404 413 clock-lanes = <0>;
... ... @@ -440,6 +449,28 @@
440 449 };
441 450 };
442 451  
  452 +&i2c_dvfs {
  453 + status = "okay";
  454 +
  455 + clock-frequency = <400000>;
  456 +
  457 + pmic: pmic@30 {
  458 + pinctrl-0 = <&irq0_pins>;
  459 + pinctrl-names = "default";
  460 +
  461 + compatible = "rohm,bd9571mwv";
  462 + reg = <0x30>;
  463 + interrupt-parent = <&intc_ex>;
  464 + interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
  465 + interrupt-controller;
  466 + #interrupt-cells = <2>;
  467 + gpio-controller;
  468 + #gpio-cells = <2>;
  469 + rohm,ddr-backup-power = <0x1>;
  470 + rohm,rstbmode-level;
  471 + };
  472 +};
  473 +
443 474 &lvds0 {
444 475 status = "okay";
445 476  
... ... @@ -458,6 +489,13 @@
458 489 };
459 490  
460 491 &lvds1 {
  492 + /*
  493 + * Even though the LVDS1 output is not connected, the encoder must be
  494 + * enabled to supply a pixel clock to the DU for the DPAD output when
  495 + * LVDS0 is in use.
  496 + */
  497 + status = "okay";
  498 +
461 499 clocks = <&cpg CPG_MOD 727>,
462 500 <&x13_clk>,
463 501 <&extal_clk>;
... ... @@ -495,6 +533,11 @@
495 533 function = "du";
496 534 };
497 535  
  536 + irq0_pins: irq0 {
  537 + groups = "intc_ex_irq0";
  538 + function = "intc_ex";
  539 + };
  540 +
498 541 pwm3_pins: pwm3 {
499 542 groups = "pwm3_b";
500 543 function = "pwm3";
... ... @@ -647,6 +690,10 @@
647 690 };
648 691  
649 692 &vin4 {
  693 + status = "okay";
  694 +};
  695 +
  696 +&vin5 {
650 697 status = "okay";
651 698 };
652 699  
arch/arm/dts/r8a77990.dtsi
Diff comments   View file @ 89c00f0
1   -/* SPDX-License-Identifier: GPL-2.0 */
  1 +// SPDX-License-Identifier: GPL-2.0
2 2 /*
3 3 * Device Tree Source for the R-Car E3 (R8A77990) SoC
4 4 *
... ... @@ -284,6 +284,76 @@
284 284 status = "disabled";
285 285 };
286 286  
  287 + cmt0: timer@e60f0000 {
  288 + compatible = "renesas,r8a77990-cmt0",
  289 + "renesas,rcar-gen3-cmt0";
  290 + reg = <0 0xe60f0000 0 0x1004>;
  291 + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
  292 + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
  293 + clocks = <&cpg CPG_MOD 303>;
  294 + clock-names = "fck";
  295 + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
  296 + resets = <&cpg 303>;
  297 + status = "disabled";
  298 + };
  299 +
  300 + cmt1: timer@e6130000 {
  301 + compatible = "renesas,r8a77990-cmt1",
  302 + "renesas,rcar-gen3-cmt1";
  303 + reg = <0 0xe6130000 0 0x1004>;
  304 + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
  305 + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
  306 + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
  307 + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
  308 + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
  309 + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
  310 + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
  311 + <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
  312 + clocks = <&cpg CPG_MOD 302>;
  313 + clock-names = "fck";
  314 + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
  315 + resets = <&cpg 302>;
  316 + status = "disabled";
  317 + };
  318 +
  319 + cmt2: timer@e6140000 {
  320 + compatible = "renesas,r8a77990-cmt1",
  321 + "renesas,rcar-gen3-cmt1";
  322 + reg = <0 0xe6140000 0 0x1004>;
  323 + interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
  324 + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
  325 + <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
  326 + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
  327 + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
  328 + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
  329 + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
  330 + <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
  331 + clocks = <&cpg CPG_MOD 301>;
  332 + clock-names = "fck";
  333 + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
  334 + resets = <&cpg 301>;
  335 + status = "disabled";
  336 + };
  337 +
  338 + cmt3: timer@e6148000 {
  339 + compatible = "renesas,r8a77990-cmt1",
  340 + "renesas,rcar-gen3-cmt1";
  341 + reg = <0 0xe6148000 0 0x1004>;
  342 + interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
  343 + <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
  344 + <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
  345 + <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
  346 + <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
  347 + <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
  348 + <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
  349 + <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
  350 + clocks = <&cpg CPG_MOD 300>;
  351 + clock-names = "fck";
  352 + power-domains = <&sysc R8A77990_PD_ALWAYS_ON>;
  353 + resets = <&cpg 300>;
  354 + status = "disabled";
  355 + };
  356 +
287 357 cpg: clock-controller@e6150000 {
288 358 compatible = "renesas,r8a77990-cpg-mssr";
289 359 reg = <0 0xe6150000 0 0x1000>;
... ... @@ -1656,7 +1726,7 @@
1656 1726 };
1657 1727  
1658 1728 csi40: csi2@feaa0000 {
1659   - compatible = "renesas,r8a77990-csi2", "renesas,rcar-gen3-csi2";
  1729 + compatible = "renesas,r8a77990-csi2";
1660 1730 reg = <0 0xfeaa0000 0 0x10000>;
1661 1731 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
1662 1732 clocks = <&cpg CPG_MOD 716>;
arch/arm/dts/r8a77995-draak.dts
Diff comments   View file @ 89c00f0
... ... @@ -20,7 +20,7 @@
20 20 };
21 21  
22 22 chosen {
23   - bootargs = "ignore_loglevel";
  23 + bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
24 24 stdout-path = "serial0:115200n8";
25 25 };
26 26  
... ... @@ -168,7 +168,6 @@
168 168 pinctrl-names = "default";
169 169 renesas,no-ether-link;
170 170 phy-handle = <&phy0>;
171   - phy-mode = "rgmii-txid";
172 171 status = "okay";
173 172  
174 173 phy0: ethernet-phy@0 {
... ... @@ -179,6 +178,18 @@
179 178 };
180 179 };
181 180  
  181 +&can0 {
  182 + pinctrl-0 = <&can0_pins>;
  183 + pinctrl-names = "default";
  184 + status = "okay";
  185 +};
  186 +
  187 +&can1 {
  188 + pinctrl-0 = <&can1_pins>;
  189 + pinctrl-names = "default";
  190 + status = "okay";
  191 +};
  192 +
182 193 &du {
183 194 pinctrl-0 = <&du_pins>;
184 195 pinctrl-names = "default";
... ... @@ -356,6 +367,13 @@
356 367 };
357 368  
358 369 &lvds1 {
  370 + /*
  371 + * Even though the LVDS1 output is not connected, the encoder must be
  372 + * enabled to supply a pixel clock to the DU for the DPAD output when
  373 + * LVDS0 is in use.
  374 + */
  375 + status = "okay";
  376 +
359 377 clocks = <&cpg CPG_MOD 727>,
360 378 <&x12_clk>,
361 379 <&extal_clk>;
... ... @@ -373,6 +391,16 @@
373 391 groups = "avb0_link", "avb0_mdio", "avb0_mii";
374 392 function = "avb0";
375 393 };
  394 + };
  395 +
  396 + can0_pins: can0 {
  397 + groups = "can0_data_a";
  398 + function = "can0";
  399 + };
  400 +
  401 + can1_pins: can1 {
  402 + groups = "can1_data_a";
  403 + function = "can1";
376 404 };
377 405  
378 406 du_pins: du {
arch/arm/dts/salvator-common.dtsi
Diff comments   View file @ 89c00f0
... ... @@ -29,6 +29,7 @@
29 29 */
30 30  
31 31 #include <dt-bindings/gpio/gpio.h>
  32 +#include <dt-bindings/input/input.h>
32 33  
33 34 / {
34 35 aliases {
... ... @@ -86,6 +87,63 @@
86 87 };
87 88 };
88 89  
  90 + keys {
  91 + compatible = "gpio-keys";
  92 +
  93 + pinctrl-0 = <&keys_pins>;
  94 + pinctrl-names = "default";
  95 +
  96 + key-1 {
  97 + gpios = <&gpio5 17 GPIO_ACTIVE_LOW>;
  98 + linux,code = <KEY_1>;
  99 + label = "SW4-1";
  100 + wakeup-source;
  101 + debounce-interval = <20>;
  102 + };
  103 + key-2 {
  104 + gpios = <&gpio5 20 GPIO_ACTIVE_LOW>;
  105 + linux,code = <KEY_2>;
  106 + label = "SW4-2";
  107 + wakeup-source;
  108 + debounce-interval = <20>;
  109 + };
  110 + key-3 {
  111 + gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
  112 + linux,code = <KEY_3>;
  113 + label = "SW4-3";
  114 + wakeup-source;
  115 + debounce-interval = <20>;
  116 + };
  117 + key-4 {
  118 + gpios = <&gpio5 23 GPIO_ACTIVE_LOW>;
  119 + linux,code = <KEY_4>;
  120 + label = "SW4-4";
  121 + wakeup-source;
  122 + debounce-interval = <20>;
  123 + };
  124 + key-a {
  125 + gpios = <&gpio6 11 GPIO_ACTIVE_LOW>;
  126 + linux,code = <KEY_A>;
  127 + label = "TSW0";
  128 + wakeup-source;
  129 + debounce-interval = <20>;
  130 + };
  131 + key-b {
  132 + gpios = <&gpio6 12 GPIO_ACTIVE_LOW>;
  133 + linux,code = <KEY_B>;
  134 + label = "TSW1";
  135 + wakeup-source;
  136 + debounce-interval = <20>;
  137 + };
  138 + key-c {
  139 + gpios = <&gpio6 13 GPIO_ACTIVE_LOW>;
  140 + linux,code = <KEY_C>;
  141 + label = "TSW2";
  142 + wakeup-source;
  143 + debounce-interval = <20>;
  144 + };
  145 + };
  146 +
89 147 reg_1p8v: regulator0 {
90 148 compatible = "regulator-fixed";
91 149 regulator-name = "fixed-1.8V";
... ... @@ -572,6 +630,11 @@
572 630 function = "intc_ex";
573 631 };
574 632  
  633 + keys_pins: keys {
  634 + pins = "GP_5_17", "GP_5_20", "GP_5_22";
  635 + bias-pull-up;
  636 + };
  637 +
575 638 pwm1_pins: pwm1 {
576 639 groups = "pwm1_a";
577 640 function = "pwm1";
... ... @@ -719,6 +782,11 @@
719 782 };
720 783 };
721 784  
  785 +&rwdt {
  786 + timeout-sec = <60>;
  787 + status = "okay";
  788 +};
  789 +
722 790 &scif1 {
723 791 pinctrl-0 = <&scif1_pins>;
724 792 pinctrl-names = "default";
... ... @@ -854,11 +922,6 @@
854 922 };
855 923  
856 924 &vin7 {
857   - status = "okay";
858   -};
859   -
860   -&rwdt {
861   - timeout-sec = <60>;
862 925 status = "okay";
863 926 };
864 927