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Commit 89d485940106c095ec69ecb12a78a42e096dece7

Authored by Marek Vasut
Committed by Stefano Babic
1 parent d339f16911
Exists in v2017.01-smarct4x and in 30 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

arm: imx6: Enable DDR calibration on Novena 

Enable the DDR calibration functionality on Novena to deal with the
memory SoDIMM on this board. Moreover, tweak the initial DDR DRAM
parameters so the calibration works properly.

Signed-off-by: Marek Vasut <marex@denx.de>

Showing 1 changed file with 14 additions and 9 deletions Side-by-side Diff

board/kosagi/novena/novena_spl.c
Diff comments   View file @ 89d4859
... ... @@ -434,8 +434,8 @@
434 434 .dram_ras = 0x00000038,
435 435 .dram_reset = 0x00000038,
436 436 /* SDCKE[0:1]: 100k pull-up */
437   - .dram_sdcke0 = 0x00003000,
438   - .dram_sdcke1 = 0x00003000,
  437 + .dram_sdcke0 = 0x00000038,
  438 + .dram_sdcke1 = 0x00000038,
439 439 /* SDBA2: pull-up disabled */
440 440 .dram_sdba2 = 0x00000000,
441 441 /* SDODT[0:1]: 100k pull-up, 40 ohm */
... ... @@ -512,10 +512,10 @@
512 512 /* Single chip select */
513 513 .ncs = 1,
514 514 .cs1_mirror = 0,
515   - .rtt_wr = 1, /* RTT_Wr = RZQ/4 */
516   - .rtt_nom = 2, /* RTT_Nom = RZQ/2 */
517   - .walat = 3, /* Write additional latency */
518   - .ralat = 7, /* Read additional latency */
  515 + .rtt_wr = 0, /* RTT_Wr = RZQ/4 */
  516 + .rtt_nom = 1, /* RTT_Nom = RZQ/2 */
  517 + .walat = 0, /* Write additional latency */
  518 + .ralat = 5, /* Read additional latency */
519 519 .mif3_mode = 3, /* Command prediction working mode */
520 520 .bi_on = 1, /* Bank interleaving enabled */
521 521 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
... ... @@ -530,9 +530,9 @@
530 530 .rowaddr = 16,
531 531 .coladdr = 10,
532 532 .pagesz = 2,
533   - .trcd = 1300,
534   - .trcmin = 4900,
535   - .trasmin = 3590,
  533 + .trcd = 1375,
  534 + .trcmin = 4875,
  535 + .trasmin = 3500,
536 536 };
537 537  
538 538 static void ccgr_init(void)
... ... @@ -600,6 +600,11 @@
600 600 /* Start the DDR DRAM */
601 601 mx6dq_dram_iocfg(64, &novena_ddr_ioregs, &novena_grp_ioregs);
602 602 mx6_dram_cfg(&novena_ddr_info, &novena_mmdc_calib, &elpida_4gib_1600);
  603 +
  604 + /* Perform DDR DRAM calibration */
  605 + udelay(100);
  606 + mmdc_do_write_level_calibration();
  607 + mmdc_do_dqs_calibration();
603 608  
604 609 /* Clear the BSS. */
605 610 memset(__bss_start, 0, __bss_end - __bss_start);