Eric Lee / smarc-uboot

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Commit 8a86dcda13140e3d89bd19eba7f65fdf936b10c0

Authored by Ye Li
1 parent 3130a174da
Exists in emb_lf_v2022.04

MLK-24958-1 clk: imx8qxp/dxl: Add clock support for LCDIF 

Add relevant clocks tree for LCDIF. According to design, LCDIF has
a slice and a dedicated eLCDIF PLL for pixel clock.
On iMX8QXP, there is pixel link mux which is muxed with LCDIF IOs.
It uses slice bypass reference clock for pix clock input.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit c189dad00743c7a3fcd80d716498289fa7cb2c40)
(cherry picked from commit 5159b4985a84be4f7a06dc8edc63e59658ca4809)
(cherry picked from commit 0cfa16a84bcdb10144d5d305cf489f7355eaab31)
(cherry picked from commit 3ba608f6ab33dd6e64bb2da0ee284b9390df4c9f)

Showing 1 changed file with 11 additions and 0 deletions Side-by-side Diff

drivers/clk/imx/clk-imx8qxp.c
Diff comments   View file @ 8a86dcd
... ... @@ -51,6 +51,11 @@
51 51 CLK_4( IMX8QXP_LSIO_FSPI0_DIV, "FSPI0_DIV", SC_R_FSPI_0, SC_PM_CLK_PER ),
52 52 CLK_4( IMX8QXP_GPMI_BCH_IO_DIV, "GPMI_IO_DIV", SC_R_NAND, SC_PM_CLK_MST_BUS ),
53 53 CLK_4( IMX8QXP_GPMI_BCH_DIV, "GPMI_BCH_DIV", SC_R_NAND, SC_PM_CLK_PER ),
  54 +
  55 + CLK_4( IMX8QXP_ELCDIF_PLL_DIV, "ELCDIF_PLL_DIV", SC_R_ELCDIF_PLL, SC_PM_CLK_PLL ),
  56 + CLK_4( IMX8QXP_LCD_PXL_DIV, "LCD_PXL_DIV", SC_R_LCD_0, SC_PM_CLK_MISC0 ),
  57 + CLK_4( IMX8QXP_LCD_DIV, "LCD_DIV", SC_R_LCD_0, SC_PM_CLK_PER ),
  58 + CLK_4( IMX8QXP_LCD_PXL_BYPASS_DIV, "LCD_PXL_BYPASS_DIV", SC_R_LCD_0, SC_PM_CLK_BYPASS ),
54 59 };
55 60  
56 61 static struct imx8_fixed_clks imx8qxp_fixed_clks[] = {
... ... @@ -193,6 +198,7 @@
193 198 CLK_5( IMX8QXP_HSIO_PHY_X1_APB_CLK, "HSIO_PHY_X1_APB_CLK", 16, HSIO_PHY_X1_LPCG, IMX8QXP_HSIO_PER_CLK ),
194 199 CLK_5( IMX8QXP_HSIO_GPIO_CLK, "HSIO_GPIO_CLK", 16, HSIO_GPIO_LPCG, IMX8QXP_HSIO_PER_CLK ),
195 200 CLK_5( IMX8QXP_HSIO_PHY_X1_PCLK, "HSIO_PHY_X1_PCLK", 0, HSIO_PHY_X1_LPCG, 0 ),
  201 + CLK_5( IMX8QXP_LCD_IPG_CLK, "LCD_IPG_CLK", 16, LCD_LPCG, IMX8QXP_IPG_DMA_CLK_ROOT ),
196 202 };
197 203  
198 204 struct imx8_mux_clks imx8qxp_mux_clks[] = {
... ... @@ -202,6 +208,11 @@
202 208 IMX8QXP_CONN_PLL1_CLK, IMX8QXP_CLK_DUMMY, IMX8QXP_CLK_DUMMY ),
203 209 CLK_MUX( IMX8QXP_SDHC2_SEL, "SDHC2_SEL", IMX8QXP_SDHC2_DIV, IMX8QXP_CLK_DUMMY, IMX8QXP_CONN_PLL0_CLK,
204 210 IMX8QXP_CONN_PLL1_CLK, IMX8QXP_CLK_DUMMY, IMX8QXP_CLK_DUMMY ),
  211 +
  212 + CLK_MUX( IMX8QXP_LCD_PXL_SEL, "LCD_PXL_SEL", IMX8QXP_LCD_PXL_DIV, IMX8QXP_CLK_DUMMY, IMX8QXP_CLK_DUMMY,
  213 + IMX8QXP_CLK_DUMMY, IMX8QXP_CLK_DUMMY, IMX8QXP_LCD_PXL_BYPASS_DIV ),
  214 + CLK_MUX( IMX8QXP_LCD_SEL, "LCD_SEL", IMX8QXP_LCD_DIV, IMX8QXP_CLK_DUMMY, IMX8QXP_CLK_DUMMY,
  215 + IMX8QXP_CLK_DUMMY, IMX8QXP_CLK_DUMMY, IMX8QXP_ELCDIF_PLL_DIV ),
205 216 };
206 217  
207 218 struct imx8_clks_collect imx8qxp_clk_collect = {