Eric Lee / smarc-uboot

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Commit 8b0044ff5942943eaa49935f49d5006b346a60f8

Authored by Oleksandr G Zhadan
Committed by York Sun
1 parent d7732faad3
Exists in v2017.01-smarct4x and in 34 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

powerpc/mpc85xx: Add board support for ucp1020 

New QorIQ p1020 based board support from Arcturus Networks Inc.
http://www.arcturusnetworks.com/products/ucp1020/

Signed-off-by: Michael Durrant <mdurrant@arcturusnetworks.com>
Signed-off-by: Oleksandr G Zhadan <oleks@arcturusnetworks.com>
[York Sun: remove patman tags from commit message]
Reviewed-by: York Sun <yorksun@freescale.com>

Showing 16 changed files with 2298 additions and 0 deletions Side-by-side Diff

arch/powerpc/cpu/mpc85xx/Kconfig
Diff comments   View file @ 8b0044f
... ... @@ -151,6 +151,9 @@
151 151 config TARGET_XPEDITE550X
152 152 bool "Support xpedite550x"
153 153  
  154 +config TARGET_UCP1020
  155 + bool "Support uCP1020"
  156 +
154 157 endchoice
155 158  
156 159 source "board/freescale/b4860qds/Kconfig"
... ... @@ -192,6 +195,7 @@
192 195 source "board/xes/xpedite520x/Kconfig"
193 196 source "board/xes/xpedite537x/Kconfig"
194 197 source "board/xes/xpedite550x/Kconfig"
  198 +source "board/Arcturus/ucp1020/Kconfig"
195 199  
196 200 endmenu
board/Arcturus/ucp1020/Kconfig
Diff comments   View file @ 8b0044f
  1 +if TARGET_UCP1020
  2 +
  3 +config SYS_BOARD
  4 + string
  5 + default "ucp1020"
  6 +
  7 +config SYS_VENDOR
  8 + string
  9 + default "Arcturus"
  10 +
  11 +config SYS_CONFIG_NAME
  12 + string
  13 + default "UCP1020"
  14 +
  15 +config SPI_FLASH
  16 + bool
  17 + default y
  18 +
  19 +config SPI_PCI
  20 + bool
  21 + default y
  22 +
  23 +choice
  24 + prompt "Target image select"
  25 +
  26 +config TARGET_UCP1020_NOR
  27 + bool "NOR flash u-boot image"
  28 +
  29 +config TARGET_UCP1020_SPIFLASH
  30 + bool "SPI flash u-boot image"
  31 +
  32 +endchoice
  33 +
  34 +if TARGET_UCP1020_SPIFLASH
  35 +config UCBOOT
  36 + bool
  37 + default y
  38 +
  39 +config SPIFLASH
  40 + bool
  41 + default y
  42 +endif
  43 +
  44 +endif
board/Arcturus/ucp1020/MAINTAINERS
Diff comments   View file @ 8b0044f
  1 +UCP1020 BOARD
  2 +M: Oleksandr Zhadan and Michael Durrant <arcsupport@arcturusnetworks.com>
  3 +S: Maintained
  4 +F: board/Arcturus/ucp1020/
  5 +F: include/configs/UCP1020.h
  6 +F: configs/UCP1020_defconfig
  7 +F: configs/UCP1020_SPIFLASH_defconfig
board/Arcturus/ucp1020/Makefile
Diff comments   View file @ 8b0044f
  1 +#
  2 +# Copyright 2013-2015 Arcturus Networks, Inc.
  3 +# based on board/freescale/p1_p2_rdb_pc/Makefile
  4 +# original copyright follows:
  5 +# Copyright 2010-2011 Freescale Semiconductor, Inc.
  6 +#
  7 +# SPDX-License-Identifier: GPL-2.0+
  8 +#
  9 +
  10 +MINIMAL=
  11 +
  12 +ifdef CONFIG_SPL_BUILD
  13 +ifdef CONFIG_SPL_INIT_MINIMAL
  14 +MINIMAL=y
  15 +endif
  16 +endif
  17 +
  18 +ifdef MINIMAL
  19 +
  20 +obj-y += spl_minimal.o tlb.o law.o
  21 +
  22 +else
  23 +ifdef CONFIG_SPL_BUILD
  24 +obj-y += spl.o
  25 +endif
  26 +
  27 +obj-y += ucp1020.o
  28 +obj-y += ddr.o
  29 +obj-y += law.o
  30 +obj-y += tlb.o
  31 +obj-y += cmd_arc.o
  32 +
  33 +endif
board/Arcturus/ucp1020/README
Diff comments   View file @ 8b0044f
  1 +The uCP1020 product family (ucp1020) is an Arcturus Networks Inc. System on Modules
  2 +product featuring a Freescale P1020 CPU, optionally populated with 1, 2 or 3 Gig-Ethernet PHYs,
  3 +DDR3, NOR Flash, eMMC NAND Flash and/or SPI Flash.
  4 +
  5 +Information on the generic product family can be found here:
  6 + http://www.arcturusnetworks.com/products/ucp1020
  7 +
  8 +The UCP1020 several configurable options
  9 +========================================
  10 +
  11 +- the selection of populated phy(s):
  12 + KSZ9031 (current default for eTSEC 1 and 3)
  13 +
  14 +- the selection of boot location:
  15 + SPI Flash or NOR flash
  16 +
  17 +The UCP1020 includes 2 default configurations
  18 +=============================================
  19 +NOR boot image:
  20 + configs/UCP1020_defconfig
  21 +SPI boot image:
  22 + configs/UCP1020_SPIFLASH_defconfig
  23 +
  24 +The UCP1020 adds an additional command in cmd_arc.c to access and program
  25 +SPI resident factory defaults for serial number, and 1, 2 or 3 Ethernet
  26 +HW Addresses.
  27 +
  28 +
  29 +Build example
  30 +=============
  31 +
  32 +make distclean
  33 +make UCP1020_defconfig
  34 +make
  35 +
  36 +Default Scripts
  37 +===============
  38 +A default upgrade scripts is included in the default environment variable example:
  39 +
  40 +B$ run tftpflash
  41 +
  42 +Dual Environment
  43 +================
  44 +
  45 +This build enables dual / failover environment environment.
  46 +
  47 +NOR Flash Partition declarations and scripts
  48 +============================================
  49 +Several scripts are available to allow TFTP of images and programming directly
  50 +into defined NOR flash partitions. Examples:
  51 +
  52 +B$ run program0
  53 +B$ run program1
  54 +B$ run program2
board/Arcturus/ucp1020/cmd_arc.c
Diff comments   View file @ 8b0044f
  1 +/*
  2 + * Command for accessing Arcturus factory environment.
  3 + *
  4 + * Copyright 2013-2015 Arcturus Networks Inc.
  5 + * http://www.arcturusnetworks.com/products/ucp1020/
  6 + * by Oleksandr G Zhadan et al.
  7 + *
  8 + * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
  9 + *
  10 + */
  11 +
  12 +#include <common.h>
  13 +#include <div64.h>
  14 +#include <malloc.h>
  15 +#include <spi_flash.h>
  16 +
  17 +#include <asm/io.h>
  18 +
  19 +#ifndef CONFIG_SF_DEFAULT_SPEED
  20 +# define CONFIG_SF_DEFAULT_SPEED 1000000
  21 +#endif
  22 +#ifndef CONFIG_SF_DEFAULT_MODE
  23 +# define CONFIG_SF_DEFAULT_MODE SPI_MODE0
  24 +#endif
  25 +#ifndef CONFIG_SF_DEFAULT_CS
  26 +# define CONFIG_SF_DEFAULT_CS 0
  27 +#endif
  28 +#ifndef CONFIG_SF_DEFAULT_BUS
  29 +# define CONFIG_SF_DEFAULT_BUS 0
  30 +#endif
  31 +
  32 +#define MAX_SERIAL_SIZE 15
  33 +#define MAX_HWADDR_SIZE 17
  34 +
  35 +#define FIRM_ADDR1 (0x200 - sizeof(smac))
  36 +#define FIRM_ADDR2 (0x400 - sizeof(smac))
  37 +#define FIRM_ADDR3 (CONFIG_ENV_SECT_SIZE + 0x200 - sizeof(smac))
  38 +#define FIRM_ADDR4 (CONFIG_ENV_SECT_SIZE + 0x400 - sizeof(smac))
  39 +
  40 +static struct spi_flash *flash;
  41 +char smac[4][18];
  42 +
  43 +static int ishwaddr(char *hwaddr)
  44 +{
  45 + if (strlen(hwaddr) == MAX_HWADDR_SIZE)
  46 + if (hwaddr[2] == ':' &&
  47 + hwaddr[5] == ':' &&
  48 + hwaddr[8] == ':' &&
  49 + hwaddr[11] == ':' &&
  50 + hwaddr[14] == ':')
  51 + return 0;
  52 + return -1;
  53 +}
  54 +
  55 +static int set_arc_product(int argc, char *const argv[])
  56 +{
  57 + int err = 0;
  58 + char *mystrerr = "ERROR: Failed to save factory info in spi location";
  59 +
  60 + if (argc != 5)
  61 + return -1;
  62 +
  63 + /* Check serial number */
  64 + if (strlen(argv[1]) != MAX_SERIAL_SIZE)
  65 + return -1;
  66 +
  67 + /* Check HWaddrs */
  68 + if (ishwaddr(argv[2]) || ishwaddr(argv[3]) || ishwaddr(argv[4]))
  69 + return -1;
  70 +
  71 + strcpy(smac[3], argv[1]);
  72 + strcpy(smac[2], argv[2]);
  73 + strcpy(smac[1], argv[3]);
  74 + strcpy(smac[0], argv[4]);
  75 +
  76 + flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
  77 + CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
  78 +
  79 + /*
  80 + * Save factory defaults
  81 + */
  82 +
  83 + if (spi_flash_write(flash, FIRM_ADDR1, sizeof(smac), smac)) {
  84 + printf("%s: %s [1]\n", __func__, mystrerr);
  85 + err++;
  86 + }
  87 + if (spi_flash_write(flash, FIRM_ADDR2, sizeof(smac), smac)) {
  88 + printf("%s: %s [2]\n", __func__, mystrerr);
  89 + err++;
  90 + }
  91 +
  92 + if (spi_flash_write(flash, FIRM_ADDR3, sizeof(smac), smac)) {
  93 + printf("%s: %s [3]\n", __func__, mystrerr);
  94 + err++;
  95 + }
  96 +
  97 + if (spi_flash_write(flash, FIRM_ADDR4, sizeof(smac), smac)) {
  98 + printf("%s: %s [4]\n", __func__, mystrerr);
  99 + err++;
  100 + }
  101 +
  102 + if (err == 4) {
  103 + printf("%s: %s [ALL]\n", __func__, mystrerr);
  104 + return -2;
  105 + }
  106 +
  107 + return 0;
  108 +}
  109 +
  110 +int get_arc_info(void)
  111 +{
  112 + int location = 1;
  113 + char *myerr = "ERROR: Failed to read all 4 factory info spi locations";
  114 +
  115 + flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
  116 + CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
  117 +
  118 + if (spi_flash_read(flash, FIRM_ADDR1, sizeof(smac), smac)) {
  119 + location++;
  120 + if (spi_flash_read(flash, FIRM_ADDR2, sizeof(smac), smac)) {
  121 + location++;
  122 + if (spi_flash_read(flash, FIRM_ADDR3, sizeof(smac),
  123 + smac)) {
  124 + location++;
  125 + if (spi_flash_read(flash, FIRM_ADDR4,
  126 + sizeof(smac), smac)) {
  127 + printf("%s: %s\n", __func__, myerr);
  128 + return -2;
  129 + }
  130 + }
  131 + }
  132 + }
  133 + if (smac[3][0] != 0) {
  134 + if (location > 1)
  135 + printf("Using region %d\n", location);
  136 + printf("SERIAL: ");
  137 + if (smac[3][0] == 0xFF) {
  138 + printf("\t<not found>\n");
  139 + } else {
  140 + printf("\t%s\n", smac[3]);
  141 + setenv("SERIAL", smac[3]);
  142 + }
  143 + }
  144 +
  145 + if (strcmp(smac[2], "00:00:00:00:00:00") == 0)
  146 + return 0;
  147 +
  148 + printf("HWADDR0:");
  149 + if (smac[2][0] == 0xFF) {
  150 + printf("\t<not found>\n");
  151 + } else {
  152 + char *ret = getenv("ethaddr");
  153 +
  154 + if (strcmp(ret, __stringify(CONFIG_ETHADDR)) == 0) {
  155 + setenv("ethaddr", smac[2]);
  156 + printf("\t%s (factory)\n", smac[2]);
  157 + } else {
  158 + printf("\t%s\n", ret);
  159 + }
  160 + }
  161 +
  162 + if (strcmp(smac[1], "00:00:00:00:00:00") == 0) {
  163 + setenv("eth1addr", smac[2]);
  164 + setenv("eth2addr", smac[2]);
  165 + return 0;
  166 + }
  167 +
  168 + printf("HWADDR1:");
  169 + if (smac[1][0] == 0xFF) {
  170 + printf("\t<not found>\n");
  171 + } else {
  172 + char *ret = getenv("eth1addr");
  173 +
  174 + if (strcmp(ret, __stringify(CONFIG_ETH1ADDR)) == 0) {
  175 + setenv("eth1addr", smac[1]);
  176 + printf("\t%s (factory)\n", smac[1]);
  177 + } else {
  178 + printf("\t%s\n", ret);
  179 + }
  180 + }
  181 +
  182 + if (strcmp(smac[0], "00:00:00:00:00:00") == 0) {
  183 + setenv("eth2addr", smac[1]);
  184 + return 0;
  185 + }
  186 +
  187 + printf("HWADDR2:");
  188 + if (smac[0][0] == 0xFF) {
  189 + printf("\t<not found>\n");
  190 + } else {
  191 + char *ret = getenv("eth2addr");
  192 +
  193 + if (strcmp(ret, __stringify(CONFIG_ETH2ADDR)) == 0) {
  194 + setenv("eth2addr", smac[0]);
  195 + printf("\t%s (factory)\n", smac[0]);
  196 + } else {
  197 + printf("\t%s\n", ret);
  198 + }
  199 + }
  200 +
  201 + return 0;
  202 +}
  203 +
  204 +static int do_arc_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
  205 +{
  206 + const char *cmd;
  207 + int ret = -1;
  208 +
  209 + cmd = argv[1];
  210 + --argc;
  211 + ++argv;
  212 +
  213 + if (strcmp(cmd, "product") == 0) {
  214 + ret = set_arc_product(argc, argv);
  215 + goto done;
  216 + }
  217 + if (strcmp(cmd, "info") == 0) {
  218 + ret = get_arc_info();
  219 + goto done;
  220 + }
  221 +done:
  222 + if (ret == -1)
  223 + return CMD_RET_USAGE;
  224 +
  225 + return ret;
  226 +}
  227 +
  228 +U_BOOT_CMD(arc, 6, 1, do_arc_cmd,
  229 + "Arcturus product command sub-system",
  230 + "product serial hwaddr0 hwaddr1 hwaddr2 - save Arcturus factory env\n"
  231 + "info - show Arcturus factory env\n\n");
board/Arcturus/ucp1020/ddr.c
Diff comments   View file @ 8b0044f
  1 +/*
  2 + * Copyright 2013-2015 Arcturus Networks, Inc.
  3 + * http://www.arcturusnetworks.com/products/ucp1020/
  4 + * based on board/freescale/p1_p2_rdb_pc/spl.c
  5 + * original copyright follows:
  6 + * Copyright 2013 Freescale Semiconductor, Inc.
  7 + *
  8 + * SPDX-License-Identifier: GPL-2.0+
  9 + */
  10 +
  11 +#include <common.h>
  12 +#include <asm/mmu.h>
  13 +#include <asm/immap_85xx.h>
  14 +#include <asm/processor.h>
  15 +#include <fsl_ddr_sdram.h>
  16 +#include <fsl_ddr_dimm_params.h>
  17 +#include <asm/io.h>
  18 +#include <asm/fsl_law.h>
  19 +
  20 +#ifdef CONFIG_SYS_DDR_RAW_TIMING
  21 +#if defined(CONFIG_UCP1020) || defined(CONFIG_UCP1020T1)
  22 +/*
  23 + * Micron MT41J128M16HA-15E
  24 + * */
  25 +dimm_params_t ddr_raw_timing = {
  26 + .n_ranks = 1,
  27 + .rank_density = 536870912u,
  28 + .capacity = 536870912u,
  29 + .primary_sdram_width = 32,
  30 + .ec_sdram_width = 8,
  31 + .registered_dimm = 0,
  32 + .mirrored_dimm = 0,
  33 + .n_row_addr = 14,
  34 + .n_col_addr = 10,
  35 + .n_banks_per_sdram_device = 8,
  36 + .edc_config = 2,
  37 + .burst_lengths_bitmask = 0x0c,
  38 +
  39 + .tckmin_x_ps = 1650,
  40 + .caslat_x = 0x7e << 4, /* 5,6,7,8,9,10 */
  41 + .taa_ps = 14050,
  42 + .twr_ps = 15000,
  43 + .trcd_ps = 13500,
  44 + .trrd_ps = 75000,
  45 + .trp_ps = 13500,
  46 + .tras_ps = 40000,
  47 + .trc_ps = 49500,
  48 + .trfc_ps = 160000,
  49 + .twtr_ps = 75000,
  50 + .trtp_ps = 75000,
  51 + .refresh_rate_ps = 7800000,
  52 + .tfaw_ps = 30000,
  53 +};
  54 +
  55 +#else
  56 +#error Missing raw timing data for this board
  57 +#endif
  58 +
  59 +int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
  60 + unsigned int controller_number,
  61 + unsigned int dimm_number)
  62 +{
  63 + const char dimm_model[] = "Fixed DDR on board";
  64 +
  65 + if ((controller_number == 0) && (dimm_number == 0)) {
  66 + memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
  67 + memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
  68 + memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
  69 + }
  70 +
  71 + return 0;
  72 +}
  73 +#endif /* CONFIG_SYS_DDR_RAW_TIMING */
  74 +
  75 +#ifdef CONFIG_SYS_DDR_CS0_BNDS
  76 +/* Fixed sdram init -- doesn't use serial presence detect. */
  77 +phys_size_t fixed_sdram(void)
  78 +{
  79 + sys_info_t sysinfo;
  80 + char buf[32];
  81 + size_t ddr_size;
  82 + fsl_ddr_cfg_regs_t ddr_cfg_regs = {
  83 + .cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
  84 + .cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
  85 + .cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
  86 +#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
  87 + .cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
  88 + .cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
  89 + .cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2,
  90 +#endif
  91 + .timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3,
  92 + .timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0,
  93 + .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1,
  94 + .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2,
  95 + .ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
  96 + .ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
  97 + .ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1,
  98 + .ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2,
  99 + .ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
  100 + .ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL,
  101 + .ddr_data_init = CONFIG_SYS_DDR_DATA_INIT,
  102 + .ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL,
  103 + .ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
  104 + .ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
  105 + .timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
  106 + .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
  107 + .ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
  108 + .ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
  109 + .ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
  110 + .ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
  111 + .ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
  112 + };
  113 +
  114 + get_sys_info(&sysinfo);
  115 + printf("Configuring DDR for %s MT/s data rate\n",
  116 + strmhz(buf, sysinfo.freq_ddrbus));
  117 +
  118 + ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
  119 +
  120 + fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
  121 +
  122 + if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
  123 + ddr_size, LAW_TRGT_IF_DDR_1) < 0) {
  124 + printf("ERROR setting Local Access Windows for DDR\n");
  125 + return 0;
  126 + };
  127 +
  128 + return ddr_size;
  129 +}
  130 +#endif
  131 +
  132 +void fsl_ddr_board_options(memctl_options_t *popts,
  133 + dimm_params_t *pdimm,
  134 + unsigned int ctrl_num)
  135 +{
  136 + int i;
  137 +
  138 + popts->clk_adjust = 6;
  139 + popts->cpo_override = 0x1f;
  140 + popts->write_data_delay = 2;
  141 + popts->half_strength_driver_enable = 1;
  142 + /* Write leveling override */
  143 + popts->wrlvl_en = 1;
  144 + popts->wrlvl_override = 1;
  145 + popts->wrlvl_sample = 0xf;
  146 + popts->wrlvl_start = 0x8;
  147 + popts->trwt_override = 1;
  148 + popts->trwt = 0;
  149 +
  150 + if (pdimm->primary_sdram_width == 64)
  151 + popts->data_bus_width = 0;
  152 + else if (pdimm->primary_sdram_width == 32)
  153 + popts->data_bus_width = 1;
  154 + else
  155 + printf("Error in DDR bus width configuration!\n");
  156 +
  157 + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  158 + popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
  159 + popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
  160 + }
  161 +}
board/Arcturus/ucp1020/law.c
Diff comments   View file @ 8b0044f
  1 +/*
  2 + * Copyright 2013-2015 Arcturus Networks, Inc.
  3 + * http://www.arcturusnetworks.com/products/ucp1020/
  4 + * based on board/freescale/p1_p2_rdb_pc/spl.c
  5 + * original copyright follows:
  6 + * Copyright 2013 Freescale Semiconductor, Inc.
  7 + *
  8 + * SPDX-License-Identifier: GPL-2.0+
  9 + */
  10 +
  11 +#include <common.h>
  12 +#include <asm/fsl_law.h>
  13 +#include <asm/mmu.h>
  14 +
  15 +struct law_entry law_table[] = {
  16 +#ifdef CONFIG_VSC7385_ENET
  17 + SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
  18 +#endif
  19 + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
  20 +#ifdef CONFIG_SYS_NAND_BASE_PHYS
  21 + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC),
  22 +#endif
  23 +};
  24 +
  25 +int num_law_entries = ARRAY_SIZE(law_table);
board/Arcturus/ucp1020/spl.c
Diff comments   View file @ 8b0044f
  1 +/*
  2 + * Copyright 2013-2015 Arcturus Networks, Inc.
  3 + * http://www.arcturusnetworks.com/products/ucp1020/
  4 + * based on board/freescale/p1_p2_rdb_pc/spl.c
  5 + * original copyright follows:
  6 + * Copyright 2013 Freescale Semiconductor, Inc.
  7 + *
  8 + * SPDX-License-Identifier: GPL-2.0+
  9 + */
  10 +
  11 +#include <common.h>
  12 +#include <ns16550.h>
  13 +#include <malloc.h>
  14 +#include <mmc.h>
  15 +#include <nand.h>
  16 +#include <i2c.h>
  17 +#include <fsl_esdhc.h>
  18 +#include <spi_flash.h>
  19 +
  20 +DECLARE_GLOBAL_DATA_PTR;
  21 +
  22 +static const u32 sysclk_tbl[] = {
  23 + 66666000, 7499900, 83332500, 8999900,
  24 + 99999000, 11111000, 12499800, 13333200
  25 +};
  26 +
  27 +phys_size_t get_effective_memsize(void)
  28 +{
  29 + return CONFIG_SYS_L2_SIZE;
  30 +}
  31 +
  32 +void board_init_f(ulong bootflag)
  33 +{
  34 + u32 plat_ratio, bus_clk;
  35 + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
  36 +
  37 + console_init_f();
  38 +
  39 + /* Set pmuxcr to allow both i2c1 and i2c2 */
  40 + setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000);
  41 + setbits_be32(&gur->pmuxcr,
  42 + in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
  43 +
  44 + /* Read back the register to synchronize the write. */
  45 + in_be32(&gur->pmuxcr);
  46 +
  47 +#ifdef CONFIG_SPL_SPI_BOOT
  48 + clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
  49 +#endif
  50 +
  51 + /* initialize selected port with appropriate baud rate */
  52 + plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
  53 + plat_ratio >>= 1;
  54 + bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
  55 + gd->bus_clk = bus_clk;
  56 +
  57 + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
  58 + bus_clk / 16 / CONFIG_BAUDRATE);
  59 +#ifdef CONFIG_SPL_MMC_BOOT
  60 + puts("\nSD boot...\n");
  61 +#elif defined(CONFIG_SPL_SPI_BOOT)
  62 + puts("\nSPI Flash boot...\n");
  63 +#endif
  64 +
  65 + /* copy code to RAM and jump to it - this should not return */
  66 + /* NOTE - code has to be copied out of NAND buffer before
  67 + * other blocks can be read.
  68 + */
  69 + relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
  70 +}
  71 +
  72 +void board_init_r(gd_t *gd, ulong dest_addr)
  73 +{
  74 + /* Pointer is writable since we allocated a register for it */
  75 + gd = (gd_t *)CONFIG_SPL_GD_ADDR;
  76 + bd_t *bd;
  77 +
  78 + memset(gd, 0, sizeof(gd_t));
  79 + bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
  80 + memset(bd, 0, sizeof(bd_t));
  81 + gd->bd = bd;
  82 + bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
  83 + bd->bi_memsize = CONFIG_SYS_L2_SIZE;
  84 +
  85 + probecpu();
  86 + get_clocks();
  87 + mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
  88 + CONFIG_SPL_RELOC_MALLOC_SIZE);
  89 +
  90 +#ifndef CONFIG_SPL_NAND_BOOT
  91 + env_init();
  92 +#endif
  93 +#ifdef CONFIG_SPL_MMC_BOOT
  94 + mmc_initialize(bd);
  95 +#endif
  96 + /* relocate environment function pointers etc. */
  97 +#ifdef CONFIG_SPL_NAND_BOOT
  98 + nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
  99 + (uchar *)CONFIG_ENV_ADDR);
  100 + gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
  101 + gd->env_valid = 1;
  102 +#else
  103 + env_relocate();
  104 +#endif
  105 +
  106 +#ifdef CONFIG_SYS_I2C
  107 + i2c_init_all();
  108 +#else
  109 + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
  110 +#endif
  111 +
  112 + gd->ram_size = initdram(0);
  113 +#ifdef CONFIG_SPL_NAND_BOOT
  114 + puts("Tertiary program loader running in sram...");
  115 +#else
  116 + puts("Second program loader running in sram...\n");
  117 +#endif
  118 +
  119 +#ifdef CONFIG_SPL_MMC_BOOT
  120 + mmc_boot();
  121 +#elif defined(CONFIG_SPL_SPI_BOOT)
  122 + spi_boot();
  123 +#elif defined(CONFIG_SPL_NAND_BOOT)
  124 + nand_boot();
  125 +#endif
  126 +}
board/Arcturus/ucp1020/spl_minimal.c
Diff comments   View file @ 8b0044f
  1 +/*
  2 + * Copyright 2013-2015 Arcturus Networks, Inc.
  3 + * http://www.arcturusnetworks.com/products/ucp1020/
  4 + * based on board/freescale/p1_p2_rdb_pc/spl_minimal.c
  5 + * original copyright follows:
  6 + * Copyright 2011 Freescale Semiconductor, Inc.
  7 + *
  8 + * SPDX-License-Identifier: GPL-2.0+
  9 + */
  10 +
  11 +#include <common.h>
  12 +#include <ns16550.h>
  13 +#include <asm/io.h>
  14 +#include <nand.h>
  15 +#include <linux/compiler.h>
  16 +#include <asm/fsl_law.h>
  17 +#include <fsl_ddr_sdram.h>
  18 +#include <asm/global_data.h>
  19 +
  20 +DECLARE_GLOBAL_DATA_PTR;
  21 +
  22 +void board_init_f(ulong bootflag)
  23 +{
  24 + u32 plat_ratio;
  25 + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
  26 +
  27 +#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
  28 + set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
  29 + set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
  30 +#endif
  31 +
  32 + /* initialize selected port with appropriate baud rate */
  33 + plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
  34 + plat_ratio >>= 1;
  35 + gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
  36 +
  37 + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
  38 + gd->bus_clk / 16 / CONFIG_BAUDRATE);
  39 +
  40 + puts("\nNAND boot... ");
  41 +
  42 + /* copy code to RAM and jump to it - this should not return */
  43 + /* NOTE - code has to be copied out of NAND buffer before
  44 + * other blocks can be read.
  45 + */
  46 + relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
  47 +}
  48 +
  49 +void board_init_r(gd_t *gd, ulong dest_addr)
  50 +{
  51 + puts("\nSecond program loader running in sram...");
  52 + nand_boot();
  53 +}
  54 +
  55 +void putc(char c)
  56 +{
  57 + if (c == '\n')
  58 + NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
  59 +
  60 + NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
  61 +}
  62 +
  63 +void puts(const char *str)
  64 +{
  65 + while (*str)
  66 + putc(*str++);
  67 +}
board/Arcturus/ucp1020/tlb.c
Diff comments   View file @ 8b0044f
  1 +/*
  2 + * Copyright 2013-2015 Arcturus Networks, Inc
  3 + * http://www.arcturusnetworks.com/products/ucp1020/
  4 + * based on board/freescale/p1_p2_rdb_pc/tlb.c
  5 + * original copyright follows:
  6 + * Copyright 2010-2011 Freescale Semiconductor, Inc.
  7 + *
  8 + * SPDX-License-Identifier: GPL-2.0+
  9 + */
  10 +
  11 +#include <common.h>
  12 +#include <asm/mmu.h>
  13 +
  14 +struct fsl_e_tlb_entry tlb_table[] = {
  15 + /* TLB 0 - for temp stack in cache */
  16 + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
  17 + CONFIG_SYS_INIT_RAM_ADDR_PHYS,
  18 + MAS3_SX | MAS3_SW | MAS3_SR, 0,
  19 + 0, 0, BOOKE_PAGESZ_4K, 0),
  20 + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  21 + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
  22 + MAS3_SX | MAS3_SW | MAS3_SR, 0,
  23 + 0, 0, BOOKE_PAGESZ_4K, 0),
  24 + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  25 + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
  26 + MAS3_SX | MAS3_SW | MAS3_SR, 0,
  27 + 0, 0, BOOKE_PAGESZ_4K, 0),
  28 + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  29 + CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
  30 + MAS3_SX | MAS3_SW | MAS3_SR, 0,
  31 + 0, 0, BOOKE_PAGESZ_4K, 0),
  32 +
  33 + /* TLB 1 */
  34 + /* *I*** - Covers boot page */
  35 + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
  36 + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I,
  37 + 0, 0, BOOKE_PAGESZ_4K, 1),
  38 +
  39 + /* *I*G* - CCSRBAR */
  40 + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
  41 + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
  42 + 0, 1, BOOKE_PAGESZ_1M, 1),
  43 +
  44 +#ifndef CONFIG_SPL_BUILD
  45 + /* W**G* - Flash/promjet, localbus */
  46 + /* This will be changed to *I*G* after relocation to RAM. */
  47 + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
  48 + MAS3_SX | MAS3_SR, MAS2_W | MAS2_G,
  49 + 0, 2, BOOKE_PAGESZ_64M, 1),
  50 +
  51 +#ifdef CONFIG_PCI
  52 + /* *I*G* - PCI memory 1.5G */
  53 + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
  54 + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
  55 + 0, 3, BOOKE_PAGESZ_1G, 1),
  56 +
  57 + /* *I*G* - PCI I/O effective: 192K */
  58 + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
  59 + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
  60 + 0, 4, BOOKE_PAGESZ_256K, 1),
  61 +#endif
  62 +
  63 +#ifdef CONFIG_VSC7385_ENET
  64 + /* *I*G - VSC7385 Switch */
  65 + SET_TLB_ENTRY(1, CONFIG_SYS_VSC7385_BASE, CONFIG_SYS_VSC7385_BASE_PHYS,
  66 + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
  67 + 0, 5, BOOKE_PAGESZ_1M, 1),
  68 +#endif
  69 +#endif /* not SPL */
  70 +
  71 +#ifdef CONFIG_SYS_NAND_BASE
  72 + /* *I*G - NAND */
  73 + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
  74 + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
  75 + 0, 7, BOOKE_PAGESZ_1M, 1),
  76 +#endif
  77 +
  78 +#if defined(CONFIG_SYS_RAMBOOT) || \
  79 + (defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
  80 + /* *I*G - eSDHC/eSPI/NAND boot */
  81 + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
  82 + MAS3_SX | MAS3_SW | MAS3_SR, 0,
  83 + 0, 8, BOOKE_PAGESZ_1G, 1),
  84 +
  85 +#endif /* RAMBOOT/SPL */
  86 +
  87 +#ifdef CONFIG_SYS_INIT_L2_ADDR
  88 + /* *I*G - L2SRAM */
  89 + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
  90 + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_G,
  91 + 0, 11, BOOKE_PAGESZ_256K, 1),
  92 +#if CONFIG_SYS_L2_SIZE >= (256 << 10)
  93 + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
  94 + CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
  95 + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
  96 + 0, 12, BOOKE_PAGESZ_256K, 1)
  97 +#endif
  98 +#endif
  99 +};
  100 +
  101 +int num_tlb_entries = ARRAY_SIZE(tlb_table);
board/Arcturus/ucp1020/ucp1020.c
Diff comments   View file @ 8b0044f
  1 +/*
  2 + * Copyright 2013-2015 Arcturus Networks, Inc.
  3 + * http://www.arcturusnetworks.com/products/ucp1020/
  4 + * by Oleksandr G Zhadan et al.
  5 + * based on board/freescale/p1_p2_rdb_pc/spl.c
  6 + * original copyright follows:
  7 + * Copyright 2013 Freescale Semiconductor, Inc.
  8 + *
  9 + * SPDX-License-Identifier: GPL-2.0+
  10 + */
  11 +
  12 +#include <common.h>
  13 +#include <command.h>
  14 +#include <hwconfig.h>
  15 +#include <pci.h>
  16 +#include <i2c.h>
  17 +#include <miiphy.h>
  18 +#include <libfdt.h>
  19 +#include <fdt_support.h>
  20 +#include <fsl_mdio.h>
  21 +#include <tsec.h>
  22 +#include <ioports.h>
  23 +#include <netdev.h>
  24 +#include <micrel.h>
  25 +#include <spi_flash.h>
  26 +#include <mmc.h>
  27 +#include <linux/ctype.h>
  28 +#include <asm/fsl_serdes.h>
  29 +#include <asm/gpio.h>
  30 +#include <asm/processor.h>
  31 +#include <asm/mmu.h>
  32 +#include <asm/cache.h>
  33 +#include <asm/immap_85xx.h>
  34 +#include <asm/fsl_pci.h>
  35 +#include <fsl_ddr_sdram.h>
  36 +#include <asm/io.h>
  37 +#include <asm/fsl_law.h>
  38 +#include <asm/fsl_lbc.h>
  39 +#include <asm/mp.h>
  40 +#include "ucp1020.h"
  41 +
  42 +void spi_set_speed(struct spi_slave *slave, uint hz)
  43 +{
  44 + /* TO DO: It's actially have to be in spi/ */
  45 +}
  46 +
  47 +/*
  48 + * To be compatible with cmd_gpio
  49 + */
  50 +int name_to_gpio(const char *name)
  51 +{
  52 + int gpio = 31 - simple_strtoul(name, NULL, 10);
  53 +
  54 + if (gpio < 16)
  55 + gpio = -1;
  56 +
  57 + return gpio;
  58 +}
  59 +
  60 +void board_gpio_init(void)
  61 +{
  62 + int i;
  63 + char envname[8], *val;
  64 +
  65 + for (i = 0; i < GPIO_MAX_NUM; i++) {
  66 + sprintf(envname, "GPIO%d", i);
  67 + val = getenv(envname);
  68 + if (val) {
  69 + char direction = toupper(val[0]);
  70 + char level = toupper(val[1]);
  71 +
  72 + if (direction == 'I') {
  73 + gpio_direction_input(i);
  74 + } else {
  75 + if (direction == 'O') {
  76 + if (level == '1')
  77 + gpio_direction_output(i, 1);
  78 + else
  79 + gpio_direction_output(i, 0);
  80 + }
  81 + }
  82 + }
  83 + }
  84 +
  85 + val = getenv("PCIE_OFF");
  86 + if (val) {
  87 + gpio_direction_input(GPIO_PCIE1_EN);
  88 + gpio_direction_input(GPIO_PCIE2_EN);
  89 + } else {
  90 + gpio_direction_output(GPIO_PCIE1_EN, 1);
  91 + gpio_direction_output(GPIO_PCIE2_EN, 1);
  92 + }
  93 +
  94 + val = getenv("SDHC_CDWP_OFF");
  95 + if (!val) {
  96 + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  97 +
  98 + setbits_be32(&gur->pmuxcr,
  99 + (MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP));
  100 + }
  101 +}
  102 +
  103 +int board_early_init_f(void)
  104 +{
  105 + return 0; /* Just in case. Could be disable in config file */
  106 +}
  107 +
  108 +int checkboard(void)
  109 +{
  110 + printf("Board: %s\n", CONFIG_BOARDNAME_LOCAL);
  111 + board_gpio_init();
  112 + printf("SD/MMC: 4-bit Mode\n");
  113 +
  114 + return 0;
  115 +}
  116 +
  117 +#ifdef CONFIG_PCI
  118 +void pci_init_board(void)
  119 +{
  120 + fsl_pcie_init_board(0);
  121 +}
  122 +#endif
  123 +
  124 +int board_early_init_r(void)
  125 +{
  126 + const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
  127 + const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
  128 +
  129 + /*
  130 + * Remap Boot flash region to caching-inhibited
  131 + * so that flash can be erased properly.
  132 + */
  133 +
  134 + /* Flush d-cache and invalidate i-cache of any FLASH data */
  135 + flush_dcache();
  136 + invalidate_icache();
  137 +
  138 + /* invalidate existing TLB entry for flash */
  139 + disable_tlb(flash_esel);
  140 +
  141 + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
  142 + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, /* perms, wimge */
  143 + 0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */
  144 +
  145 + return 0;
  146 +}
  147 +
  148 +int board_phy_config(struct phy_device *phydev)
  149 +{
  150 +#if defined(CONFIG_PHY_MICREL_KSZ9021)
  151 + int regval;
  152 + static int cnt;
  153 +
  154 + if (cnt++ == 0)
  155 + printf("PHYs address [");
  156 +
  157 + if (phydev->addr == TSEC1_PHY_ADDR || phydev->addr == TSEC3_PHY_ADDR) {
  158 + regval =
  159 + ksz9021_phy_extended_read(phydev,
  160 + MII_KSZ9021_EXT_STRAP_STATUS);
  161 + /*
  162 + * min rx data delay
  163 + */
  164 + ksz9021_phy_extended_write(phydev,
  165 + MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
  166 + 0x6666);
  167 + /*
  168 + * max rx/tx clock delay, min rx/tx control
  169 + */
  170 + ksz9021_phy_extended_write(phydev,
  171 + MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
  172 + 0xf6f6);
  173 + printf("0x%x", (regval & 0x1f));
  174 + } else {
  175 + printf("0x%x", (TSEC2_PHY_ADDR & 0x1f));
  176 + }
  177 + if (cnt == 3)
  178 + printf("] ");
  179 + else
  180 + printf(",");
  181 +#endif
  182 +
  183 +#if defined(CONFIG_PHY_MICREL_KSZ9031_DEBUG)
  184 + regval = ksz9031_phy_extended_read(phydev, 2, 0x01, 0x4000);
  185 + if (regval >= 0)
  186 + printf(" (ADDR 0x%x) ", regval & 0x1f);
  187 +#endif
  188 +
  189 + return 0;
  190 +}
  191 +
  192 +int last_stage_init(void)
  193 +{
  194 + static char newkernelargs[256];
  195 + static u8 id1[16];
  196 + static u8 id2;
  197 + struct mmc *mmc;
  198 + char *sval, *kval;
  199 +
  200 + if (i2c_read(CONFIG_SYS_I2C_IDT6V49205B, 7, 1, &id1[0], 2) < 0) {
  201 + printf("Error reading i2c IDT6V49205B information!\n");
  202 + } else {
  203 + printf("IDT6V49205B(0x%02x): ready\n", id1[1]);
  204 + i2c_read(CONFIG_SYS_I2C_IDT6V49205B, 4, 1, &id1[0], 2);
  205 + if (!(id1[1] & 0x02)) {
  206 + id1[1] |= 0x02;
  207 + i2c_write(CONFIG_SYS_I2C_IDT6V49205B, 4, 1, &id1[0], 2);
  208 + asm("nop; nop");
  209 + }
  210 + }
  211 +
  212 + if (i2c_read(CONFIG_SYS_I2C_NCT72_ADDR, 0xFE, 1, &id2, 1) < 0)
  213 + printf("Error reading i2c NCT72 information!\n");
  214 + else
  215 + printf("NCT72(0x%x): ready\n", id2);
  216 +
  217 + kval = getenv("kernelargs");
  218 +
  219 + mmc = find_mmc_device(0);
  220 + if (mmc)
  221 + if (!mmc_init(mmc)) {
  222 + printf("MMC/SD card detected\n");
  223 + if (kval) {
  224 + int n = strlen(defkargs);
  225 + char *tmp = strstr(kval, defkargs);
  226 +
  227 + *tmp = 0;
  228 + strcpy(newkernelargs, kval);
  229 + strcat(newkernelargs, " ");
  230 + strcat(newkernelargs, mmckargs);
  231 + strcat(newkernelargs, " ");
  232 + strcat(newkernelargs, &tmp[n]);
  233 + setenv("kernelargs", newkernelargs);
  234 + } else {
  235 + setenv("kernelargs", mmckargs);
  236 + }
  237 + }
  238 + get_arc_info();
  239 +
  240 + if (kval) {
  241 + sval = getenv("SERIAL");
  242 + if (sval) {
  243 + strcpy(newkernelargs, "SN=");
  244 + strcat(newkernelargs, sval);
  245 + strcat(newkernelargs, " ");
  246 + strcat(newkernelargs, kval);
  247 + setenv("kernelargs", newkernelargs);
  248 + }
  249 + } else {
  250 + printf("Error reading kernelargs env variable!\n");
  251 + }
  252 +
  253 + return 0;
  254 +}
  255 +
  256 +int board_eth_init(bd_t *bis)
  257 +{
  258 + struct fsl_pq_mdio_info mdio_info;
  259 + struct tsec_info_struct tsec_info[4];
  260 +#ifdef CONFIG_TSEC2
  261 + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  262 +#endif
  263 + int num = 0;
  264 +
  265 +#ifdef CONFIG_TSEC1
  266 + SET_STD_TSEC_INFO(tsec_info[num], 1);
  267 + num++;
  268 +#endif
  269 +#ifdef CONFIG_TSEC2
  270 + SET_STD_TSEC_INFO(tsec_info[num], 2);
  271 + if (is_serdes_configured(SGMII_TSEC2)) {
  272 + if (!(in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_SGMII2_DIS)) {
  273 + puts("eTSEC2 is in sgmii mode.\n");
  274 + tsec_info[num].flags |= TSEC_SGMII;
  275 + tsec_info[num].phyaddr = TSEC2_PHY_ADDR_SGMII;
  276 + }
  277 + }
  278 + num++;
  279 +#endif
  280 +#ifdef CONFIG_TSEC3
  281 + SET_STD_TSEC_INFO(tsec_info[num], 3);
  282 + num++;
  283 +#endif
  284 +
  285 + if (!num) {
  286 + printf("No TSECs initialized\n");
  287 + return 0;
  288 + }
  289 +
  290 + mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
  291 + mdio_info.name = DEFAULT_MII_NAME;
  292 +
  293 + fsl_pq_mdio_init(bis, &mdio_info);
  294 +
  295 + tsec_eth_init(bis, tsec_info, num);
  296 +
  297 + return pci_eth_init(bis);
  298 +}
  299 +
  300 +#ifdef CONFIG_OF_BOARD_SETUP
  301 +int ft_board_setup(void *blob, bd_t *bd)
  302 +{
  303 + phys_addr_t base;
  304 + phys_size_t size;
  305 + const char *soc_usb_compat = "fsl-usb2-dr";
  306 + int err, usb1_off, usb2_off;
  307 +
  308 + ft_cpu_setup(blob, bd);
  309 +
  310 + base = getenv_bootm_low();
  311 + size = getenv_bootm_size();
  312 +
  313 + fdt_fixup_memory(blob, (u64)base, (u64)size);
  314 +
  315 + FT_FSL_PCI_SETUP;
  316 +
  317 +#if defined(CONFIG_HAS_FSL_DR_USB)
  318 + fdt_fixup_dr_usb(blob, bd);
  319 +#endif
  320 +
  321 +#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
  322 + /* Delete eLBC node as it is muxed with USB2 controller */
  323 + if (hwconfig("usb2")) {
  324 + const char *soc_elbc_compat = "fsl,p1020-elbc";
  325 + int off = fdt_node_offset_by_compatible(blob, -1,
  326 + soc_elbc_compat);
  327 + if (off < 0) {
  328 + printf
  329 + ("WARNING: could not find compatible node %s: %s\n",
  330 + soc_elbc_compat, fdt_strerror(off));
  331 + return off;
  332 + }
  333 + err = fdt_del_node(blob, off);
  334 + if (err < 0) {
  335 + printf("WARNING: could not remove %s: %s\n",
  336 + soc_elbc_compat, fdt_strerror(err));
  337 + }
  338 + return err;
  339 + }
  340 +#endif
  341 +
  342 +/* Delete USB2 node as it is muxed with eLBC */
  343 + usb1_off = fdt_node_offset_by_compatible(blob, -1, soc_usb_compat);
  344 + if (usb1_off < 0) {
  345 + printf("WARNING: could not find compatible node %s: %s.\n",
  346 + soc_usb_compat, fdt_strerror(usb1_off));
  347 + return usb1_off;
  348 + }
  349 + usb2_off =
  350 + fdt_node_offset_by_compatible(blob, usb1_off, soc_usb_compat);
  351 + if (usb2_off < 0) {
  352 + printf("WARNING: could not find compatible node %s: %s.\n",
  353 + soc_usb_compat, fdt_strerror(usb2_off));
  354 + return usb2_off;
  355 + }
  356 + err = fdt_del_node(blob, usb2_off);
  357 + if (err < 0) {
  358 + printf("WARNING: could not remove %s: %s.\n",
  359 + soc_usb_compat, fdt_strerror(err));
  360 + }
  361 + return 0;
  362 +}
  363 +#endif
board/Arcturus/ucp1020/ucp1020.h
Diff comments   View file @ 8b0044f
  1 +/*
  2 + * Copyright 2013-2015 Arcturus Networks, Inc.
  3 + * http://www.arcturusnetworks.com/products/ucp1020/
  4 + * by Oleksandr G Zhadan et al.
  5 + *
  6 + * SPDX-License-Identifier: GPL-2.0+
  7 + */
  8 +
  9 +#ifndef __UCP1020_H__
  10 +#define __UCP1020_H__
  11 +
  12 +#define GPIO0 31
  13 +#define GPIO1 30
  14 +#define GPIO2 29
  15 +#define GPIO3 28
  16 +#define GPIO4 27
  17 +#define GPIO5 26
  18 +#define GPIO6 25
  19 +#define GPIO7 24
  20 +#define GPIO8 23
  21 +#define GPIO9 22
  22 +#define GPIO10 21
  23 +#define GPIO11 20
  24 +#define GPIO12 19
  25 +#define GPIO13 18
  26 +#define GPIO14 17
  27 +#define GPIO15 16
  28 +#define GPIO_MAX_NUM 16
  29 +
  30 +#define GPIO_SDHC_CD GPIO8
  31 +#define GPIO_SDHC_WP GPIO9
  32 +#define GPIO_USB_PCTL0 GPIO10
  33 +#define GPIO_PCIE1_EN GPIO11
  34 +#define GPIO_PCIE2_EN GPIO10
  35 +#define GPIO_USB_PCTL1 GPIO11
  36 +
  37 +#define GPIO_WD GPIO15
  38 +
  39 +static char *defkargs = "root=/dev/mtdblock1 rootfstype=cramfs ro";
  40 +static char *mmckargs = "root=/dev/mmcblk0p1 rootwait rw";
  41 +
  42 +int get_arc_info(void);
  43 +
  44 +#endif
configs/UCP1020_SPIFLASH_defconfig
Diff comments   View file @ 8b0044f
  1 +CONFIG_PPC=y
  2 +CONFIG_MPC85xx=y
  3 +CONFIG_TARGET_UCP1020=y
  4 +CONFIG_TARGET_UCP1020_SPIFLASH=y
  5 +CONFIG_SPI_FLASH=y
  6 +CONFIG_UCP1020=y
configs/UCP1020_defconfig
Diff comments   View file @ 8b0044f
  1 +CONFIG_PPC=y
  2 +CONFIG_MPC85xx=y
  3 +CONFIG_TARGET_UCP1020=y
  4 +CONFIG_SPI_FLASH=y
  5 +CONFIG_UCP1020=y
include/configs/UCP1020.h
Diff comments   View file @ 8b0044f
Changes suppressed. Click to show
  1 +/*
  2 + * Copyright 2013-2015 Arcturus Networks, Inc.
  3 + * http://www.arcturusnetworks.com/products/ucp1020/
  4 + * based on include/configs/p1_p2_rdb_pc.h
  5 + * original copyright follows:
  6 + * Copyright 2009-2011 Freescale Semiconductor, Inc.
  7 + *
  8 + * SPDX-License-Identifier: GPL-2.0+
  9 + */
  10 +
  11 +/*
  12 + * QorIQ uCP1020-xx boards configuration file
  13 + */
  14 +#ifndef __CONFIG_H
  15 +#define __CONFIG_H
  16 +
  17 +#define CONFIG_SYS_GENERIC_BOARD
  18 +#define CONFIG_DISPLAY_BOARDINFO
  19 +
  20 +#define CONFIG_FSL_ELBC
  21 +#define CONFIG_PCI
  22 +#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
  23 +#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
  24 +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
  25 +#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
  26 +#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
  27 +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
  28 +
  29 +#if defined(CONFIG_TARTGET_UCP1020T1)
  30 +
  31 +#define CONFIG_UCP1020_REV_1_3
  32 +
  33 +#define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1"
  34 +#define CONFIG_P1020
  35 +
  36 +#define CONFIG_TSEC_ENET
  37 +#define CONFIG_TSEC1
  38 +#define CONFIG_TSEC3
  39 +#define CONFIG_HAS_ETH0
  40 +#define CONFIG_HAS_ETH1
  41 +#define CONFIG_ETHADDR 00:19:D3:FF:FF:FF
  42 +#define CONFIG_ETH1ADDR 00:19:D3:FF:FF:FE
  43 +#define CONFIG_ETH2ADDR 00:19:D3:FF:FF:FD
  44 +#define CONFIG_IPADDR 10.80.41.229
  45 +#define CONFIG_SERVERIP 10.80.41.227
  46 +#define CONFIG_NETMASK 255.255.252.0
  47 +#define CONFIG_ETHPRIME "eTSEC3"
  48 +
  49 +#ifndef CONFIG_SPI_FLASH
  50 +#define CONFIG_SPI_FLASH y
  51 +#endif
  52 +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
  53 +
  54 +#define CONFIG_MMC
  55 +#define CONFIG_SYS_L2_SIZE (256 << 10)
  56 +
  57 +#define CONFIG_LAST_STAGE_INIT
  58 +
  59 +#if !defined(CONFIG_DONGLE)
  60 +#define CONFIG_SILENT_CONSOLE
  61 +#endif
  62 +
  63 +#endif
  64 +
  65 +#if defined(CONFIG_TARGET_UCP1020)
  66 +
  67 +#define CONFIG_UCP1020
  68 +#define CONFIG_UCP1020_REV_1_3
  69 +
  70 +#define CONFIG_BOARDNAME_LOCAL "uCP1020-64EEE512-OU1-XR"
  71 +#define CONFIG_P1020
  72 +
  73 +#define CONFIG_TSEC_ENET
  74 +#define CONFIG_TSEC1
  75 +#define CONFIG_TSEC2
  76 +#define CONFIG_TSEC3
  77 +#define CONFIG_HAS_ETH0
  78 +#define CONFIG_HAS_ETH1
  79 +#define CONFIG_HAS_ETH2
  80 +#define CONFIG_ETHADDR 00:06:3B:FF:FF:FF
  81 +#define CONFIG_ETH1ADDR 00:06:3B:FF:FF:FE
  82 +#define CONFIG_ETH2ADDR 00:06:3B:FF:FF:FD
  83 +#define CONFIG_IPADDR 192.168.1.81
  84 +#define CONFIG_IPADDR1 192.168.1.82
  85 +#define CONFIG_IPADDR2 192.168.1.83
  86 +#define CONFIG_SERVERIP 192.168.1.80
  87 +#define CONFIG_GATEWAYIP 102.168.1.1
  88 +#define CONFIG_NETMASK 255.255.255.0
  89 +#define CONFIG_ETHPRIME "eTSEC1"
  90 +
  91 +#ifndef CONFIG_SPI_FLASH
  92 +#define CONFIG_SPI_FLASH y
  93 +#endif
  94 +#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
  95 +
  96 +#define CONFIG_MMC
  97 +#define CONFIG_SYS_L2_SIZE (256 << 10)
  98 +
  99 +#define CONFIG_LAST_STAGE_INIT
  100 +
  101 +#endif
  102 +
  103 +#ifdef CONFIG_SDCARD
  104 +#define CONFIG_RAMBOOT_SDCARD
  105 +#define CONFIG_SYS_RAMBOOT
  106 +#define CONFIG_SYS_EXTRA_ENV_RELOC
  107 +#define CONFIG_SYS_TEXT_BASE 0x11000000
  108 +#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
  109 +#endif
  110 +
  111 +#ifdef CONFIG_SPIFLASH
  112 +#define CONFIG_RAMBOOT_SPIFLASH
  113 +#define CONFIG_SYS_RAMBOOT
  114 +#define CONFIG_SYS_EXTRA_ENV_RELOC
  115 +#define CONFIG_SYS_TEXT_BASE 0x11000000
  116 +#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
  117 +#endif
  118 +
  119 +#ifndef CONFIG_SYS_TEXT_BASE
  120 +#define CONFIG_SYS_TEXT_BASE 0xeff80000
  121 +#endif
  122 +#define CONFIG_SYS_TEXT_BASE_NOR 0xeff80000
  123 +
  124 +#ifndef CONFIG_RESET_VECTOR_ADDRESS
  125 +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
  126 +#endif
  127 +
  128 +#ifndef CONFIG_SYS_MONITOR_BASE
  129 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  130 +#endif
  131 +
  132 +/* High Level Configuration Options */
  133 +#define CONFIG_BOOKE
  134 +#define CONFIG_E500
  135 +/* #define CONFIG_MPC85xx */
  136 +
  137 +#define CONFIG_MP
  138 +
  139 +#define CONFIG_FSL_LAW
  140 +
  141 +#define CONFIG_ENV_OVERWRITE
  142 +
  143 +#define CONFIG_CMD_SATA
  144 +#define CONFIG_SATA_SIL
  145 +#define CONFIG_SYS_SATA_MAX_DEVICE 2
  146 +#define CONFIG_LIBATA
  147 +#define CONFIG_LBA48
  148 +
  149 +#define CONFIG_SYS_CLK_FREQ 66666666
  150 +#define CONFIG_DDR_CLK_FREQ 66666666
  151 +
  152 +#define CONFIG_HWCONFIG
  153 +
  154 +#define CONFIG_DTT_ADM1021 1 /* ADM1021 temp sensor support */
  155 +#define CONFIG_SYS_DTT_BUS_NUM 1 /* The I2C bus for DTT */
  156 +#define CONFIG_DTT_SENSORS { 0, 1 } /* Sensor index */
  157 +/*
  158 + * ADM1021/NCT72 temp sensor configuration (see dtt/adm1021.c for details).
  159 + * there will be one entry in this array for each two (dummy) sensors in
  160 + * CONFIG_DTT_SENSORS.
  161 + *
  162 + * For uCP1020 module:
  163 + * - only one ADM1021/NCT72
  164 + * - i2c addr 0x41
  165 + * - conversion rate 0x02 = 0.25 conversions/second
  166 + * - ALERT output disabled
  167 + * - local temp sensor enabled, min set to 0 deg, max set to 85 deg
  168 + * - remote temp sensor enabled, min set to 0 deg, max set to 85 deg
  169 + */
  170 +#define CONFIG_SYS_DTT_ADM1021 { { CONFIG_SYS_I2C_NCT72_ADDR, \
  171 + 0x02, 0, 1, 0, 85, 1, 0, 85} }
  172 +
  173 +#define CONFIG_CMD_DTT
  174 +
  175 +/*
  176 + * These can be toggled for performance analysis, otherwise use default.
  177 + */
  178 +#define CONFIG_L2_CACHE
  179 +#define CONFIG_BTB
  180 +
  181 +#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */
  182 +
  183 +#define CONFIG_ENABLE_36BIT_PHYS
  184 +
  185 +#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
  186 +#define CONFIG_SYS_MEMTEST_END 0x1fffffff
  187 +#define CONFIG_PANIC_HANG /* do not reset board on panic */
  188 +
  189 +#define CONFIG_SYS_CCSRBAR 0xffe00000
  190 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
  191 +
  192 +/* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
  193 + SPL code*/
  194 +#ifdef CONFIG_SPL_BUILD
  195 +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  196 +#endif
  197 +
  198 +/* DDR Setup */
  199 +#define CONFIG_DDR_ECC_ENABLE
  200 +#define CONFIG_SYS_FSL_DDR3
  201 +#ifndef CONFIG_DDR_ECC_ENABLE
  202 +#define CONFIG_SYS_DDR_RAW_TIMING
  203 +#define CONFIG_DDR_SPD
  204 +#endif
  205 +#define CONFIG_SYS_SPD_BUS_NUM 1
  206 +#undef CONFIG_FSL_DDR_INTERACTIVE
  207 +
  208 +#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M
  209 +#define CONFIG_CHIP_SELECTS_PER_CTRL 1
  210 +#define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
  211 +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
  212 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  213 +
  214 +#define CONFIG_NUM_DDR_CONTROLLERS 1
  215 +#define CONFIG_DIMM_SLOTS_PER_CTLR 1
  216 +
  217 +/* Default settings for DDR3 */
  218 +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
  219 +#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
  220 +#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
  221 +#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
  222 +#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
  223 +#define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
  224 +
  225 +#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
  226 +#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
  227 +#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
  228 +#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
  229 +
  230 +#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
  231 +#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
  232 +#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
  233 +#define CONFIG_SYS_DDR_RCW_1 0x00000000
  234 +#define CONFIG_SYS_DDR_RCW_2 0x00000000
  235 +#ifdef CONFIG_DDR_ECC_ENABLE
  236 +#define CONFIG_SYS_DDR_CONTROL 0xE70C0000 /* Type = DDR3 & ECC */
  237 +#else
  238 +#define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
  239 +#endif
  240 +#define CONFIG_SYS_DDR_CONTROL_2 0x04401050
  241 +#define CONFIG_SYS_DDR_TIMING_4 0x00220001
  242 +#define CONFIG_SYS_DDR_TIMING_5 0x03402400
  243 +
  244 +#define CONFIG_SYS_DDR_TIMING_3 0x00020000
  245 +#define CONFIG_SYS_DDR_TIMING_0 0x00330004
  246 +#define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
  247 +#define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
  248 +#define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
  249 +#define CONFIG_SYS_DDR_MODE_1 0x40461520
  250 +#define CONFIG_SYS_DDR_MODE_2 0x8000c000
  251 +#define CONFIG_SYS_DDR_INTERVAL 0x0C300000
  252 +
  253 +#undef CONFIG_CLOCKS_IN_MHZ
  254 +
  255 +/*
  256 + * Memory map
  257 + *
  258 + * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
  259 + * 0x8000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable(PCIe * 2)
  260 + * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
  261 + * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 256K cacheable
  262 + * (early boot only)
  263 + * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
  264 + * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
  265 + * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
  266 + */
  267 +
  268 +/*
  269 + * Local Bus Definitions
  270 + */
  271 +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
  272 +#define CONFIG_SYS_FLASH_BASE 0xec000000
  273 +
  274 +#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
  275 +
  276 +#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
  277 + | BR_PS_16 | BR_V)
  278 +
  279 +#define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
  280 +
  281 +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
  282 +#define CONFIG_SYS_FLASH_QUIET_TEST
  283 +#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
  284 +
  285 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  286 +
  287 +#undef CONFIG_SYS_FLASH_CHECKSUM
  288 +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  289 +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  290 +
  291 +#define CONFIG_FLASH_CFI_DRIVER
  292 +#define CONFIG_SYS_FLASH_CFI
  293 +#define CONFIG_SYS_FLASH_EMPTY_INFO
  294 +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  295 +
  296 +#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
  297 +
  298 +#define CONFIG_SYS_INIT_RAM_LOCK
  299 +#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
  300 +/* Initial L1 address */
  301 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
  302 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
  303 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
  304 +/* Size of used area in RAM */
  305 +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
  306 +
  307 +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
  308 + GENERATED_GBL_DATA_SIZE)
  309 +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  310 +
  311 +#define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */
  312 +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
  313 +
  314 +#define CONFIG_SYS_PMC_BASE 0xff980000
  315 +#define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
  316 +#define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
  317 + BR_PS_8 | BR_V)
  318 +#define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
  319 + OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
  320 + OR_GPCM_EAD)
  321 +
  322 +#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
  323 +#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
  324 +#ifdef CONFIG_NAND_FSL_ELBC
  325 +#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
  326 +#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
  327 +#endif
  328 +
  329 +/* Serial Port - controlled on board with jumper J8
  330 + * open - index 2
  331 + * shorted - index 1
  332 + */
  333 +#define CONFIG_CONS_INDEX 1
  334 +#undef CONFIG_SERIAL_SOFTWARE_FIFO
  335 +#define CONFIG_SYS_NS16550
  336 +#define CONFIG_SYS_NS16550_SERIAL
  337 +#define CONFIG_SYS_NS16550_REG_SIZE 1
  338 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  339 +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
  340 +#define CONFIG_NS16550_MIN_FUNCTIONS
  341 +#endif
  342 +
  343 +#define CONFIG_SYS_BAUDRATE_TABLE \
  344 + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  345 +
  346 +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
  347 +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
  348 +
  349 +/* Use the HUSH parser */
  350 +#define CONFIG_SYS_HUSH_PARSER
  351 +
  352 +/*
  353 + * Pass open firmware flat tree
  354 + */
  355 +#define CONFIG_OF_LIBFDT
  356 +#define CONFIG_OF_BOARD_SETUP
  357 +#define CONFIG_OF_STDOUT_VIA_ALIAS
  358 +
  359 +/* new uImage format support */
  360 +#define CONFIG_FIT
  361 +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
  362 +
  363 +/* I2C */
  364 +#define CONFIG_SYS_I2C
  365 +#define CONFIG_SYS_I2C_FSL
  366 +#define CONFIG_SYS_FSL_I2C_SPEED 400000
  367 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
  368 +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
  369 +#define CONFIG_SYS_FSL_I2C2_SPEED 400000
  370 +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
  371 +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
  372 +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
  373 +#define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
  374 +
  375 +#define CONFIG_RTC_DS1337
  376 +#define CONFIG_SYS_RTC_DS1337_NOOSC
  377 +#define CONFIG_SYS_I2C_RTC_ADDR 0x68
  378 +#define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
  379 +#define CONFIG_SYS_I2C_NCT72_ADDR 0x4C
  380 +#define CONFIG_SYS_I2C_IDT6V49205B 0x69
  381 +
  382 +/*
  383 + * eSPI - Enhanced SPI
  384 + */
  385 +#define CONFIG_HARD_SPI
  386 +#define CONFIG_FSL_ESPI
  387 +
  388 +#define CONFIG_SPI_FLASH_SST 1
  389 +#define CONFIG_SPI_FLASH_STMICRO 1
  390 +#define CONFIG_SPI_FLASH_WINBOND 1
  391 +#define CONFIG_CMD_SF 1
  392 +#define CONFIG_CMD_SPI 1
  393 +#define CONFIG_SF_DEFAULT_SPEED 10000000
  394 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
  395 +
  396 +#if defined(CONFIG_PCI)
  397 +/*
  398 + * General PCI
  399 + * Memory space is mapped 1-1, but I/O space must start from 0.
  400 + */
  401 +
  402 +/* controller 2, direct to uli, tgtid 2, Base address 9000 */
  403 +#define CONFIG_SYS_PCIE2_NAME "PCIe SLOT CON9"
  404 +#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
  405 +#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
  406 +#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
  407 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
  408 +#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
  409 +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
  410 +#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
  411 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
  412 +
  413 +/* controller 1, Slot 2, tgtid 1, Base address a000 */
  414 +#define CONFIG_SYS_PCIE1_NAME "PCIe SLOT CON10"
  415 +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
  416 +#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
  417 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
  418 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  419 +#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
  420 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  421 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
  422 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
  423 +
  424 +#define CONFIG_PCI_PNP /* do pci plug-and-play */
  425 +#define CONFIG_E1000 /* Defind e1000 pci Ethernet card*/
  426 +#define CONFIG_CMD_PCI
  427 +#define CONFIG_CMD_NET
  428 +
  429 +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  430 +#define CONFIG_DOS_PARTITION
  431 +#endif /* CONFIG_PCI */
  432 +
  433 +/*
  434 + * Environment
  435 + */
  436 +#ifdef CONFIG_ENV_FIT_UCBOOT
  437 +
  438 +#define CONFIG_ENV_IS_IN_FLASH
  439 +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x20000)
  440 +#define CONFIG_ENV_SIZE 0x20000
  441 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
  442 +
  443 +#else
  444 +
  445 +#define CONFIG_ENV_SPI_BUS 0
  446 +#define CONFIG_ENV_SPI_CS 0
  447 +#define CONFIG_ENV_SPI_MAX_HZ 10000000
  448 +#define CONFIG_ENV_SPI_MODE 0
  449 +
  450 +#ifdef CONFIG_RAMBOOT_SPIFLASH
  451 +
  452 +#define CONFIG_ENV_IS_IN_SPI_FLASH
  453 +#define CONFIG_ENV_SIZE 0x3000 /* 12KB */
  454 +#define CONFIG_ENV_OFFSET 0x2000 /* 8KB */
  455 +#define CONFIG_ENV_SECT_SIZE 0x1000
  456 +
  457 +#if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT)
  458 +/* Address and size of Redundant Environment Sector */
  459 +#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
  460 +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
  461 +#endif
  462 +
  463 +#elif defined(CONFIG_RAMBOOT_SDCARD)
  464 +#define CONFIG_ENV_IS_IN_MMC
  465 +#define CONFIG_FSL_FIXED_MMC_LOCATION
  466 +#define CONFIG_ENV_SIZE 0x2000
  467 +#define CONFIG_SYS_MMC_ENV_DEV 0
  468 +
  469 +#elif defined(CONFIG_SYS_RAMBOOT)
  470 +#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
  471 +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
  472 +#define CONFIG_ENV_SIZE 0x2000
  473 +
  474 +#else
  475 +#define CONFIG_ENV_IS_IN_FLASH
  476 +#define CONFIG_ENV_BASE (CONFIG_SYS_FLASH_BASE)
  477 +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
  478 +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
  479 +#define CONFIG_ENV_ADDR (CONFIG_ENV_BASE + 0xC0000)
  480 +#if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT)
  481 +/* Address and size of Redundant Environment Sector */
  482 +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
  483 +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
  484 +#endif
  485 +
  486 +#endif
  487 +
  488 +#endif /* CONFIG_ENV_FIT_UCBOOT */
  489 +
  490 +#define CONFIG_LOADS_ECHO /* echo on for serial download */
  491 +#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
  492 +
  493 +/*
  494 + * Command line configuration.
  495 + */
  496 +#include <config_cmd_default.h>
  497 +
  498 +#define CONFIG_CMD_IRQ
  499 +#define CONFIG_CMD_PING
  500 +#define CONFIG_CMD_I2C
  501 +#define CONFIG_CMD_MII
  502 +#define CONFIG_CMD_DATE
  503 +#define CONFIG_CMD_ELF
  504 +#define CONFIG_CMD_I2C
  505 +#define CONFIG_CMD_IRQ
  506 +#define CONFIG_CMD_MII
  507 +#define CONFIG_CMD_PING
  508 +#define CONFIG_CMD_SETEXPR
  509 +#define CONFIG_CMD_REGINFO
  510 +#define CONFIG_CMD_ERRATA
  511 +#define CONFIG_CMD_CRAMFS
  512 +#define CONFIG_CRAMFS_CMDLINE
  513 +
  514 +/*
  515 + * USB
  516 + */
  517 +#define CONFIG_HAS_FSL_DR_USB
  518 +
  519 +#if defined(CONFIG_HAS_FSL_DR_USB)
  520 +#define CONFIG_USB_EHCI
  521 +
  522 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  523 +
  524 +#ifdef CONFIG_USB_EHCI
  525 +#define CONFIG_CMD_USB
  526 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  527 +#define CONFIG_USB_EHCI_FSL
  528 +#define CONFIG_USB_STORAGE
  529 +#endif
  530 +#endif
  531 +
  532 +#undef CONFIG_WATCHDOG /* watchdog disabled */
  533 +
  534 +#ifdef CONFIG_MMC
  535 +#define CONFIG_FSL_ESDHC
  536 +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
  537 +#define CONFIG_CMD_MMC
  538 +#define CONFIG_MMC_SPI
  539 +#define CONFIG_CMD_MMC_SPI
  540 +#define CONFIG_GENERIC_MMC
  541 +#endif
  542 +
  543 +#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) || defined(CONFIG_FSL_SATA)
  544 +#define CONFIG_CMD_EXT2
  545 +#define CONFIG_CMD_FAT
  546 +#define CONFIG_DOS_PARTITION
  547 +#endif
  548 +
  549 +/* Misc Extra Settings */
  550 +#define CONFIG_CMD_GPIO 1
  551 +#undef CONFIG_WATCHDOG /* watchdog disabled */
  552 +
  553 +/*
  554 + * Miscellaneous configurable options
  555 + */
  556 +#define CONFIG_SYS_LONGHELP /* undef to save memory */
  557 +#define CONFIG_CMDLINE_EDITING /* Command-line editing */
  558 +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  559 +#define CONFIG_SYS_PROMPT "B$ " /* Monitor Command Prompt */
  560 +#if defined(CONFIG_CMD_KGDB)
  561 +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  562 +#else
  563 +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  564 +#endif
  565 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  566 + /* Print Buffer Size */
  567 +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  568 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
  569 +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */
  570 +
  571 +/*
  572 + * For booting Linux, the board info and command line data
  573 + * have to be in the first 64 MB of memory, since this is
  574 + * the maximum mapped by the Linux kernel during initialization.
  575 + */
  576 +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
  577 +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
  578 +
  579 +#if defined(CONFIG_CMD_KGDB)
  580 +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  581 +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
  582 +#endif
  583 +
  584 +/*
  585 + * Environment Configuration
  586 + */
  587 +
  588 +#if defined(CONFIG_TSEC_ENET)
  589 +
  590 +#if defined(CONFIG_UCP1020_REV_1_2)
  591 +#define CONFIG_PHY_MICREL_KSZ9021
  592 +#elif defined(CONFIG_UCP1020_REV_1_3)
  593 +#define CONFIG_PHY_MICREL_KSZ9031
  594 +#else
  595 +#error "UCP1020 module revision is not defined !!!"
  596 +#endif
  597 +
  598 +#define CONFIG_CMD_DHCP
  599 +#define CONFIG_BOOTP_SERVERIP
  600 +
  601 +#define CONFIG_MII /* MII PHY management */
  602 +#define CONFIG_TSEC1_NAME "eTSEC1"
  603 +#define CONFIG_TSEC2_NAME "eTSEC2"
  604 +#define CONFIG_TSEC3_NAME "eTSEC3"
  605 +
  606 +#define TSEC1_PHY_ADDR 4
  607 +#define TSEC2_PHY_ADDR 0
  608 +#define TSEC2_PHY_ADDR_SGMII 0x00
  609 +#define TSEC3_PHY_ADDR 6
  610 +
  611 +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  612 +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  613 +#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  614 +
  615 +#define TSEC1_PHYIDX 0
  616 +#define TSEC2_PHYIDX 0
  617 +#define TSEC3_PHYIDX 0
  618 +
  619 +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
  620 +
  621 +#endif
  622 +
  623 +#define CONFIG_HOSTNAME UCP1020
  624 +#define CONFIG_ROOTPATH "/opt/nfsroot"
  625 +#define CONFIG_BOOTFILE "uImage"
  626 +#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
  627 +
  628 +/* default location for tftp and bootm */
  629 +#define CONFIG_LOADADDR 1000000
  630 +
  631 +/*
  632 + * Autobooting
  633 + */
  634 +#define CONFIG_AUTOBOOT_KEYED
  635 +#define CONFIG_AUTOBOOT_STOP_STR "\x1b"
  636 +#define DEBUG_BOOTKEYS 0
  637 +#undef CONFIG_AUTOBOOT_DELAY_STR
  638 +#undef CONFIG_BOOTARGS
  639 +#define CONFIG_AUTOBOOT_PROMPT "Autobooting in %d seconds, " \
  640 + "press \"<Esc>\" to stop\n", bootdelay
  641 +
  642 +#define CONFIG_BOOTARGS /* the boot command will set bootargs */
  643 +
  644 +#define CONFIG_BAUDRATE 115200
  645 +
  646 +#if defined(CONFIG_DONGLE)
  647 +
  648 +#define CONFIG_BOOTDELAY 1 /* autoboot after 1 seconds */
  649 +#define CONFIG_EXTRA_ENV_SETTINGS \
  650 +"bootcmd=run prog_spi_mbrbootcramfs\0" \
  651 +"bootfile=uImage\0" \
  652 +"consoledev=ttyS0\0" \
  653 +"cramfsfile=image.cramfs\0" \
  654 +"dtbaddr=0x00c00000\0" \
  655 +"dtbfile=image.dtb\0" \
  656 +"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
  657 +"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
  658 +"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
  659 +"fileaddr=0x01000000\0" \
  660 +"filesize=0x00080000\0" \
  661 +"flashmbr=sf probe 0; " \
  662 + "tftp $loadaddr $mbr; " \
  663 + "sf erase $mbr_offset +$filesize; " \
  664 + "sf write $loadaddr $mbr_offset $filesize\0" \
  665 +"flashrecovery=tftp $recoveryaddr $cramfsfile; " \
  666 + "protect off $nor_recoveryaddr +$filesize; " \
  667 + "erase $nor_recoveryaddr +$filesize; " \
  668 + "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \
  669 + "protect on $nor_recoveryaddr +$filesize\0 " \
  670 +"flashuboot=tftp $ubootaddr $ubootfile; " \
  671 + "protect off $nor_ubootaddr +$filesize; " \
  672 + "erase $nor_ubootaddr +$filesize; " \
  673 + "cp.b $ubootaddr $nor_ubootaddr $filesize; " \
  674 + "protect on $nor_ubootaddr +$filesize\0 " \
  675 +"flashworking=tftp $workingaddr $cramfsfile; " \
  676 + "protect off $nor_workingaddr +$filesize; " \
  677 + "erase $nor_workingaddr +$filesize; " \
  678 + "cp.b $workingaddr $nor_workingaddr $filesize; " \
  679 + "protect on $nor_workingaddr +$filesize\0 " \
  680 +"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
  681 +"kerneladdr=0x01100000\0" \
  682 +"kernelfile=uImage\0" \
  683 +"loadaddr=0x01000000\0" \
  684 +"mbr=uCP1020d.mbr\0" \
  685 +"mbr_offset=0x00000000\0" \
  686 +"mmbr=uCP1020Quiet.mbr\0" \
  687 +"mmcpart=0:2\0" \
  688 +"mmc__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \
  689 + "mmc erase 1 1; " \
  690 + "mmc write $loadaddr 1 1\0" \
  691 +"mmc__uboot=fatload mmc $mmcpart $loadaddr $ubootfile; " \
  692 + "mmc erase 0x40 0x400; " \
  693 + "mmc write $loadaddr 0x40 0x400\0" \
  694 +"netdev=eth0\0" \
  695 +"nor_recoveryaddr=0xEC0A0000\0" \
  696 +"nor_ubootaddr=0xEFF80000\0" \
  697 +"nor_workingaddr=0xECFA0000\0" \
  698 +"norbootrecovery=setenv bootargs $recoverybootargs" \
  699 + " console=$consoledev,$baudrate $othbootargs; " \
  700 + "run norloadrecovery; " \
  701 + "bootm $kerneladdr - $dtbaddr\0" \
  702 +"norbootworking=setenv bootargs $workingbootargs" \
  703 + " console=$consoledev,$baudrate $othbootargs; " \
  704 + "run norloadworking; " \
  705 + "bootm $kerneladdr - $dtbaddr\0" \
  706 +"norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
  707 + "setenv cramfsaddr $nor_recoveryaddr; " \
  708 + "cramfsload $dtbaddr $dtbfile; " \
  709 + "cramfsload $kerneladdr $kernelfile\0" \
  710 +"norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
  711 + "setenv cramfsaddr $nor_workingaddr; " \
  712 + "cramfsload $dtbaddr $dtbfile; " \
  713 + "cramfsload $kerneladdr $kernelfile\0" \
  714 +"prog_spi_mbr=run spi__mbr\0" \
  715 +"prog_spi_mbrboot=run spi__mbr; run spi__boot1; run spi__boot2\0" \
  716 +"prog_spi_mbrbootcramfs=run spi__mbr; run spi__boot1; run spi__boot2; " \
  717 + "run spi__cramfs\0" \
  718 +"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
  719 + " console=$consoledev,$baudrate $othbootargs; " \
  720 + "tftp $rootfsaddr $rootfsfile; " \
  721 + "tftp $loadaddr $kernelfile; " \
  722 + "tftp $dtbaddr $dtbfile; " \
  723 + "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
  724 +"ramdisk_size=120000\0" \
  725 +"ramdiskfile=rootfs.ext2.gz.uboot\0" \
  726 +"recoveryaddr=0x02F00000\0" \
  727 +"recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \
  728 +"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
  729 + "mw.l 0xffe0f008 0x00400000\0" \
  730 +"rootfsaddr=0x02F00000\0" \
  731 +"rootfsfile=rootfs.ext2.gz.uboot\0" \
  732 +"rootpath=/opt/nfsroot\0" \
  733 +"spi__boot1=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
  734 + "protect off 0xeC000000 +$filesize; " \
  735 + "erase 0xEC000000 +$filesize; " \
  736 + "cp.b $loadaddr 0xEC000000 $filesize; " \
  737 + "cmp.b $loadaddr 0xEC000000 $filesize; " \
  738 + "protect on 0xeC000000 +$filesize\0" \
  739 +"spi__boot2=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
  740 + "protect off 0xeFF80000 +$filesize; " \
  741 + "erase 0xEFF80000 +$filesize; " \
  742 + "cp.b $loadaddr 0xEFF80000 $filesize; " \
  743 + "cmp.b $loadaddr 0xEFF80000 $filesize; " \
  744 + "protect on 0xeFF80000 +$filesize\0" \
  745 +"spi__bootd=fatload mmc $mmcpart $loadaddr $ubootd; " \
  746 + "sf probe 0; sf erase 0x8000 +$filesize; " \
  747 + "sf write $loadaddr 0x8000 $filesize\0" \
  748 +"spi__cramfs=fatload mmc $mmcpart $loadaddr image.cramfs; " \
  749 + "protect off 0xec0a0000 +$filesize; " \
  750 + "erase 0xeC0A0000 +$filesize; " \
  751 + "cp.b $loadaddr 0xeC0A0000 $filesize; " \
  752 + "protect on 0xec0a0000 +$filesize\0" \
  753 +"spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \
  754 + "sf probe 1; sf erase 0 +$filesize; " \
  755 + "sf write $loadaddr 0 $filesize\0" \
  756 +"spi__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \
  757 + "sf probe 0; sf erase 0 +$filesize; " \
  758 + "sf write $loadaddr 0 $filesize\0" \
  759 +"tftpflash=tftpboot $loadaddr $uboot; " \
  760 + "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
  761 + "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
  762 + "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
  763 + "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
  764 + "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
  765 +"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
  766 +"ubootaddr=0x01000000\0" \
  767 +"ubootfile=u-boot.bin\0" \
  768 +"ubootd=u-boot4dongle.bin\0" \
  769 +"upgrade=run flashworking\0" \
  770 +"usb_phy_type=ulpi\0 " \
  771 +"workingaddr=0x02F00000\0" \
  772 +"workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
  773 +
  774 +#else
  775 +
  776 +#if defined(CONFIG_UCP1020T1)
  777 +
  778 +#define CONFIG_BOOTDELAY 2 /* autoboot after 2 sec, -1 disables auto-boot */
  779 +#define CONFIG_EXTRA_ENV_SETTINGS \
  780 +"bootcmd=run releasefpga; run norbootworking || run norbootrecovery\0" \
  781 +"bootfile=uImage\0" \
  782 +"consoledev=ttyS0\0" \
  783 +"cramfsfile=image.cramfs\0" \
  784 +"dtbaddr=0x00c00000\0" \
  785 +"dtbfile=image.dtb\0" \
  786 +"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
  787 +"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
  788 +"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
  789 +"fileaddr=0x01000000\0" \
  790 +"filesize=0x00080000\0" \
  791 +"flashmbr=sf probe 0; " \
  792 + "tftp $loadaddr $mbr; " \
  793 + "sf erase $mbr_offset +$filesize; " \
  794 + "sf write $loadaddr $mbr_offset $filesize\0" \
  795 +"flashrecovery=tftp $recoveryaddr $cramfsfile; " \
  796 + "protect off $nor_recoveryaddr +$filesize; " \
  797 + "erase $nor_recoveryaddr +$filesize; " \
  798 + "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \
  799 + "protect on $nor_recoveryaddr +$filesize\0 " \
  800 +"flashuboot=tftp $ubootaddr $ubootfile; " \
  801 + "protect off $nor_ubootaddr +$filesize; " \
  802 + "erase $nor_ubootaddr +$filesize; " \
  803 + "cp.b $ubootaddr $nor_ubootaddr $filesize; " \
  804 + "protect on $nor_ubootaddr +$filesize\0 " \
  805 +"flashworking=tftp $workingaddr $cramfsfile; " \
  806 + "protect off $nor_workingaddr +$filesize; " \
  807 + "erase $nor_workingaddr +$filesize; " \
  808 + "cp.b $workingaddr $nor_workingaddr $filesize; " \
  809 + "protect on $nor_workingaddr +$filesize\0 " \
  810 +"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
  811 +"kerneladdr=0x01100000\0" \
  812 +"kernelfile=uImage\0" \
  813 +"loadaddr=0x01000000\0" \
  814 +"mbr=uCP1020.mbr\0" \
  815 +"mbr_offset=0x00000000\0" \
  816 +"netdev=eth0\0" \
  817 +"nor_recoveryaddr=0xEC0A0000\0" \
  818 +"nor_ubootaddr=0xEFF80000\0" \
  819 +"nor_workingaddr=0xECFA0000\0" \
  820 +"norbootrecovery=setenv bootargs $recoverybootargs" \
  821 + " console=$consoledev,$baudrate $othbootargs; " \
  822 + "run norloadrecovery; " \
  823 + "bootm $kerneladdr - $dtbaddr\0" \
  824 +"norbootworking=setenv bootargs $workingbootargs" \
  825 + " console=$consoledev,$baudrate $othbootargs; " \
  826 + "run norloadworking; " \
  827 + "bootm $kerneladdr - $dtbaddr\0" \
  828 +"norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
  829 + "setenv cramfsaddr $nor_recoveryaddr; " \
  830 + "cramfsload $dtbaddr $dtbfile; " \
  831 + "cramfsload $kerneladdr $kernelfile\0" \
  832 +"norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
  833 + "setenv cramfsaddr $nor_workingaddr; " \
  834 + "cramfsload $dtbaddr $dtbfile; " \
  835 + "cramfsload $kerneladdr $kernelfile\0" \
  836 +"othbootargs=quiet\0" \
  837 +"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
  838 + " console=$consoledev,$baudrate $othbootargs; " \
  839 + "tftp $rootfsaddr $rootfsfile; " \
  840 + "tftp $loadaddr $kernelfile; " \
  841 + "tftp $dtbaddr $dtbfile; " \
  842 + "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
  843 +"ramdisk_size=120000\0" \
  844 +"ramdiskfile=rootfs.ext2.gz.uboot\0" \
  845 +"recoveryaddr=0x02F00000\0" \
  846 +"recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \
  847 +"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
  848 + "mw.l 0xffe0f008 0x00400000\0" \
  849 +"rootfsaddr=0x02F00000\0" \
  850 +"rootfsfile=rootfs.ext2.gz.uboot\0" \
  851 +"rootpath=/opt/nfsroot\0" \
  852 +"silent=1\0" \
  853 +"tftpflash=tftpboot $loadaddr $uboot; " \
  854 + "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
  855 + "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
  856 + "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
  857 + "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
  858 + "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
  859 +"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
  860 +"ubootaddr=0x01000000\0" \
  861 +"ubootfile=u-boot.bin\0" \
  862 +"upgrade=run flashworking\0" \
  863 +"workingaddr=0x02F00000\0" \
  864 +"workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
  865 +
  866 +#else /* For Arcturus Modules */
  867 +
  868 +#define CONFIG_BOOTDELAY 2 /* autoboot after 2 sec, -1 disables auto-boot */
  869 +#define CONFIG_EXTRA_ENV_SETTINGS \
  870 +"bootcmd=run norkernel\0" \
  871 +"bootfile=uImage\0" \
  872 +"consoledev=ttyS0\0" \
  873 +"dtbaddr=0x00c00000\0" \
  874 +"dtbfile=image.dtb\0" \
  875 +"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
  876 +"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
  877 +"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
  878 +"fileaddr=0x01000000\0" \
  879 +"filesize=0x00080000\0" \
  880 +"flashmbr=sf probe 0; " \
  881 + "tftp $loadaddr $mbr; " \
  882 + "sf erase $mbr_offset +$filesize; " \
  883 + "sf write $loadaddr $mbr_offset $filesize\0" \
  884 +"flashuboot=tftp $loadaddr $ubootfile; " \
  885 + "protect off $nor_ubootaddr0 +$filesize; " \
  886 + "erase $nor_ubootaddr0 +$filesize; " \
  887 + "cp.b $loadaddr $nor_ubootaddr0 $filesize; " \
  888 + "protect on $nor_ubootaddr0 +$filesize; " \
  889 + "protect off $nor_ubootaddr1 +$filesize; " \
  890 + "erase $nor_ubootaddr1 +$filesize; " \
  891 + "cp.b $loadaddr $nor_ubootaddr1 $filesize; " \
  892 + "protect on $nor_ubootaddr1 +$filesize\0 " \
  893 +"format0=protect off $part0base +$part0size; " \
  894 + "erase $part0base +$part0size\0" \
  895 +"format1=protect off $part1base +$part1size; " \
  896 + "erase $part1base +$part1size\0" \
  897 +"format2=protect off $part2base +$part2size; " \
  898 + "erase $part2base +$part2size\0" \
  899 +"format3=protect off $part3base +$part3size; " \
  900 + "erase $part3base +$part3size\0" \
  901 +"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
  902 +"kerneladdr=0x01100000\0" \
  903 +"kernelargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" \
  904 +"kernelfile=uImage\0" \
  905 +"loadaddr=0x01000000\0" \
  906 +"mbr=uCP1020.mbr\0" \
  907 +"mbr_offset=0x00000000\0" \
  908 +"netdev=eth0\0" \
  909 +"nor_ubootaddr0=0xEC000000\0" \
  910 +"nor_ubootaddr1=0xEFF80000\0" \
  911 +"norkernel=setenv bootargs $kernelargs console=$consoledev,$baudrate; " \
  912 + "run norkernelload; " \
  913 + "bootm $kerneladdr - $dtbaddr\0" \
  914 +"norkernelload=mw.l $kerneladdr 0x0 0x00a00000; " \
  915 + "setenv cramfsaddr $part0base; " \
  916 + "cramfsload $dtbaddr $dtbfile; " \
  917 + "cramfsload $kerneladdr $kernelfile\0" \
  918 +"part0base=0xEC100000\0" \
  919 +"part0size=0x00700000\0" \
  920 +"part1base=0xEC800000\0" \
  921 +"part1size=0x02000000\0" \
  922 +"part2base=0xEE800000\0" \
  923 +"part2size=0x00800000\0" \
  924 +"part3base=0xEF000000\0" \
  925 +"part3size=0x00F80000\0" \
  926 +"partENVbase=0xEC080000\0" \
  927 +"partENVsize=0x00080000\0" \
  928 +"program0=tftp part0-000000.bin; " \
  929 + "protect off $part0base +$filesize; " \
  930 + "erase $part0base +$filesize; " \
  931 + "cp.b $loadaddr $part0base $filesize; " \
  932 + "echo Verifying...; " \
  933 + "cmp.b $loadaddr $part0base $filesize\0" \
  934 +"program1=tftp part1-000000.bin; " \
  935 + "protect off $part1base +$filesize; " \
  936 + "erase $part1base +$filesize; " \
  937 + "cp.b $loadaddr $part1base $filesize; " \
  938 + "echo Verifying...; " \
  939 + "cmp.b $loadaddr $part1base $filesize\0" \
  940 +"program2=tftp part2-000000.bin; " \
  941 + "protect off $part2base +$filesize; " \
  942 + "erase $part2base +$filesize; " \
  943 + "cp.b $loadaddr $part2base $filesize; " \
  944 + "echo Verifying...; " \
  945 + "cmp.b $loadaddr $part2base $filesize\0" \
  946 +"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
  947 + " console=$consoledev,$baudrate $othbootargs; " \
  948 + "tftp $rootfsaddr $rootfsfile; " \
  949 + "tftp $loadaddr $kernelfile; " \
  950 + "tftp $dtbaddr $dtbfile; " \
  951 + "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
  952 +"ramdisk_size=120000\0" \
  953 +"ramdiskfile=rootfs.ext2.gz.uboot\0" \
  954 +"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
  955 + "mw.l 0xffe0f008 0x00400000\0" \
  956 +"rootfsaddr=0x02F00000\0" \
  957 +"rootfsfile=rootfs.ext2.gz.uboot\0" \
  958 +"rootpath=/opt/nfsroot\0" \
  959 +"spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \
  960 + "sf probe 0; sf erase 0 +$filesize; " \
  961 + "sf write $loadaddr 0 $filesize\0" \
  962 +"spi__boot=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
  963 + "protect off 0xeC000000 +$filesize; " \
  964 + "erase 0xEC000000 +$filesize; " \
  965 + "cp.b $loadaddr 0xEC000000 $filesize; " \
  966 + "cmp.b $loadaddr 0xEC000000 $filesize; " \
  967 + "protect on 0xeC000000 +$filesize\0" \
  968 +"tftpflash=tftpboot $loadaddr $uboot; " \
  969 + "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
  970 + "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
  971 + "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
  972 + "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
  973 + "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
  974 +"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
  975 +"ubootfile=u-boot.bin\0" \
  976 +"upgrade=run flashuboot\0" \
  977 +"usb_phy_type=ulpi\0 " \
  978 +"boot_nfs= " \
  979 + "setenv bootargs root=/dev/nfs rw " \
  980 + "nfsroot=$serverip:$rootpath " \
  981 + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  982 + "console=$consoledev,$baudrate $othbootargs;" \
  983 + "tftp $loadaddr $bootfile;" \
  984 + "tftp $fdtaddr $fdtfile;" \
  985 + "bootm $loadaddr - $fdtaddr\0" \
  986 +"boot_hd = " \
  987 + "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
  988 + "console=$consoledev,$baudrate $othbootargs;" \
  989 + "usb start;" \
  990 + "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
  991 + "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
  992 + "bootm $loadaddr - $fdtaddr\0" \
  993 +"boot_usb_fat = " \
  994 + "setenv bootargs root=/dev/ram rw " \
  995 + "console=$consoledev,$baudrate $othbootargs " \
  996 + "ramdisk_size=$ramdisk_size;" \
  997 + "usb start;" \
  998 + "fatload usb 0:2 $loadaddr $bootfile;" \
  999 + "fatload usb 0:2 $fdtaddr $fdtfile;" \
  1000 + "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
  1001 + "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \
  1002 +"boot_usb_ext2 = " \
  1003 + "setenv bootargs root=/dev/ram rw " \
  1004 + "console=$consoledev,$baudrate $othbootargs " \
  1005 + "ramdisk_size=$ramdisk_size;" \
  1006 + "usb start;" \
  1007 + "ext2load usb 0:4 $loadaddr $bootfile;" \
  1008 + "ext2load usb 0:4 $fdtaddr $fdtfile;" \
  1009 + "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
  1010 + "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \
  1011 +"boot_nor = " \
  1012 + "setenv bootargs root=/dev/$jffs2nor rw " \
  1013 + "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
  1014 + "bootm $norbootaddr - $norfdtaddr\0 " \
  1015 +"boot_ram = " \
  1016 + "setenv bootargs root=/dev/ram rw " \
  1017 + "console=$consoledev,$baudrate $othbootargs " \
  1018 + "ramdisk_size=$ramdisk_size;" \
  1019 + "tftp $ramdiskaddr $ramdiskfile;" \
  1020 + "tftp $loadaddr $bootfile;" \
  1021 + "tftp $fdtaddr $fdtfile;" \
  1022 + "bootm $loadaddr $ramdiskaddr $fdtaddr\0"
  1023 +
  1024 +#endif
  1025 +#endif
  1026 +
  1027 +#endif /* __CONFIG_H */