Eric Lee / smarc-uboot

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Commit 8b0bfc6804ad140a3bd31bfb2c15fc7d69c15f5c

Authored by wdenk
1 parent 384cc68744
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

* Patch by Yuli Barcohen, 08 Nov 2004: 

Add support for Analogue & Micro Rattler boards.
  Tested on Rattler8248.

* Patch by Andre Renaud, 08 Nov 2004:
  Fix watchdog support in common/lcd.c

* Patch by Marc Leeman, 05 Nov 2003:
  Enable all 4 PCMBRW buffers for the MPC8245 processor since the CPU
  bug only affects the XPC8245 processors

Showing 16 changed files with 752 additions and 26 deletions Side-by-side Diff

... ... @@ -2,6 +2,17 @@
2 2 Changes for U-Boot 1.1.3:
3 3 ======================================================================
4 4  
  5 +* Patch by Yuli Barcohen, 08 Nov 2004:
  6 + Add support for Analogue & Micro Rattler boards.
  7 + Tested on Rattler8248.
  8 +
  9 +* Patch by Andre Renaud, 08 Nov 2004:
  10 + Fix watchdog support in common/lcd.c
  11 +
  12 +* Patch by Marc Leeman, 05 Nov 2003:
  13 + Enable all 4 PCMBRW buffers for the MPC8245 processor since the CPU
  14 + bug only affects the XPC8245 processors
  15 +
5 16 * Patches by Josef Wagner, 29 Oct 2004:
6 17 - Add support for MicroSys CPU87 board
7 18 - Add support for MicroSys PM854 board
... ... @@ -40,6 +40,7 @@
40 40 D: Support for Zephyr Engineering ZPC.1900 board.
41 41 D: Support for Interphase iSPAN boards.
42 42 D: Support for Analogue&Micro Adder boards.
  43 +D: Support for Analogue&Micro Rattler boards.
43 44 W: http://www.arabellasw.com
44 45  
45 46 N: Jerry van Baren
... ... @@ -34,6 +34,7 @@
34 34 Adder MPC87x/MPC852T
35 35 ISPAN MPC8260
36 36 MPC8260ADS MPC826x/MPC827x/MPC8280
  37 + Rattler MPC8248
37 38 ZPC1900 MPC8265
38 39  
39 40 Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>
... ... @@ -98,11 +98,12 @@
98 98  
99 99 LIST_8260=" \
100 100 atc cogent_mpc8260 CPU86 CPU87 \
101   - ep8260 gw8260 hymod IPHASE4539
  101 + ep8260 gw8260 hymod IPHASE4539 \
102 102 ISPAN MPC8260ADS MPC8266ADS MPC8272ADS \
103   - PM826 PM828 ppmc8260 RPXsuper \
104   - rsdproto sacsng sbc8260 SCM \
105   - TQM8260_AC TQM8260_AD TQM8260_AE ZPC1900 \
  103 + PM826 PM828 ppmc8260 Rattler8248 \
  104 + RPXsuper rsdproto sacsng sbc8260 \
  105 + SCM TQM8260_AC TQM8260_AD TQM8260_AE \
  106 + ZPC1900 \
106 107 "
107 108  
108 109 #########################################################################
... ... @@ -972,7 +972,6 @@
972 972 fi; \
973 973 echo "export CONFIG_BOOT_ROM" >> config.mk;
974 974  
975   -
976 975 ep8260_config: unconfig
977 976 @./mkconfig $(@:_config=) ppc mpc8260 ep8260
978 977  
... ... @@ -1066,6 +1065,12 @@
1066 1065  
1067 1066 ppmc8260_config: unconfig
1068 1067 @./mkconfig $(@:_config=) ppc mpc8260 ppmc8260
  1068 +
  1069 +Rattler8248_config \
  1070 +Rattler_config: unconfig
  1071 + $(if $(findstring 8248,$@), \
  1072 + @echo "#define CONFIG_MPC8248" > include/config.h)
  1073 + @./mkconfig -a Rattler ppc mpc8260 rattler
1069 1074  
1070 1075 RPXsuper_config: unconfig
1071 1076 @./mkconfig $(@:_config=) ppc mpc8260 rpxsuper
... ... @@ -134,7 +134,7 @@
134 134 break;
135 135 case FLASH_28F128J3A: printf ("28F128J3A (128 Mbit, 128 x 128K)\n");
136 136 break;
137   -
  137 +
138 138 default: printf ("Unknown Chip Type\n");
139 139 break;
140 140 }
141 141  
142 142  
... ... @@ -224,15 +224,15 @@
224 224 info->size = 0x01000000;
225 225 sector_offset = 0x40000;
226 226 break; /* => 2x8 MB */
227   -
  227 +
228 228 case (INTEL_ID_28F128J3A):
229 229 info->flash_id += FLASH_28F128J3A;
230 230 info->sector_count = 128;
231 231 info->size = 0x02000000;
232 232 sector_offset = 0x40000;
233 233 break; /* => 2x16 MB */
234   -
235 234  
  235 +
236 236 case SHARP_ID_28F016SCL:
237 237 case SHARP_ID_28F016SCZ:
238 238 info->flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT;
... ... @@ -325,7 +325,7 @@
325 325 asm("sync");
326 326  
327 327 last = start = get_timer (0);
328   -
  328 +
329 329 /* Disable interrupts which might cause a timeout here */
330 330 flag = disable_interrupts();
331 331  
... ... @@ -367,7 +367,7 @@
367 367 last = now;
368 368 }
369 369 }
370   -
  370 +
371 371 /* reset to read mode */
372 372 *addr = 0xFFFFFFFF;
373 373 asm("sync");
... ... @@ -87,9 +87,9 @@
87 87 {
88 88 volatile ccsr_gur_t *gur= &immap->im_gur;
89 89 int i,x;
90   -
  90 +
91 91 x = 10;
92   -
  92 +
93 93 /*
94 94 * Work around to stabilize DDR DLL
95 95 */
... ... @@ -106,7 +106,7 @@
106 106 asm("sync;isync;msync");
107 107 x++;
108 108 }
109   - }
  109 + }
110 110 #endif
111 111  
112 112 #if defined(CONFIG_SPD_EEPROM)
board/rattler/Makefile
Diff comments   View file @ 8b0bfc6
  1 +#
  2 +# (C) Copyright 2001-2005
  3 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 +#
  5 +# See file CREDITS for list of people who contributed to this
  6 +# project.
  7 +#
  8 +# This program is free software; you can redistribute it and/or
  9 +# modify it under the terms of the GNU General Public License as
  10 +# published by the Free Software Foundation; either version 2 of
  11 +# the License, or (at your option) any later version.
  12 +#
  13 +# This program is distributed in the hope that it will be useful,
  14 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16 +# GNU General Public License for more details.
  17 +#
  18 +# You should have received a copy of the GNU General Public License
  19 +# along with this program; if not, write to the Free Software
  20 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 +# MA 02111-1307 USA
  22 +#
  23 +
  24 +include $(TOPDIR)/config.mk
  25 +
  26 +LIB = lib$(BOARD).a
  27 +
  28 +OBJS := $(BOARD).o
  29 +
  30 +$(LIB): $(OBJS) $(SOBJS)
  31 + $(AR) crv $@ $(OBJS)
  32 +
  33 +clean:
  34 + rm -f $(SOBJS) $(OBJS)
  35 +
  36 +distclean: clean
  37 + rm -f $(LIB) core *.bak .depend
  38 +
  39 +#########################################################################
  40 +
  41 +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
  42 + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
  43 +
  44 +-include .depend
  45 +
  46 +#########################################################################
board/rattler/config.mk
Diff comments   View file @ 8b0bfc6
  1 +#
  2 +# (C) Copyright 2001-2005
  3 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 +#
  5 +# Modified by, Yuli Barcohen, Arabella Software Ltd. <yuli@arabellasw.com>
  6 +#
  7 +# See file CREDITS for list of people who contributed to this
  8 +# project.
  9 +#
  10 +# This program is free software; you can redistribute it and/or
  11 +# modify it under the terms of the GNU General Public License as
  12 +# published by the Free Software Foundation; either version 2 of
  13 +# the License, or (at your option) any later version.
  14 +#
  15 +# This program is distributed in the hope that it will be useful,
  16 +# but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18 +# GNU General Public License for more details.
  19 +#
  20 +# You should have received a copy of the GNU General Public License
  21 +# along with this program; if not, write to the Free Software
  22 +# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23 +# MA 02111-1307 USA
  24 +#
  25 +
  26 +#
  27 +# Rattler series boards by Analogue & Micro
  28 +#
  29 +
  30 +TEXT_BASE = 0xFE000000
board/rattler/rattler.c
Diff comments   View file @ 8b0bfc6
  1 +/*
  2 + * Copyright (C) 2004 Arabella Software Ltd.
  3 + * Yuli Barcohen <yuli@arabellasw.com>
  4 + *
  5 + * Support for Analogue&Micro Rattler boards family.
  6 + * Tested on Rattler8248.
  7 + *
  8 + * See file CREDITS for list of people who contributed to this
  9 + * project.
  10 + *
  11 + * This program is free software; you can redistribute it and/or
  12 + * modify it under the terms of the GNU General Public License as
  13 + * published by the Free Software Foundation; either version 2 of
  14 + * the License, or (at your option) any later version.
  15 + *
  16 + * This program is distributed in the hope that it will be useful,
  17 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19 + * GNU General Public License for more details.
  20 + *
  21 + * You should have received a copy of the GNU General Public License
  22 + * along with this program; if not, write to the Free Software
  23 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24 + * MA 02111-1307 USA
  25 + */
  26 +
  27 +#include <common.h>
  28 +#include <mpc8260.h>
  29 +#include <ioports.h>
  30 +
  31 +/*
  32 + * I/O Port configuration table
  33 + *
  34 + * if conf is 1, then that port pin will be configured at boot time
  35 + * according to the five values podr/pdir/ppar/psor/pdat for that entry
  36 + */
  37 +
  38 +#define CFG_FCC1 (CONFIG_ETHER_INDEX == 1)
  39 +#define CFG_FCC2 (CONFIG_ETHER_INDEX == 2)
  40 +
  41 +const iop_conf_t iop_conf_tab[4][32] = {
  42 +
  43 + /* Port A */
  44 + { /* conf ppar psor pdir podr pdat */
  45 + /* PA31 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */
  46 + /* PA30 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */
  47 + /* PA29 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */
  48 + /* PA28 */ { CFG_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */
  49 + /* PA27 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */
  50 + /* PA26 */ { CFG_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */
  51 + /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */
  52 + /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */
  53 + /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */
  54 + /* PA22 */ { 1, 0, 0, 1, 0, 1 }, /* Eth PHYs reset */
  55 + /* PA21 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */
  56 + /* PA20 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */
  57 + /* PA19 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */
  58 + /* PA18 */ { CFG_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */
  59 + /* PA17 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */
  60 + /* PA16 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */
  61 + /* PA15 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */
  62 + /* PA14 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */
  63 + /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */
  64 + /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */
  65 + /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */
  66 + /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */
  67 + /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 TxD */
  68 + /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 RxD */
  69 + /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */
  70 + /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */
  71 + /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */
  72 + /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */
  73 + /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */
  74 + /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */
  75 + /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */
  76 + /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */
  77 + },
  78 +
  79 + /* Port B */
  80 + { /* conf ppar psor pdir podr pdat */
  81 + /* PB31 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
  82 + /* PB30 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
  83 + /* PB29 */ { CFG_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
  84 + /* PB28 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
  85 + /* PB27 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
  86 + /* PB26 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
  87 + /* PB25 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
  88 + /* PB24 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
  89 + /* PB23 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
  90 + /* PB22 */ { CFG_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
  91 + /* PB21 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
  92 + /* PB20 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
  93 + /* PB19 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
  94 + /* PB18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
  95 + /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
  96 + /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
  97 + /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
  98 + /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
  99 + /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
  100 + /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
  101 + /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
  102 + /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
  103 + /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
  104 + /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
  105 + /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
  106 + /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
  107 + /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
  108 + /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
  109 + /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
  110 + /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
  111 + /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
  112 + /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */
  113 + },
  114 +
  115 + /* Port C */
  116 + { /* conf ppar psor pdir podr pdat */
  117 + /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
  118 + /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
  119 + /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */
  120 + /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */
  121 + /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */
  122 + /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
  123 + /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */
  124 + /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */
  125 + /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */
  126 + /* PC22 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 TxClk (CLK10) */
  127 + /* PC21 */ { CFG_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 RxClk (CLK11) */
  128 + /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */
  129 + /* PC19 */ { 0, 0, 0, 0, 0, 0 }, /* PC19 */
  130 + /* PC18 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 TxClk (CLK14) */
  131 + /* PC17 */ { CFG_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 RxClk (CLK15) */
  132 + /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */
  133 + /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
  134 + /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */
  135 + /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */
  136 + /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */
  137 + /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
  138 + /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */
  139 + /* PC9 */ { 1, 0, 0, 1, 0, 1 }, /* MDIO */
  140 + /* PC8 */ { 1, 0, 0, 1, 0, 1 }, /* MDC */
  141 + /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
  142 + /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
  143 + /* PC5 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TxD */
  144 + /* PC4 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RxD */
  145 + /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
  146 + /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
  147 + /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
  148 + /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */
  149 + },
  150 +
  151 + /* Port D */
  152 + { /* conf ppar psor pdir podr pdat */
  153 + /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RxD */
  154 + /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TxD */
  155 + /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */
  156 + /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */
  157 + /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */
  158 + /* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* PD26 */
  159 + /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */
  160 + /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */
  161 + /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */
  162 + /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */
  163 + /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */
  164 + /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */
  165 + /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */
  166 + /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */
  167 + /* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */
  168 + /* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */
  169 + /* PD15 */ { 0, 0, 0, 0, 0, 0 }, /* PD15 */
  170 + /* PD14 */ { 0, 0, 0, 0, 0, 0 }, /* PD14 */
  171 + /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
  172 + /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
  173 + /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
  174 + /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
  175 + /* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* PD9 */
  176 + /* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* PD8 */
  177 + /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */
  178 + /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */
  179 + /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */
  180 + /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */
  181 + /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
  182 + /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
  183 + /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
  184 + /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */
  185 + }
  186 +};
  187 +
  188 +long int initdram(int board_type)
  189 +{
  190 + long int msize = CFG_SDRAM_SIZE;
  191 +
  192 +#ifndef CFG_RAMBOOT
  193 + volatile immap_t *immap = (immap_t *)CFG_IMMR;
  194 + volatile memctl8260_t *memctl = &immap->im_memctl;
  195 + vu_char *ramaddr = (vu_char *)CFG_SDRAM_BASE;
  196 + uchar c = 0xFF;
  197 + uint psdmr = CFG_PSDMR;
  198 + int i;
  199 +
  200 + immap->im_siu_conf.sc_ppc_acr = 0x02;
  201 + immap->im_siu_conf.sc_ppc_alrh = 0x30126745;
  202 + immap->im_siu_conf.sc_tescr1 = 0x00004000;
  203 +
  204 + memctl->memc_mptpr = CFG_MPTPR;
  205 +
  206 + /* Initialise 60x bus SDRAM */
  207 + memctl->memc_psrt = CFG_PSRT;
  208 + memctl->memc_or1 = CFG_SDRAM_OR;
  209 + memctl->memc_br1 = CFG_SDRAM_BR;
  210 + memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */
  211 + *ramaddr = c;
  212 + memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */
  213 + for (i = 0; i < 8; i++)
  214 + *ramaddr = c;
  215 + memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; /* Mode Register write */
  216 + *ramaddr = c;
  217 + memctl->memc_psdmr = psdmr | PSDMR_RFEN; /* Refresh enable */
  218 + *ramaddr = c;
  219 +#endif /* !CFG_RAMBOOT */
  220 +
  221 + /* Return total 60x bus SDRAM size */
  222 + return msize * 1024 * 1024;
  223 +}
  224 +
  225 +int checkboard(void)
  226 +{
  227 + vu_char *bcsr = (vu_char *)CFG_BCSR;
  228 +
  229 + printf("Board: Rattler Rev. %c\n", bcsr[0x20] + 0x40);
  230 + return 0;
  231 +}
board/rattler/u-boot.lds
Diff comments   View file @ 8b0bfc6
  1 +/*
  2 + * (C) Copyright 2001-2005
  3 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4 + *
  5 + * Modified by Yuli Barcohen <yuli@arabellasw.com>
  6 + *
  7 + * See file CREDITS for list of people who contributed to this
  8 + * project.
  9 + *
  10 + * This program is free software; you can redistribute it and/or
  11 + * modify it under the terms of the GNU General Public License as
  12 + * published by the Free Software Foundation; either version 2 of
  13 + * the License, or (at your option) any later version.
  14 + *
  15 + * This program is distributed in the hope that it will be useful,
  16 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18 + * GNU General Public License for more details.
  19 + *
  20 + * You should have received a copy of the GNU General Public License
  21 + * along with this program; if not, write to the Free Software
  22 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23 + * MA 02111-1307 USA
  24 + */
  25 +
  26 +OUTPUT_ARCH(powerpc)
  27 +SECTIONS
  28 +{
  29 + /* Read-only sections, merged into text segment: */
  30 + . = + SIZEOF_HEADERS;
  31 + .interp : { *(.interp) }
  32 + .hash : { *(.hash) }
  33 + .dynsym : { *(.dynsym) }
  34 + .dynstr : { *(.dynstr) }
  35 + .rel.text : { *(.rel.text) }
  36 + .rela.text : { *(.rela.text) }
  37 + .rel.data : { *(.rel.data) }
  38 + .rela.data : { *(.rela.data) }
  39 + .rel.rodata : { *(.rel.rodata) }
  40 + .rela.rodata : { *(.rela.rodata) }
  41 + .rel.got : { *(.rel.got) }
  42 + .rela.got : { *(.rela.got) }
  43 + .rel.ctors : { *(.rel.ctors) }
  44 + .rela.ctors : { *(.rela.ctors) }
  45 + .rel.dtors : { *(.rel.dtors) }
  46 + .rela.dtors : { *(.rela.dtors) }
  47 + .rel.bss : { *(.rel.bss) }
  48 + .rela.bss : { *(.rela.bss) }
  49 + .rel.plt : { *(.rel.plt) }
  50 + .rela.plt : { *(.rela.plt) }
  51 + .init : { *(.init) }
  52 + .plt : { *(.plt) }
  53 + .text :
  54 + {
  55 + cpu/mpc8260/start.o (.text)
  56 + *(.text)
  57 + *(.fixup)
  58 + *(.got1)
  59 + . = ALIGN(16);
  60 + *(.rodata)
  61 + *(.rodata1)
  62 + *(.rodata.str1.4)
  63 + }
  64 + .fini : { *(.fini) } =0
  65 + .ctors : { *(.ctors) }
  66 + .dtors : { *(.dtors) }
  67 +
  68 + /* Read-write section, merged into data segment: */
  69 + . = (. + 0x0FFF) & 0xFFFFF000;
  70 + _erotext = .;
  71 + PROVIDE (erotext = .);
  72 + .reloc :
  73 + {
  74 + *(.got)
  75 + _GOT2_TABLE_ = .;
  76 + *(.got2)
  77 + _FIXUP_TABLE_ = .;
  78 + *(.fixup)
  79 + }
  80 + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2;
  81 + __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
  82 +
  83 + .data :
  84 + {
  85 + *(.data)
  86 + *(.data1)
  87 + *(.sdata)
  88 + *(.sdata2)
  89 + *(.dynamic)
  90 + CONSTRUCTORS
  91 + }
  92 + _edata = .;
  93 + PROVIDE (edata = .);
  94 +
  95 + __u_boot_cmd_start = .;
  96 + .u_boot_cmd : { *(.u_boot_cmd) }
  97 + __u_boot_cmd_end = .;
  98 +
  99 +
  100 + __start___ex_table = .;
  101 + __ex_table : { *(__ex_table) }
  102 + __stop___ex_table = .;
  103 +
  104 + . = ALIGN(4096);
  105 + __init_begin = .;
  106 + .text.init : { *(.text.init) }
  107 + .data.init : { *(.data.init) }
  108 + . = ALIGN(4096);
  109 + __init_end = .;
  110 +
  111 + __bss_start = .;
  112 + .bss :
  113 + {
  114 + *(.sbss) *(.scommon)
  115 + *(.dynbss)
  116 + *(.bss)
  117 + *(COMMON)
  118 + }
  119 + _end = . ;
  120 + PROVIDE (end = .);
  121 +}
  122 +ENTRY(_start)
... ... @@ -40,13 +40,13 @@
40 40 #include <post.h>
41 41 #endif
42 42 #include <lcd.h>
  43 +#include <watchdog.h>
43 44  
44 45 #if defined(CONFIG_PXA250)
45 46 #include <asm/byteorder.h>
46 47 #endif
47 48  
48 49 #if defined(CONFIG_MPC823)
49   -#include <watchdog.h>
50 50 #include <lcdvideo.h>
51 51 #endif
52 52  
cpu/mpc824x/cpu_init.c
Diff comments   View file @ 8b0bfc6
... ... @@ -106,6 +106,21 @@
106 106 CONFIG_READ_BYTE(AMBOR,val);
107 107 CONFIG_WRITE_BYTE(AMBOR,val|0x1);
108 108  
  109 +#if 0
  110 + /*
  111 + * The following bug only affects older (XPC8245) processors.
  112 + * DMA transfers initiated by external devices get corrupted due
  113 + * to a hardware scheduling problem.
  114 + *
  115 + * The effect is:
  116 + * when transferring X words, the first 32 words are transferred
  117 + * OK, the next 3 x 32 words are 'old' data (from previous DMA)
  118 + * while the rest of the X words is xferred fine.
  119 + *
  120 + * Disabling 3 of the 4 32 word hardware buffers solves the problem
  121 + * with no significant performance loss.
  122 + */
  123 +
109 124 CONFIG_READ_BYTE(PCMBCR,val);
110 125 /* in order not to corrupt data which is being read over the PCI bus
111 126 * with the PPC as slave, we need to reduce the number of PCMRBs to 1,
... ... @@ -117,10 +132,8 @@
117 132 #else
118 133 CONFIG_WRITE_BYTE(PCMBCR,(val|0x80)); /* 2 PCMRBs */
119 134 CONFIG_WRITE_BYTE(PCMBCR,(val|0x40)); /* 3 PCMRBs */
120   - /* default, 4 PCMRBs are used, so don't change the
121   - * register is this is _really_ what you want: data
122   - * corruption with no performance gain
123   - */
  135 + /* default, 4 PCMRBs are used */
  136 +#endif
124 137 #endif
125 138 #endif
126 139  
include/configs/CPU87.h
Diff comments   View file @ 8b0bfc6
... ... @@ -113,8 +113,6 @@
113 113  
114 114 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
115 115  
116   -#undef CONFIG_CLOCKS_IN_MHZ
117   -
118 116 #define CONFIG_PREBOOT \
119 117 "echo; " \
120 118 "echo Type \"run flash_nfs\" to mount root filesystem over NFS; " \
include/configs/PM854.h
Diff comments   View file @ 8b0bfc6
... ... @@ -144,19 +144,14 @@
144 144 #undef CFG_RAMBOOT
145 145 #endif
146 146  
147   -
148   -#undef CONFIG_CLOCKS_IN_MHZ
149   -
150   -
151 147 /*
152 148 * Local Bus Definitions
153 149 */
154   -
155 150 #define CFG_LBC_LCRR 0x00030004 /* LB clock ratio reg */
156 151 #define CFG_LBC_LBCR 0x00000000 /* LB config reg */
157 152 #define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
158 153 #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
159   -
  154 +
160 155  
161 156 #define CONFIG_L1_INIT_RAM
162 157 #define CFG_INIT_RAM_LOCK 1
include/configs/Rattler.h
Diff comments   View file @ 8b0bfc6
  1 +/*
  2 + * Copyright (C) 2004 Arabella Software Ltd.
  3 + * Yuli Barcohen <yuli@arabellasw.com>
  4 + *
  5 + * U-Boot configuration for Analogue&Micro Rattler boards.
  6 + *
  7 + * See file CREDITS for list of people who contributed to this
  8 + * project.
  9 + *
  10 + * This program is free software; you can redistribute it and/or
  11 + * modify it under the terms of the GNU General Public License as
  12 + * published by the Free Software Foundation; either version 2 of
  13 + * the License, or (at your option) any later version.
  14 + *
  15 + * This program is distributed in the hope that it will be useful,
  16 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18 + * GNU General Public License for more details.
  19 + *
  20 + * You should have received a copy of the GNU General Public License
  21 + * along with this program; if not, write to the Free Software
  22 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23 + * MA 02111-1307 USA
  24 + */
  25 +
  26 +#ifndef __CONFIG_H
  27 +#define __CONFIG_H
  28 +
  29 +#ifdef CONFIG_MPC8248
  30 +#define CPU_ID_STR "MPC8248"
  31 +#else
  32 +#define CONFIG_MPC8260
  33 +#define CPU_ID_STR "MPC8250"
  34 +#endif /* CONFIG_MPC8248 */
  35 +
  36 +#define CONFIG_RATTLER /* Analogue&Micro Rattler board */
  37 +
  38 +#undef DEBUG
  39 +
  40 +/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
  41 +#define CONFIG_ENV_OVERWRITE
  42 +
  43 +/*
  44 + * Select serial console configuration
  45 + *
  46 + * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  47 + * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  48 + * for SCC).
  49 + */
  50 +#define CONFIG_CONS_ON_SMC /* Console is on SMC */
  51 +#undef CONFIG_CONS_ON_SCC /* It's not on SCC */
  52 +#undef CONFIG_CONS_NONE /* It's not on external UART */
  53 +#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */
  54 +
  55 +/*
  56 + * Select ethernet configuration
  57 + *
  58 + * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
  59 + * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
  60 + * SCC, 1-3 for FCC)
  61 + *
  62 + * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
  63 + * must be defined elsewhere (as for the console), or CFG_CMD_NET must
  64 + * be removed from CONFIG_COMMANDS to remove support for networking.
  65 + */
  66 +#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */
  67 +#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */
  68 +#undef CONFIG_ETHER_NONE /* No external Ethernet */
  69 +
  70 +#ifdef CONFIG_ETHER_ON_FCC
  71 +
  72 +#define CONFIG_ETHER_INDEX 1 /* FCC1 is used for Ethernet */
  73 +
  74 +#if (CONFIG_ETHER_INDEX == 1)
  75 +
  76 +/* - Rx clock is CLK11
  77 + * - Tx clock is CLK10
  78 + * - BDs/buffers on 60x bus
  79 + * - Full duplex
  80 + */
  81 +#define CFG_CMXFCR_MASK (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
  82 +#define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK10)
  83 +#define CFG_CPMFCR_RAMTYPE 0
  84 +#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
  85 +
  86 +#elif (CONFIG_ETHER_INDEX == 2)
  87 +
  88 +/* - Rx clock is CLK15
  89 + * - Tx clock is CLK14
  90 + * - BDs/buffers on 60x bus
  91 + * - Full duplex
  92 + */
  93 +#define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
  94 +#define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK14)
  95 +#define CFG_CPMFCR_RAMTYPE 0
  96 +#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
  97 +
  98 +#endif /* CONFIG_ETHER_INDEX */
  99 +
  100 +#define CONFIG_MII /* MII PHY management */
  101 +#define CONFIG_BITBANGMII /* Bit-banged MDIO interface */
  102 +/*
  103 + * GPIO pins used for bit-banged MII communications
  104 + */
  105 +#define MDIO_PORT 2 /* Port C */
  106 +#define MDIO_ACTIVE (iop->pdir |= 0x00400000)
  107 +#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
  108 +#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
  109 +
  110 +#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
  111 + else iop->pdat &= ~0x00400000
  112 +
  113 +#define MDC(bit) if(bit) iop->pdat |= 0x00800000; \
  114 + else iop->pdat &= ~0x00800000
  115 +
  116 +#define MIIDELAY udelay(1)
  117 +
  118 +#endif /* CONFIG_ETHER_ON_FCC */
  119 +
  120 +#ifndef CONFIG_8260_CLKIN
  121 +#define CONFIG_8260_CLKIN 100000000 /* in Hz */
  122 +#endif
  123 +
  124 +#define CONFIG_BAUDRATE 38400
  125 +
  126 +#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
  127 + | CFG_CMD_DHCP \
  128 + | CFG_CMD_ECHO \
  129 + | CFG_CMD_IMMAP \
  130 + | CFG_CMD_JFFS2 \
  131 + | CFG_CMD_MII \
  132 + | CFG_CMD_PING \
  133 + )
  134 +
  135 +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  136 +#include <cmd_confdefs.h>
  137 +
  138 +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
  139 +#define CONFIG_BOOTCOMMAND "bootm FE040000" /* autoboot command */
  140 +#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw mtdparts=phys:1M(ROM)ro,-(root)"
  141 +
  142 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  143 +#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
  144 +#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
  145 +#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
  146 +#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
  147 +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
  148 +#endif
  149 +
  150 +#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
  151 +#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
  152 +
  153 +/*
  154 + * Miscellaneous configurable options
  155 + */
  156 +#define CFG_HUSH_PARSER
  157 +#define CFG_PROMPT_HUSH_PS2 "> "
  158 +#define CFG_LONGHELP /* undef to save memory */
  159 +#define CFG_PROMPT "=> " /* Monitor Command Prompt */
  160 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  161 +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
  162 +#else
  163 +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
  164 +#endif
  165 +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  166 +#define CFG_MAXARGS 16 /* max number of command args */
  167 +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
  168 +
  169 +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
  170 +#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
  171 +
  172 +#define CFG_LOAD_ADDR 0x100000 /* default load address */
  173 +
  174 +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
  175 +
  176 +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
  177 +
  178 +#define CFG_FLASH_BASE 0xFE000000
  179 +#define CFG_FLASH_CFI
  180 +#define CFG_FLASH_CFI_DRIVER
  181 +#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */
  182 +#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */
  183 +
  184 +#define CFG_DIRECT_FLASH_TFTP
  185 +
  186 +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
  187 +#define CFG_JFFS2_FIRST_BANK 0
  188 +#define CFG_JFFS2_NUM_BANKS CFG_MAX_FLASH_BANKS
  189 +#define CFG_JFFS2_FIRST_SECTOR 16
  190 +#define CFG_JFFS2_SORT_FRAGMENTS
  191 +#endif /* CFG_CMD_JFFS2 */
  192 +
  193 +#define CFG_MONITOR_BASE TEXT_BASE
  194 +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
  195 +#define CFG_RAMBOOT
  196 +#endif
  197 +
  198 +#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
  199 +
  200 +#define CFG_ENV_IS_IN_FLASH
  201 +
  202 +#ifdef CFG_ENV_IS_IN_FLASH
  203 +#define CFG_ENV_SECT_SIZE 0x10000
  204 +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
  205 +#endif /* CFG_ENV_IS_IN_FLASH */
  206 +
  207 +#define CFG_DEFAULT_IMMR 0xFF010000
  208 +
  209 +#define CFG_IMMR 0xF0000000
  210 +
  211 +#define CFG_INIT_RAM_ADDR CFG_IMMR
  212 +#define CFG_INIT_RAM_END 0x2000 /* End of used area in DPRAM */
  213 +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
  214 +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  215 +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
  216 +
  217 +#define CFG_SDRAM_BASE 0x00000000
  218 +#define CFG_SDRAM_SIZE 32
  219 +#define CFG_SDRAM_BR (CFG_SDRAM_BASE | 0x00000041)
  220 +#define CFG_SDRAM_OR 0xFE002EC0
  221 +
  222 +#define CFG_BCSR 0xFC000000
  223 +
  224 +/* Hard reset configuration word */
  225 +#define CFG_HRCW_MASTER 0x0A06875A /* Not used - provided by FPGA */
  226 +/* No slaves */
  227 +#define CFG_HRCW_SLAVE1 0
  228 +#define CFG_HRCW_SLAVE2 0
  229 +#define CFG_HRCW_SLAVE3 0
  230 +#define CFG_HRCW_SLAVE4 0
  231 +#define CFG_HRCW_SLAVE5 0
  232 +#define CFG_HRCW_SLAVE6 0
  233 +#define CFG_HRCW_SLAVE7 0
  234 +
  235 +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  236 +#define BOOTFLAG_WARM 0x02 /* Software reboot */
  237 +
  238 +#define CFG_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
  239 +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  240 +
  241 +#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
  242 +#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  243 +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
  244 +#endif
  245 +
  246 +#define CFG_HID0_INIT 0
  247 +#define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE)
  248 +
  249 +#define CFG_HID2 0
  250 +
  251 +#define CFG_SIUMCR 0x0E04C000
  252 +#define CFG_SYPCR 0xFFFFFFC3
  253 +#define CFG_BCR 0x00000000
  254 +#define CFG_SCCR SCCR_DFBRG01
  255 +
  256 +#define CFG_RMR RMR_CSRE
  257 +#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
  258 +#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
  259 +#define CFG_RCCR 0
  260 +
  261 +#define CFG_PSDMR 0x8249A452
  262 +#define CFG_PSRT 0x1F
  263 +#define CFG_MPTPR 0x2000
  264 +
  265 +#define CFG_BR0_PRELIM (CFG_FLASH_BASE | 0x00001001)
  266 +#define CFG_OR0_PRELIM 0xFF001ED6
  267 +#define CFG_BR7_PRELIM (CFG_BCSR | 0x00000801)
  268 +#define CFG_OR7_PRELIM 0xFFFF87F6
  269 +
  270 +#define CFG_RESET_ADDRESS 0xC0000000
  271 +
  272 +#endif /* __CONFIG_H */