Commit 8b2a31f13362521e65ccb4c7d73db467068e8e6a
Committed by
Stefano Babic
1 parent
2d58296f3e
Exists in
smarc_8mq_lf_v2020.04
and in
12 other branches
gpio: mxc_gpio: add support for i.MX8
Add i.MX8 support, there are 8 GPIO banks. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Anatolij Gustschin <agust@denx.de> Cc: Stefano Babic <sbabic@denx.de>
Showing 2 changed files with 42 additions and 9 deletions Side-by-side Diff
arch/arm/include/asm/arch-imx8/gpio.h
1 | +/* SPDX-License-Identifier: GPL-2.0+ */ | |
2 | +/* | |
3 | + * Copyright 2018 NXP | |
4 | + */ | |
5 | + | |
6 | +#ifndef __ASM_ARCH_IMX8_GPIO_H | |
7 | +#define __ASM_ARCH_IMX8_GPIO_H | |
8 | + | |
9 | +#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) | |
10 | +/* GPIO registers */ | |
11 | +struct gpio_regs { | |
12 | + u32 gpio_dr; /* data */ | |
13 | + u32 gpio_dir; /* direction */ | |
14 | + u32 gpio_psr; /* pad satus */ | |
15 | +}; | |
16 | +#endif | |
17 | + | |
18 | +/* IMX8 the GPIO index is from 0 not 1 */ | |
19 | +#define IMX_GPIO_NR(port, index) (((port) * 32) + ((index) & 31)) | |
20 | + | |
21 | +#endif /* __ASM_ARCH_IMX8_GPIO_H */ |
drivers/gpio/mxc_gpio.c
... | ... | @@ -40,21 +40,27 @@ |
40 | 40 | [2] = GPIO3_BASE_ADDR, |
41 | 41 | #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \ |
42 | 42 | defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ |
43 | - defined(CONFIG_MX7) || defined(CONFIG_MX8M) | |
43 | + defined(CONFIG_MX7) || defined(CONFIG_MX8M) || \ | |
44 | + defined(CONFIG_ARCH_IMX8) | |
44 | 45 | [3] = GPIO4_BASE_ADDR, |
45 | 46 | #endif |
46 | 47 | #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ |
47 | - defined(CONFIG_MX7) || defined(CONFIG_MX8M) | |
48 | + defined(CONFIG_MX7) || defined(CONFIG_MX8M) || \ | |
49 | + defined(CONFIG_ARCH_IMX8) | |
48 | 50 | [4] = GPIO5_BASE_ADDR, |
49 | 51 | #if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL) || defined(CONFIG_MX8M)) |
50 | 52 | [5] = GPIO6_BASE_ADDR, |
51 | 53 | #endif |
52 | 54 | #endif |
53 | -#if defined(CONFIG_MX53) || defined(CONFIG_MX6) || defined(CONFIG_MX7) | |
55 | +#if defined(CONFIG_MX53) || defined(CONFIG_MX6) || defined(CONFIG_MX7) || \ | |
56 | + defined(CONFIG_ARCH_IMX8) | |
54 | 57 | #if !(defined(CONFIG_MX6UL) || defined(CONFIG_MX6ULL)) |
55 | 58 | [6] = GPIO7_BASE_ADDR, |
56 | 59 | #endif |
57 | 60 | #endif |
61 | +#if defined(CONFIG_ARCH_IMX8) | |
62 | + [7] = GPIO8_BASE_ADDR, | |
63 | +#endif | |
58 | 64 | }; |
59 | 65 | |
60 | 66 | static int mxc_gpio_direction(unsigned int gpio, |
61 | 67 | |
62 | 68 | |
63 | 69 | |
... | ... | @@ -347,19 +353,22 @@ |
347 | 353 | { 2, (struct gpio_regs *)GPIO3_BASE_ADDR }, |
348 | 354 | #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \ |
349 | 355 | defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ |
350 | - defined(CONFIG_MX8M) | |
356 | + defined(CONFIG_MX8M) || defined(CONFIG_ARCH_IMX8) | |
351 | 357 | { 3, (struct gpio_regs *)GPIO4_BASE_ADDR }, |
352 | 358 | #endif |
353 | 359 | #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ |
354 | - defined(CONFIG_MX8M) | |
360 | + defined(CONFIG_MX8M) || defined(CONFIG_ARCH_IMX8) | |
355 | 361 | { 4, (struct gpio_regs *)GPIO5_BASE_ADDR }, |
356 | 362 | #ifndef CONFIG_MX8M |
357 | 363 | { 5, (struct gpio_regs *)GPIO6_BASE_ADDR }, |
358 | 364 | #endif |
359 | 365 | #endif |
360 | -#if defined(CONFIG_MX53) || defined(CONFIG_MX6) | |
366 | +#if defined(CONFIG_MX53) || defined(CONFIG_MX6) || defined(CONFIG_ARCH_IMX8) | |
361 | 367 | { 6, (struct gpio_regs *)GPIO7_BASE_ADDR }, |
362 | 368 | #endif |
369 | +#if defined(CONFIG_ARCH_IMX8) | |
370 | + { 7, (struct gpio_regs *)GPIO8_BASE_ADDR }, | |
371 | +#endif | |
363 | 372 | }; |
364 | 373 | |
365 | 374 | U_BOOT_DEVICES(mxc_gpios) = { |
366 | 375 | |
367 | 376 | |
368 | 377 | |
... | ... | @@ -368,18 +377,21 @@ |
368 | 377 | { "gpio_mxc", &mxc_plat[2] }, |
369 | 378 | #if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \ |
370 | 379 | defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ |
371 | - defined(CONFIG_MX8M) | |
380 | + defined(CONFIG_MX8M) || defined(CONFIG_ARCH_IMX8) | |
372 | 381 | { "gpio_mxc", &mxc_plat[3] }, |
373 | 382 | #endif |
374 | 383 | #if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6) || \ |
375 | - defined(CONFIG_MX8M) | |
384 | + defined(CONFIG_MX8M) || defined(CONFIG_ARCH_IMX8) | |
376 | 385 | { "gpio_mxc", &mxc_plat[4] }, |
377 | 386 | #ifndef CONFIG_MX8M |
378 | 387 | { "gpio_mxc", &mxc_plat[5] }, |
379 | 388 | #endif |
380 | 389 | #endif |
381 | -#if defined(CONFIG_MX53) || defined(CONFIG_MX6) | |
390 | +#if defined(CONFIG_MX53) || defined(CONFIG_MX6) || defined(CONFIG_ARCH_IMX8) | |
382 | 391 | { "gpio_mxc", &mxc_plat[6] }, |
392 | +#endif | |
393 | +#if defined(CONFIG_ARCH_IMX8) | |
394 | + { "gpio_mxc", &mxc_plat[7] }, | |
383 | 395 | #endif |
384 | 396 | }; |
385 | 397 | #endif |