s5pc1xx: add support SMDKC100 board

Adds new board SMDKC100 that uses s5pc100 SoC Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: HeungJun, Kim <riverful.kim@samsung.com>

s5pc1xx: add support SMDKC100 board
Adds new board SMDKC100 that uses s5pc100 SoC Signed-off-by: Minkyu Kang <mk7.kang@samsung.com> Signed-off-by: HeungJun, Kim <riverful.kim@samsung.com>
Minkyu Kang · Tom Rix
1 parent dd2c9e6a3b
Showing 11 changed files with 923 additions and 0 deletions Side-by-side Diff
MAINTAINERS
MAKEALL
Makefile
board/samsung/smdkc100/Makefile
board/samsung/smdkc100/config.mk
board/samsung/smdkc100/lowlevel_init.S
board/samsung/smdkc100/mem_setup.S
board/samsung/smdkc100/onenand.c
board/samsung/smdkc100/smdkc100.c
doc/README.s5pc1xx
include/configs/smdkc100.h
@@ -735,6 +735,10 @@
 	lart		SA1100
 	dnp1110		SA1110
  
+Minkyu Kang <mk7.kang@samsung.com>
+
+	SMDKC100	ARM CORTEX-A8 (S5PC100 SoC)
+
 -------------------------------------------------------------------------
  
 Unknown / orphaned boards:
@@ -605,6 +605,7 @@
 	omap3_pandora		\
 	omap3_zoom1		\
 	omap3_zoom2		\
+	smdkc100		\
 "
  
 #########################################################################
@@ -3144,6 +3144,9 @@
 omap3_zoom2_config :	unconfig
 	@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 zoom2 logicpd omap3
  
+smdkc100_config:	unconfig
+	@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 smdkc100 samsung s5pc1xx
+
 #########################################################################
 ## XScale Systems
 #########################################################################
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS-y	:= smdkc100.o
+COBJS-$(CONFIG_SAMSUNG_ONENAND)	+= onenand.o
+SOBJS	:= lowlevel_init.o
+
+SRCS    := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(SOBJS) $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(SOBJS) $(OBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
+#
+# Copyright (C) 2008 # Samsung Elecgtronics
+# Kyungmin Park <kyungmin.park@samsung.com>
+#
+
+# On S5PC100 we use the 128 MiB OneDRAM bank at
+#
+# 0x30000000 to 0x35000000 (80MiB)
+# 0x38000000 to 0x40000000 (128MiB)
+#
+# On S5PC110 we use the 128 MiB OneDRAM bank at
+#
+# 0x30000000 to 0x35000000 (80MiB)
+# 0x40000000 to 0x48000000 (128MiB)
+#
+TEXT_BASE = 0x34800000
+/*
+ * Copyright (C) 2009 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/power.h>
+
+/*
+ * Register usages:
+ *
+ * r5 has zero always
+ */
+
+_TEXT_BASE:
+	.word	TEXT_BASE
+
+	.globl lowlevel_init
+lowlevel_init:
+	mov	r9, lr
+
+	/* r5 has always zero */
+	mov	r5, #0
+
+	ldr	r8, =S5PC100_GPIO_BASE
+
+	/* Disable Watchdog */
+	ldr	r0, =S5PC100_WATCHDOG_BASE		@0xEA200000
+	orr	r0, r0, #0x0
+	str	r5, [r0]
+
+#ifndef CONFIG_ONENAND_IPL
+	/* setting SRAM */
+	ldr	r0, =S5PC100_SROMC_BASE
+	ldr	r1, =0x9
+	str	r1, [r0]
+#endif
+
+	/* S5PC100 has 3 groups of interrupt sources */
+	ldr	r0, =S5PC100_VIC0_BASE			@0xE4000000
+	ldr	r1, =S5PC100_VIC1_BASE			@0xE4000000
+	ldr	r2, =S5PC100_VIC2_BASE			@0xE4000000
+
+	/* Disable all interrupts (VIC0, VIC1 and VIC2) */
+	mvn	r3, #0x0
+	str	r3, [r0, #0x14]				@INTENCLEAR
+	str	r3, [r1, #0x14]				@INTENCLEAR
+	str	r3, [r2, #0x14]				@INTENCLEAR
+
+#ifndef CONFIG_ONENAND_IPL
+	/* Set all interrupts as IRQ */
+	str	r5, [r0, #0xc]				@INTSELECT
+	str	r5, [r1, #0xc]				@INTSELECT
+	str	r5, [r2, #0xc]				@INTSELECT
+
+	/* Pending Interrupt Clear */
+	str	r5, [r0, #0xf00]			@INTADDRESS
+	str	r5, [r1, #0xf00]			@INTADDRESS
+	str	r5, [r2, #0xf00]			@INTADDRESS
+#endif
+
+#ifndef CONFIG_ONENAND_IPL
+	/* for UART */
+	bl uart_asm_init
+
+	/* for TZPC */
+	bl tzpc_asm_init
+#endif
+
+#ifdef CONFIG_ONENAND_IPL
+	/* init system clock */
+	bl	system_clock_init
+
+	bl	mem_ctrl_asm_init
+
+	/* Wakeup support. Don't know if it's going to be used, untested. */
+	ldr	r0, =S5PC100_RST_STAT
+	ldr	r1, [r0]
+	bic	r1, r1, #0xfffffff7
+	cmp	r1, #0x8
+	beq	wakeup_reset
+#endif
+
+1:
+	mov	lr, r9
+	mov	pc, lr
+
+#ifdef CONFIG_ONENAND_IPL
+wakeup_reset:
+
+	/* Clear wakeup status register */
+	ldr	r0, =S5PC100_WAKEUP_STAT
+	ldr	r1, [r0]
+	str	r1, [r0]
+
+	/* Load return address and jump to kernel */
+	ldr	r0, =S5PC100_INFORM0
+
+	/* r1 = physical address of s5pc100_cpu_resume function */
+	ldr	r1, [r0]
+
+	/* Jump to kernel (sleep.S) */
+	mov	pc, r1
+	nop
+	nop
+#endif
+
+/*
+ * system_clock_init: Initialize core clock and bus clock.
+ * void system_clock_init(void)
+ */
+system_clock_init:
+	ldr	r8, =S5PC1XX_CLOCK_BASE		@ 0xE0100000
+
+	/* Set Clock divider */
+	ldr	r1, =0x00011110
+	str	r1, [r8, #0x304]
+	ldr	r1, =0x1
+	str	r1, [r8, #0x308]
+	ldr	r1, =0x00011301
+	str	r1, [r8, #0x300]
+
+	/* Set Lock Time */
+	ldr	r1, =0xe10			@ Locktime : 0xe10 = 3600
+	str	r1, [r8, #0x000]		@ APLL_LOCK
+	str	r1, [r8, #0x004]		@ MPLL_LOCK
+	str	r1, [r8, #0x008]		@ EPLL_LOCK
+	str	r1, [r8, #0x00C]		@ HPLL_LOCK
+
+	/* APLL_CON */
+	ldr	r1, =0x81bc0400		@ SDIV 0, PDIV 4, MDIV 444 (1332MHz)
+	str	r1, [r8, #0x100]
+	/* MPLL_CON */
+	ldr	r1, =0x80590201		@ SDIV 1, PDIV 2, MDIV 89 (267MHz)
+	str	r1, [r8, #0x104]
+	/* EPLL_CON */
+	ldr	r1, =0x80870303		@ SDIV 3, PDIV 3, MDIV 135 (67.5MHz)
+	str	r1, [r8, #0x108]
+	/* HPLL_CON */
+	ldr	r1, =0x80600603
+	str	r1, [r8, #0x10C]
+
+	/* Set Source Clock */
+	ldr	r1, =0x1111			@ A, M, E, HPLL Muxing
+	str	r1, [r8, #0x200]		@ CLK_SRC0
+
+	ldr	r1, =0x1000001			@ Uart Clock & CLK48M Muxing
+	str	r1, [r8, #0x204]		@ CLK_SRC1
+
+	ldr	r1, =0x9000			@ ARMCLK/4
+	str	r1, [r8, #0x400]		@ CLK_OUT
+
+	/* wait at least 200us to stablize all clock */
+	mov	r2, #0x10000
+1:	subs	r2, r2, #1
+	bne	1b
+
+	mov	pc, lr
+
+#ifndef CONFIG_ONENAND_IPL
+/*
+ * uart_asm_init: Initialize UART's pins
+ */
+uart_asm_init:
+	mov	r0, r8
+	ldr	r1, =0x22222222
+	str	r1, [r0, #0x0]			@ GPA0_CON
+	ldr	r1, =0x00022222
+	str	r1, [r0, #0x20]			@ GPA1_CON
+
+	mov	pc, lr
+
+/*
+ * tzpc_asm_init: Initialize TZPC
+ */
+tzpc_asm_init:
+	ldr	r0, =0xE3800000
+	mov	r1, #0x0
+	str	r1, [r0]
+	mov	r1, #0xff
+	str	r1, [r0, #0x804]
+	str	r1, [r0, #0x810]
+
+	ldr	r0, =0xE2800000
+	str	r1, [r0, #0x804]
+	str	r1, [r0, #0x810]
+	str	r1, [r0, #0x81C]
+
+	ldr	r0, =0xE2900000
+	str	r1, [r0, #0x804]
+	str	r1, [r0, #0x810]
+
+	mov	pc, lr
+#endif
+/*
+ * Originates from Samsung's u-boot 1.1.6 port to S5PC1xx
+ *
+ * Copyright (C) 2009 Samsung Electrnoics
+ * Inki Dae <inki.dae@samsung.com>
+ * Heungjun Kim <riverful.kim@samsung.com>
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+
+	.globl mem_ctrl_asm_init
+mem_ctrl_asm_init:
+	ldr	r6, =S5PC100_DMC_BASE			@ 0xE6000000
+
+	/* DLL parameter setting */
+	ldr	r1, =0x50101000
+	str	r1, [r6, #0x018]			@ PHYCONTROL0
+	ldr	r1, =0xf4
+	str	r1, [r6, #0x01C]			@ PHYCONTROL1
+	ldr	r1, =0x0
+	str	r1, [r6, #0x020]			@ PHYCONTROL2
+
+	/* DLL on */
+	ldr	r1, =0x50101002
+	str	r1, [r6, #0x018]			@ PHYCONTROL0
+
+	/* DLL start */
+	ldr	r1, =0x50101003
+	str	r1, [r6, #0x018]			@ PHYCONTROL0
+
+	/* Force value locking for DLL off */
+	str	r1, [r6, #0x018]			@ PHYCONTROL0
+
+	/* DLL off */
+	ldr	r1, =0x50101001
+	str	r1, [r6, #0x018]			@ PHYCONTROL0
+
+	/* auto refresh off */
+	ldr	r1, =0xff001010
+	str	r1, [r6, #0x000]			@ CONCONTROL
+
+	/*
+	 * Burst Length 4, 2 chips, 32-bit, LPDDR
+	 * OFF: dynamic self refresh, force precharge, dynamic power down off
+	 */
+	ldr	r1, =0x00212100
+	str	r1, [r6, #0x004]			@ MEMCONTROL
+
+	/*
+	 * Note:
+	 * If Bank0 has OneDRAM we place it at 0x2800'0000
+	 * So finally Bank1 should address start at at 0x2000'0000
+	 */
+	mov	r4, #0x0
+
+swap_memory:
+	/*
+	 * Bank0
+	 * 0x30 -> 0x30000000
+	 * 0xf8 -> 0x37FFFFFF
+	 * [15:12] 0: Linear
+	 * [11:8 ] 2: 9 bits
+	 * [ 7:4 ] 2: 14 bits
+	 * [ 3:0 ] 2: 4 banks
+	 */
+	ldr	r1, =0x30f80222
+	/* if r4 is 1, swap the bank */
+	cmp	r4, #0x1
+	orreq	r1, r1, #0x08000000
+	str	r1, [r6, #0x008]			@ MEMCONFIG0
+
+	/*
+	 * Bank1
+	 * 0x38 -> 0x38000000
+	 * 0xf8 -> 0x3fFFFFFF
+	 * [15:12] 0: Linear
+	 * [11:8 ] 2: 9 bits
+	 * [ 7:4 ] 2: 14 bits
+	 * [ 3:0 ] 2: 4 banks
+	 */
+	ldr	r1, =0x38f80222
+	/* if r4 is 1, swap the bank */
+	cmp	r4, #0x1
+	biceq	r1, r1, #0x08000000
+	str	r1, [r6, #0x00c]			@ MEMCONFIG1
+
+	ldr	r1, =0x20000000
+	str	r1, [r6, #0x014]			@ PRECHCONFIG
+
+	/*
+	 * FIXME: Please verify these values
+	 * 7.8us * 166MHz %LE %LONG1294(0x50E)
+	 * 7.8us * 133MHz %LE %LONG1038(0x40E),
+	 * 7.8us * 100MHz %LE %LONG780(0x30C),
+	 * 7.8us * 20MHz  %LE %LONG156(0x9C),
+	 * 7.8us * 10MHz  %LE %LONG78(0x4E)
+	 */
+	ldr	r1, =0x0000050e
+	str	r1, [r6, #0x030]			@ TIMINGAREF
+
+	/* 166 MHz */
+	ldr	r1, =0x0c233287
+	str	r1, [r6, #0x034]			@ TIMINGROW
+
+	/* twtr=3 twr=2 trtp=3 cl=3 wl=3 rl=3 */
+	ldr	r1, =0x32330303
+	str	r1, [r6, #0x038]			@ TIMINGDATA
+
+	/* tfaw=4 sxsr=0x14 txp=0x14 tcke=3 tmrd=3 */
+	ldr	r1, =0x04141433
+	str	r1, [r6, #0x03C]			@ TIMINGPOWER
+
+	/* chip0 Deselect */
+	ldr	r1, =0x07000000
+	str	r1, [r6, #0x010]			@ DIRECTCMD
+
+	/* chip0 PALL */
+	ldr	r1, =0x01000000
+	str	r1, [r6, #0x010]			@ DIRECTCMD
+
+	/* chip0 REFA */
+	ldr	r1, =0x05000000
+	str	r1, [r6, #0x010]			@ DIRECTCMD
+	/* chip0 REFA */
+	str	r1, [r6, #0x010]			@ DIRECTCMD
+
+	/* chip0 MRS, CL%LE %LONG3, BL%LE %LONG4 */
+	ldr	r1, =0x00000032
+	str	r1, [r6, #0x010]			@ DIRECTCMD
+
+	/* chip1 Deselect */
+	ldr	r1, =0x07100000
+	str	r1, [r6, #0x010]			@ DIRECTCMD
+
+	/* chip1 PALL */
+	ldr	r1, =0x01100000
+	str	r1, [r6, #0x010]			@ DIRECTCMD
+
+	/* chip1 REFA */
+	ldr	r1, =0x05100000
+	str	r1, [r6, #0x010]			@ DIRECTCMD
+	/* chip1 REFA */
+	str	r1, [r6, #0x010]			@ DIRECTCMD
+
+	/* chip1 MRS, CL%LE %LONG3, BL%LE %LONG4 */
+	ldr	r1, =0x00100032
+	str	r1, [r6, #0x010]			@ DIRECTCMD
+
+	/* auto refresh on */
+	ldr	r1, =0xff002030
+	str	r1, [r6, #0x000]			@ CONCONTROL
+
+	/* PwrdnConfig */
+	ldr	r1, =0x00100002
+	str	r1, [r6, #0x028]			@ PWRDNCONFIG
+
+	/* BL%LE %LONG */
+	ldr	r1, =0xff212100
+	str	r1, [r6, #0x004]			@ MEMCONTROL
+
+
+	/* Try to test memory area */
+	cmp	r4, #0x1
+	beq	1f
+
+	mov	r4, #0x1
+	ldr	r1, =0x37ffff00
+	str	r4, [r1]
+	str	r4, [r1, #0x4]				@ dummy write
+	ldr	r0, [r1]
+	cmp	r0, r4
+	bne	swap_memory
+
+1:
+	mov	pc, lr
+
+	.ltorg
+/*
+ * Copyright (C) 2008-2009 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/mtd/compat.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/onenand.h>
+#include <linux/mtd/samsung_onenand.h>
+
+#include <onenand_uboot.h>
+
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+
+void onenand_board_init(struct mtd_info *mtd)
+{
+	struct onenand_chip *this = mtd->priv;
+	struct s5pc100_clock *clk = (struct s5pc100_clock *)S5PC1XX_CLOCK_BASE;
+	struct samsung_onenand *onenand;
+	int value;
+
+	this->base = (void *)S5PC100_ONENAND_BASE;
+	onenand = (struct samsung_onenand *)this->base;
+
+	/* D0 Domain memory clock gating */
+	value = readl(&clk->gate_d01);
+	value &= ~(1 << 2);		/* CLK_ONENANDC */
+	value |= (1 << 2);
+	writel(value, &clk->gate_d01);
+
+	value = readl(&clk->src0);
+	value &= ~(1 << 24);		/* MUX_1nand: 0 from HCLKD0 */
+	value &= ~(1 << 20);		/* MUX_HREF: 0 from FIN_27M */
+	writel(value, &clk->src0);
+
+	value = readl(&clk->div1);
+	value &= ~(3 << 16);		/* PCLKD1_RATIO */
+	value |= (1 << 16);
+	writel(value, &clk->div1);
+
+	writel(ONENAND_MEM_RESET_COLD, &onenand->mem_reset);
+
+	while (!(readl(&onenand->int_err_stat) & RST_CMP))
+		continue;
+
+	writel(RST_CMP, &onenand->int_err_ack);
+
+	/*
+	 * Access_Clock [2:0]
+	 * 166 MHz, 134 Mhz : 3
+	 * 100 Mhz, 60 Mhz  : 2
+	 */
+	writel(0x3, &onenand->acc_clock);
+
+	writel(INT_ERR_ALL, &onenand->int_err_mask);
+	writel(1 << 0, &onenand->int_pin_en);	/* Enable */
+
+	value = readl(&onenand->int_err_mask);
+	value &= ~RDY_ACT;
+	writel(value, &onenand->int_err_mask);
+
+	s3c_onenand_init(mtd);
+}
+/*
+ *  Copyright (C) 2008-2009 Samsung Electronics
+ *  Minkyu Kang <mk7.kang@samsung.com>
+ *  Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+	gd->bd->bi_arch_number = MACH_TYPE_SMDKC100;
+	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+	return 0;
+}
+
+int dram_init(void)
+{
+	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+	gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
+						PHYS_SDRAM_1_SIZE);
+
+	return 0;
+}
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+	printf("Board:\tSMDKC100\n");
+	return 0;
+}
+#endif
+
+Summary
+=======
+
+This README is about U-Boot support for SAMSUNG's ARM Cortex-A8 based S5PC1xx
+family of SoCs (S5PC100 [1] and S5PC110).
+
+Currently the following board is supported:
+
+* SMDKC100 [2]
+
+Toolchain
+=========
+
+While ARM Cortex-A8 support ARM v7 instruction set (-march=armv7a) we compile
+with -march=armv5 to allow more compilers to work. For U-Boot code this has
+no performance impact.
+
+Build
+=====
+
+* SMDKC100
+
+make smdkc100_config
+make
+
+
+Interfaces
+==========
+
+cpu
+
+To check SoC:
+
+	if (cpu_is_s5pc100())
+		printf("cpu is s5pc100\n");
+
+	or
+
+	if (cpu_is_s5pc110())
+		printf("cpu is s5pc110\n");
+
+gpio
+	not supported yet.
+
+Links
+=====
+
+[1] S5PC100:
+
+http://www.samsung.com/global/business/semiconductor/productInfo.do?
+fmly_id=229&partnum=S5PC100
+
+[2] SMDKC100:
+
+http://meritech.co.kr/eng/products/product_view.php?num=28
+/*
+ * (C) Copyright 2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * HeungJun Kim <riverful.kim@samsung.com>
+ * Inki Dae <inki.dae@samsung.com>
+ *
+ * Configuation settings for the SAMSUNG SMDKC100 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_ARMCORTEXA8	1	/* This is an ARM V7 CPU core */
+#define CONFIG_SAMSUNG		1	/* in a SAMSUNG core */
+#define CONFIG_S5PC1XX		1	/* which is in a S5PC1XX Family */
+#define CONFIG_S5PC100		1	/* which is in a S5PC100 */
+#define CONFIG_SMDKC100		1	/* working with SMDKC100 */
+
+#include <asm/arch/cpu.h>		/* get chip and board defs */
+
+#define CONFIG_ARCH_CPU_INIT
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#undef CONFIG_SKIP_RELOCATE_UBOOT
+
+#define CONFIG_L2_OFF
+
+/* input clock of PLL: SMDKC100 has 12MHz input clock */
+#define CONFIG_SYS_CLK_FREQ		12000000
+
+/* DRAM Base */
+#define CONFIG_SYS_SDRAM_BASE		0x30000000
+
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_INITRD_TAG
+#define CONFIG_CMDLINE_EDITING
+
+/*
+ * Size of malloc() pool
+ * 1MB = 0x100000, 0x100000 = 1024 * 1024
+ */
+#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (1 << 20))
+#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes for */
+						/* initial data */
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL0			1	/* use SERIAL 0 on SMDKC100 */
+#define CONFIG_SERIAL_MULTI		1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE			115200
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_NAND
+#undef CONFIG_CMD_NET
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_ONENAND
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_MTDPARTS
+
+#define CONFIG_BOOTDELAY	3
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+
+#define MTDIDS_DEFAULT		"onenand0=s3c-onenand"
+#define MTDPARTS_DEFAULT	"mtdparts=s3c-onenand:256k(bootloader)"\
+				",128k@0x40000(params)"\
+				",3m@0x60000(kernel)"\
+				",16m@0x360000(test)"\
+				",-(UBI)"
+
+#define NORMAL_MTDPARTS_DEFAULT MTDPARTS_DEFAULT
+
+#define CONFIG_BOOTCOMMAND	"run ubifsboot"
+
+#define CONFIG_RAMDISK_BOOT	"root=/dev/ram0 rw rootfstype=ext2" \
+				" console=ttySAC0,115200n8" \
+				" mem=128M"
+
+#define CONFIG_COMMON_BOOT	"console=ttySAC0,115200n8" \
+				" mem=128M " \
+				" " MTDPARTS_DEFAULT
+
+#define CONFIG_BOOTARGS	"root=/dev/mtdblock5 ubi.mtd=4" \
+			" rootfstype=cramfs " CONFIG_COMMON_BOOT
+
+#define CONFIG_UPDATEB	"updateb=onenand erase 0x0 0x40000;" \
+			" onenand write 0x32008000 0x0 0x40000\0"
+
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_EXTRA_ENV_SETTINGS					\
+	CONFIG_UPDATEB \
+	"updatek=" \
+		"onenand erase 0x60000 0x300000;" \
+		"onenand write 0x31008000 0x60000 0x300000\0" \
+	"updateu=" \
+		"onenand erase block 147-4095;" \
+		"onenand write 0x32000000 0x1260000 0x8C0000\0" \
+	"bootk=" \
+		"onenand read 0x30007FC0 0x60000 0x300000;" \
+		"bootm 0x30007FC0\0" \
+	"flashboot=" \
+		"set bootargs root=/dev/mtdblock${bootblock} " \
+		"rootfstype=${rootfstype} " \
+		"ubi.mtd=${ubiblock} ${opts} " CONFIG_COMMON_BOOT ";" \
+		"run bootk\0" \
+	"ubifsboot=" \
+		"set bootargs root=ubi0!rootfs rootfstype=ubifs " \
+		" ubi.mtd=${ubiblock} ${opts} " CONFIG_COMMON_BOOT "; " \
+		"run bootk\0" \
+	"boottrace=setenv opts initcall_debug; run bootcmd\0" \
+	"android=" \
+		"set bootargs root=ubi0!ramdisk ubi.mtd=${ubiblock} " \
+		"rootfstype=ubifs init=/init.sh " CONFIG_COMMON_BOOT "; " \
+		"run bootk\0" \
+	"nfsboot=" \
+		"set bootargs root=/dev/nfs ubi.mtd=${ubiblock} " \
+		"nfsroot=${nfsroot},nolock " \
+		"ip=${ipaddr}:${serverip}:${gatewayip}:" \
+		"${netmask}:nowplus:usb0:off " CONFIG_COMMON_BOOT "; " \
+		"run bootk\0" \
+	"ramboot=" \
+		"set bootargs " CONFIG_RAMDISK_BOOT \
+		" initrd=0x33000000,8M ramdisk=8192\0" \
+	"rootfstype=cramfs\0" \
+	"mtdparts=" MTDPARTS_DEFAULT "\0" \
+	"meminfo=mem=128M\0" \
+	"nfsroot=/nfsroot/arm\0" \
+	"bootblock=5\0" \
+	"ubiblock=4\0" \
+	"ubi=enabled"
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP		/* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser	*/
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_SYS_PROMPT		"SMDKC100 # "
+#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE	384	/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x5e00000)
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE
+
+#define CONFIG_SYS_HZ			1000
+
+/* valid baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE	(256 << 10)	/* 256 KiB */
+
+/* SMDKC100 has 1 banks of DRAM, we use only one in U-Boot */
+#define CONFIG_NR_DRAM_BANKS	1
+#define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE	/* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE	(128 << 20)	/* 0x8000000, 128 MB Bank #1 */
+
+#define CONFIG_SYS_MONITOR_BASE	0x00000000
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_NO_FLASH		1
+
+#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* 256 KiB */
+#define CONFIG_IDENT_STRING		" for SMDKC100"
+
+#define CONFIG_SYS_64BIT_VSPRINTF
+
+#if !defined(CONFIG_NAND_SPL) && (TEXT_BASE >= 0xc0000000)
+#define CONFIG_ENABLE_MMU
+#endif
+
+#ifdef CONFIG_ENABLE_MMU
+#define CONFIG_SYS_MAPPED_RAM_BASE	0xc0000000
+#else
+#define CONFIG_SYS_MAPPED_RAM_BASE	CONFIG_SYS_SDRAM_BASE
+#endif
+
+/*-----------------------------------------------------------------------
+ * Boot configuration
+ */
+#define CONFIG_ENV_IS_IN_ONENAND	1
+#define CONFIG_ENV_SIZE			(128 << 10)	/* 128KiB, 0x20000 */
+#define CONFIG_ENV_ADDR			(256 << 10)	/* 256KiB, 0x40000 */
+#define CONFIG_ENV_OFFSET		(256 << 10)	/* 256KiB, 0x40000 */
+
+#define CONFIG_USE_ONENAND_BOARD_INIT
+#define CONFIG_SAMSUNG_ONENAND		1
+#define CONFIG_SYS_ONENAND_BASE		0xE7100000
+
+#define CONFIG_DOS_PARTITION		1
+
+#endif	/* __CONFIG_H */
...	...	@@ -735,6 +735,10 @@
735	735	lart SA1100
736	736	dnp1110 SA1110
737	737
	738	+Minkyu Kang <mk7.kang@samsung.com>
	739	+
	740	+ SMDKC100 ARM CORTEX-A8 (S5PC100 SoC)
	741	+
738	742	-------------------------------------------------------------------------
739	743
740	744	Unknown / orphaned boards:
...	...	@@ -605,6 +605,7 @@
605	605	omap3_pandora \
606	606	omap3_zoom1 \
607	607	omap3_zoom2 \
	608	+ smdkc100 \
608	609	"
609	610
610	611	#########################################################################
...	...	@@ -3144,6 +3144,9 @@
3144	3144	omap3_zoom2_config : unconfig
3145	3145	@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 zoom2 logicpd omap3
3146	3146
	3147	+smdkc100_config: unconfig
	3148	+ @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 smdkc100 samsung s5pc1xx
	3149	+
3147	3150	#########################################################################
3148	3151	## XScale Systems
3149	3152	#########################################################################
	1	+#
	2	+# (C) Copyright 2000, 2001, 2002
	3	+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	+#
	5	+# (C) Copyright 2008
	6	+# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
	7	+#
	8	+# See file CREDITS for list of people who contributed to this
	9	+# project.
	10	+#
	11	+# This program is free software; you can redistribute it and/or
	12	+# modify it under the terms of the GNU General Public License as
	13	+# published by the Free Software Foundation; either version 2 of
	14	+# the License, or (at your option) any later version.
	15	+#
	16	+# This program is distributed in the hope that it will be useful,
	17	+# but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	+# GNU General Public License for more details.
	20	+#
	21	+# You should have received a copy of the GNU General Public License
	22	+# along with this program; if not, write to the Free Software
	23	+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	+# MA 02111-1307 USA
	25	+#
	26	+
	27	+include $(TOPDIR)/config.mk
	28	+
	29	+LIB = $(obj)lib$(BOARD).a
	30	+
	31	+COBJS-y := smdkc100.o
	32	+COBJS-$(CONFIG_SAMSUNG_ONENAND) += onenand.o
	33	+SOBJS := lowlevel_init.o
	34	+
	35	+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
	36	+OBJS := $(addprefix $(obj),$(COBJS-y))
	37	+SOBJS := $(addprefix $(obj),$(SOBJS))
	38	+
	39	+$(LIB): $(obj).depend $(SOBJS) $(OBJS)
	40	+ $(AR) $(ARFLAGS) $@ $(SOBJS) $(OBJS)
	41	+
	42	+clean:
	43	+ rm -f $(SOBJS) $(OBJS)
	44	+
	45	+distclean: clean
	46	+ rm -f $(LIB) core *.bak $(obj).depend
	47	+
	48	+#########################################################################
	49	+
	50	+# defines $(obj).depend target
	51	+include $(SRCTREE)/rules.mk
	52	+
	53	+sinclude $(obj).depend
	54	+
	55	+#########################################################################
	1	+#
	2	+# Copyright (C) 2008 # Samsung Elecgtronics
	3	+# Kyungmin Park <kyungmin.park@samsung.com>
	4	+#
	5	+
	6	+# On S5PC100 we use the 128 MiB OneDRAM bank at
	7	+#
	8	+# 0x30000000 to 0x35000000 (80MiB)
	9	+# 0x38000000 to 0x40000000 (128MiB)
	10	+#
	11	+# On S5PC110 we use the 128 MiB OneDRAM bank at
	12	+#
	13	+# 0x30000000 to 0x35000000 (80MiB)
	14	+# 0x40000000 to 0x48000000 (128MiB)
	15	+#
	16	+TEXT_BASE = 0x34800000
	1	+/*
	2	+ * Copyright (C) 2009 Samsung Electronics
	3	+ * Kyungmin Park <kyungmin.park@samsung.com>
	4	+ * Minkyu Kang <mk7.kang@samsung.com>
	5	+ *
	6	+ * See file CREDITS for list of people who contributed to this
	7	+ * project.
	8	+ *
	9	+ * This program is free software; you can redistribute it and/or
	10	+ * modify it under the terms of the GNU General Public License as
	11	+ * published by the Free Software Foundation; either version 2 of
	12	+ * the License, or (at your option) any later version.
	13	+ *
	14	+ * This program is distributed in the hope that it will be useful,
	15	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	+ * GNU General Public License for more details.
	18	+ *
	19	+ * You should have received a copy of the GNU General Public License
	20	+ * along with this program; if not, write to the Free Software
	21	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	+ * MA 02111-1307 USA
	23	+ */
	24	+
	25	+#include <config.h>
	26	+#include <version.h>
	27	+#include <asm/arch/cpu.h>
	28	+#include <asm/arch/power.h>
	29	+
	30	+/*
	31	+ * Register usages:
	32	+ *
	33	+ * r5 has zero always
	34	+ */
	35	+
	36	+_TEXT_BASE:
	37	+ .word TEXT_BASE
	38	+
	39	+ .globl lowlevel_init
	40	+lowlevel_init:
	41	+ mov r9, lr
	42	+
	43	+ /* r5 has always zero */
	44	+ mov r5, #0
	45	+
	46	+ ldr r8, =S5PC100_GPIO_BASE
	47	+
	48	+ /* Disable Watchdog */
	49	+ ldr r0, =S5PC100_WATCHDOG_BASE @0xEA200000
	50	+ orr r0, r0, #0x0
	51	+ str r5, [r0]
	52	+
	53	+#ifndef CONFIG_ONENAND_IPL
	54	+ /* setting SRAM */
	55	+ ldr r0, =S5PC100_SROMC_BASE
	56	+ ldr r1, =0x9
	57	+ str r1, [r0]
	58	+#endif
	59	+
	60	+ /* S5PC100 has 3 groups of interrupt sources */
	61	+ ldr r0, =S5PC100_VIC0_BASE @0xE4000000
	62	+ ldr r1, =S5PC100_VIC1_BASE @0xE4000000
	63	+ ldr r2, =S5PC100_VIC2_BASE @0xE4000000
	64	+
	65	+ /* Disable all interrupts (VIC0, VIC1 and VIC2) */
	66	+ mvn r3, #0x0
	67	+ str r3, [r0, #0x14] @INTENCLEAR
	68	+ str r3, [r1, #0x14] @INTENCLEAR
	69	+ str r3, [r2, #0x14] @INTENCLEAR
	70	+
	71	+#ifndef CONFIG_ONENAND_IPL
	72	+ /* Set all interrupts as IRQ */
	73	+ str r5, [r0, #0xc] @INTSELECT
	74	+ str r5, [r1, #0xc] @INTSELECT
	75	+ str r5, [r2, #0xc] @INTSELECT
	76	+
	77	+ /* Pending Interrupt Clear */
	78	+ str r5, [r0, #0xf00] @INTADDRESS
	79	+ str r5, [r1, #0xf00] @INTADDRESS
	80	+ str r5, [r2, #0xf00] @INTADDRESS
	81	+#endif
	82	+
	83	+#ifndef CONFIG_ONENAND_IPL
	84	+ /* for UART */
	85	+ bl uart_asm_init
	86	+
	87	+ /* for TZPC */
	88	+ bl tzpc_asm_init
	89	+#endif
	90	+
	91	+#ifdef CONFIG_ONENAND_IPL
	92	+ /* init system clock */
	93	+ bl system_clock_init
	94	+
	95	+ bl mem_ctrl_asm_init
	96	+
	97	+ /* Wakeup support. Don't know if it's going to be used, untested. */
	98	+ ldr r0, =S5PC100_RST_STAT
	99	+ ldr r1, [r0]
	100	+ bic r1, r1, #0xfffffff7
	101	+ cmp r1, #0x8
	102	+ beq wakeup_reset
	103	+#endif
	104	+
	105	+1:
	106	+ mov lr, r9
	107	+ mov pc, lr
	108	+
	109	+#ifdef CONFIG_ONENAND_IPL
	110	+wakeup_reset:
	111	+
	112	+ /* Clear wakeup status register */
	113	+ ldr r0, =S5PC100_WAKEUP_STAT
	114	+ ldr r1, [r0]
	115	+ str r1, [r0]
	116	+
	117	+ /* Load return address and jump to kernel */
	118	+ ldr r0, =S5PC100_INFORM0
	119	+
	120	+ /* r1 = physical address of s5pc100_cpu_resume function */
	121	+ ldr r1, [r0]
	122	+
	123	+ /* Jump to kernel (sleep.S) */
	124	+ mov pc, r1
	125	+ nop
	126	+ nop
	127	+#endif
	128	+
	129	+/*
	130	+ * system_clock_init: Initialize core clock and bus clock.
	131	+ * void system_clock_init(void)
	132	+ */
	133	+system_clock_init:
	134	+ ldr r8, =S5PC1XX_CLOCK_BASE @ 0xE0100000
	135	+
	136	+ /* Set Clock divider */
	137	+ ldr r1, =0x00011110
	138	+ str r1, [r8, #0x304]
	139	+ ldr r1, =0x1
	140	+ str r1, [r8, #0x308]
	141	+ ldr r1, =0x00011301
	142	+ str r1, [r8, #0x300]
	143	+
	144	+ /* Set Lock Time */
	145	+ ldr r1, =0xe10 @ Locktime : 0xe10 = 3600
	146	+ str r1, [r8, #0x000] @ APLL_LOCK
	147	+ str r1, [r8, #0x004] @ MPLL_LOCK
	148	+ str r1, [r8, #0x008] @ EPLL_LOCK
	149	+ str r1, [r8, #0x00C] @ HPLL_LOCK
	150	+
	151	+ /* APLL_CON */
	152	+ ldr r1, =0x81bc0400 @ SDIV 0, PDIV 4, MDIV 444 (1332MHz)
	153	+ str r1, [r8, #0x100]
	154	+ /* MPLL_CON */
	155	+ ldr r1, =0x80590201 @ SDIV 1, PDIV 2, MDIV 89 (267MHz)
	156	+ str r1, [r8, #0x104]
	157	+ /* EPLL_CON */
	158	+ ldr r1, =0x80870303 @ SDIV 3, PDIV 3, MDIV 135 (67.5MHz)
	159	+ str r1, [r8, #0x108]
	160	+ /* HPLL_CON */
	161	+ ldr r1, =0x80600603
	162	+ str r1, [r8, #0x10C]
	163	+
	164	+ /* Set Source Clock */
	165	+ ldr r1, =0x1111 @ A, M, E, HPLL Muxing
	166	+ str r1, [r8, #0x200] @ CLK_SRC0
	167	+
	168	+ ldr r1, =0x1000001 @ Uart Clock & CLK48M Muxing
	169	+ str r1, [r8, #0x204] @ CLK_SRC1
	170	+
	171	+ ldr r1, =0x9000 @ ARMCLK/4
	172	+ str r1, [r8, #0x400] @ CLK_OUT
	173	+
	174	+ /* wait at least 200us to stablize all clock */
	175	+ mov r2, #0x10000
	176	+1: subs r2, r2, #1
	177	+ bne 1b
	178	+
	179	+ mov pc, lr
	180	+
	181	+#ifndef CONFIG_ONENAND_IPL
	182	+/*
	183	+ * uart_asm_init: Initialize UART's pins
	184	+ */
	185	+uart_asm_init:
	186	+ mov r0, r8
	187	+ ldr r1, =0x22222222
	188	+ str r1, [r0, #0x0] @ GPA0_CON
	189	+ ldr r1, =0x00022222
	190	+ str r1, [r0, #0x20] @ GPA1_CON
	191	+
	192	+ mov pc, lr
	193	+
	194	+/*
	195	+ * tzpc_asm_init: Initialize TZPC
	196	+ */
	197	+tzpc_asm_init:
	198	+ ldr r0, =0xE3800000
	199	+ mov r1, #0x0
	200	+ str r1, [r0]
	201	+ mov r1, #0xff
	202	+ str r1, [r0, #0x804]
	203	+ str r1, [r0, #0x810]
	204	+
	205	+ ldr r0, =0xE2800000
	206	+ str r1, [r0, #0x804]
	207	+ str r1, [r0, #0x810]
	208	+ str r1, [r0, #0x81C]
	209	+
	210	+ ldr r0, =0xE2900000
	211	+ str r1, [r0, #0x804]
	212	+ str r1, [r0, #0x810]
	213	+
	214	+ mov pc, lr
	215	+#endif
	1	+/*
	2	+ * Originates from Samsung's u-boot 1.1.6 port to S5PC1xx
	3	+ *
	4	+ * Copyright (C) 2009 Samsung Electrnoics
	5	+ * Inki Dae <inki.dae@samsung.com>
	6	+ * Heungjun Kim <riverful.kim@samsung.com>
	7	+ * Minkyu Kang <mk7.kang@samsung.com>
	8	+ * Kyungmin Park <kyungmin.park@samsung.com>
	9	+ *
	10	+ * See file CREDITS for list of people who contributed to this
	11	+ * project.
	12	+ *
	13	+ * This program is free software; you can redistribute it and/or
	14	+ * modify it under the terms of the GNU General Public License as
	15	+ * published by the Free Software Foundation; either version 2 of
	16	+ * the License, or (at your option) any later version.
	17	+ *
	18	+ * This program is distributed in the hope that it will be useful,
	19	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	20	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	21	+ * GNU General Public License for more details.
	22	+ *
	23	+ * You should have received a copy of the GNU General Public License
	24	+ * along with this program; if not, write to the Free Software
	25	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	26	+ * MA 02111-1307 USA
	27	+ */
	28	+
	29	+#include <config.h>
	30	+
	31	+ .globl mem_ctrl_asm_init
	32	+mem_ctrl_asm_init:
	33	+ ldr r6, =S5PC100_DMC_BASE @ 0xE6000000
	34	+
	35	+ /* DLL parameter setting */
	36	+ ldr r1, =0x50101000
	37	+ str r1, [r6, #0x018] @ PHYCONTROL0
	38	+ ldr r1, =0xf4
	39	+ str r1, [r6, #0x01C] @ PHYCONTROL1
	40	+ ldr r1, =0x0
	41	+ str r1, [r6, #0x020] @ PHYCONTROL2
	42	+
	43	+ /* DLL on */
	44	+ ldr r1, =0x50101002
	45	+ str r1, [r6, #0x018] @ PHYCONTROL0
	46	+
	47	+ /* DLL start */
	48	+ ldr r1, =0x50101003
	49	+ str r1, [r6, #0x018] @ PHYCONTROL0
	50	+
	51	+ /* Force value locking for DLL off */
	52	+ str r1, [r6, #0x018] @ PHYCONTROL0
	53	+
	54	+ /* DLL off */
	55	+ ldr r1, =0x50101001
	56	+ str r1, [r6, #0x018] @ PHYCONTROL0
	57	+
	58	+ /* auto refresh off */
	59	+ ldr r1, =0xff001010
	60	+ str r1, [r6, #0x000] @ CONCONTROL
	61	+
	62	+ /*
	63	+ * Burst Length 4, 2 chips, 32-bit, LPDDR
	64	+ * OFF: dynamic self refresh, force precharge, dynamic power down off
	65	+ */
	66	+ ldr r1, =0x00212100
	67	+ str r1, [r6, #0x004] @ MEMCONTROL
	68	+
	69	+ /*
	70	+ * Note:
	71	+ * If Bank0 has OneDRAM we place it at 0x2800'0000
	72	+ * So finally Bank1 should address start at at 0x2000'0000
	73	+ */
	74	+ mov r4, #0x0
	75	+
	76	+swap_memory:
	77	+ /*
	78	+ * Bank0
	79	+ * 0x30 -> 0x30000000
	80	+ * 0xf8 -> 0x37FFFFFF
	81	+ * [15:12] 0: Linear
	82	+ * [11:8 ] 2: 9 bits
	83	+ * [ 7:4 ] 2: 14 bits
	84	+ * [ 3:0 ] 2: 4 banks
	85	+ */
	86	+ ldr r1, =0x30f80222
	87	+ /* if r4 is 1, swap the bank */
	88	+ cmp r4, #0x1
	89	+ orreq r1, r1, #0x08000000
	90	+ str r1, [r6, #0x008] @ MEMCONFIG0
	91	+
	92	+ /*
	93	+ * Bank1
	94	+ * 0x38 -> 0x38000000
	95	+ * 0xf8 -> 0x3fFFFFFF
	96	+ * [15:12] 0: Linear
	97	+ * [11:8 ] 2: 9 bits
	98	+ * [ 7:4 ] 2: 14 bits
	99	+ * [ 3:0 ] 2: 4 banks
	100	+ */
	101	+ ldr r1, =0x38f80222
	102	+ /* if r4 is 1, swap the bank */
	103	+ cmp r4, #0x1
	104	+ biceq r1, r1, #0x08000000
	105	+ str r1, [r6, #0x00c] @ MEMCONFIG1
	106	+
	107	+ ldr r1, =0x20000000
	108	+ str r1, [r6, #0x014] @ PRECHCONFIG
	109	+
	110	+ /*
	111	+ * FIXME: Please verify these values
	112	+ * 7.8us * 166MHz %LE %LONG1294(0x50E)
	113	+ * 7.8us * 133MHz %LE %LONG1038(0x40E),
	114	+ * 7.8us * 100MHz %LE %LONG780(0x30C),
	115	+ * 7.8us * 20MHz %LE %LONG156(0x9C),
	116	+ * 7.8us * 10MHz %LE %LONG78(0x4E)
	117	+ */
	118	+ ldr r1, =0x0000050e
	119	+ str r1, [r6, #0x030] @ TIMINGAREF
	120	+
	121	+ /* 166 MHz */
	122	+ ldr r1, =0x0c233287
	123	+ str r1, [r6, #0x034] @ TIMINGROW
	124	+
	125	+ /* twtr=3 twr=2 trtp=3 cl=3 wl=3 rl=3 */
	126	+ ldr r1, =0x32330303
	127	+ str r1, [r6, #0x038] @ TIMINGDATA
	128	+
	129	+ /* tfaw=4 sxsr=0x14 txp=0x14 tcke=3 tmrd=3 */
	130	+ ldr r1, =0x04141433
	131	+ str r1, [r6, #0x03C] @ TIMINGPOWER
	132	+
	133	+ /* chip0 Deselect */
	134	+ ldr r1, =0x07000000
	135	+ str r1, [r6, #0x010] @ DIRECTCMD
	136	+
	137	+ /* chip0 PALL */
	138	+ ldr r1, =0x01000000
	139	+ str r1, [r6, #0x010] @ DIRECTCMD
	140	+
	141	+ /* chip0 REFA */
	142	+ ldr r1, =0x05000000
	143	+ str r1, [r6, #0x010] @ DIRECTCMD
	144	+ /* chip0 REFA */
	145	+ str r1, [r6, #0x010] @ DIRECTCMD
	146	+
	147	+ /* chip0 MRS, CL%LE %LONG3, BL%LE %LONG4 */
	148	+ ldr r1, =0x00000032
	149	+ str r1, [r6, #0x010] @ DIRECTCMD
	150	+
	151	+ /* chip1 Deselect */
	152	+ ldr r1, =0x07100000
	153	+ str r1, [r6, #0x010] @ DIRECTCMD
	154	+
	155	+ /* chip1 PALL */
	156	+ ldr r1, =0x01100000
	157	+ str r1, [r6, #0x010] @ DIRECTCMD
	158	+
	159	+ /* chip1 REFA */
	160	+ ldr r1, =0x05100000
	161	+ str r1, [r6, #0x010] @ DIRECTCMD
	162	+ /* chip1 REFA */
	163	+ str r1, [r6, #0x010] @ DIRECTCMD
	164	+
	165	+ /* chip1 MRS, CL%LE %LONG3, BL%LE %LONG4 */
	166	+ ldr r1, =0x00100032
	167	+ str r1, [r6, #0x010] @ DIRECTCMD
	168	+
	169	+ /* auto refresh on */
	170	+ ldr r1, =0xff002030
	171	+ str r1, [r6, #0x000] @ CONCONTROL
	172	+
	173	+ /* PwrdnConfig */
	174	+ ldr r1, =0x00100002
	175	+ str r1, [r6, #0x028] @ PWRDNCONFIG
	176	+
	177	+ /* BL%LE %LONG */
	178	+ ldr r1, =0xff212100
	179	+ str r1, [r6, #0x004] @ MEMCONTROL
	180	+
	181	+
	182	+ /* Try to test memory area */
	183	+ cmp r4, #0x1
	184	+ beq 1f
	185	+
	186	+ mov r4, #0x1
	187	+ ldr r1, =0x37ffff00
	188	+ str r4, [r1]
	189	+ str r4, [r1, #0x4] @ dummy write
	190	+ ldr r0, [r1]
	191	+ cmp r0, r4
	192	+ bne swap_memory
	193	+
	194	+1:
	195	+ mov pc, lr
	196	+
	197	+ .ltorg
	1	+/*
	2	+ * Copyright (C) 2008-2009 Samsung Electronics
	3	+ * Kyungmin Park <kyungmin.park@samsung.com>
	4	+ *
	5	+ * See file CREDITS for list of people who contributed to this
	6	+ * project.
	7	+ *
	8	+ * This program is free software; you can redistribute it and/or
	9	+ * modify it under the terms of the GNU General Public License as
	10	+ * published by the Free Software Foundation; either version 2 of
	11	+ * the License, or (at your option) any later version.
	12	+ *
	13	+ * This program is distributed in the hope that it will be useful,
	14	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	+ * GNU General Public License for more details.
	17	+ *
	18	+ * You should have received a copy of the GNU General Public License
	19	+ * along with this program; if not, write to the Free Software
	20	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	+ * MA 02111-1307 USA
	22	+ */
	23	+
	24	+#include <common.h>
	25	+#include <linux/mtd/compat.h>
	26	+#include <linux/mtd/mtd.h>
	27	+#include <linux/mtd/onenand.h>
	28	+#include <linux/mtd/samsung_onenand.h>
	29	+
	30	+#include <onenand_uboot.h>
	31	+
	32	+#include <asm/io.h>
	33	+#include <asm/arch/clock.h>
	34	+
	35	+void onenand_board_init(struct mtd_info *mtd)
	36	+{
	37	+ struct onenand_chip *this = mtd->priv;
	38	+ struct s5pc100_clock clk = (struct s5pc100_clock )S5PC1XX_CLOCK_BASE;
	39	+ struct samsung_onenand *onenand;
	40	+ int value;
	41	+
	42	+ this->base = (void *)S5PC100_ONENAND_BASE;
	43	+ onenand = (struct samsung_onenand *)this->base;
	44	+
	45	+ /* D0 Domain memory clock gating */
	46	+ value = readl(&clk->gate_d01);
	47	+ value &= ~(1 << 2); /* CLK_ONENANDC */
	48	+ value \|= (1 << 2);
	49	+ writel(value, &clk->gate_d01);
	50	+
	51	+ value = readl(&clk->src0);
	52	+ value &= ~(1 << 24); /* MUX_1nand: 0 from HCLKD0 */
	53	+ value &= ~(1 << 20); /* MUX_HREF: 0 from FIN_27M */
	54	+ writel(value, &clk->src0);
	55	+
	56	+ value = readl(&clk->div1);
	57	+ value &= ~(3 << 16); /* PCLKD1_RATIO */
	58	+ value \|= (1 << 16);
	59	+ writel(value, &clk->div1);
	60	+
	61	+ writel(ONENAND_MEM_RESET_COLD, &onenand->mem_reset);
	62	+
	63	+ while (!(readl(&onenand->int_err_stat) & RST_CMP))
	64	+ continue;
	65	+
	66	+ writel(RST_CMP, &onenand->int_err_ack);
	67	+
	68	+ /*
	69	+ * Access_Clock [2:0]
	70	+ * 166 MHz, 134 Mhz : 3
	71	+ * 100 Mhz, 60 Mhz : 2
	72	+ */
	73	+ writel(0x3, &onenand->acc_clock);
	74	+
	75	+ writel(INT_ERR_ALL, &onenand->int_err_mask);
	76	+ writel(1 << 0, &onenand->int_pin_en); /* Enable */
	77	+
	78	+ value = readl(&onenand->int_err_mask);
	79	+ value &= ~RDY_ACT;
	80	+ writel(value, &onenand->int_err_mask);
	81	+
	82	+ s3c_onenand_init(mtd);
	83	+}
	1	+
	2	+Summary
	3	+=======
	4	+
	5	+This README is about U-Boot support for SAMSUNG's ARM Cortex-A8 based S5PC1xx
	6	+family of SoCs (S5PC100 [1] and S5PC110).
	7	+
	8	+Currently the following board is supported:
	9	+
	10	+* SMDKC100 [2]
	11	+
	12	+Toolchain
	13	+=========
	14	+
	15	+While ARM Cortex-A8 support ARM v7 instruction set (-march=armv7a) we compile
	16	+with -march=armv5 to allow more compilers to work. For U-Boot code this has
	17	+no performance impact.
	18	+
	19	+Build
	20	+=====
	21	+
	22	+* SMDKC100
	23	+
	24	+make smdkc100_config
	25	+make
	26	+
	27	+
	28	+Interfaces
	29	+==========
	30	+
	31	+cpu
	32	+
	33	+To check SoC:
	34	+
	35	+ if (cpu_is_s5pc100())
	36	+ printf("cpu is s5pc100\n");
	37	+
	38	+ or
	39	+
	40	+ if (cpu_is_s5pc110())
	41	+ printf("cpu is s5pc110\n");
	42	+
	43	+gpio
	44	+ not supported yet.
	45	+
	46	+Links
	47	+=====
	48	+
	49	+[1] S5PC100:
	50	+
	51	+http://www.samsung.com/global/business/semiconductor/productInfo.do?
	52	+fmly_id=229&partnum=S5PC100
	53	+
	54	+[2] SMDKC100:
	55	+
	56	+http://meritech.co.kr/eng/products/product_view.php?num=28
	1	+/*
	2	+ * (C) Copyright 2009 Samsung Electronics
	3	+ * Minkyu Kang <mk7.kang@samsung.com>
	4	+ * HeungJun Kim <riverful.kim@samsung.com>
	5	+ * Inki Dae <inki.dae@samsung.com>
	6	+ *
	7	+ * Configuation settings for the SAMSUNG SMDKC100 board.
	8	+ *
	9	+ * See file CREDITS for list of people who contributed to this
	10	+ * project.
	11	+ *
	12	+ * This program is free software; you can redistribute it and/or
	13	+ * modify it under the terms of the GNU General Public License as
	14	+ * published by the Free Software Foundation; either version 2 of
	15	+ * the License, or (at your option) any later version.
	16	+ *
	17	+ * This program is distributed in the hope that it will be useful,
	18	+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
	19	+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	20	+ * GNU General Public License for more details.
	21	+ *
	22	+ * You should have received a copy of the GNU General Public License
	23	+ * along with this program; if not, write to the Free Software
	24	+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	25	+ * MA 02111-1307 USA
	26	+ */
	27	+
	28	+#ifndef __CONFIG_H
	29	+#define __CONFIG_H
	30	+
	31	+/*
	32	+ * High Level Configuration Options
	33	+ * (easy to change)
	34	+ */
	35	+#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
	36	+#define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */
	37	+#define CONFIG_S5PC1XX 1 /* which is in a S5PC1XX Family */
	38	+#define CONFIG_S5PC100 1 /* which is in a S5PC100 */
	39	+#define CONFIG_SMDKC100 1 /* working with SMDKC100 */
	40	+
	41	+#include <asm/arch/cpu.h> /* get chip and board defs */
	42	+
	43	+#define CONFIG_ARCH_CPU_INIT
	44	+
	45	+#define CONFIG_DISPLAY_CPUINFO
	46	+#define CONFIG_DISPLAY_BOARDINFO
	47	+
	48	+#undef CONFIG_SKIP_RELOCATE_UBOOT
	49	+
	50	+#define CONFIG_L2_OFF
	51	+
	52	+/* input clock of PLL: SMDKC100 has 12MHz input clock */
	53	+#define CONFIG_SYS_CLK_FREQ 12000000
	54	+
	55	+/* DRAM Base */
	56	+#define CONFIG_SYS_SDRAM_BASE 0x30000000
	57	+
	58	+#define CONFIG_SETUP_MEMORY_TAGS
	59	+#define CONFIG_CMDLINE_TAG
	60	+#define CONFIG_INITRD_TAG
	61	+#define CONFIG_CMDLINE_EDITING
	62	+
	63	+/*
	64	+ * Size of malloc() pool
	65	+ * 1MB = 0x100000, 0x100000 = 1024 * 1024
	66	+ */
	67	+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
	68	+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes for */
	69	+ /* initial data */
	70	+/*
	71	+ * select serial console configuration
	72	+ */
	73	+#define CONFIG_SERIAL0 1 /* use SERIAL 0 on SMDKC100 */
	74	+#define CONFIG_SERIAL_MULTI 1
	75	+
	76	+/* allow to overwrite serial and ethaddr */
	77	+#define CONFIG_ENV_OVERWRITE
	78	+#define CONFIG_BAUDRATE 115200
	79	+
	80	+/***********************************************************
	81	+ * Command definition
	82	+ ***********************************************************/
	83	+#include <config_cmd_default.h>
	84	+
	85	+#undef CONFIG_CMD_FLASH
	86	+#undef CONFIG_CMD_IMLS
	87	+#undef CONFIG_CMD_NAND
	88	+#undef CONFIG_CMD_NET
	89	+
	90	+#define CONFIG_CMD_CACHE
	91	+#define CONFIG_CMD_REGINFO
	92	+#define CONFIG_CMD_ONENAND
	93	+#define CONFIG_CMD_ELF
	94	+#define CONFIG_CMD_FAT
	95	+#define CONFIG_CMD_MTDPARTS
	96	+
	97	+#define CONFIG_BOOTDELAY 3
	98	+
	99	+#define CONFIG_ZERO_BOOTDELAY_CHECK
	100	+
	101	+#define CONFIG_MTD_DEVICE
	102	+#define CONFIG_MTD_PARTITIONS
	103	+
	104	+#define MTDIDS_DEFAULT "onenand0=s3c-onenand"
	105	+#define MTDPARTS_DEFAULT "mtdparts=s3c-onenand:256k(bootloader)"\
	106	+ ",128k@0x40000(params)"\
	107	+ ",3m@0x60000(kernel)"\
	108	+ ",16m@0x360000(test)"\
	109	+ ",-(UBI)"
	110	+
	111	+#define NORMAL_MTDPARTS_DEFAULT MTDPARTS_DEFAULT
	112	+
	113	+#define CONFIG_BOOTCOMMAND "run ubifsboot"
	114	+
	115	+#define CONFIG_RAMDISK_BOOT "root=/dev/ram0 rw rootfstype=ext2" \
	116	+ " console=ttySAC0,115200n8" \
	117	+ " mem=128M"
	118	+
	119	+#define CONFIG_COMMON_BOOT "console=ttySAC0,115200n8" \
	120	+ " mem=128M " \
	121	+ " " MTDPARTS_DEFAULT
	122	+
	123	+#define CONFIG_BOOTARGS "root=/dev/mtdblock5 ubi.mtd=4" \
	124	+ " rootfstype=cramfs " CONFIG_COMMON_BOOT
	125	+
	126	+#define CONFIG_UPDATEB "updateb=onenand erase 0x0 0x40000;" \
	127	+ " onenand write 0x32008000 0x0 0x40000\0"
	128	+
	129	+#define CONFIG_ENV_OVERWRITE
	130	+#define CONFIG_EXTRA_ENV_SETTINGS \
	131	+ CONFIG_UPDATEB \
	132	+ "updatek=" \
	133	+ "onenand erase 0x60000 0x300000;" \
	134	+ "onenand write 0x31008000 0x60000 0x300000\0" \
	135	+ "updateu=" \
	136	+ "onenand erase block 147-4095;" \
	137	+ "onenand write 0x32000000 0x1260000 0x8C0000\0" \
	138	+ "bootk=" \
	139	+ "onenand read 0x30007FC0 0x60000 0x300000;" \
	140	+ "bootm 0x30007FC0\0" \
	141	+ "flashboot=" \
	142	+ "set bootargs root=/dev/mtdblock${bootblock} " \
	143	+ "rootfstype=${rootfstype} " \
	144	+ "ubi.mtd=${ubiblock} ${opts} " CONFIG_COMMON_BOOT ";" \
	145	+ "run bootk\0" \
	146	+ "ubifsboot=" \
	147	+ "set bootargs root=ubi0!rootfs rootfstype=ubifs " \
	148	+ " ubi.mtd=${ubiblock} ${opts} " CONFIG_COMMON_BOOT "; " \
	149	+ "run bootk\0" \
	150	+ "boottrace=setenv opts initcall_debug; run bootcmd\0" \
	151	+ "android=" \
	152	+ "set bootargs root=ubi0!ramdisk ubi.mtd=${ubiblock} " \
	153	+ "rootfstype=ubifs init=/init.sh " CONFIG_COMMON_BOOT "; " \
	154	+ "run bootk\0" \
	155	+ "nfsboot=" \
	156	+ "set bootargs root=/dev/nfs ubi.mtd=${ubiblock} " \
	157	+ "nfsroot=${nfsroot},nolock " \
	158	+ "ip=${ipaddr}:${serverip}:${gatewayip}:" \
	159	+ "${netmask}:nowplus:usb0:off " CONFIG_COMMON_BOOT "; " \
	160	+ "run bootk\0" \
	161	+ "ramboot=" \
	162	+ "set bootargs " CONFIG_RAMDISK_BOOT \
	163	+ " initrd=0x33000000,8M ramdisk=8192\0" \
	164	+ "rootfstype=cramfs\0" \
	165	+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
	166	+ "meminfo=mem=128M\0" \
	167	+ "nfsroot=/nfsroot/arm\0" \
	168	+ "bootblock=5\0" \
	169	+ "ubiblock=4\0" \
	170	+ "ubi=enabled"
	171	+
	172	+/*
	173	+ * Miscellaneous configurable options
	174	+ */
	175	+#define CONFIG_SYS_LONGHELP /* undef to save memory */
	176	+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
	177	+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
	178	+#define CONFIG_SYS_PROMPT "SMDKC100 # "
	179	+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	180	+#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
	181	+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	182	+/* Boot Argument Buffer Size */
	183	+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	184	+/* memtest works on */
	185	+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
	186	+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5e00000)
	187	+#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
	188	+
	189	+#define CONFIG_SYS_HZ 1000
	190	+
	191	+/* valid baudrates */
	192	+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	193	+
	194	+/*-----------------------------------------------------------------------
	195	+ * Stack sizes
	196	+ *
	197	+ * The stack sizes are set up in start.S using the settings below
	198	+ */
	199	+#define CONFIG_STACKSIZE (256 << 10) /* 256 KiB */
	200	+
	201	+/* SMDKC100 has 1 banks of DRAM, we use only one in U-Boot */
	202	+#define CONFIG_NR_DRAM_BANKS 1
	203	+#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* SDRAM Bank #1 */
	204	+#define PHYS_SDRAM_1_SIZE (128 << 20) /* 0x8000000, 128 MB Bank #1 */
	205	+
	206	+#define CONFIG_SYS_MONITOR_BASE 0x00000000
	207	+
	208	+/*-----------------------------------------------------------------------
	209	+ * FLASH and environment organization
	210	+ */
	211	+#define CONFIG_SYS_NO_FLASH 1
	212	+
	213	+#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 KiB */
	214	+#define CONFIG_IDENT_STRING " for SMDKC100"
	215	+
	216	+#define CONFIG_SYS_64BIT_VSPRINTF
	217	+
	218	+#if !defined(CONFIG_NAND_SPL) && (TEXT_BASE >= 0xc0000000)
	219	+#define CONFIG_ENABLE_MMU
	220	+#endif
	221	+
	222	+#ifdef CONFIG_ENABLE_MMU
	223	+#define CONFIG_SYS_MAPPED_RAM_BASE 0xc0000000
	224	+#else
	225	+#define CONFIG_SYS_MAPPED_RAM_BASE CONFIG_SYS_SDRAM_BASE
	226	+#endif
	227	+
	228	+/*-----------------------------------------------------------------------
	229	+ * Boot configuration
	230	+ */
	231	+#define CONFIG_ENV_IS_IN_ONENAND 1
	232	+#define CONFIG_ENV_SIZE (128 << 10) /* 128KiB, 0x20000 */
	233	+#define CONFIG_ENV_ADDR (256 << 10) /* 256KiB, 0x40000 */
	234	+#define CONFIG_ENV_OFFSET (256 << 10) /* 256KiB, 0x40000 */
	235	+
	236	+#define CONFIG_USE_ONENAND_BOARD_INIT
	237	+#define CONFIG_SAMSUNG_ONENAND 1
	238	+#define CONFIG_SYS_ONENAND_BASE 0xE7100000
	239	+
	240	+#define CONFIG_DOS_PARTITION 1
	241	+
	242	+#endif /* __CONFIG_H */