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Commit 8bde63eb3f79d68f693201528dafc8ae7aa087de

Authored by Shinya Kuribayashi
Committed by Shinya Kuribayashi
1 parent 7daf2ebe91
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

[MIPS] Rename Alchemy processor configs into CONFIG_SOC_* 

CONFIG_SOC_AU1X00

  Common Alchemy Au1x00 stuff. All Alchemy processor based machines
  need to have this config as a system type specifier.

CONFIG_SOC_AU1000, CONFIG_SOC_AU1100, CONFIG_SOC_AU1200,
CONFIG_SOC_AU1500, CONFIG_SOC_AU1550

  Machine type specifiers. Each port should have one of aboves.

Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>

Showing 8 changed files with 26 additions and 26 deletions Side-by-side Diff

cpu/mips/au1x00_eth.c
Diff comments   View file @ 8bde63e
... ... @@ -23,7 +23,7 @@
23 23 */
24 24 #include <config.h>
25 25  
26   -#ifdef CONFIG_AU1X00
  26 +#ifdef CONFIG_SOC_AU1X00
27 27  
28 28 #if defined(CFG_DISCOVER_PHY)
29 29 #error "PHY not supported yet"
30 30  
31 31  
32 32  
... ... @@ -33,20 +33,20 @@
33 33  
34 34 /* I assume ethernet behaves like au1000 */
35 35  
36   -#ifdef CONFIG_AU1000
  36 +#ifdef CONFIG_SOC_AU1000
37 37 /* Base address differ between cpu:s */
38 38 #define ETH0_BASE AU1000_ETH0_BASE
39 39 #define MAC0_ENABLE AU1000_MAC0_ENABLE
40 40 #else
41   -#ifdef CONFIG_AU1100
  41 +#ifdef CONFIG_SOC_AU1100
42 42 #define ETH0_BASE AU1100_ETH0_BASE
43 43 #define MAC0_ENABLE AU1100_MAC0_ENABLE
44 44 #else
45   -#ifdef CONFIG_AU1500
  45 +#ifdef CONFIG_SOC_AU1500
46 46 #define ETH0_BASE AU1500_ETH0_BASE
47 47 #define MAC0_ENABLE AU1500_MAC0_ENABLE
48 48 #else
49   -#ifdef CONFIG_AU1550
  49 +#ifdef CONFIG_SOC_AU1550
50 50 #define ETH0_BASE AU1550_ETH0_BASE
51 51 #define MAC0_ENABLE AU1550_MAC0_ENABLE
52 52 #else
... ... @@ -308,5 +308,5 @@
308 308 return 1;
309 309 }
310 310  
311   -#endif /* CONFIG_AU1X00 */
  311 +#endif /* CONFIG_SOC_AU1X00 */
cpu/mips/au1x00_serial.c
Diff comments   View file @ 8bde63e
... ... @@ -27,7 +27,7 @@
27 27  
28 28 #include <config.h>
29 29  
30   -#ifdef CONFIG_AU1X00
  30 +#ifdef CONFIG_SOC_AU1X00
31 31  
32 32 #include <common.h>
33 33 #include <asm/au1x00.h>
... ... @@ -132,5 +132,5 @@
132 132 }
133 133 return 0;
134 134 }
135   -#endif /* CONFIG_SERIAL_AU1X00 */
  135 +#endif /* CONFIG_SOC_AU1X00 */
cpu/mips/au1x00_usb_ohci.c
Diff comments   View file @ 8bde63e
... ... @@ -35,7 +35,7 @@
35 35  
36 36 #include <config.h>
37 37  
38   -#if defined(CONFIG_AU1X00) && defined(CONFIG_USB_OHCI)
  38 +#if defined(CONFIG_SOC_AU1X00) && defined(CONFIG_USB_OHCI)
39 39  
40 40 /* #include <pci.h> no PCI on the AU1x00 */
41 41  
include/asm-mips/addrspace.h
Diff comments   View file @ 8bde63e
... ... @@ -131,13 +131,13 @@
131 131 * Returns the uncached address of a sdram address
132 132 */
133 133 #ifndef __ASSEMBLY__
134   -#if defined(CONFIG_AU1X00) || defined(CONFIG_TB0229)
  134 +#if defined(CONFIG_SOC_AU1X00) || defined(CONFIG_TB0229)
135 135 /* We use a 36 bit physical address map here and
136 136 cannot access physical memory directly from core */
137 137 #define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000)
138   -#else /* !CONFIG_AU1X00 */
  138 +#else /* !CONFIG_SOC_AU1X00 */
139 139 #define UNCACHED_SDRAM(a) KSEG1ADDR(a)
140   -#endif /* CONFIG_AU1X00 */
  140 +#endif /* CONFIG_SOC_AU1X00 */
141 141 #endif /* __ASSEMBLY__ */
142 142  
143 143 /*
include/asm-mips/au1x00.h
Diff comments   View file @ 8bde63e
... ... @@ -137,7 +137,7 @@
137 137 #define CP0_DEBUG $23
138 138  
139 139 /* SDRAM Controller */
140   -#ifdef CONFIG_AU1550
  140 +#ifdef CONFIG_SOC_AU1550
141 141  
142 142 #define MEM_SDMODE0 0xB4000800
143 143 #define MEM_SDMODE1 0xB4000808
... ... @@ -156,7 +156,7 @@
156 156 #define MEM_SDWRMD1 0xB4000888
157 157 #define MEM_SDWRMD2 0xB4000890
158 158  
159   -#else /* CONFIG_AU1550 */
  159 +#else /* CONFIG_SOC_AU1550 */
160 160  
161 161 #define MEM_SDMODE0 0xB4000000
162 162 #define MEM_SDMODE1 0xB4000004
... ... @@ -174,7 +174,7 @@
174 174 #define MEM_SDWRMD1 0xB4000028
175 175 #define MEM_SDWRMD2 0xB400002C
176 176  
177   -#endif /* CONFIG_AU1550 */
  177 +#endif /* CONFIG_SOC_AU1550 */
178 178  
179 179 #define MEM_SDSLEEP 0xB4000030
180 180 #define MEM_SDSMCKE 0xB4000034
include/configs/dbau1x00.h
Diff comments   View file @ 8bde63e
... ... @@ -30,21 +30,21 @@
30 30  
31 31 #define CONFIG_MIPS32 1 /* MIPS32 CPU core */
32 32 #define CONFIG_DBAU1X00 1
33   -#define CONFIG_AU1X00 1 /* alchemy series cpu */
  33 +#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
34 34  
35 35 #ifdef CONFIG_DBAU1000
36 36 /* Also known as Merlot */
37   -#define CONFIG_AU1000 1
  37 +#define CONFIG_SOC_AU1000 1
38 38 #else
39 39 #ifdef CONFIG_DBAU1100
40   -#define CONFIG_AU1100 1
  40 +#define CONFIG_SOC_AU1100 1
41 41 #else
42 42 #ifdef CONFIG_DBAU1500
43   -#define CONFIG_AU1500 1
  43 +#define CONFIG_SOC_AU1500 1
44 44 #else
45 45 #ifdef CONFIG_DBAU1550
46 46 /* Cabernet */
47   -#define CONFIG_AU1550 1
  47 +#define CONFIG_SOC_AU1550 1
48 48 #else
49 49 #error "No valid board set"
50 50 #endif
include/configs/gth2.h
Diff comments   View file @ 8bde63e
... ... @@ -30,9 +30,9 @@
30 30  
31 31 #define CONFIG_MIPS32 1 /* MIPS32 CPU core */
32 32 #define CONFIG_GTH2 1
33   -#define CONFIG_AU1X00 1 /* alchemy series cpu */
  33 +#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
34 34  
35   -#define CONFIG_AU1000 1
  35 +#define CONFIG_SOC_AU1000 1
36 36  
37 37 #define CONFIG_MISC_INIT_R 1
38 38  
include/configs/pb1x00.h
Diff comments   View file @ 8bde63e
... ... @@ -30,16 +30,16 @@
30 30  
31 31 #define CONFIG_MIPS32 1 /* MIPS32 CPU core */
32 32 #define CONFIG_PB1X00 1
33   -#define CONFIG_AU1X00 1 /* alchemy series cpu */
  33 +#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
34 34  
35 35 #ifdef CONFIG_PB1000
36   -#define CONFIG_AU1000 1
  36 +#define CONFIG_SOC_AU1000 1
37 37 #else
38 38 #ifdef CONFIG_PB1100
39   -#define CONFIG_AU1100 1
  39 +#define CONFIG_SOC_AU1100 1
40 40 #else
41 41 #ifdef CONFIG_PB1500
42   -#define CONFIG_AU1500 1
  42 +#define CONFIG_SOC_AU1500 1
43 43 #else
44 44 #error "No valid board set"
45 45 #endif