mx6sabresd: Add SPI NOR support

mx6sabre board has a m25p32 SPI NOR connected to ECSPI1 port. Add support for it. This patch allows the SPI NOR flash to be succesfully detected: => sf probe SF: Detected M25P32 with page size 256 Bytes, erase size 64 KiB, total 4 MiB Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

mx6sabresd: Add SPI NOR support
mx6sabre board has a m25p32 SPI NOR connected to ECSPI1 port. Add support for it. This patch allows the SPI NOR flash to be succesfully detected: => sf probe SF: Detected M25P32 with page size 256 Bytes, erase size 64 KiB, total 4 MiB Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Fabio Estevam · Stefano Babic
1 parent b48e3b0410
Showing 2 changed files with 31 additions and 0 deletions Side-by-side Diff
board/freescale/mx6sabresd/mx6sabresd.c
include/configs/mx6sabre_common.h
@@ -37,6 +37,9 @@
 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  
+#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
+		      PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+
 int dram_init(void)
 {
 	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
@@ -120,6 +123,18 @@
 	MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 };
  
+iomux_v3_cfg_t const ecspi1_pads[] = {
+	MX6_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_spi(void)
+{
+	imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
+}
+
 static void setup_iomux_uart(void)
 {
 	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
@@ -454,6 +469,10 @@
 {
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+#ifdef CONFIG_MXC_SPI
+	setup_spi();
+#endif
  
 	return 0;
 }
@@ -18,6 +18,7 @@
 #define CONFIG_DISPLAY_BOARDINFO
  
 #include <asm/arch/imx-regs.h>
+#include <asm/imx-common/gpio.h>
  
 #define CONFIG_CMDLINE_TAG
 #define CONFIG_SETUP_MEMORY_TAGS
@@ -59,6 +60,17 @@
  
 #define CONFIG_PHYLIB
 #define CONFIG_PHY_ATHEROS
+
+#define CONFIG_CMD_SF
+#ifdef CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_STMICRO
+#define CONFIG_MXC_SPI
+#define CONFIG_SF_DEFAULT_BUS		0
+#define CONFIG_SF_DEFAULT_CS		(0 | (IMX_GPIO_NR(4, 9) << 8))
+#define CONFIG_SF_DEFAULT_SPEED		20000000
+#define CONFIG_SF_DEFAULT_MODE		SPI_MODE_0
+#endif
  
 /* allow to overwrite serial and ethaddr */
 #define CONFIG_ENV_OVERWRITE
...	...	@@ -37,6 +37,9 @@
37	37	#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP \| \
38	38	PAD_CTL_SPEED_MED \| PAD_CTL_DSE_40ohm \| PAD_CTL_HYS)
39	39
	40	+#define SPI_PAD_CTRL (PAD_CTL_HYS \| PAD_CTL_SPEED_MED \| \
	41	+ PAD_CTL_DSE_40ohm \| PAD_CTL_SRE_FAST)
	42	+
40	43	int dram_init(void)
41	44	{
42	45	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
...	...	@@ -120,6 +123,18 @@
120	123	MX6_PAD_SD4_DAT7__SD4_DATA7 \| MUX_PAD_CTRL(USDHC_PAD_CTRL),
121	124	};
122	125
	126	+iomux_v3_cfg_t const ecspi1_pads[] = {
	127	+ MX6_PAD_KEY_COL0__ECSPI1_SCLK \| MUX_PAD_CTRL(SPI_PAD_CTRL),
	128	+ MX6_PAD_KEY_COL1__ECSPI1_MISO \| MUX_PAD_CTRL(SPI_PAD_CTRL),
	129	+ MX6_PAD_KEY_ROW0__ECSPI1_MOSI \| MUX_PAD_CTRL(SPI_PAD_CTRL),
	130	+ MX6_PAD_KEY_ROW1__GPIO4_IO09 \| MUX_PAD_CTRL(NO_PAD_CTRL),
	131	+};
	132	+
	133	+static void setup_spi(void)
	134	+{
	135	+ imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
	136	+}
	137	+
123	138	static void setup_iomux_uart(void)
124	139	{
125	140	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
...	...	@@ -454,6 +469,10 @@
454	469	{
455	470	/* address of boot parameters */
456	471	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
	472	+
	473	+#ifdef CONFIG_MXC_SPI
	474	+ setup_spi();
	475	+#endif
457	476
458	477	return 0;
459	478	}
...	...	@@ -18,6 +18,7 @@
18	18	#define CONFIG_DISPLAY_BOARDINFO
19	19
20	20	#include <asm/arch/imx-regs.h>
	21	+#include <asm/imx-common/gpio.h>
21	22
22	23	#define CONFIG_CMDLINE_TAG
23	24	#define CONFIG_SETUP_MEMORY_TAGS
...	...	@@ -59,6 +60,17 @@
59	60
60	61	#define CONFIG_PHYLIB
61	62	#define CONFIG_PHY_ATHEROS
	63	+
	64	+#define CONFIG_CMD_SF
	65	+#ifdef CONFIG_CMD_SF
	66	+#define CONFIG_SPI_FLASH
	67	+#define CONFIG_SPI_FLASH_STMICRO
	68	+#define CONFIG_MXC_SPI
	69	+#define CONFIG_SF_DEFAULT_BUS 0
	70	+#define CONFIG_SF_DEFAULT_CS (0 \| (IMX_GPIO_NR(4, 9) << 8))
	71	+#define CONFIG_SF_DEFAULT_SPEED 20000000
	72	+#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
	73	+#endif
62	74
63	75	/* allow to overwrite serial and ethaddr */
64	76	#define CONFIG_ENV_OVERWRITE