Eric Lee / smarc-uboot

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Commit 8c211af8f8c0617c40ccf4f0df557e4fbf6073ea

Authored by Horatiu Vultur
Committed by Daniel Schwierzeck
1 parent 06d270cf57
Exists in smarc_8mq_lf_v2020.04 and in 10 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, emb_lf_v2023.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

net: mscc: ocelot: Update DTS for Ocelot pcb120. 

Update device tree for ocelot to add support for ocelot pcb120.

Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com>

Showing 5 changed files with 167 additions and 81 deletions Side-by-side Diff

... ... @@ -577,6 +577,7 @@
577 577 F: drivers/gpio/mscc_sgpio.c
578 578 F: drivers/spi/mscc_bb_spi.c
579 579 F: include/configs/vcoreiii.h
  580 +F: include/dt-bindings/mscc/
580 581 F: drivers/pinctrl/mscc/
581 582 F: drivers/net/mscc_eswitch/
582 583  
arch/mips/dts/mscc,ocelot.dtsi
Diff comments   View file @ 8c211af
... ... @@ -112,32 +112,33 @@
112 112 status = "disabled";
113 113 };
114 114  
115   - switch@1010000 {
  115 + switch: switch@1010000 {
116 116 pinctrl-0 = <&miim1_pins>;
117 117 pinctrl-names = "default";
118 118  
119 119 compatible = "mscc,vsc7514-switch";
120   - reg = <0x1010000 0x10000>, /* VTSS_TO_SYS */
121   - <0x1030000 0x10000>, /* VTSS_TO_REW */
122   - <0x1080000 0x100>, /* VTSS_TO_DEVCPU_QS */
123   - <0x10d0000 0x10000>, /* VTSS_TO_HSIO */
124   - <0x11e0000 0x100>, /* VTSS_TO_DEV_0 */
125   - <0x11f0000 0x100>, /* VTSS_TO_DEV_1 */
126   - <0x1200000 0x100>, /* VTSS_TO_DEV_2 */
127   - <0x1210000 0x100>, /* VTSS_TO_DEV_3 */
128   - <0x1220000 0x100>, /* VTSS_TO_DEV_4 */
129   - <0x1230000 0x100>, /* VTSS_TO_DEV_5 */
130   - <0x1240000 0x100>, /* VTSS_TO_DEV_6 */
131   - <0x1250000 0x100>, /* VTSS_TO_DEV_7 */
132   - <0x1260000 0x100>, /* VTSS_TO_DEV_8 */
133   - <0x1270000 0x100>, /* NA */
134   - <0x1280000 0x100>, /* NA */
135   - <0x1800000 0x80000>, /* VTSS_TO_QSYS */
136   - <0x1880000 0x10000>; /* VTSS_TO_ANA */
137   - reg-names = "sys", "rew", "qs", "hsio", "port0",
138   - "port1", "port2", "port3", "port4", "port5",
139   - "port6", "port7", "port8", "port9",
140   - "port10", "qsys", "ana";
  120 +
  121 + reg = <0x11e0000 0x100>, // VTSS_TO_DEV_0
  122 + <0x11f0000 0x100>, // VTSS_TO_DEV_1
  123 + <0x1200000 0x100>, // VTSS_TO_DEV_2
  124 + <0x1210000 0x100>, // VTSS_TO_DEV_3
  125 + <0x1220000 0x100>, // VTSS_TO_DEV_4
  126 + <0x1230000 0x100>, // VTSS_TO_DEV_5
  127 + <0x1240000 0x100>, // VTSS_TO_DEV_6
  128 + <0x1250000 0x100>, // VTSS_TO_DEV_7
  129 + <0x1260000 0x100>, // VTSS_TO_DEV_8
  130 + <0x1270000 0x100>, // VTSS_TO_DEV_9
  131 + <0x1280000 0x100>, // VTSS_TO_DEV_10
  132 + <0x1010000 0x10000>, // VTSS_TO_SYS
  133 + <0x1030000 0x10000>, // VTSS_TO_REW
  134 + <0x1080000 0x100>, // VTSS_TO_DEVCPU_QS
  135 + <0x10d0000 0x10000>, // VTSS_TO_HSIO
  136 + <0x1800000 0x80000>,// VTSS_TO_QSYS
  137 + <0x1880000 0x10000>;// VTSS_TO_ANA
  138 + reg-names = "port0", "port1", "port2", "port3", "port4",
  139 + "port5", "port6", "port7", "port8", "port9",
  140 + "port10",
  141 + "sys", "rew", "qs", "hsio", "qsys", "ana";
141 142 interrupts = <21 22>;
142 143 interrupt-names = "xtr", "inj";
143 144 status = "okay";
... ... @@ -145,40 +146,6 @@
145 146 ethernet-ports {
146 147 #address-cells = <1>;
147 148 #size-cells = <0>;
148   -
149   - port0: port@0 {
150   - reg = <0>;
151   - };
152   - port1: port@1 {
153   - reg = <1>;
154   - };
155   - port2: port@2 {
156   - reg = <2>;
157   - };
158   - port3: port@3 {
159   - reg = <3>;
160   - };
161   - port4: port@4 {
162   - reg = <4>;
163   - };
164   - port5: port@5 {
165   - reg = <5>;
166   - };
167   - port6: port@6 {
168   - reg = <6>;
169   - };
170   - port7: port@7 {
171   - reg = <7>;
172   - };
173   - port8: port@8 {
174   - reg = <8>;
175   - };
176   - port9: port@9 {
177   - reg = <9>;
178   - };
179   - port10: port@10 {
180   - reg = <10>;
181   - };
182 149 };
183 150 };
184 151  
185 152  
186 153  
... ... @@ -186,21 +153,27 @@
186 153 #address-cells = <1>;
187 154 #size-cells = <0>;
188 155 compatible = "mscc,ocelot-miim";
189   - reg = <0x107009c 0x24>, <0x10700f0 0x8>;
  156 + reg = <0x107009c 0x24>;
190 157 interrupts = <14>;
191 158 status = "disabled";
  159 + };
192 160  
193   - phy0: ethernet-phy@0 {
194   - reg = <0>;
195   - };
196   - phy1: ethernet-phy@1 {
197   - reg = <1>;
198   - };
199   - phy2: ethernet-phy@2 {
200   - reg = <2>;
201   - };
202   - phy3: ethernet-phy@3 {
203   - reg = <3>;
  161 + mdio1: mdio@10700f0 {
  162 + #address-cells = <1>;
  163 + #size-cells = <0>;
  164 + compatible = "mscc,ocelot-miim";
  165 + reg = <0x10700c0 0x24>;
  166 + interrupts = <14>;
  167 + status = "disabled";
  168 + };
  169 +
  170 + hsio: syscon@10d0000 {
  171 + compatible = "mscc,ocelot-hsio", "syscon", "simple-mfd";
  172 + reg = <0x10d0000 0x10000>;
  173 +
  174 + serdes_hsio: serdes_hsio {
  175 + compatible = "mscc,vsc7514-serdes";
  176 + #phy-cells = <3>;
204 177 };
205 178 };
206 179  
arch/mips/dts/ocelot_pcb120.dts
Diff comments   View file @ 8c211af
... ... @@ -5,6 +5,7 @@
5 5  
6 6 /dts-v1/;
7 7 #include "mscc,ocelot_pcb.dtsi"
  8 +#include <dt-bindings/mscc/ocelot_data.h>
8 9  
9 10 / {
10 11 model = "Ocelot PCB120 Reference Board";
... ... @@ -84,5 +85,80 @@
84 85 &sgpio {
85 86 status = "okay";
86 87 mscc,sgpio-ports = <0x000FFFFF>;
  88 +};
  89 +
  90 +&mdio0 {
  91 + status = "okay";
  92 +
  93 + phy4: ethernet-phy@4 {
  94 + reg = <3>;
  95 + };
  96 + phy5: ethernet-phy@5 {
  97 + reg = <2>;
  98 + };
  99 + phy6: ethernet-phy@6 {
  100 + reg = <1>;
  101 + };
  102 + phy7: ethernet-phy@7 {
  103 + reg = <0>;
  104 + };
  105 +};
  106 +
  107 +&mdio1 {
  108 + status = "okay";
  109 +
  110 + phy0: ethernet-phy@0 {
  111 + reg = <3>;
  112 + };
  113 + phy1: ethernet-phy@1 {
  114 + reg = <2>;
  115 + };
  116 + phy2: ethernet-phy@2 {
  117 + reg = <1>;
  118 + };
  119 + phy3: ethernet-phy@3 {
  120 + reg = <0>;
  121 + };
  122 +};
  123 +
  124 +&switch {
  125 + ethernet-ports {
  126 + port0: port@0 {
  127 + reg = <5>;
  128 + phy-handle = <&phy0>;
  129 + phys = <&serdes_hsio 5 SERDES1G(2) PHY_MODE_SGMII>;
  130 + };
  131 + port1: port@1 {
  132 + reg = <9>;
  133 + phy-handle = <&phy1>;
  134 + phys = <&serdes_hsio 9 SERDES1G(3) PHY_MODE_SGMII>;
  135 + };
  136 + port2: port@2 {
  137 + reg = <6>;
  138 + phy-handle = <&phy2>;
  139 + phys = <&serdes_hsio 6 SERDES1G(4) PHY_MODE_SGMII>;
  140 + };
  141 + port3: port@3 {
  142 + reg = <4>;
  143 + phy-handle = <&phy3>;
  144 + phys = <&serdes_hsio 4 SERDES1G(5) PHY_MODE_SGMII>;
  145 + };
  146 + port4: port@4 {
  147 + reg = <3>;
  148 + phy-handle = <&phy4>;
  149 + };
  150 + port5: port@5 {
  151 + reg = <2>;
  152 + phy-handle = <&phy5>;
  153 + };
  154 + port6: port@6 {
  155 + reg = <1>;
  156 + phy-handle = <&phy6>;
  157 + };
  158 + port7: port@7 {
  159 + reg = <0>;
  160 + phy-handle = <&phy7>;
  161 + };
  162 + };
87 163 };
arch/mips/dts/ocelot_pcb123.dts
Diff comments   View file @ 8c211af
... ... @@ -38,21 +38,39 @@
38 38  
39 39 &mdio0 {
40 40 status = "okay";
41   -};
42 41  
43   -&port0 {
44   - phy-handle = <&phy0>;
  42 + phy0: ethernet-phy@0 {
  43 + reg = <0>;
  44 + };
  45 + phy1: ethernet-phy@1 {
  46 + reg = <1>;
  47 + };
  48 + phy2: ethernet-phy@2 {
  49 + reg = <2>;
  50 + };
  51 + phy3: ethernet-phy@3 {
  52 + reg = <3>;
  53 + };
45 54 };
46 55  
47   -&port1 {
48   - phy-handle = <&phy1>;
49   -};
50   -
51   -&port2 {
52   - phy-handle = <&phy2>;
53   -};
54   -
55   -&port3 {
56   - phy-handle = <&phy3>;
  56 +&switch {
  57 + ethernet-ports {
  58 + port0: port@0 {
  59 + reg = <2>;
  60 + phy-handle = <&phy2>;
  61 + };
  62 + port1: port@1 {
  63 + reg = <3>;
  64 + phy-handle = <&phy3>;
  65 + };
  66 + port2: port@2 {
  67 + reg = <0>;
  68 + phy-handle = <&phy0>;
  69 + };
  70 + port3: port@3 {
  71 + reg = <1>;
  72 + phy-handle = <&phy1>;
  73 + };
  74 + };
57 75 };
include/dt-bindings/mscc/ocelot_data.h
Diff comments   View file @ 8c211af
  1 +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
  2 +/*
  3 + * Copyright (c) 2019 Microsemi Corporation
  4 + */
  5 +
  6 +#ifndef _OCELOT_DATA_H_
  7 +#define _OCELOT_DATA_H_
  8 +
  9 +#define SERDES1G(x) (x)
  10 +#define SERDES1G_MAX SERDES1G(7)
  11 +#define SERDES6G(x) (SERDES1G_MAX + 1 + (x))
  12 +#define SERDES6G_MAX SERDES6G(11)
  13 +#define SERDES_MAX (SERDES6G_MAX + 1)
  14 +
  15 +/* similar with phy_interface_t */
  16 +#define PHY_MODE_SGMII 2
  17 +#define PHY_MODE_QSGMII 4
  18 +
  19 +#endif