Eric Lee / smarc-uboot

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Commit 8ca78f2c89cd058e498fa438f57accc2e810bb98

Authored by Peter Tyser
Committed by Wolfgang Denk
1 parent a72dbae2cc
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

fsl: Clean up printing of PCI boot info 

Previously boards used a variety of indentations, newline styles, and
colon styles for the PCI information that is printed on bootup.  This
patch unifies the style to look like:

...
NAND:  1024 MiB
PCIE1: connected as Root Complex
           Scanning PCI bus 01
        04  01  8086  1010  0200  00
        04  01  8086  1010  0200  00
        03  00  10b5  8112  0604  00
        02  01  10b5  8518  0604  00
        02  02  10b5  8518  0604  00
        08  00  1957  0040  0b20  00
        07  00  10b5  8518  0604  00
        09  00  10b5  8112  0604  00
        07  01  10b5  8518  0604  00
        07  02  10b5  8518  0604  00
        06  00  10b5  8518  0604  00
        02  03  10b5  8518  0604  00
        01  00  10b5  8518  0604  00
PCIE1: Bus 00 - 0b
PCIE2: connected as Root Complex
           Scanning PCI bus 0d
        0d  00  1957  0040  0b20  00
PCIE2: Bus 0c - 0d
In:    serial
...

Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
CC: wd@denx.de
CC: sr@denx.de
CC: galak@kernel.crashing.org

Showing 24 changed files with 147 additions and 147 deletions Side-by-side Diff

board/atum8548/atum8548.c
Diff comments   View file @ 8ca78f2
... ... @@ -218,14 +218,14 @@
218 218  
219 219 pcie1_hose.region_count = 1;
220 220 #endif
221   - printf (" PCIE1 connected to Slot as %s (base addr %lx)\n",
  221 + printf ("PCIE1: connected to Slot as %s (base addr %lx)\n",
222 222 pcie_ep ? "Endpoint" : "Root Complex",
223 223 pci_info[num].regs);
224 224  
225 225 first_free_busno = fsl_pci_init_port(&pci_info[num++],
226 226 &pcie1_hose, first_free_busno);
227 227 } else {
228   - printf (" PCIE1: disabled\n");
  228 + printf("PCIE1: disabled\n");
229 229 }
230 230  
231 231 puts("\n");
... ... @@ -242,7 +242,7 @@
242 242 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
243 243 SET_STD_PCI_INFO(pci_info[num], 1);
244 244 pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
245   - printf ("\n PCI1: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
  245 + printf("PCI1: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
246 246 (pci_32) ? 32 : 64,
247 247 (pci_speed == 33333000) ? "33" :
248 248 (pci_speed == 66666000) ? "66" : "unknown",
... ... @@ -254,7 +254,7 @@
254 254 first_free_busno = fsl_pci_init_port(&pci_info[num++],
255 255 &pci1_hose, first_free_busno);
256 256 } else {
257   - printf (" PCI: disabled\n");
  257 + printf("PCI1: disabled\n");
258 258 }
259 259  
260 260 puts("\n");
261 261  
... ... @@ -267,11 +267,11 @@
267 267 SET_STD_PCI_INFO(pci_info[num], 2);
268 268 pci_agent = fsl_setup_hose(&pci2_hose, pci_info[num].regs);
269 269  
270   - puts (" PCI2\n");
  270 + puts("PCI2\n");
271 271 first_free_busno = fsl_pci_init_port(&pci_info[num++],
272 272 &pci1_hose, first_free_busno);
273 273 } else {
274   - printf (" PCI2: disabled\n");
  274 + printf("PCI2: disabled\n");
275 275 }
276 276 puts("\n");
277 277 #else
board/freescale/corenet_ds/pci.c
Diff comments   View file @ 8ca78f2
... ... @@ -68,13 +68,13 @@
68 68 LAW_TRGT_IF_PCIE_1);
69 69 SET_STD_PCIE_INFO(pci_info[num], 1);
70 70 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
71   - printf(" PCIE1 connected to Slot 1 as %s (base addr %lx)\n",
  71 + printf("PCIE1: connected to Slot 1 as %s (base addr %lx)\n",
72 72 pcie_ep ? "End Point" : "Root Complex",
73 73 pci_info[num].regs);
74 74 first_free_busno = fsl_pci_init_port(&pci_info[num++],
75 75 &pcie1_hose, first_free_busno);
76 76 } else {
77   - printf (" PCIE1: disabled\n");
  77 + printf("PCIE1: disabled\n");
78 78 }
79 79 #else
80 80 setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE1); /* disable */
81 81  
... ... @@ -90,13 +90,13 @@
90 90 LAW_TRGT_IF_PCIE_2);
91 91 SET_STD_PCIE_INFO(pci_info[num], 2);
92 92 pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
93   - printf(" PCIE2 connected to Slot 3 as %s (base addr %lx)\n",
  93 + printf("PCIE2: connected to Slot 3 as %s (base addr %lx)\n",
94 94 pcie_ep ? "End Point" : "Root Complex",
95 95 pci_info[num].regs);
96 96 first_free_busno = fsl_pci_init_port(&pci_info[num++],
97 97 &pcie2_hose, first_free_busno);
98 98 } else {
99   - printf (" PCIE2: disabled\n");
  99 + printf("PCIE2: disabled\n");
100 100 }
101 101 #else
102 102 setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE2); /* disable */
103 103  
... ... @@ -112,13 +112,13 @@
112 112 LAW_TRGT_IF_PCIE_3);
113 113 SET_STD_PCIE_INFO(pci_info[num], 3);
114 114 pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
115   - printf(" PCIE3 connected to Slot 2 as %s (base addr %lx)\n",
  115 + printf("PCIE3: connected to Slot 2 as %s (base addr %lx)\n",
116 116 pcie_ep ? "End Point" : "Root Complex",
117 117 pci_info[num].regs);
118 118 first_free_busno = fsl_pci_init_port(&pci_info[num++],
119 119 &pcie3_hose, first_free_busno);
120 120 } else {
121   - printf (" PCIE3: disabled\n");
  121 + printf("PCIE3: disabled\n");
122 122 }
123 123 #else
124 124 setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE3); /* disable */
125 125  
... ... @@ -134,13 +134,13 @@
134 134 LAW_TRGT_IF_PCIE_4);
135 135 SET_STD_PCIE_INFO(pci_info[num], 4);
136 136 pcie_ep = fsl_setup_hose(&pcie4_hose, pci_info[num].regs);
137   - printf(" PCIE4 connected to as %s (base addr %lx)\n",
  137 + printf("PCIE4: connected to as %s (base addr %lx)\n",
138 138 pcie_ep ? "End Point" : "Root Complex",
139 139 pci_info[num].regs);
140 140 first_free_busno = fsl_pci_init_port(&pci_info[num++],
141 141 &pcie4_hose, first_free_busno);
142 142 } else {
143   - printf (" PCIE4: disabled\n");
  143 + printf("PCIE4: disabled\n");
144 144 }
145 145 #else
146 146 setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_PCIE4); /* disable */
board/freescale/mpc8536ds/mpc8536ds.c
Diff comments   View file @ 8ca78f2
... ... @@ -229,13 +229,13 @@
229 229 LAW_TRGT_IF_PCIE_3);
230 230 SET_STD_PCIE_INFO(pci_info[num], 3);
231 231 pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
232   - printf (" PCIE3 connected to Slot3 as %s (base address %lx)\n",
  232 + printf("PCIE3: connected to Slot3 as %s (base address %lx)\n",
233 233 pcie_ep ? "Endpoint" : "Root Complex",
234 234 pci_info[num].regs);
235 235 first_free_busno = fsl_pci_init_port(&pci_info[num++],
236 236 &pcie3_hose, first_free_busno);
237 237 } else {
238   - printf (" PCIE3: disabled\n");
  238 + printf("PCIE3: disabled\n");
239 239 }
240 240  
241 241 puts("\n");
242 242  
... ... @@ -253,13 +253,13 @@
253 253 LAW_TRGT_IF_PCIE_1);
254 254 SET_STD_PCIE_INFO(pci_info[num], 1);
255 255 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
256   - printf (" PCIE1 connected to Slot1 as %s (base address %lx)\n",
  256 + printf("PCIE1: connected to Slot1 as %s (base address %lx)\n",
257 257 pcie_ep ? "Endpoint" : "Root Complex",
258 258 pci_info[num].regs);
259 259 first_free_busno = fsl_pci_init_port(&pci_info[num++],
260 260 &pcie1_hose, first_free_busno);
261 261 } else {
262   - printf (" PCIE1: disabled\n");
  262 + printf("PCIE1: disabled\n");
263 263 }
264 264  
265 265 puts("\n");
266 266  
... ... @@ -277,13 +277,13 @@
277 277 LAW_TRGT_IF_PCIE_2);
278 278 SET_STD_PCIE_INFO(pci_info[num], 2);
279 279 pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
280   - printf (" PCIE2 connected to Slot 2 as %s (base address %lx)\n",
  280 + printf("PCIE2: connected to Slot 2 as %s (base address %lx)\n",
281 281 pcie_ep ? "Endpoint" : "Root Complex",
282 282 pci_info[num].regs);
283 283 first_free_busno = fsl_pci_init_port(&pci_info[num++],
284 284 &pcie2_hose, first_free_busno);
285 285 } else {
286   - printf (" PCIE2: disabled\n");
  286 + printf("PCIE2: disabled\n");
287 287 }
288 288  
289 289 puts("\n");
... ... @@ -304,7 +304,7 @@
304 304 LAW_TRGT_IF_PCI);
305 305 SET_STD_PCI_INFO(pci_info[num], 1);
306 306 pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
307   - printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
  307 + printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
308 308 (pci_32) ? 32 : 64,
309 309 (pci_speed == 33333000) ? "33" :
310 310 (pci_speed == 66666000) ? "66" : "unknown",
... ... @@ -316,7 +316,7 @@
316 316 first_free_busno = fsl_pci_init_port(&pci_info[num++],
317 317 &pci1_hose, first_free_busno);
318 318 } else {
319   - printf (" PCI: disabled\n");
  319 + printf("PCI: disabled\n");
320 320 }
321 321  
322 322 puts("\n");
board/freescale/mpc8540ads/mpc8540ads.c
Diff comments   View file @ 8ca78f2
... ... @@ -47,10 +47,10 @@
47 47 puts("Board: ADS\n");
48 48  
49 49 #ifdef CONFIG_PCI
50   - printf(" PCI1: 32 bit, %d MHz (compiled)\n",
  50 + printf("PCI1: 32 bit, %d MHz (compiled)\n",
51 51 CONFIG_SYS_CLK_FREQ / 1000000);
52 52 #else
53   - printf(" PCI1: disabled\n");
  53 + printf("PCI1: disabled\n");
54 54 #endif
55 55  
56 56 /*
board/freescale/mpc8541cds/mpc8541cds.c
Diff comments   View file @ 8ca78f2
... ... @@ -221,17 +221,17 @@
221 221 MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
222 222 MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
223 223  
224   - printf (" PCI1: %d bit, %s MHz, %s\n",
  224 + printf("PCI1: %d bit, %s MHz, %s\n",
225 225 (pci1_32) ? 32 : 64,
226 226 (pci1_speed == 33000000) ? "33" :
227 227 (pci1_speed == 66000000) ? "66" : "unknown",
228 228 pci1_clk_sel ? "sync" : "async");
229 229  
230 230 if (pci_dual) {
231   - printf (" PCI2: 32 bit, 66 MHz, %s\n",
  231 + printf("PCI2: 32 bit, 66 MHz, %s\n",
232 232 pci2_clk_sel ? "sync" : "async");
233 233 } else {
234   - printf (" PCI2: disabled\n");
  234 + printf("PCI2: disabled\n");
235 235 }
236 236  
237 237 /*
board/freescale/mpc8544ds/mpc8544ds.c
Diff comments   View file @ 8ca78f2
... ... @@ -142,9 +142,9 @@
142 142  
143 143 pcie3_hose.region_count = 1;
144 144 #endif
145   - printf (" PCIE3 connected to ULI as %s (base addr %lx)\n",
146   - pcie_ep ? "Endpoint" : "Root Complex",
147   - pci_info[num].regs);
  145 + printf("PCIE3: connected to ULI as %s (base addr %lx)\n",
  146 + pcie_ep ? "Endpoint" : "Root Complex",
  147 + pci_info[num].regs);
148 148 first_free_busno = fsl_pci_init_port(&pci_info[num++],
149 149 &pcie3_hose, first_free_busno);
150 150  
... ... @@ -154,7 +154,7 @@
154 154 */
155 155 in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BUS);
156 156 } else {
157   - printf (" PCIE3: disabled\n");
  157 + printf("PCIE3: disabled\n");
158 158 }
159 159 puts("\n");
160 160 #else
161 161  
... ... @@ -177,14 +177,14 @@
177 177  
178 178 pcie1_hose.region_count = 1;
179 179 #endif
180   - printf (" PCIE1 connected to Slot 2 as %s (base addr %lx)\n",
  180 + printf("PCIE1: connected to Slot 2 as %s (base addr %lx)\n",
181 181 pcie_ep ? "Endpoint" : "Root Complex",
182 182 pci_info[num].regs);
183 183  
184 184 first_free_busno = fsl_pci_init_port(&pci_info[num++],
185 185 &pcie1_hose, first_free_busno);
186 186 } else {
187   - printf (" PCIE1: disabled\n");
  187 + printf("PCIE1: disabled\n");
188 188 }
189 189  
190 190 puts("\n");
191 191  
... ... @@ -208,13 +208,13 @@
208 208  
209 209 pcie2_hose.region_count = 1;
210 210 #endif
211   - printf (" PCIE2 connected to Slot 1 as %s (base addr %lx)\n",
212   - pcie_ep ? "Endpoint" : "Root Complex",
213   - pci_info[num].regs);
  211 + printf("PCIE2: connected to Slot 1 as %s (base addr %lx)\n",
  212 + pcie_ep ? "Endpoint" : "Root Complex",
  213 + pci_info[num].regs);
214 214 first_free_busno = fsl_pci_init_port(&pci_info[num++],
215 215 &pcie2_hose, first_free_busno);
216 216 } else {
217   - printf (" PCIE2: disabled\n");
  217 + printf("PCIE2: disabled\n");
218 218 }
219 219  
220 220 puts("\n");
... ... @@ -231,7 +231,7 @@
231 231 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
232 232 SET_STD_PCI_INFO(pci_info[num], 1);
233 233 pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
234   - printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
  234 + printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
235 235 (pci_32) ? 32 : 64,
236 236 (pci_speed == 33333000) ? "33" :
237 237 (pci_speed == 66666000) ? "66" : "unknown",
... ... @@ -243,7 +243,7 @@
243 243 first_free_busno = fsl_pci_init_port(&pci_info[num++],
244 244 &pci1_hose, first_free_busno);
245 245 } else {
246   - printf (" PCI: disabled\n");
  246 + printf("PCI: disabled\n");
247 247 }
248 248  
249 249 puts("\n");
board/freescale/mpc8548cds/mpc8548cds.c
Diff comments   View file @ 8ca78f2
... ... @@ -284,7 +284,7 @@
284 284 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
285 285 SET_STD_PCI_INFO(pci_info[num], 1);
286 286 pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
287   - printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
  287 + printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
288 288 (pci_32) ? 32 : 64,
289 289 (pci_speed == 33333000) ? "33" :
290 290 (pci_speed == 66666000) ? "66" : "unknown",
... ... @@ -308,7 +308,7 @@
308 308 }
309 309 #endif
310 310 } else {
311   - printf (" PCI: disabled\n");
  311 + printf("PCI: disabled\n");
312 312 }
313 313  
314 314 puts("\n");
315 315  
... ... @@ -321,10 +321,10 @@
321 321 uint pci2_clk_sel = porpllsr & 0x4000; /* PORPLLSR[17] */
322 322 uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */
323 323 if (pci_dual) {
324   - printf (" PCI2: 32 bit, 66 MHz, %s\n",
  324 + printf("PCI2: 32 bit, 66 MHz, %s\n",
325 325 pci2_clk_sel ? "sync" : "async");
326 326 } else {
327   - printf (" PCI2: disabled\n");
  327 + printf("PCI2: disabled\n");
328 328 }
329 329 }
330 330 #else
331 331  
... ... @@ -337,14 +337,14 @@
337 337 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
338 338 SET_STD_PCIE_INFO(pci_info[num], 1);
339 339 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
340   - printf (" PCIE1 connected to Slot as %s (base addr %lx)\n",
341   - pcie_ep ? "Endpoint" : "Root Complex",
342   - pci_info[num].regs);
  340 + printf("PCIE1: connected to Slot as %s (base addr %lx)\n",
  341 + pcie_ep ? "Endpoint" : "Root Complex",
  342 + pci_info[num].regs);
343 343  
344 344 first_free_busno = fsl_pci_init_port(&pci_info[num++],
345 345 &pcie1_hose, first_free_busno);
346 346 } else {
347   - printf (" PCIE1: disabled\n");
  347 + printf("PCIE1: disabled\n");
348 348 }
349 349  
350 350 puts("\n");
board/freescale/mpc8555cds/mpc8555cds.c
Diff comments   View file @ 8ca78f2
... ... @@ -219,17 +219,17 @@
219 219 MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
220 220 MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
221 221  
222   - printf (" PCI1: %d bit, %s MHz, %s\n",
  222 + printf("PCI1: %d bit, %s MHz, %s\n",
223 223 (pci1_32) ? 32 : 64,
224 224 (pci1_speed == 33000000) ? "33" :
225 225 (pci1_speed == 66000000) ? "66" : "unknown",
226 226 pci1_clk_sel ? "sync" : "async");
227 227  
228 228 if (pci_dual) {
229   - printf (" PCI2: 32 bit, 66 MHz, %s\n",
  229 + printf("PCI2: 32 bit, 66 MHz, %s\n",
230 230 pci2_clk_sel ? "sync" : "async");
231 231 } else {
232   - printf (" PCI2: disabled\n");
  232 + printf("PCI2: disabled\n");
233 233 }
234 234  
235 235 /*
board/freescale/mpc8560ads/mpc8560ads.c
Diff comments   View file @ 8ca78f2
... ... @@ -252,10 +252,10 @@
252 252 puts("Board: ADS\n");
253 253  
254 254 #ifdef CONFIG_PCI
255   - printf(" PCI1: 32 bit, %d MHz (compiled)\n",
  255 + printf("PCI1: 32 bit, %d MHz (compiled)\n",
256 256 CONFIG_SYS_CLK_FREQ / 1000000);
257 257 #else
258   - printf(" PCI1: disabled\n");
  258 + printf("PCI1: disabled\n");
259 259 #endif
260 260  
261 261 /*
board/freescale/mpc8568mds/mpc8568mds.c
Diff comments   View file @ 8ca78f2
... ... @@ -378,7 +378,7 @@
378 378 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
379 379 SET_STD_PCI_INFO(pci_info[num], 1);
380 380 pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
381   - printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
  381 + printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
382 382 (pci_32) ? 32 : 64,
383 383 (pci_speed == 33333000) ? "33" :
384 384 (pci_speed == 66666000) ? "66" : "unknown",
... ... @@ -390,7 +390,7 @@
390 390 first_free_busno = fsl_pci_init_port(&pci_info[num++],
391 391 &pci1_hose, first_free_busno);
392 392 } else {
393   - printf (" PCI: disabled\n");
  393 + printf("PCI: disabled\n");
394 394 }
395 395  
396 396 puts("\n");
397 397  
... ... @@ -404,14 +404,14 @@
404 404 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
405 405 SET_STD_PCIE_INFO(pci_info[num], 1);
406 406 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
407   - printf (" PCIE1 connected to Slot as %s (base addr %lx)\n",
  407 + printf("PCIE1: connected to Slot as %s (base addr %lx)\n",
408 408 pcie_ep ? "Endpoint" : "Root Complex",
409 409 pci_info[num].regs);
410 410  
411 411 first_free_busno = fsl_pci_init_port(&pci_info[num++],
412 412 &pcie1_hose, first_free_busno);
413 413 } else {
414   - printf (" PCIE1: disabled\n");
  414 + printf("PCIE1: disabled\n");
415 415 }
416 416  
417 417 puts("\n");
board/freescale/mpc8569mds/mpc8569mds.c
Diff comments   View file @ 8ca78f2
... ... @@ -584,13 +584,13 @@
584 584 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
585 585 SET_STD_PCIE_INFO(pci_info[num], 1);
586 586 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
587   - printf (" PCIE1 connected to Slot as %s (base addr %lx)\n",
588   - pcie_ep ? "Endpoint" : "Root Complex",
589   - pci_info[num].regs);
  587 + printf("PCIE1: connected to Slot as %s (base addr %lx)\n",
  588 + pcie_ep ? "Endpoint" : "Root Complex",
  589 + pci_info[num].regs);
590 590 first_free_busno = fsl_pci_init_port(&pci_info[num++],
591 591 &pcie1_hose, first_free_busno);
592 592 } else {
593   - printf (" PCIE1: disabled\n");
  593 + printf("PCIE1: disabled\n");
594 594 }
595 595  
596 596 puts("\n");
board/freescale/mpc8572ds/mpc8572ds.c
Diff comments   View file @ 8ca78f2
... ... @@ -192,9 +192,9 @@
192 192 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){
193 193 SET_STD_PCIE_INFO(pci_info[num], 3);
194 194 pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
195   - printf (" PCIE3 connected to ULI as %s (base addr %lx)\n",
196   - pcie_ep ? "Endpoint" : "Root Complex",
197   - pci_info[num].regs);
  195 + printf("PCIE3: connected to ULI as %s (base addr %lx)\n",
  196 + pcie_ep ? "Endpoint" : "Root Complex",
  197 + pci_info[num].regs);
198 198 first_free_busno = fsl_pci_init_port(&pci_info[num++],
199 199 &pcie3_hose, first_free_busno);
200 200 /*
... ... @@ -211,7 +211,7 @@
211 211 in_be32(p);
212 212 }
213 213 } else {
214   - printf (" PCIE3: disabled\n");
  214 + printf("PCIE3: disabled\n");
215 215 }
216 216 puts("\n");
217 217 #else
218 218  
... ... @@ -224,13 +224,13 @@
224 224 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){
225 225 SET_STD_PCIE_INFO(pci_info[num], 2);
226 226 pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
227   - printf (" PCIE2 connected to Slot 1 as %s (base addr %lx)\n",
228   - pcie_ep ? "Endpoint" : "Root Complex",
229   - pci_info[num].regs);
  227 + printf("PCIE2: connected to Slot 1 as %s (base addr %lx)\n",
  228 + pcie_ep ? "Endpoint" : "Root Complex",
  229 + pci_info[num].regs);
230 230 first_free_busno = fsl_pci_init_port(&pci_info[num++],
231 231 &pcie2_hose, first_free_busno);
232 232 } else {
233   - printf (" PCIE2: disabled\n");
  233 + printf("PCIE2: disabled\n");
234 234 }
235 235  
236 236 puts("\n");
237 237  
... ... @@ -244,13 +244,13 @@
244 244 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
245 245 SET_STD_PCIE_INFO(pci_info[num], 1);
246 246 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
247   - printf (" PCIE1 connected to Slot 2 as %s (base addr %lx)\n",
  247 + printf("PCIE1: connected to Slot 2 as %s (base addr %lx)\n",
248 248 pcie_ep ? "Endpoint" : "Root Complex",
249 249 pci_info[num].regs);
250 250 first_free_busno = fsl_pci_init_port(&pci_info[num++],
251 251 &pcie1_hose, first_free_busno);
252 252 } else {
253   - printf (" PCIE1: disabled\n");
  253 + printf("PCIE1: disabled\n");
254 254 }
255 255  
256 256 puts("\n");
board/freescale/mpc8610hpcd/mpc8610hpcd.c
Diff comments   View file @ 8ca78f2
... ... @@ -244,14 +244,14 @@
244 244 if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)){
245 245 SET_STD_PCIE_INFO(pci_info[num], 1);
246 246 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
247   - printf (" PCIE1 connected to ULI as %s (base addr %lx)\n",
248   - pcie_ep ? "Endpoint" : "Root Complex",
249   - pci_info[num].regs);
  247 + printf("PCIE1: connected to ULI as %s (base addr %lx)\n",
  248 + pcie_ep ? "Endpoint" : "Root Complex",
  249 + pci_info[num].regs);
250 250  
251 251 first_free_busno = fsl_pci_init_port(&pci_info[num++],
252 252 &pcie1_hose, first_free_busno);
253 253 } else {
254   - printf (" PCIE1: disabled\n");
  254 + printf("PCIE1: disabled\n");
255 255 }
256 256  
257 257 puts("\n");
258 258  
... ... @@ -265,13 +265,13 @@
265 265 if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE2)){
266 266 SET_STD_PCIE_INFO(pci_info[num], 2);
267 267 pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
268   - printf (" PCIE2 connected to Slot as %s (base addr %lx)\n",
269   - pcie_ep ? "Endpoint" : "Root Complex",
270   - pci_info[num].regs);
  268 + printf("PCIE2: connected to Slot as %s (base addr %lx)\n",
  269 + pcie_ep ? "Endpoint" : "Root Complex",
  270 + pci_info[num].regs);
271 271 first_free_busno = fsl_pci_init_port(&pci_info[num++],
272 272 &pcie2_hose, first_free_busno);
273 273 } else {
274   - printf (" PCIE2: disabled\n");
  274 + printf("PCIE2: disabled\n");
275 275 }
276 276  
277 277 puts("\n");
278 278  
... ... @@ -283,14 +283,14 @@
283 283 if (!(devdisr & MPC86xx_DEVDISR_PCI1)) {
284 284 SET_STD_PCI_INFO(pci_info[num], 1);
285 285 pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
286   - printf(" PCI connected to PCI slots as %s" \
  286 + printf("PCI: connected to PCI slots as %s" \
287 287 " (base address %lx)\n",
288 288 pci_agent ? "Agent" : "Host",
289 289 pci_info[num].regs);
290 290 first_free_busno = fsl_pci_init_port(&pci_info[num++],
291 291 &pci1_hose, first_free_busno);
292 292 } else {
293   - printf (" PCI: disabled\n");
  293 + printf("PCI: disabled\n");
294 294 }
295 295  
296 296 puts("\n");
board/freescale/mpc8641hpcn/mpc8641hpcn.c
Diff comments   View file @ 8ca78f2
... ... @@ -157,9 +157,9 @@
157 157 if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
158 158 SET_STD_PCIE_INFO(pci_info[num], 1);
159 159 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
160   - printf(" PCIE1 connected to ULI as %s (base addr %lx)\n",
161   - pcie_ep ? "Endpoint" : "Root Complex",
162   - pci_info[num].regs);
  160 + printf("PCIE1: connected to ULI as %s (base addr %lx)\n",
  161 + pcie_ep ? "Endpoint" : "Root Complex",
  162 + pci_info[num].regs);
163 163 first_free_busno = fsl_pci_init_port(&pci_info[num++],
164 164 &pcie1_hose, first_free_busno);
165 165  
166 166  
167 167  
168 168  
... ... @@ -171,22 +171,22 @@
171 171 + CONFIG_SYS_PCIE1_MEM_SIZE - 0x1000000)));
172 172  
173 173 } else {
174   - puts(" PCIE1: disabled\n");
  174 + puts("PCIE1: disabled\n");
175 175 }
176 176 #else
177   - puts(" PCIE1: disabled\n");
  177 + puts("PCIE1: disabled\n");
178 178 #endif /* CONFIG_PCIE1 */
179 179  
180 180 #ifdef CONFIG_PCIE2
181 181 SET_STD_PCIE_INFO(pci_info[num], 2);
182 182 pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
183   - printf(" PCIE2 connected as %s (base addr %lx)\n",
184   - pcie_ep ? "Endpoint" : "Root Complex",
185   - pci_info[num].regs);
  183 + printf("PCIE2: connected as %s (base addr %lx)\n",
  184 + pcie_ep ? "Endpoint" : "Root Complex",
  185 + pci_info[num].regs);
186 186 first_free_busno = fsl_pci_init_port(&pci_info[num++],
187 187 &pcie2_hose, first_free_busno);
188 188 #else
189   - puts(" PCIE2: disabled\n");
  189 + puts("PCIE2: disabled\n");
190 190 #endif /* CONFIG_PCIE2 */
191 191  
192 192 }
board/freescale/p1022ds/p1022ds.c
Diff comments   View file @ 8ca78f2
... ... @@ -225,7 +225,7 @@
225 225 set_next_law(info->mem_phys, law_size_bits(info->mem_size), info->law);
226 226 set_next_law(info->io_phys, law_size_bits(info->io_size), info->law);
227 227 is_endpoint = fsl_setup_hose(hose, info->regs);
228   - printf(" PCIE%u connected to %s as %s (base addr %lx)\n",
  228 + printf("PCIE%u: connected to %s as %s (base addr %lx)\n",
229 229 info->pci_num, connected,
230 230 is_endpoint ? "Endpoint" : "Root Complex", info->regs);
231 231 bus_number = fsl_pci_init_port(info, hose, bus_number);
... ... @@ -255,7 +255,7 @@
255 255 SET_STD_PCIE_INFO(pci_info, 1);
256 256 configure_pcie(&pci_info, &pcie1_hose, serdes_slot_name(PCIE1));
257 257 } else {
258   - printf(" PCIE1: disabled\n");
  258 + printf("PCIE1: disabled\n");
259 259 }
260 260 #else
261 261 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
... ... @@ -266,7 +266,7 @@
266 266 SET_STD_PCIE_INFO(pci_info, 2);
267 267 configure_pcie(&pci_info, &pcie2_hose, serdes_slot_name(PCIE2));
268 268 } else {
269   - printf(" PCIE2: disabled\n");
  269 + printf("PCIE2: disabled\n");
270 270 }
271 271 #else
272 272 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
... ... @@ -277,7 +277,7 @@
277 277 SET_STD_PCIE_INFO(pci_info, 3);
278 278 configure_pcie(&pci_info, &pcie3_hose, serdes_slot_name(PCIE3));
279 279 } else {
280   - printf(" PCIE3: disabled\n");
  280 + printf("PCIE3: disabled\n");
281 281 }
282 282 #else
283 283 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
board/freescale/p1_p2_rdb/pci.c
Diff comments   View file @ 8ca78f2
... ... @@ -65,13 +65,13 @@
65 65 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
66 66 SET_STD_PCIE_INFO(pci_info[num], 2);
67 67 pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
68   - printf(" PCIE2 connected to Slot 1 as %s (base addr %lx)\n",
69   - pcie_ep ? "Endpoint" : "Root Complex",
70   - pci_info[num].regs);
  68 + printf("PCIE2: connected to Slot 1 as %s (base addr %lx)\n",
  69 + pcie_ep ? "Endpoint" : "Root Complex",
  70 + pci_info[num].regs);
71 71 first_free_busno = fsl_pci_init_port(&pci_info[num++],
72 72 &pcie2_hose, first_free_busno);
73 73 } else {
74   - printf (" PCIE2: disabled\n");
  74 + printf("PCIE2: disabled\n");
75 75 }
76 76 puts("\n");
77 77 #else
78 78  
... ... @@ -84,13 +84,13 @@
84 84 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
85 85 SET_STD_PCIE_INFO(pci_info[num], 1);
86 86 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
87   - printf(" PCIE1 connected to Slot 2 as %s (base addr %lx)\n",
88   - pcie_ep ? "Endpoint" : "Root Complex",
89   - pci_info[num].regs);
  87 + printf("PCIE1: connected to Slot 2 as %s (base addr %lx)\n",
  88 + pcie_ep ? "Endpoint" : "Root Complex",
  89 + pci_info[num].regs);
90 90 first_free_busno = fsl_pci_init_port(&pci_info[num++],
91 91 &pcie1_hose, first_free_busno);
92 92 } else {
93   - printf (" PCIE1: disabled\n");
  93 + printf("PCIE1: disabled\n");
94 94 }
95 95 puts("\n");
96 96 #else
board/freescale/p2020ds/p2020ds.c
Diff comments   View file @ 8ca78f2
... ... @@ -218,9 +218,9 @@
218 218 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)) {
219 219 SET_STD_PCIE_INFO(pci_info[num], 2);
220 220 pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
221   - printf(" PCIE2 connected to ULI as %s (base addr %lx)\n",
222   - pcie_ep ? "Endpoint" : "Root Complex",
223   - pci_info[num].regs);
  221 + printf("PCIE2: connected to ULI as %s (base addr %lx)\n",
  222 + pcie_ep ? "Endpoint" : "Root Complex",
  223 + pci_info[num].regs);
224 224 first_free_busno = fsl_pci_init_port(&pci_info[num++],
225 225 &pcie2_hose, first_free_busno);
226 226  
... ... @@ -245,7 +245,7 @@
245 245 }
246 246 #endif
247 247 } else {
248   - printf(" PCIE2: disabled\n");
  248 + printf("PCIE2: disabled\n");
249 249 }
250 250 puts("\n");
251 251 #else
252 252  
... ... @@ -258,13 +258,13 @@
258 258 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)) {
259 259 SET_STD_PCIE_INFO(pci_info[num], 3);
260 260 pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
261   - printf(" PCIE3 connected to Slot 1 as %s (base addr %lx)\n",
262   - pcie_ep ? "Endpoint" : "Root Complex",
263   - pci_info[num].regs);
  261 + printf("PCIE3: connected to Slot 1 as %s (base addr %lx)\n",
  262 + pcie_ep ? "Endpoint" : "Root Complex",
  263 + pci_info[num].regs);
264 264 first_free_busno = fsl_pci_init_port(&pci_info[num++],
265 265 &pcie3_hose, first_free_busno);
266 266 } else {
267   - printf(" PCIE3: disabled\n");
  267 + printf("PCIE3: disabled\n");
268 268 }
269 269 puts("\n");
270 270 #else
271 271  
... ... @@ -277,13 +277,13 @@
277 277 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) {
278 278 SET_STD_PCIE_INFO(pci_info[num], 1);
279 279 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
280   - printf(" PCIE1 connected to Slot 2 as %s (base addr %lx)\n",
281   - pcie_ep ? "Endpoint" : "Root Complex",
282   - pci_info[num].regs);
  280 + printf("PCIE1: connected to Slot 2 as %s (base addr %lx)\n",
  281 + pcie_ep ? "Endpoint" : "Root Complex",
  282 + pci_info[num].regs);
283 283 first_free_busno = fsl_pci_init_port(&pci_info[num++],
284 284 &pcie1_hose, first_free_busno);
285 285 } else {
286   - printf(" PCIE1: disabled\n");
  286 + printf("PCIE1: disabled\n");
287 287 }
288 288 puts("\n");
289 289 #else
... ... @@ -59,10 +59,10 @@
59 59 puts("Board: MicroSys PM854\n");
60 60  
61 61 #ifdef CONFIG_PCI
62   - printf(" PCI1: 32 bit, %d MHz (compiled)\n",
  62 + printf("PCI1: 32 bit, %d MHz (compiled)\n",
63 63 CONFIG_SYS_CLK_FREQ / 1000000);
64 64 #else
65   - printf(" PCI1: disabled\n");
  65 + printf("PCI1: disabled\n");
66 66 #endif
67 67  
68 68 /*
... ... @@ -213,10 +213,10 @@
213 213 puts("Board: MicroSys PM856\n");
214 214  
215 215 #ifdef CONFIG_PCI
216   - printf(" PCI1: 32 bit, %d MHz (compiled)\n",
  216 + printf("PCI1: 32 bit, %d MHz (compiled)\n",
217 217 CONFIG_SYS_CLK_FREQ / 1000000);
218 218 #else
219   - printf(" PCI1: disabled\n");
  219 + printf("PCI1: disabled\n");
220 220 #endif
221 221  
222 222 /*
board/sbc8548/sbc8548.c
Diff comments   View file @ 8ca78f2
... ... @@ -342,7 +342,7 @@
342 342 uint pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
343 343 uint pci_speed = CONFIG_SYS_CLK_FREQ; /* get_clock_freq() */
344 344  
345   - printf (" PCI host: %d bit, %s MHz, %s, %s\n",
  345 + printf("PCI: Host, %d bit, %s MHz, %s, %s\n",
346 346 (pci_32) ? 32 : 64,
347 347 (pci_speed == 33000000) ? "33" :
348 348 (pci_speed == 66000000) ? "66" : "unknown",
... ... @@ -353,7 +353,7 @@
353 353 first_free_busno = fsl_pci_init_port(&pci_info[num++],
354 354 &pci1_hose, first_free_busno);
355 355 } else {
356   - printf (" PCI: disabled\n");
  356 + printf("PCI: disabled\n");
357 357 }
358 358  
359 359 puts("\n");
360 360  
... ... @@ -368,11 +368,11 @@
368 368  
369 369 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
370 370 SET_STD_PCIE_INFO(pci_info[num], 1);
371   - printf (" PCIE at base address %lx\n", pci_info[num].regs);
  371 + printf("PCIE: base address %lx\n", pci_info[num].regs);
372 372 first_free_busno = fsl_pci_init_port(&pci_info[num++],
373 373 &pcie1_hose, first_free_busno);
374 374 } else {
375   - printf (" PCIE: disabled\n");
  375 + printf("PCIE: disabled\n");
376 376 }
377 377  
378 378 puts("\n");
board/sbc8641d/sbc8641d.c
Diff comments   View file @ 8ca78f2
... ... @@ -221,29 +221,29 @@
221 221 if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIEX1)) {
222 222 SET_STD_PCIE_INFO(pci_info[num], 1);
223 223 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
224   - printf(" PCIE1 connected as %s (base addr %lx)\n",
225   - pcie_ep ? "Endpoint" : "Root Complex",
226   - pci_info[num].regs);
  224 + printf("PCIE1: connected as %s (base addr %lx)\n",
  225 + pcie_ep ? "Endpoint" : "Root Complex",
  226 + pci_info[num].regs);
227 227 first_free_busno = fsl_pci_init_port(&pci_info[num++],
228 228 &pcie1_hose, first_free_busno);
229 229 } else {
230   - puts(" PCIE1: disabled\n");
  230 + puts("PCIE1: disabled\n");
231 231 }
232 232 #else
233   - puts(" PCIE1: disabled\n");
  233 + puts("PCIE1: disabled\n");
234 234 #endif /* CONFIG_PCIE1 */
235 235  
236 236 #ifdef CONFIG_PCIE2
237 237  
238 238 SET_STD_PCIE_INFO(pci_info[num], 2);
239 239 pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
240   - printf(" PCIE2 connected as %s (base addr %lx)\n",
241   - pcie_ep ? "Endpoint" : "Root Complex",
242   - pci_info[num].regs);
  240 + printf("PCIE2: connected as %s (base addr %lx)\n",
  241 + pcie_ep ? "Endpoint" : "Root Complex",
  242 + pci_info[num].regs);
243 243 first_free_busno = fsl_pci_init_port(&pci_info[num++],
244 244 &pcie2_hose, first_free_busno);
245 245 #else
246   - puts(" PCIE2: disabled\n");
  246 + puts("PCIE2: disabled\n");
247 247 #endif /* CONFIG_PCIE2 */
248 248 }
249 249  
board/tqc/tqm85xx/tqm85xx.c
Diff comments   View file @ 8ca78f2
... ... @@ -567,7 +567,7 @@
567 567 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
568 568 SET_STD_PCI_INFO(pci_info[num], 1);
569 569 pcie_ep = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
570   - printf ("\n PCI1: %d bit, %s MHz, %s, %s, %s\n",
  570 + printf("PCI1: %d bit, %s MHz, %s, %s, %s\n",
571 571 (pci_32) ? 32 : 64,
572 572 (pci_speed == 33333333) ? "33" :
573 573 (pci_speed == 66666666) ? "66" : "unknown",
... ... @@ -591,7 +591,7 @@
591 591 }
592 592 #endif
593 593 } else {
594   - printf(" PCI1: disabled\n");
  594 + printf("PCI1: disabled\n");
595 595 }
596 596 #else
597 597 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1);
598 598  
... ... @@ -603,12 +603,12 @@
603 603 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) {
604 604 SET_STD_PCIE_INFO(pci_info[num], 1);
605 605 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
606   - printf(" PCIE1 connected as %s\n",
  606 + printf("PCIE1: connected as %s\n",
607 607 pcie_ep ? "Endpoint" : "Root Complex");
608 608 first_free_busno = fsl_pci_init_port(&pci_info[num++],
609 609 &pcie1_hose, first_free_busno);
610 610 } else {
611   - printf(" PCIE1: disabled\n");
  611 + printf("PCIE1: disabled\n");
612 612 }
613 613 #else
614 614 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE);
board/xes/common/fsl_8xxx_pci.c
Diff comments   View file @ 8ca78f2
... ... @@ -95,7 +95,7 @@
95 95 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
96 96 SET_STD_PCI_INFO(pci_info[num], 1);
97 97 pcie_ep = fsl_setup_hose(&pci1_hose, pci_info[num].regs);
98   - printf("\n PCI1: %d bit %s, %s %d MHz, %s, %s\n",
  98 + printf("PCI1: %d bit %s, %s %d MHz, %s, %s\n",
99 99 pci_32 ? 32 : 64,
100 100 pcix ? "PCIX" : "PCI",
101 101 pci_spd_norm ? ">=" : "<=",
... ... @@ -106,7 +106,7 @@
106 106 first_free_busno = fsl_pci_init_port(&pci_info[num++],
107 107 &pci1_hose, first_free_busno);
108 108 } else {
109   - printf(" PCI1: disabled\n");
  109 + printf("PCI1: disabled\n");
110 110 }
111 111 #elif defined CONFIG_MPC8548
112 112 /* PCI1 not present on MPC8572 */
113 113  
... ... @@ -119,12 +119,12 @@
119 119 if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE1)) {
120 120 SET_STD_PCIE_INFO(pci_info[num], 1);
121 121 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
122   - printf(" PCIE1 connected as %s\n",
  122 + printf("PCIE1: connected as %s\n",
123 123 pcie_ep ? "Endpoint" : "Root Complex");
124 124 first_free_busno = fsl_pci_init_port(&pci_info[num++],
125 125 &pcie1_hose, first_free_busno);
126 126 } else {
127   - printf(" PCIE1: disabled\n");
  127 + printf("PCIE1: disabled\n");
128 128 }
129 129 #else
130 130 setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE1);
131 131  
... ... @@ -136,12 +136,12 @@
136 136 if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE2)) {
137 137 SET_STD_PCIE_INFO(pci_info[num], 2);
138 138 pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
139   - printf(" PCIE2 connected as %s\n",
  139 + printf("PCIE2: connected as %s\n",
140 140 pcie_ep ? "Endpoint" : "Root Complex");
141 141 first_free_busno = fsl_pci_init_port(&pci_info[num++],
142 142 &pcie2_hose, first_free_busno);
143 143 } else {
144   - printf(" PCIE2: disabled\n");
  144 + printf("PCIE2: disabled\n");
145 145 }
146 146 #else
147 147 setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE2);
148 148  
... ... @@ -153,12 +153,12 @@
153 153 if (pcie_configured && !(devdisr & MPC8xxx_DEVDISR_PCIE3)) {
154 154 SET_STD_PCIE_INFO(pci_info[num], 3);
155 155 pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
156   - printf(" PCIE3 connected as %s\n",
  156 + printf("PCIE3: connected as %s\n",
157 157 pcie_ep ? "Endpoint" : "Root Complex");
158 158 first_free_busno = fsl_pci_init_port(&pci_info[num++],
159 159 &pcie3_hose, first_free_busno);
160 160 } else {
161   - printf(" PCIE3: disabled\n");
  161 + printf("PCIE3: disabled\n");
162 162 }
163 163 #else
164 164 setbits_be32(&gur->devdisr, MPC8xxx_DEVDISR_PCIE3);
drivers/pci/fsl_pci_init.c
Diff comments   View file @ 8ca78f2
... ... @@ -391,11 +391,11 @@
391 391 * 1 == pci agent or pcie end-point
392 392 */
393 393 if (!temp8) {
394   - printf(" Scanning PCI bus %02x\n",
  394 + printf(" Scanning PCI bus %02x\n",
395 395 hose->current_busno);
396 396 hose->last_busno = pci_hose_scan_bus(hose, hose->current_busno);
397 397 } else {
398   - debug(" Not scanning PCI bus %02x. PI=%x\n",
  398 + debug(" Not scanning PCI bus %02x. PI=%x\n",
399 399 hose->current_busno, temp8);
400 400 hose->last_busno = hose->current_busno;
401 401 }
... ... @@ -482,9 +482,9 @@
482 482 }
483 483  
484 484 pci_hose_read_config_byte(hose, dev, FSL_PCIE_CAP_ID, &pcie_cap);
485   - printf(" PCI%s%x on bus %02x - %02x\n", pcie_cap == PCI_CAP_ID_EXP ?
486   - "E" : "", pci_info->pci_num,
487   - hose->first_busno, hose->last_busno);
  485 + printf("PCI%s%x: Bus %02x - %02x\n", pcie_cap == PCI_CAP_ID_EXP ?
  486 + "E" : "", pci_info->pci_num,
  487 + hose->first_busno, hose->last_busno);
488 488  
489 489 return(hose->last_busno + 1);
490 490 }